[PATCH] D121785: The [3/3] Fix mangle problem when variable used in inline asm (Support ARR[BaseReg+IndexReg+..] in PIC model)

Kan Shengchen via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Mon Mar 21 20:46:36 PDT 2022


skan added inline comments.


================
Comment at: llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp:489-491
+      // This case mostly happen in inline asm, e.g. Arr[BaseReg + IndexReg]
+      // can not intruduce additional register in inline asm in PIC model.
+      if (IsPIC && (!SymName.empty() || AttachToOperandIdx))
----------------
Why do you need to check `AttachToOperandIdx` and `SymName` at same time?


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D121785/new/

https://reviews.llvm.org/D121785



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