[PATCH] D122186: [RISCV] Special case sign extended scalars when type legalizing nxvXi64 .vx instrinsics on RV32.

[Zakk Chen via Phabricator via llvm-commits]

khchen accepted this revision.
khchen added a comment.
This revision is now accepted and ready to land.

Thanks, LGTM!



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Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:4625
 
   // If this is a sign-extended 32-bit constant, we can truncate it and rely
   // on the instruction to sign-extend since SEW>XLEN.
----------------
nit: Need to update comment.


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Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:4751
   // We need to convert the scalar to a splat vector.
   // FIXME: Can we implicitly truncate the scalar if it is known to
   // be sign extended?
----------------
nit: Maybe we remove this FIXME comment now?


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https://reviews.llvm.org/D122186