[llvm] 35a7be6 - [SDAG] enable binop identity constant folds for shifts
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Mon Mar 21 06:03:07 PDT 2022
Author: Simon Pilgrim
Date: 2022-03-21T13:02:50Z
New Revision: 35a7be6ccb614a0b5d30c7f92aa2539bb0cf0dda
URL: https://github.com/llvm/llvm-project/commit/35a7be6ccb614a0b5d30c7f92aa2539bb0cf0dda
DIFF: https://github.com/llvm/llvm-project/commit/35a7be6ccb614a0b5d30c7f92aa2539bb0cf0dda.diff
LOG: [SDAG] enable binop identity constant folds for shifts
Add shl/srl/sra to the list of ops that we canonicalize with a select to expose an identity merge
Differential Revision: https://reviews.llvm.org/D122070
Added:
Modified:
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
llvm/test/CodeGen/X86/vector-bo-select.ll
Removed:
################################################################################
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index d25eda6b2dc52..4cda3092d48d3 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -2163,6 +2163,9 @@ static SDValue foldSelectWithIdentityConstant(SDNode *N, SelectionDAG &DAG,
switch (Opcode) {
case ISD::ADD: // X + 0 --> X
case ISD::SUB: // X - 0 --> X
+ case ISD::SHL: // X << 0 --> X
+ case ISD::SRA: // X s>> 0 --> X
+ case ISD::SRL: // X u>> 0 --> X
return C->isZero();
}
}
diff --git a/llvm/test/CodeGen/X86/vector-bo-select.ll b/llvm/test/CodeGen/X86/vector-bo-select.ll
index 068070a68c149..8677197e287e9 100644
--- a/llvm/test/CodeGen/X86/vector-bo-select.ll
+++ b/llvm/test/CodeGen/X86/vector-bo-select.ll
@@ -1237,8 +1237,8 @@ define <4 x i32> @shl_v4i32(<4 x i1> %b, <4 x i32> noundef %x, <4 x i32> noundef
; AVX512VL: # %bb.0:
; AVX512VL-NEXT: vpslld $31, %xmm0, %xmm0
; AVX512VL-NEXT: vptestmd %xmm0, %xmm0, %k1
-; AVX512VL-NEXT: vmovdqa32 %xmm2, %xmm0 {%k1} {z}
-; AVX512VL-NEXT: vpsllvd %xmm0, %xmm1, %xmm0
+; AVX512VL-NEXT: vpsllvd %xmm2, %xmm1, %xmm1 {%k1}
+; AVX512VL-NEXT: vmovdqa %xmm1, %xmm0
; AVX512VL-NEXT: retq
%s = select <4 x i1> %b, <4 x i32> %y, <4 x i32> zeroinitializer
%r = shl <4 x i32> %x, %s
@@ -1301,9 +1301,9 @@ define <16 x i32> @shl_v16i32_swap(<16 x i1> %b, <16 x i32> noundef %x, <16 x i3
; AVX512: # %bb.0:
; AVX512-NEXT: vpmovsxbd %xmm0, %zmm0
; AVX512-NEXT: vpslld $31, %zmm0, %zmm0
-; AVX512-NEXT: vptestnmd %zmm0, %zmm0, %k1
-; AVX512-NEXT: vmovdqa32 %zmm2, %zmm0 {%k1} {z}
-; AVX512-NEXT: vpsllvd %zmm0, %zmm1, %zmm0
+; AVX512-NEXT: vptestmd %zmm0, %zmm0, %k1
+; AVX512-NEXT: vpsllvd %zmm2, %zmm1, %zmm0
+; AVX512-NEXT: vmovdqa32 %zmm1, %zmm0 {%k1}
; AVX512-NEXT: retq
%s = select <16 x i1> %b, <16 x i32> zeroinitializer, <16 x i32> %y
%r = shl <16 x i32> %x, %s
@@ -1365,8 +1365,7 @@ define <8 x i32> @shl_v8i32_cast_cond(i8 noundef zeroext %pb, <8 x i32> noundef
; AVX512VL-LABEL: shl_v8i32_cast_cond:
; AVX512VL: # %bb.0:
; AVX512VL-NEXT: kmovw %edi, %k1
-; AVX512VL-NEXT: vmovdqa32 %ymm1, %ymm1 {%k1} {z}
-; AVX512VL-NEXT: vpsllvd %ymm1, %ymm0, %ymm0
+; AVX512VL-NEXT: vpsllvd %ymm1, %ymm0, %ymm0 {%k1}
; AVX512VL-NEXT: retq
%b = bitcast i8 %pb to <8 x i1>
%s = select <8 x i1> %b, <8 x i32> %y, <8 x i32> zeroinitializer
@@ -1394,8 +1393,7 @@ define <8 x i64> @shl_v8i64_cast_cond(i8 noundef zeroext %pb, <8 x i64> noundef
; AVX512-LABEL: shl_v8i64_cast_cond:
; AVX512: # %bb.0:
; AVX512-NEXT: kmovw %edi, %k1
-; AVX512-NEXT: vmovdqa64 %zmm1, %zmm1 {%k1} {z}
-; AVX512-NEXT: vpsllvq %zmm1, %zmm0, %zmm0
+; AVX512-NEXT: vpsllvq %zmm1, %zmm0, %zmm0 {%k1}
; AVX512-NEXT: retq
%b = bitcast i8 %pb to <8 x i1>
%s = select <8 x i1> %b, <8 x i64> %y, <8 x i64> zeroinitializer
@@ -1426,8 +1424,8 @@ define <4 x i32> @lshr_v4i32(<4 x i1> %b, <4 x i32> noundef %x, <4 x i32> nounde
; AVX512VL: # %bb.0:
; AVX512VL-NEXT: vpslld $31, %xmm0, %xmm0
; AVX512VL-NEXT: vptestmd %xmm0, %xmm0, %k1
-; AVX512VL-NEXT: vmovdqa32 %xmm2, %xmm0 {%k1} {z}
-; AVX512VL-NEXT: vpsrlvd %xmm0, %xmm1, %xmm0
+; AVX512VL-NEXT: vpsrlvd %xmm2, %xmm1, %xmm1 {%k1}
+; AVX512VL-NEXT: vmovdqa %xmm1, %xmm0
; AVX512VL-NEXT: retq
%s = select <4 x i1> %b, <4 x i32> %y, <4 x i32> zeroinitializer
%r = lshr <4 x i32> %x, %s
@@ -1490,9 +1488,9 @@ define <16 x i32> @lshr_v16i32_swap(<16 x i1> %b, <16 x i32> noundef %x, <16 x i
; AVX512: # %bb.0:
; AVX512-NEXT: vpmovsxbd %xmm0, %zmm0
; AVX512-NEXT: vpslld $31, %zmm0, %zmm0
-; AVX512-NEXT: vptestnmd %zmm0, %zmm0, %k1
-; AVX512-NEXT: vmovdqa32 %zmm2, %zmm0 {%k1} {z}
-; AVX512-NEXT: vpsrlvd %zmm0, %zmm1, %zmm0
+; AVX512-NEXT: vptestmd %zmm0, %zmm0, %k1
+; AVX512-NEXT: vpsrlvd %zmm2, %zmm1, %zmm0
+; AVX512-NEXT: vmovdqa32 %zmm1, %zmm0 {%k1}
; AVX512-NEXT: retq
%s = select <16 x i1> %b, <16 x i32> zeroinitializer, <16 x i32> %y
%r = lshr <16 x i32> %x, %s
@@ -1554,8 +1552,7 @@ define <8 x i32> @lshr_v8i32_cast_cond(i8 noundef zeroext %pb, <8 x i32> noundef
; AVX512VL-LABEL: lshr_v8i32_cast_cond:
; AVX512VL: # %bb.0:
; AVX512VL-NEXT: kmovw %edi, %k1
-; AVX512VL-NEXT: vmovdqa32 %ymm1, %ymm1 {%k1} {z}
-; AVX512VL-NEXT: vpsrlvd %ymm1, %ymm0, %ymm0
+; AVX512VL-NEXT: vpsrlvd %ymm1, %ymm0, %ymm0 {%k1}
; AVX512VL-NEXT: retq
%b = bitcast i8 %pb to <8 x i1>
%s = select <8 x i1> %b, <8 x i32> %y, <8 x i32> zeroinitializer
@@ -1583,8 +1580,7 @@ define <8 x i64> @lshr_v8i64_cast_cond(i8 noundef zeroext %pb, <8 x i64> noundef
; AVX512-LABEL: lshr_v8i64_cast_cond:
; AVX512: # %bb.0:
; AVX512-NEXT: kmovw %edi, %k1
-; AVX512-NEXT: vmovdqa64 %zmm1, %zmm1 {%k1} {z}
-; AVX512-NEXT: vpsrlvq %zmm1, %zmm0, %zmm0
+; AVX512-NEXT: vpsrlvq %zmm1, %zmm0, %zmm0 {%k1}
; AVX512-NEXT: retq
%b = bitcast i8 %pb to <8 x i1>
%s = select <8 x i1> %b, <8 x i64> %y, <8 x i64> zeroinitializer
@@ -1615,8 +1611,8 @@ define <4 x i32> @ashr_v4i32(<4 x i1> %b, <4 x i32> noundef %x, <4 x i32> nounde
; AVX512VL: # %bb.0:
; AVX512VL-NEXT: vpslld $31, %xmm0, %xmm0
; AVX512VL-NEXT: vptestmd %xmm0, %xmm0, %k1
-; AVX512VL-NEXT: vmovdqa32 %xmm2, %xmm0 {%k1} {z}
-; AVX512VL-NEXT: vpsravd %xmm0, %xmm1, %xmm0
+; AVX512VL-NEXT: vpsravd %xmm2, %xmm1, %xmm1 {%k1}
+; AVX512VL-NEXT: vmovdqa %xmm1, %xmm0
; AVX512VL-NEXT: retq
%s = select <4 x i1> %b, <4 x i32> %y, <4 x i32> zeroinitializer
%r = ashr <4 x i32> %x, %s
@@ -1679,9 +1675,9 @@ define <16 x i32> @ashr_v16i32_swap(<16 x i1> %b, <16 x i32> noundef %x, <16 x i
; AVX512: # %bb.0:
; AVX512-NEXT: vpmovsxbd %xmm0, %zmm0
; AVX512-NEXT: vpslld $31, %zmm0, %zmm0
-; AVX512-NEXT: vptestnmd %zmm0, %zmm0, %k1
-; AVX512-NEXT: vmovdqa32 %zmm2, %zmm0 {%k1} {z}
-; AVX512-NEXT: vpsravd %zmm0, %zmm1, %zmm0
+; AVX512-NEXT: vptestmd %zmm0, %zmm0, %k1
+; AVX512-NEXT: vpsravd %zmm2, %zmm1, %zmm0
+; AVX512-NEXT: vmovdqa32 %zmm1, %zmm0 {%k1}
; AVX512-NEXT: retq
%s = select <16 x i1> %b, <16 x i32> zeroinitializer, <16 x i32> %y
%r = ashr <16 x i32> %x, %s
@@ -1743,8 +1739,7 @@ define <8 x i32> @ashr_v8i32_cast_cond(i8 noundef zeroext %pb, <8 x i32> noundef
; AVX512VL-LABEL: ashr_v8i32_cast_cond:
; AVX512VL: # %bb.0:
; AVX512VL-NEXT: kmovw %edi, %k1
-; AVX512VL-NEXT: vmovdqa32 %ymm1, %ymm1 {%k1} {z}
-; AVX512VL-NEXT: vpsravd %ymm1, %ymm0, %ymm0
+; AVX512VL-NEXT: vpsravd %ymm1, %ymm0, %ymm0 {%k1}
; AVX512VL-NEXT: retq
%b = bitcast i8 %pb to <8 x i1>
%s = select <8 x i1> %b, <8 x i32> %y, <8 x i32> zeroinitializer
@@ -1779,8 +1774,7 @@ define <8 x i64> @ashr_v8i64_cast_cond(i8 noundef zeroext %pb, <8 x i64> noundef
; AVX512-LABEL: ashr_v8i64_cast_cond:
; AVX512: # %bb.0:
; AVX512-NEXT: kmovw %edi, %k1
-; AVX512-NEXT: vmovdqa64 %zmm1, %zmm1 {%k1} {z}
-; AVX512-NEXT: vpsravq %zmm1, %zmm0, %zmm0
+; AVX512-NEXT: vpsravq %zmm1, %zmm0, %zmm0 {%k1}
; AVX512-NEXT: retq
%b = bitcast i8 %pb to <8 x i1>
%s = select <8 x i1> %b, <8 x i64> %y, <8 x i64> zeroinitializer
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