[PATCH] D122051: [RISCV] The immediate version of sgt/ugt lowering to slti/sltiu + xori

[LiqinWeng via Phabricator via llvm-commits]

Miss_Grape added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfo.td:355
+// A 12-bit signed immediate sub one where the imm range will be [-2049, 2046].
+def simm12_sub1 : ImmLeaf<XLenVT,
+  [{return (isInt<12>(Imm) && Imm != 2047) || Imm == -2049;}]>;
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benshi001 wrote:
> benshi001 wrote:
> > The zero value should be excluded, which is not needed to do `li`, and case just 
> >  be used with the register `X0`.
> I think
> 
> 1. The form `(-2049 <= Imm && Imm < 0) || (0 < Imm && Imm <= 2046)` is more clear.
> 
> 2. Do a further check that the imm node has only one use.
I don't think we need to specifically consider the case of Imm == 0， riscv-gcc did not exclude it alone


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https://reviews.llvm.org/D122051