[PATCH] D122125: [PowerPC] generate CTR loops instructions after ISEL

[ChenZheng via Phabricator via llvm-commits]

shchenz created this revision.
shchenz added reviewers: jsji, nemanjai, PowerPC.
Herald added subscribers: steven.zhang, kbarton, hiraditya, mgorny.
Herald added a project: All.
shchenz requested review of this revision.
Herald added a project: LLVM.
Herald added a subscriber: llvm-commits.

This was first raised in https://reviews.llvm.org/D81353#2078725.

We solved many bugs related to PowerPC generating CTR Loops too early and after ISEL we found there is CTR clobber in the CTR loop. So we have to exclude the CTR clobber instructions in hardware loop insertion pass one by one.

This patch implements a new way to generate the CTR loops. Now the intrinsics inserted in hardware loop pass will be mapped to pseudo instructions and these pseudo instructions will be expanded to CTR loop or normal compare+branch loop based on the result of a new added post-isel pass `PPCCTRLoop`.

This is the first part, including:
1: pseudo instructions for the CTR loops.
2: a new pass to expand the pseudo instructions.

One or more follow up patches will map the  hardware loop intrinsics to the new added pseudo instructions  and delete the CTR clobber check in hardware loop insertion pass.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D122125

Files:
  llvm/lib/Target/PowerPC/CMakeLists.txt
  llvm/lib/Target/PowerPC/PPC.h
  llvm/lib/Target/PowerPC/PPCCTRLoops.cpp
  llvm/lib/Target/PowerPC/PPCInstr64Bit.td
  llvm/lib/Target/PowerPC/PPCInstrInfo.td
  llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
  llvm/test/CodeGen/PowerPC/O3-pipeline.ll
  llvm/test/CodeGen/PowerPC/ctrloops.mir

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