[PATCH] D122084: [X86] combineAddOrSubToADCOrSBB - Fold ADD/SUB + (AND(SRL(X,Y),1) -> ADC/SBB+BT(X,Y)

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon planned changes to this revision.
RKSimon added a comment.

In D122084#3394717 <https://reviews.llvm.org/D122084#3394717>, @craig.topper wrote:

> Is this still an interesting optimization if the ISD::SRL doesn't exist? Replacing (and X, 1) with bt X, 0 to get the carry flag?

Yes, we have special cases for both the lsb and msb bits that don't get matched yet as LowerAndToBT doesn't currently handle them. I have a test for the msb case, but not the lsb one.



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Comment at: llvm/test/CodeGen/X86/add-sub-bool.ll:129
 
 define i32 @test_i32_sub_sub_idx(i32 %x, i32 %y, i32 %z) {
 ; X86-LABEL: test_i32_sub_sub_idx:
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pengfei wrote:
> So the test actually tests for `%x - (%y - bool(%z & (1 << 30))`? The name seems misleading which implies it tests for `test_sub` in PR35256.
Sorry, I was trying to test all permutations of the adds/subs to see whether any folds stall further optimizations. I'll update the comment at the top.


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