[PATCH] D121152: [RISCV] Add more sign-extending ops to MIR sext.w pass.

[Kito Cheng via Phabricator via llvm-commits]

kito-cheng added a comment.

Tested and committed with testcase update (due to label name change).


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D121152/new/

https://reviews.llvm.org/D121152