[llvm] 920c2e5 - [X86][NFC] Rename target feature hasCMov->hasCMOV
Shengchen Kan via llvm-commits
llvm-commits at lists.llvm.org
Thu Mar 17 23:06:12 PDT 2022
Author: Shengchen Kan
Date: 2022-03-18T14:05:52+08:00
New Revision: 920c2e576377281e52adba3e3244fb8a930d3841
URL: https://github.com/llvm/llvm-project/commit/920c2e576377281e52adba3e3244fb8a930d3841
DIFF: https://github.com/llvm/llvm-project/commit/920c2e576377281e52adba3e3244fb8a930d3841.diff
LOG: [X86][NFC] Rename target feature hasCMov->hasCMOV
This is a follow-up patch for D121975.
Added:
Modified:
llvm/lib/Target/X86/X86FastISel.cpp
llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
llvm/lib/Target/X86/X86ISelLowering.cpp
llvm/lib/Target/X86/X86InstrCMovSetCC.td
llvm/lib/Target/X86/X86InstrCompiler.td
llvm/lib/Target/X86/X86InstrFPStack.td
llvm/lib/Target/X86/X86InstrInfo.cpp
llvm/lib/Target/X86/X86InstrInfo.td
llvm/lib/Target/X86/X86Subtarget.cpp
llvm/lib/Target/X86/X86Subtarget.h
Removed:
################################################################################
diff --git a/llvm/lib/Target/X86/X86FastISel.cpp b/llvm/lib/Target/X86/X86FastISel.cpp
index 1ac998b7ff7ed..cbdb7327d1949 100644
--- a/llvm/lib/Target/X86/X86FastISel.cpp
+++ b/llvm/lib/Target/X86/X86FastISel.cpp
@@ -2036,7 +2036,7 @@ bool X86FastISel::X86SelectDivRem(const Instruction *I) {
/// the select.
bool X86FastISel::X86FastEmitCMoveSelect(MVT RetVT, const Instruction *I) {
// Check if the subtarget supports these instructions.
- if (!Subtarget->hasCMov())
+ if (!Subtarget->hasCMOV())
return false;
// FIXME: Add support for i8.
diff --git a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
index 7feef2a7b9651..ea421b7d75bd1 100644
--- a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
+++ b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
@@ -5514,7 +5514,7 @@ void X86DAGToDAGISel::Select(SDNode *Node) {
MVT CmpVT = N0.getSimpleValueType();
// Floating point needs special handling if we don't have FCOMI.
- if (Subtarget->hasCMov())
+ if (Subtarget->hasCMOV())
break;
bool IsSignaling = Node->getOpcode() == X86ISD::STRICT_FCMPS;
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 7f169d8bb83d2..f3f78a624d69d 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -200,7 +200,7 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
}
// Integer absolute.
- if (Subtarget.hasCMov()) {
+ if (Subtarget.hasCMOV()) {
setOperationAction(ISD::ABS , MVT::i16 , Custom);
setOperationAction(ISD::ABS , MVT::i32 , Custom);
if (Subtarget.is64Bit())
@@ -23466,7 +23466,7 @@ X86TargetLowering::BuildSDIVPow2(SDNode *N, const APInt &Divisor,
// Only perform this transform if CMOV is supported otherwise the select
// below will become a branch.
- if (!Subtarget.hasCMov())
+ if (!Subtarget.hasCMOV())
return SDValue();
// fold (sdiv X, pow2)
@@ -24656,7 +24656,7 @@ SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
return (Op1.getOpcode() == ISD::CTTZ_ZERO_UNDEF && Op1.hasOneUse() &&
Op1.getOperand(0) == CmpOp0 && isAllOnesConstant(Op2));
};
- if (Subtarget.hasCMov() && (VT == MVT::i32 || VT == MVT::i64) &&
+ if (Subtarget.hasCMOV() && (VT == MVT::i32 || VT == MVT::i64) &&
((CondCode == X86::COND_NE && MatchFFSMinus1(Op1, Op2)) ||
(CondCode == X86::COND_E && MatchFFSMinus1(Op2, Op1)))) {
// Keep Cmp.
@@ -24684,7 +24684,7 @@ SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
DAG.getTargetConstant(X86::COND_B, DL, MVT::i8),
Sub.getValue(1));
return DAG.getNode(ISD::OR, DL, VT, SBB, Y);
- } else if (!Subtarget.hasCMov() && CondCode == X86::COND_E &&
+ } else if (!Subtarget.hasCMOV() && CondCode == X86::COND_E &&
Cmp.getOperand(0).getOpcode() == ISD::AND &&
isOneConstant(Cmp.getOperand(0).getOperand(1))) {
SDValue Src1, Src2;
@@ -24739,7 +24739,7 @@ SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
SDValue Cmp = Cond.getOperand(1);
bool IllegalFPCMov = false;
if (VT.isFloatingPoint() && !VT.isVector() &&
- !isScalarFPTypeInSSEReg(VT) && Subtarget.hasCMov()) // FPStack?
+ !isScalarFPTypeInSSEReg(VT) && Subtarget.hasCMOV()) // FPStack?
IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
@@ -24820,7 +24820,7 @@ SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
// legal, but EmitLoweredSelect() can not deal with these extensions
// being inserted between two CMOV's. (in i16 case too TBN)
// https://bugs.llvm.org/show_bug.cgi?id=40974
- if ((Op.getValueType() == MVT::i8 && Subtarget.hasCMov()) ||
+ if ((Op.getValueType() == MVT::i8 && Subtarget.hasCMOV()) ||
(Op.getValueType() == MVT::i16 && !X86::mayFoldLoad(Op1, Subtarget) &&
!X86::mayFoldLoad(Op2, Subtarget))) {
Op1 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, Op1);
@@ -45100,7 +45100,7 @@ static SDValue combineCMov(SDNode *N, SelectionDAG &DAG,
if (!(FalseOp.getValueType() == MVT::f80 ||
(FalseOp.getValueType() == MVT::f64 && !Subtarget.hasSSE2()) ||
(FalseOp.getValueType() == MVT::f32 && !Subtarget.hasSSE1())) ||
- !Subtarget.hasCMov() || hasFPCMov(CC)) {
+ !Subtarget.hasCMOV() || hasFPCMov(CC)) {
SDValue Ops[] = {FalseOp, TrueOp, DAG.getTargetConstant(CC, DL, MVT::i8),
Flags};
return DAG.getNode(X86ISD::CMOV, DL, N->getValueType(0), Ops);
diff --git a/llvm/lib/Target/X86/X86InstrCMovSetCC.td b/llvm/lib/Target/X86/X86InstrCMovSetCC.td
index 330b8c7a8a43a..79ac2a2d80191 100644
--- a/llvm/lib/Target/X86/X86InstrCMovSetCC.td
+++ b/llvm/lib/Target/X86/X86InstrCMovSetCC.td
@@ -14,7 +14,7 @@
// CMOV instructions.
let isCodeGenOnly = 1, ForceDisassemble = 1 in {
-let Uses = [EFLAGS], Predicates = [HasCMov], Constraints = "$src1 = $dst",
+let Uses = [EFLAGS], Predicates = [HasCMOV], Constraints = "$src1 = $dst",
isCommutable = 1, SchedRW = [WriteCMOV] in {
def CMOV16rr
: I<0x40, MRMSrcRegCC, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2, ccode:$cond),
@@ -35,7 +35,7 @@ let Uses = [EFLAGS], Predicates = [HasCMov], Constraints = "$src1 = $dst",
(X86cmov GR64:$src1, GR64:$src2, timm:$cond, EFLAGS))]>, TB;
}
-let Uses = [EFLAGS], Predicates = [HasCMov], Constraints = "$src1 = $dst",
+let Uses = [EFLAGS], Predicates = [HasCMOV], Constraints = "$src1 = $dst",
SchedRW = [WriteCMOV.Folded, WriteCMOV.ReadAfterFold] in {
def CMOV16rm
: I<0x40, MRMSrcMemCC, (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2, ccode:$cond),
@@ -52,7 +52,7 @@ let Uses = [EFLAGS], Predicates = [HasCMov], Constraints = "$src1 = $dst",
"cmov${cond}{q}\t{$src2, $dst|$dst, $src2}",
[(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
timm:$cond, EFLAGS))]>, TB;
-} // Uses = [EFLAGS], Predicates = [HasCMov], Constraints = "$src1 = $dst"
+} // Uses = [EFLAGS], Predicates = [HasCMOV], Constraints = "$src1 = $dst"
} // isCodeGenOnly = 1, ForceDisassemble = 1
def inv_cond_XFORM : SDNodeXForm<imm, [{
@@ -63,7 +63,7 @@ def inv_cond_XFORM : SDNodeXForm<imm, [{
// Conditional moves with folded loads with operands swapped and conditions
// inverted.
-let Predicates = [HasCMov] in {
+let Predicates = [HasCMOV] in {
def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, timm:$cond, EFLAGS),
(CMOV16rm GR16:$src2, addr:$src1, (inv_cond_XFORM timm:$cond))>;
def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, timm:$cond, EFLAGS),
diff --git a/llvm/lib/Target/X86/X86InstrCompiler.td b/llvm/lib/Target/X86/X86InstrCompiler.td
index 6d9ccebf962ae..c14c1f6855087 100644
--- a/llvm/lib/Target/X86/X86InstrCompiler.td
+++ b/llvm/lib/Target/X86/X86InstrCompiler.td
@@ -544,10 +544,10 @@ let usesCustomInserter = 1, hasNoSchedulingInfo = 1, Uses = [EFLAGS] in {
// i8 register pressure.
defm _GR8 : CMOVrr_PSEUDO<GR8, i8>;
- let Predicates = [NoCMov] in {
+ let Predicates = [NoCMOV] in {
defm _GR32 : CMOVrr_PSEUDO<GR32, i32>;
defm _GR16 : CMOVrr_PSEUDO<GR16, i16>;
- } // Predicates = [NoCMov]
+ } // Predicates = [NoCMOV]
// fcmov doesn't handle all possible EFLAGS, provide a fallback if there is no
// SSE1/SSE2.
diff --git a/llvm/lib/Target/X86/X86InstrFPStack.td b/llvm/lib/Target/X86/X86InstrFPStack.td
index e310f369be089..a68d61043c5c4 100644
--- a/llvm/lib/Target/X86/X86InstrFPStack.td
+++ b/llvm/lib/Target/X86/X86InstrFPStack.td
@@ -423,9 +423,9 @@ def FBSTPm : FPI<0xDF, MRM6m, (outs), (ins f80mem:$dst), "fbstp\t$dst">;
// Floating point cmovs.
class FpIf32CMov<dag outs, dag ins, FPFormat fp, list<dag> pattern> :
- FpI_<outs, ins, fp, pattern>, Requires<[FPStackf32, HasCMov]>;
+ FpI_<outs, ins, fp, pattern>, Requires<[FPStackf32, HasCMOV]>;
class FpIf64CMov<dag outs, dag ins, FPFormat fp, list<dag> pattern> :
- FpI_<outs, ins, fp, pattern>, Requires<[FPStackf64, HasCMov]>;
+ FpI_<outs, ins, fp, pattern>, Requires<[FPStackf64, HasCMOV]>;
multiclass FPCMov<PatLeaf cc> {
def _Fp32 : FpIf32CMov<(outs RFP32:$dst), (ins RFP32:$src1, RFP32:$src2),
@@ -440,7 +440,7 @@ multiclass FPCMov<PatLeaf cc> {
CondMovFP,
[(set RFP80:$dst, (X86cmov RFP80:$src1, RFP80:$src2,
cc, EFLAGS))]>,
- Requires<[HasCMov]>;
+ Requires<[HasCMOV]>;
}
let SchedRW = [WriteFCMOV] in {
@@ -455,7 +455,7 @@ defm CMOVNE : FPCMov<X86_COND_NE>;
defm CMOVNP : FPCMov<X86_COND_NP>;
} // Uses = [EFLAGS], Constraints = "$src1 = $dst"
-let Predicates = [HasCMov] in {
+let Predicates = [HasCMOV] in {
// These are not factored because there's no clean way to pass DA/DB.
def CMOVB_F : FPI<0xDA, MRM0r, (outs), (ins RSTi:$op),
"fcmovb\t{$op, %st|st, $op}">;
@@ -473,7 +473,7 @@ def CMOVNE_F : FPI<0xDB, MRM1r, (outs), (ins RSTi:$op),
"fcmovne\t{$op, %st|st, $op}">;
def CMOVNP_F : FPI<0xDB, MRM3r, (outs), (ins RSTi:$op),
"fcmovnu\t{$op, %st|st, $op}">;
-} // Predicates = [HasCMov]
+} // Predicates = [HasCMOV]
} // SchedRW
let mayRaiseFPException = 1 in {
@@ -664,22 +664,22 @@ let SchedRW = [WriteFCom], mayRaiseFPException = 1 in {
let Defs = [EFLAGS, FPSW], Uses = [FPCW] in {
def UCOM_FpIr32: FpI_<(outs), (ins RFP32:$lhs, RFP32:$rhs), CompareFP,
[(set EFLAGS, (X86any_fcmp RFP32:$lhs, RFP32:$rhs))]>,
- Requires<[FPStackf32, HasCMov]>;
+ Requires<[FPStackf32, HasCMOV]>;
def UCOM_FpIr64: FpI_<(outs), (ins RFP64:$lhs, RFP64:$rhs), CompareFP,
[(set EFLAGS, (X86any_fcmp RFP64:$lhs, RFP64:$rhs))]>,
- Requires<[FPStackf64, HasCMov]>;
+ Requires<[FPStackf64, HasCMOV]>;
def UCOM_FpIr80: FpI_<(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP,
[(set EFLAGS, (X86any_fcmp RFP80:$lhs, RFP80:$rhs))]>,
- Requires<[HasCMov]>;
+ Requires<[HasCMOV]>;
def COM_FpIr32: FpI_<(outs), (ins RFP32:$lhs, RFP32:$rhs), CompareFP,
[(set EFLAGS, (X86strict_fcmps RFP32:$lhs, RFP32:$rhs))]>,
- Requires<[FPStackf32, HasCMov]>;
+ Requires<[FPStackf32, HasCMOV]>;
def COM_FpIr64: FpI_<(outs), (ins RFP64:$lhs, RFP64:$rhs), CompareFP,
[(set EFLAGS, (X86strict_fcmps RFP64:$lhs, RFP64:$rhs))]>,
- Requires<[FPStackf64, HasCMov]>;
+ Requires<[FPStackf64, HasCMOV]>;
def COM_FpIr80: FpI_<(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP,
[(set EFLAGS, (X86strict_fcmps RFP80:$lhs, RFP80:$rhs))]>,
- Requires<[HasCMov]>;
+ Requires<[HasCMOV]>;
}
let Uses = [ST0, FPCW] in {
diff --git a/llvm/lib/Target/X86/X86InstrInfo.cpp b/llvm/lib/Target/X86/X86InstrInfo.cpp
index cc0c4770135cd..50b26a0bd4201 100644
--- a/llvm/lib/Target/X86/X86InstrInfo.cpp
+++ b/llvm/lib/Target/X86/X86InstrInfo.cpp
@@ -3463,7 +3463,7 @@ bool X86InstrInfo::canInsertSelect(const MachineBasicBlock &MBB,
Register FalseReg, int &CondCycles,
int &TrueCycles, int &FalseCycles) const {
// Not all subtargets have cmov instructions.
- if (!Subtarget.hasCMov())
+ if (!Subtarget.hasCMOV())
return false;
if (Cond.size() != 1)
return false;
diff --git a/llvm/lib/Target/X86/X86InstrInfo.td b/llvm/lib/Target/X86/X86InstrInfo.td
index f4f185fafe899..f9de801574d1a 100644
--- a/llvm/lib/Target/X86/X86InstrInfo.td
+++ b/llvm/lib/Target/X86/X86InstrInfo.td
@@ -875,8 +875,8 @@ def relocImm : ComplexPattern<iAny, 1, "selectRelocImm",
// X86 Instruction Predicate Definitions.
def TruePredicate : Predicate<"true">;
-def HasCMov : Predicate<"Subtarget->hasCMov()">;
-def NoCMov : Predicate<"!Subtarget->hasCMov()">;
+def HasCMOV : Predicate<"Subtarget->hasCMOV()">;
+def NoCMOV : Predicate<"!Subtarget->hasCMOV()">;
def HasMMX : Predicate<"Subtarget->hasMMX()">;
def Has3DNow : Predicate<"Subtarget->hasThreeDNow()">;
diff --git a/llvm/lib/Target/X86/X86Subtarget.cpp b/llvm/lib/Target/X86/X86Subtarget.cpp
index bdb85bb5e92bb..3105a5bce98db 100644
--- a/llvm/lib/Target/X86/X86Subtarget.cpp
+++ b/llvm/lib/Target/X86/X86Subtarget.cpp
@@ -359,7 +359,7 @@ const RegisterBankInfo *X86Subtarget::getRegBankInfo() const {
}
bool X86Subtarget::enableEarlyIfConversion() const {
- return hasCMov() && X86EarlyIfConv;
+ return hasCMOV() && X86EarlyIfConv;
}
void X86Subtarget::getPostRAMutations(
diff --git a/llvm/lib/Target/X86/X86Subtarget.h b/llvm/lib/Target/X86/X86Subtarget.h
index 30574e9048282..ed7fbe4b21027 100644
--- a/llvm/lib/Target/X86/X86Subtarget.h
+++ b/llvm/lib/Target/X86/X86Subtarget.h
@@ -636,7 +636,7 @@ class X86Subtarget final : public X86GenSubtargetInfo {
bool hasNOPL() const { return HasNOPL; }
// SSE codegen depends on cmovs, and all SSE1+ processors support them.
// All 64-bit processors support cmov.
- bool hasCMov() const { return HasCMOV || X86SSELevel >= SSE1 || is64Bit(); }
+ bool hasCMOV() const { return HasCMOV || X86SSELevel >= SSE1 || is64Bit(); }
bool hasSSE1() const { return X86SSELevel >= SSE1; }
bool hasSSE2() const { return X86SSELevel >= SSE2; }
bool hasSSE3() const { return X86SSELevel >= SSE3; }
More information about the llvm-commits
mailing list