[llvm] 31906a6 - [AtomicExpand][PowerPC] Fix all-one mask value

Kai Luo via llvm-commits llvm-commits at lists.llvm.org
Thu Mar 17 22:36:04 PDT 2022


Author: Kai Luo
Date: 2022-03-18T13:35:54+08:00
New Revision: 31906a6090ac2ea513fe5b3e24a2f82e29ca28c3

URL: https://github.com/llvm/llvm-project/commit/31906a6090ac2ea513fe5b3e24a2f82e29ca28c3
DIFF: https://github.com/llvm/llvm-project/commit/31906a6090ac2ea513fe5b3e24a2f82e29ca28c3.diff

LOG: [AtomicExpand][PowerPC] Fix all-one mask value

When generating a all-one mask value whose bitwidth is larger than 64, signed extension should be used rather then zero extension.

Reviewed By: jsji

Differential Revision: https://reviews.llvm.org/D120865

Added: 
    

Modified: 
    llvm/lib/CodeGen/AtomicExpandPass.cpp
    llvm/test/CodeGen/PowerPC/atomics-i128.ll
    llvm/test/Transforms/AtomicExpand/PowerPC/cmpxchg.ll

Removed: 
    


################################################################################
diff  --git a/llvm/lib/CodeGen/AtomicExpandPass.cpp b/llvm/lib/CodeGen/AtomicExpandPass.cpp
index 3a0eb96443cd9..1f7f7839bdfc0 100644
--- a/llvm/lib/CodeGen/AtomicExpandPass.cpp
+++ b/llvm/lib/CodeGen/AtomicExpandPass.cpp
@@ -704,7 +704,7 @@ static PartwordMaskValues createMaskInstrs(IRBuilder<> &Builder, Instruction *I,
     PMV.AlignedAddr = Addr;
     PMV.AlignedAddrAlignment = AddrAlign;
     PMV.ShiftAmt = ConstantInt::get(PMV.ValueType, 0);
-    PMV.Mask = ConstantInt::get(PMV.ValueType, ~0);
+    PMV.Mask = ConstantInt::get(PMV.ValueType, ~0, /*isSigned*/ true);
     return PMV;
   }
 

diff  --git a/llvm/test/CodeGen/PowerPC/atomics-i128.ll b/llvm/test/CodeGen/PowerPC/atomics-i128.ll
index 75466a2f87998..95a2eb5df45ec 100644
--- a/llvm/test/CodeGen/PowerPC/atomics-i128.ll
+++ b/llvm/test/CodeGen/PowerPC/atomics-i128.ll
@@ -473,8 +473,9 @@ define i1 @cas_acqrel_acquire_check_succ(i128* %a, i128 %cmp, i128 %new) {
 ; CHECK-NEXT:    stqcx. r8, 0, r3
 ; CHECK-NEXT:  .LBB11_4: # %entry
 ; CHECK-NEXT:    lwsync
-; CHECK-NEXT:    xor r3, r5, r9
-; CHECK-NEXT:    or r3, r3, r4
+; CHECK-NEXT:    xor r3, r4, r8
+; CHECK-NEXT:    xor r4, r5, r9
+; CHECK-NEXT:    or r3, r4, r3
 ; CHECK-NEXT:    cntlzd r3, r3
 ; CHECK-NEXT:    rldicl r3, r3, 58, 63
 ; CHECK-NEXT:    blr

diff  --git a/llvm/test/Transforms/AtomicExpand/PowerPC/cmpxchg.ll b/llvm/test/Transforms/AtomicExpand/PowerPC/cmpxchg.ll
index e1cbcd3fcf2d6..4c5b0eb03f3a3 100644
--- a/llvm/test/Transforms/AtomicExpand/PowerPC/cmpxchg.ll
+++ b/llvm/test/Transforms/AtomicExpand/PowerPC/cmpxchg.ll
@@ -24,7 +24,7 @@ define i1 @test_cmpxchg_seq_cst(i128* %addr, i128 %desire, i128 %new) {
 ; CHECK-NEXT:    [[TMP4:%.*]] = shl i128 [[HI64]], 64
 ; CHECK-NEXT:    [[VAL64:%.*]] = or i128 [[LO64]], [[TMP4]]
 ; CHECK-NEXT:    [[TMP5:%.*]] = insertvalue { i128, i1 } undef, i128 [[VAL64]], 0
-; CHECK-NEXT:    [[TMP6:%.*]] = and i128 [[VAL64]], 18446744073709551615
+; CHECK-NEXT:    [[TMP6:%.*]] = and i128 [[VAL64]], -1
 ; CHECK-NEXT:    [[SUCCESS:%.*]] = icmp eq i128 [[CMPVAL_SHIFTED]], [[TMP6]]
 ; CHECK-NEXT:    [[TMP7:%.*]] = insertvalue { i128, i1 } [[TMP5]], i1 [[SUCCESS]], 1
 ; CHECK-NEXT:    [[SUCC:%.*]] = extractvalue { i128, i1 } [[TMP7]], 1


        


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