[PATCH] D121524: [AMDGPU] use scalar shift for SALU users in frame index elimination

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


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Comment at: llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp:2237
         // In an entry function/kernel the offset is already swizzled.
-
+        bool IsSALU = TII->isSALU(*MI);
+        const TargetRegisterClass *RC = IsSALU ? &AMDGPU::SReg_32RegClass
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It would be a bit more appropriate to check the class of the use operand


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D121524/new/

https://reviews.llvm.org/D121524