[PATCH] D121914: [AMDGPU] Stop using getMinimalPhysRegClass in LowerFormalArguments
Jay Foad via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Thu Mar 17 08:24:45 PDT 2022
This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG313f306b2684: [AMDGPU] Stop using getMinimalPhysRegClass in LowerFormalArguments (authored by foad).
Changed prior to commit:
https://reviews.llvm.org/D121914?vs=416178&id=416187#toc
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D121914/new/
https://reviews.llvm.org/D121914
Files:
llvm/lib/Target/AMDGPU/SIISelLowering.cpp
Index: llvm/lib/Target/AMDGPU/SIISelLowering.cpp
===================================================================
--- llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -2548,7 +2548,13 @@
assert(VA.isRegLoc() && "Parameter must be in a register!");
Register Reg = VA.getLocReg();
- const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg, VT);
+ const TargetRegisterClass *RC = nullptr;
+ if (AMDGPU::VGPR_32RegClass.contains(Reg))
+ RC = &AMDGPU::VGPR_32RegClass;
+ else if (AMDGPU::SGPR_32RegClass.contains(Reg))
+ RC = &AMDGPU::SGPR_32RegClass;
+ else
+ llvm_unreachable("Unexpected register class in LowerFormalArguments!");
EVT ValVT = VA.getValVT();
Reg = MF.addLiveIn(Reg, RC);
-------------- next part --------------
A non-text attachment was scrubbed...
Name: D121914.416187.patch
Type: text/x-patch
Size: 791 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20220317/cf69fab6/attachment.bin>
More information about the llvm-commits
mailing list