[PATCH] D121914: [AMDGPU] Stop using getMinimalPhysRegClass in LowerFormalArguments

Thu Mar 17 08:11:34 PDT 2022

Joe_Nash accepted this revision.
Joe_Nash added a comment.

In D121914#3389344 <https://reviews.llvm.org/D121914#3389344>, @arsenm wrote:

> In D121914#3389343 <https://reviews.llvm.org/D121914#3389343>, @arsenm wrote:
>
>> In D121914#3389338 <https://reviews.llvm.org/D121914#3389338>, @Joe_Nash wrote:
>>
>>> I think a switch case over known RegClasses that we want to use is the way to go. The only question is do we need to handle more cases. Is this passing testing? When I put assert(VT.getSizeInBits() == 32) here I get massive test failures. So what happens to wider types, they all become VGPR_32?
>>
>> All arguments are supposed to be split into 32 bit pieces before they reach here
>
> I'm assuming your failures are on 16-bit types which still use a 32-bit register class

Yep. When I put assert(VT.getSizeInBits() <= 32) they go away.

Ok. LGTM

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https://reviews.llvm.org/D121914