[llvm] 9c632b6 - [AMDGPU][MC] A fix for commit 5977dfb
Dmitry Preobrazhensky via llvm-commits
llvm-commits at lists.llvm.org
Thu Mar 17 04:41:45 PDT 2022
Author: Dmitry Preobrazhensky
Date: 2022-03-17T14:41:21+03:00
New Revision: 9c632b61ebf2d8dbc45112d4b799e6a61e99a44d
URL: https://github.com/llvm/llvm-project/commit/9c632b61ebf2d8dbc45112d4b799e6a61e99a44d
DIFF: https://github.com/llvm/llvm-project/commit/9c632b61ebf2d8dbc45112d4b799e6a61e99a44d.diff
LOG: [AMDGPU][MC] A fix for commit 5977dfb
The commit code https://github.com/llvm/llvm-project/commit/5977dfba64099e224cba12f580b6867e7a3d149a
failed to compile with GCC5. This patch addresses the issue.
For a related discussion, see https://reviews.llvm.org/D121696
Added:
Modified:
llvm/lib/Target/AMDGPU/Utils/AMDGPUAsmUtils.cpp
llvm/lib/Target/AMDGPU/Utils/AMDGPUAsmUtils.h
Removed:
################################################################################
diff --git a/llvm/lib/Target/AMDGPU/Utils/AMDGPUAsmUtils.cpp b/llvm/lib/Target/AMDGPU/Utils/AMDGPUAsmUtils.cpp
index 228023ef8d500..880937927cfd7 100644
--- a/llvm/lib/Target/AMDGPU/Utils/AMDGPUAsmUtils.cpp
+++ b/llvm/lib/Target/AMDGPU/Utils/AMDGPUAsmUtils.cpp
@@ -56,7 +56,7 @@ namespace Hwreg {
// Disable lint checking for this block since it makes the table unreadable.
// NOLINTBEGIN
const CustomOperand<const MCSubtargetInfo &> Opr[] = {
- {},
+ {{""}},
{{"HW_REG_MODE"}, ID_MODE},
{{"HW_REG_STATUS"}, ID_STATUS},
{{"HW_REG_TRAPSTS"}, ID_TRAPSTS},
@@ -68,13 +68,13 @@ const CustomOperand<const MCSubtargetInfo &> Opr[] = {
{{"HW_REG_GPR_ALLOC"}, ID_GPR_ALLOC},
{{"HW_REG_LDS_ALLOC"}, ID_LDS_ALLOC},
{{"HW_REG_IB_STS"}, ID_IB_STS},
- {},
- {},
- {},
- {},
- {},
- {},
- {},
+ {{""}},
+ {{""}},
+ {{""}},
+ {{""}},
+ {{""}},
+ {{""}},
+ {{""}},
{{"HW_REG_SH_MEM_BASES"}, ID_MEM_BASES, isGFX9Plus},
{{"HW_REG_TBA_LO"}, ID_TBA_LO, isGFX9_GFX10},
{{"HW_REG_TBA_HI"}, ID_TBA_HI, isGFX9_GFX10},
@@ -90,9 +90,9 @@ const CustomOperand<const MCSubtargetInfo &> Opr[] = {
{{"HW_REG_HW_ID1"}, ID_HW_ID1, isGFX10Plus},
{{"HW_REG_HW_ID2"}, ID_HW_ID2, isGFX10Plus},
{{"HW_REG_POPS_PACKER"}, ID_POPS_PACKER, isGFX10},
- {},
- {},
- {},
+ {{""}},
+ {{""}},
+ {{""}},
{{"HW_REG_SHADER_CYCLES"}, ID_SHADER_CYCLES, isGFX10_BEncoding},
// GFX940 specific registers
diff --git a/llvm/lib/Target/AMDGPU/Utils/AMDGPUAsmUtils.h b/llvm/lib/Target/AMDGPU/Utils/AMDGPUAsmUtils.h
index d08035b77ff47..ec05adb68393c 100644
--- a/llvm/lib/Target/AMDGPU/Utils/AMDGPUAsmUtils.h
+++ b/llvm/lib/Target/AMDGPU/Utils/AMDGPUAsmUtils.h
@@ -24,7 +24,7 @@ const int OPR_ID_UNKNOWN = -1;
const int OPR_ID_UNSUPPORTED = -2;
template <class T> struct CustomOperand {
- StringLiteral Name = "";
+ StringLiteral Name;
int Encoding = 0;
bool (*Cond)(T Context) = nullptr;
};
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