[PATCH] D121774: [RISCV] support fcmp in zfinx,zdinx,zhinx

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:101
+    addRegisterClass(MVT::f64, &RISCV::GPRF64RegClass);
+    addRegisterClass(MVT::f64, &RISCV::GPRPF64RegClass);
+  }
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I think you need to check Subtarget.is64Bit() here. You can't assign a type to two register classes. The type is used as the key to a map. The second call overwrites the first.


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  https://reviews.llvm.org/D121774/new/

https://reviews.llvm.org/D121774