[PATCH] D121833: [SelectionDAG][RISCV][AMDGPU][ARM] Improve SimplifyDemandedBits for SHL with variable shift amount.

Matt Arsenault via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Wed Mar 16 16:53:36 PDT 2022

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arsenm added a comment.

Seems like it should get a dedicated test to stress the edge cases


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D121833/new/

https://reviews.llvm.org/D121833

Previous message: [PATCH] D121833: [SelectionDAG][RISCV][AMDGPU][ARM] Improve SimplifyDemandedBits for SHL with variable shift amount.
Next message: [PATCH] D120449: [RISCV][RVV] Add strict vfcvt intrinsics that have side effects for dynamically-set rounding mode
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