[PATCH] D121833: [SelectionDAG][RISCV][AMDGPU][ARM] Improve SimplifyDemandedBits for SHL with variable shift amount.

[Craig Topper via Phabricator via llvm-commits]

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If we have a variable shift amount and the demanded mask has leading
zeros, we can propagate those leading zeros to not demand those bits
from operand 0. This can allow zero_extend/sign_extend to become
any_extend. This pattern can occur due to C integer promotion rules.

This transform is already done by InstCombineSimplifyDemanded.cpp where
sign_extend can be turned into zero_extend for example.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D121833

Files:
  llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
  llvm/test/CodeGen/AMDGPU/shl.ll
  llvm/test/CodeGen/AMDGPU/shl.v2i16.ll
  llvm/test/CodeGen/RISCV/alu16.ll
  llvm/test/CodeGen/RISCV/alu8.ll
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/while-loops.ll

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