[PATCH] D121675: [RISCV] Add pattern for vnsrl.wi and vnsra.wi instructions

Tue Mar 15 20:51:27 PDT 2022

craig.topper added inline comments.

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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td:681

+multiclass VPatBinarySDNode_V_WI<SDNode op, string instruction_name> {
+  foreach vti = AllWidenableIntVectors in {
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Jimerlife wrote:
> craig.topper wrote:
> > The new pattern and the existing patterns are all checking for the VL being exactly X0. Why is that?
> This patch https://reviews.llvm.org/D118845 move VLMax to X0
That wasn't what I was referring to. Most of the patterns in this file use `VLOpFrag` not `X0` so that they work for fixed vectors and VP intrinsics too. This pattern only works VLMax scalable vectors.

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D121675/new/

https://reviews.llvm.org/D121675