[PATCH] D121675: [RISCV] Add pattern for vnsrl.wi and vnsra.wi instructions
WangLian via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Tue Mar 15 19:38:24 PDT 2022
Jimerlife marked an inline comment as done.
Jimerlife added inline comments.
================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td:681
+multiclass VPatBinarySDNode_V_WI<SDNode op, string instruction_name> {
+ foreach vti = AllWidenableIntVectors in {
----------------
craig.topper wrote:
> The new pattern and the existing patterns are all checking for the VL being exactly X0. Why is that?
This patch https://reviews.llvm.org/D118845 move VLMax to X0
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D121675/new/
https://reviews.llvm.org/D121675
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