[PATCH] D121675: [RISCV] Add pattern for vnsrl.wi and vnsra.wi instructions

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td:681
 
+multiclass VPatBinarySDNode_V_WI<SDNode op, string instruction_name> {
+  foreach vti = AllWidenableIntVectors in {
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The new pattern and the existing patterns are all checking for the VL being exactly X0. Why is that?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D121675/new/

https://reviews.llvm.org/D121675