[PATCH] D121206: [AARCH64] ssbs should be enabled by default for cortex-x1, cortex-x1c, cortex-a77

[Ties Stuij via Phabricator via llvm-commits]

stuij marked 2 inline comments as done.
stuij added inline comments.


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Comment at: llvm/lib/Target/AArch64/AArch64.td:978
                                  FeatureNEON, FeatureRCPC, FeaturePerfMon,
                                  FeatureSPE, FeatureFullFP16, FeatureDotProd];
   list<SubtargetFeature> X1C  = [HasV8_2aOps, FeatureCrypto, FeatureFPARMv8,
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amilendra wrote:
> stuij wrote:
> > dmgreen wrote:
> > > X1 and A77 missing SSBS too. Should they be added at the same time?
> > Yes they should. Thanks!
> Maybe add unit tests for X1 and A77 too?
I did. See the top file.

In general it'd be good to have better testing for individual cores. This will happen more structurally in future changes.


Repository:
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  https://reviews.llvm.org/D121206/new/

https://reviews.llvm.org/D121206