[PATCH] D121206: [AARCH64] ssbs should be enabled by default for cortex-x1, cortex-x1c, cortex-a77

[Amilendra Kodithuwakku via Phabricator via llvm-commits]

amilendra accepted this revision.
amilendra added inline comments.
This revision is now accepted and ready to land.


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Comment at: llvm/lib/Target/AArch64/AArch64.td:978
                                  FeatureNEON, FeatureRCPC, FeaturePerfMon,
                                  FeatureSPE, FeatureFullFP16, FeatureDotProd];
   list<SubtargetFeature> X1C  = [HasV8_2aOps, FeatureCrypto, FeatureFPARMv8,
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stuij wrote:
> dmgreen wrote:
> > X1 and A77 missing SSBS too. Should they be added at the same time?
> Yes they should. Thanks!
Maybe add unit tests for X1 and A77 too?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D121206/new/

https://reviews.llvm.org/D121206