[PATCH] D121491: [AMDGPU] Restrict machine copy propagation from creating unaligned classes

[Christudasan Devadasan via Phabricator via llvm-commits]

cdevadas added a comment.

In general, invoking `adjustAllocatableRegClass` post-regalloc doesn't sound good to me. 
I'm in favor of the code that you added to get the aligned regclasses. 
But what's the need to adjust the AV operands beforehand? They'll meet the condition as we have the `_align2` versions for the superclasses available now.



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Comment at: llvm/lib/Target/AMDGPU/SIInstrInfo.cpp:4777
+    if (Size > 32) {
+      if (SIRegisterInfo::isVGPRClass(RC))
+        RC = RI.getVGPRClassForBitWidth(Size);
----------------
Factor this out into a separate function?
We have the following code already used at least 2 more places in our backend.


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Comment at: llvm/test/CodeGen/AMDGPU/mcp-aligned-vgprs.mir:12
+    renamable $vgpr0_vgpr1 = V_PK_MUL_F32 0, $sgpr0_sgpr1, 0, 0, 0, 0, 0, 0, 0, implicit $mode, implicit $exec
+    renamable $vgpr3_vgpr4 = COPY killed renamable $vgpr0_vgpr1
+    S_ENDPGM 0, implicit $vgpr3_vgpr4
----------------
Why does such a copy exist in the first place?
The register pair given for 64-bit Dst operand of COPY itself is unaligned. 
One situation I can imagine is when the Dst is the odd subpart of a higher tuple. 
But in that case, shouldn't that info be given in the instruction as an implicit operand?


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  https://reviews.llvm.org/D121491/new/

https://reviews.llvm.org/D121491