[PATCH] D121447: [RISCV] Add basic code modeling for fixed length vector reduction.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added a comment.

In D121447#3376510 <https://reviews.llvm.org/D121447#3376510>, @fakepaper56 wrote:

> I think  `getTypeLegalizationCost` is imprecise for RVV fixed length vector. Take `v4i8` as an example, `getTypeLegalizationCost` thinks `v4i8` should split to 4 `v1i8` since `v4i8` is not legal type. But `v4i8` is expanded to `extract_subvector` of a `nxv1i8`.

I think that's because you didn't pass -riscv-v-vector-bits-min in the test. Fixed vectors are scalarized without that. That also means the cost model needs to check ST->useRVVForFixedLengthVectors().


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