[PATCH] D121447: [RISCV] Add basic code modeling for fixed length vector reduction.

[Yeting Kuo via Phabricator via llvm-commits]

fakepaper56 added a comment.

I think  `getTypeLegalizationCost` is imprecise for RVV fixed length vector. Take `v4i8` as an example, `getTypeLegalizationCost` thinks `v4i8` should split to 4 `v1i8` since `v4i8` is not legal type. But `v4i8` is expanded to `extract_subvector` of a `nxv1i8`.


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  https://reviews.llvm.org/D121447/new/

https://reviews.llvm.org/D121447