[PATCH] D121297: [AArch64][SVE] Change the asserts in LowerToPredicatedOp to check for legal types
David Sherwood via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Fri Mar 11 01:58:19 PST 2022
This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGaeeb1199b4b4: [AArch64][SVE] Change the asserts in LowerToPredicatedOp to check for legal… (authored by david-arm).
Changed prior to commit:
https://reviews.llvm.org/D121297?vs=414302&id=414616#toc
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D121297/new/
https://reviews.llvm.org/D121297
Files:
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
llvm/test/CodeGen/AArch64/sve-fixed-length-no-vscale-range.ll
Index: llvm/test/CodeGen/AArch64/sve-fixed-length-no-vscale-range.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/AArch64/sve-fixed-length-no-vscale-range.ll
@@ -0,0 +1,32 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s | FileCheck %s
+
+target triple = "aarch64-unknown-linux-gnu"
+
+define <2 x i64> @mul_v2i64(<2 x i64> %op1, <2 x i64> %op2) #0 {
+; CHECK-LABEL: mul_v2i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
+; CHECK-NEXT: ptrue p0.d, vl2
+; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1
+; CHECK-NEXT: mul z0.d, p0/m, z0.d, z1.d
+; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
+; CHECK-NEXT: ret
+ %res = mul <2 x i64> %op1, %op2
+ ret <2 x i64> %res
+}
+
+define <4 x i32> @sdiv_v4i32(<4 x i32> %op1, <4 x i32> %op2) #0 {
+; CHECK-LABEL: sdiv_v4i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
+; CHECK-NEXT: ptrue p0.s, vl4
+; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1
+; CHECK-NEXT: sdiv z0.s, p0/m, z0.s, z1.s
+; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
+; CHECK-NEXT: ret
+ %res = sdiv <4 x i32> %op1, %op2
+ ret <4 x i32> %res
+}
+
+attributes #0 = { "target-features"="+sve" }
Index: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
===================================================================
--- llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -20031,8 +20031,7 @@
auto Pg = getPredicateForVector(DAG, DL, VT);
if (VT.isFixedLengthVector()) {
- assert(VT.getFixedSizeInBits() <= Subtarget->getMinSVEVectorSizeInBits() &&
- "Cannot use SVE to lower fixed length predicated op!");
+ assert(isTypeLegal(VT) && "Expected only legal fixed-width types");
EVT ContainerVT = getContainerForFixedLengthVector(DAG, VT);
// Create list of operands by converting existing ones to scalable types.
@@ -20050,9 +20049,8 @@
continue;
}
- assert(V.getValueType().getFixedSizeInBits() <=
- Subtarget->getMinSVEVectorSizeInBits() &&
- "Only fixed length vectors are supported!");
+ assert(isTypeLegal(V.getValueType()) &&
+ "Expected only legal fixed-width types");
Operands.push_back(convertToScalableVector(DAG, ContainerVT, V));
}
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