[PATCH] D121297: [AArch64][SVE] Change the asserts in LowerToPredicatedOp to check for legal types

[Paul Walker via Phabricator via llvm-commits]

paulwalker-arm accepted this revision.
paulwalker-arm added inline comments.
This revision is now accepted and ready to land.


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Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:19981
   if (VT.isFixedLengthVector()) {
-    assert(VT.getFixedSizeInBits() <= Subtarget->getMinSVEVectorSizeInBits() &&
-           "Cannot use SVE to lower fixed length predicated op!");
+    assert(DAG.getTargetLoweringInfo().isTypeLegal(VT) &&
+           "Expected only legal fixed-width types");
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This is a target lowering function so you should be able to call `isTypeLegal()` directly.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D121297/new/

https://reviews.llvm.org/D121297