[PATCH] D119834: [RISCV] Add fixed-length vector instrinsics for segment load

[Luke via Phabricator via llvm-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG0803dba7dd99: [RISCV] Add fixed-length vector instrinsics for segment load (authored by luke957).

Changed prior to commit:
  https://reviews.llvm.org/D119834?vs=411126&id=414288#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D119834/new/

https://reviews.llvm.org/D119834

Files:
  llvm/include/llvm/IR/IntrinsicsRISCV.td
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/test/CodeGen/RISCV/rvv/fixed-vector-segN-load.ll

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