[PATCH] D119834: [RISCV] Add fixed-length vector instrinsics for segment load

[Craig Topper via Phabricator via llvm-commits]

craig.topper accepted this revision.
craig.topper added a comment.
This revision is now accepted and ready to land.

LGTM to me other than those 2 comments to change 8 to 9.



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Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:4846
+    auto *Load = cast<MemIntrinsicSDNode>(Op);
+    SmallVector<EVT, 8> ContainerVTs(NF, ContainerVT);
+    ContainerVTs.push_back(MVT::Other);
----------------
Use 9 instead of 8. Since NF is <= 8 and you push one additional item for MVT::Other.


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Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:4853
+                                Load->getMemoryVT(), Load->getMemOperand());
+    SmallVector<SDValue, 8> Results;
+    for (unsigned int RetIdx = 0; RetIdx < NF; RetIdx++)
----------------
Use 9 instead of 8.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D119834/new/

https://reviews.llvm.org/D119834