[PATCH] D121320: X86ISelDAGToDAG: Transform TEST + MOV64ri to SHR + TEST

[Matthias Braun via Phabricator via llvm-commits]

MatzeB added inline comments.


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Comment at: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:5631
+          // If the mask covers the most significant bit, then we can replace
+          // TEST+AND with a SHR and check eflags.
+          if (LeadingZeros == 0) {
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craig.topper wrote:
> Are we emitting TEST+SHR rather than SHR by itself.
It seems we emit a `TEST` here but a separate transformation will identify the `TEST` as redundant and re-use the flags of the shift instruction.


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Comment at: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:5636
+            // If the mask covers the least signifcant bit, then we can replace
+            // TEST+AND with a SHL and check eflags.
+          } else if (TrailingZeros == 0) {
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craig.topper wrote:
> Same question.
as above.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D121320/new/

https://reviews.llvm.org/D121320