[PATCH] D121320: X86ISelDAGToDAG: Transform TEST + MOV64ri to SHR + TEST

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:5631
+          // If the mask covers the most significant bit, then we can replace
+          // TEST+AND with a SHR and check eflags.
+          if (LeadingZeros == 0) {
----------------
Are we emitting TEST+SHR rather than SHR by itself.


================
Comment at: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:5636
+            // If the mask covers the least signifcant bit, then we can replace
+            // TEST+AND with a SHL and check eflags.
+          } else if (TrailingZeros == 0) {
----------------
Same question.


================
Comment at: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:5669
+          MachineSDNode *Test;
+          if (SubRegIdx == 0) {
+            Test = CurDAG->getMachineNode(X86::TEST64rr, dl, MVT::i32, Shift,
----------------
Initialize `TestOpcode` to `X86::TEST64rr` instead of `DELETED_NODE`. Then this becomes

```
if (SubRegIdx != 0)
  Shift = CurDAG->getTargetExtractSubreg(SubRegIdx, dl, SubRegVT, Shift);
Test = CurDAG->getMachineNode(TestOpcode, dl, MVT::i32, Shift, Shift);
ReplaceNode(Node, Test)
```


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D121320/new/

https://reviews.llvm.org/D121320