[PATCH] D121152: [RISCV] Add more sign-extending ops to MIR sext.w pass.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVSExtWRemoval.cpp:176
+
+    // For these We just need to check if the 1st operand is sign extended.
+    case RISCV::BCLRI:
----------------
"For these, we"


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D121152/new/

https://reviews.llvm.org/D121152