[PATCH] D121152: [RISCV] Add more sign-extending ops to MIR sext.w pass.

[Mohammed Nurul Hoque via Phabricator via llvm-commits]

mohammed-nurulhoque created this revision.
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This patch adds single-bit and bit-counting ops to list of sign-extending ops.

A single-bit write propagates sign-extendedness if it's not in the sign-bits.

Bit extraction and bit counting always outputs a small number, so sign-extended.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D121152

Files:
  llvm/lib/Target/RISCV/RISCVSExtWRemoval.cpp
  llvm/test/CodeGen/RISCV/sextw-removal.ll

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