[llvm] 0b75b39 - [RISCV] Merge more rv32/rv64 vector intrinsic tests that contain the same content.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Fri Mar 4 16:35:25 PST 2022
Author: Craig Topper
Date: 2022-03-04T16:34:59-08:00
New Revision: 0b75b39a7038bbbeb8bf92ffba08e36f64782ca3
URL: https://github.com/llvm/llvm-project/commit/0b75b39a7038bbbeb8bf92ffba08e36f64782ca3
DIFF: https://github.com/llvm/llvm-project/commit/0b75b39a7038bbbeb8bf92ffba08e36f64782ca3.diff
LOG: [RISCV] Merge more rv32/rv64 vector intrinsic tests that contain the same content.
Use sed to convert iXLen to i32/i64 before running the test.
Added:
llvm/test/CodeGen/RISCV/rvv/vaadd.ll
llvm/test/CodeGen/RISCV/rvv/vaaddu.ll
llvm/test/CodeGen/RISCV/rvv/vadd.ll
llvm/test/CodeGen/RISCV/rvv/vasub.ll
llvm/test/CodeGen/RISCV/rvv/vasubu.ll
llvm/test/CodeGen/RISCV/rvv/vmerge.ll
llvm/test/CodeGen/RISCV/rvv/vmfeq.ll
llvm/test/CodeGen/RISCV/rvv/vmfge.ll
llvm/test/CodeGen/RISCV/rvv/vmfgt.ll
llvm/test/CodeGen/RISCV/rvv/vmfle.ll
llvm/test/CodeGen/RISCV/rvv/vmflt.ll
llvm/test/CodeGen/RISCV/rvv/vmfne.ll
llvm/test/CodeGen/RISCV/rvv/vmsbf.ll
llvm/test/CodeGen/RISCV/rvv/vmul.ll
llvm/test/CodeGen/RISCV/rvv/vmulh.ll
llvm/test/CodeGen/RISCV/rvv/vmulhsu.ll
llvm/test/CodeGen/RISCV/rvv/vmulhu.ll
llvm/test/CodeGen/RISCV/rvv/vrsub.ll
llvm/test/CodeGen/RISCV/rvv/vsub.ll
Modified:
Removed:
llvm/test/CodeGen/RISCV/rvv/vaadd-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vaadd-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vaaddu-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vaaddu-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vadd-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vadd-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vasub-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vasub-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vasubu-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vasubu-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vmerge-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vmerge-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vmfeq-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vmfeq-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vmfge-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vmfge-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vmfgt-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vmfgt-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vmfle-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vmfle-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vmflt-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vmflt-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vmfne-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vmfne-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vmsbf-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vmsbf-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vmul-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vmul-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vmulh-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vmulh-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vmulhsu-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vmulhsu-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vmulhu-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vmulhu-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vrsub-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vrsub-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vsub-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vsub-rv64.ll
################################################################################
diff --git a/llvm/test/CodeGen/RISCV/rvv/vaadd-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vaadd-rv64.ll
deleted file mode 100644
index 76d556d6be40b..0000000000000
--- a/llvm/test/CodeGen/RISCV/rvv/vaadd-rv64.ll
+++ /dev/null
@@ -1,2074 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs \
-; RUN: < %s | FileCheck %s
-declare <vscale x 1 x i8> @llvm.riscv.vaadd.nxv1i8.nxv1i8(
- <vscale x 1 x i8>,
- <vscale x 1 x i8>,
- <vscale x 1 x i8>,
- i64);
-
-define <vscale x 1 x i8> @intrinsic_vaadd_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vaadd_vv_nxv1i8_nxv1i8_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
-; CHECK-NEXT: vaadd.vv v8, v8, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i8> @llvm.riscv.vaadd.nxv1i8.nxv1i8(
- <vscale x 1 x i8> undef,
- <vscale x 1 x i8> %0,
- <vscale x 1 x i8> %1,
- i64 %2)
-
- ret <vscale x 1 x i8> %a
-}
-
-declare <vscale x 1 x i8> @llvm.riscv.vaadd.mask.nxv1i8.nxv1i8(
- <vscale x 1 x i8>,
- <vscale x 1 x i8>,
- <vscale x 1 x i8>,
- <vscale x 1 x i1>,
- i64,
- i64);
-
-define <vscale x 1 x i8> @intrinsic_vaadd_mask_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv1i8_nxv1i8_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
-; CHECK-NEXT: vaadd.vv v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i8> @llvm.riscv.vaadd.mask.nxv1i8.nxv1i8(
- <vscale x 1 x i8> %0,
- <vscale x 1 x i8> %1,
- <vscale x 1 x i8> %2,
- <vscale x 1 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 1 x i8> %a
-}
-
-declare <vscale x 2 x i8> @llvm.riscv.vaadd.nxv2i8.nxv2i8(
- <vscale x 2 x i8>,
- <vscale x 2 x i8>,
- <vscale x 2 x i8>,
- i64);
-
-define <vscale x 2 x i8> @intrinsic_vaadd_vv_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vaadd_vv_nxv2i8_nxv2i8_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
-; CHECK-NEXT: vaadd.vv v8, v8, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i8> @llvm.riscv.vaadd.nxv2i8.nxv2i8(
- <vscale x 2 x i8> undef,
- <vscale x 2 x i8> %0,
- <vscale x 2 x i8> %1,
- i64 %2)
-
- ret <vscale x 2 x i8> %a
-}
-
-declare <vscale x 2 x i8> @llvm.riscv.vaadd.mask.nxv2i8.nxv2i8(
- <vscale x 2 x i8>,
- <vscale x 2 x i8>,
- <vscale x 2 x i8>,
- <vscale x 2 x i1>,
- i64,
- i64);
-
-define <vscale x 2 x i8> @intrinsic_vaadd_mask_vv_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv2i8_nxv2i8_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
-; CHECK-NEXT: vaadd.vv v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i8> @llvm.riscv.vaadd.mask.nxv2i8.nxv2i8(
- <vscale x 2 x i8> %0,
- <vscale x 2 x i8> %1,
- <vscale x 2 x i8> %2,
- <vscale x 2 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 2 x i8> %a
-}
-
-declare <vscale x 4 x i8> @llvm.riscv.vaadd.nxv4i8.nxv4i8(
- <vscale x 4 x i8>,
- <vscale x 4 x i8>,
- <vscale x 4 x i8>,
- i64);
-
-define <vscale x 4 x i8> @intrinsic_vaadd_vv_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vaadd_vv_nxv4i8_nxv4i8_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
-; CHECK-NEXT: vaadd.vv v8, v8, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i8> @llvm.riscv.vaadd.nxv4i8.nxv4i8(
- <vscale x 4 x i8> undef,
- <vscale x 4 x i8> %0,
- <vscale x 4 x i8> %1,
- i64 %2)
-
- ret <vscale x 4 x i8> %a
-}
-
-declare <vscale x 4 x i8> @llvm.riscv.vaadd.mask.nxv4i8.nxv4i8(
- <vscale x 4 x i8>,
- <vscale x 4 x i8>,
- <vscale x 4 x i8>,
- <vscale x 4 x i1>,
- i64,
- i64);
-
-define <vscale x 4 x i8> @intrinsic_vaadd_mask_vv_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv4i8_nxv4i8_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
-; CHECK-NEXT: vaadd.vv v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i8> @llvm.riscv.vaadd.mask.nxv4i8.nxv4i8(
- <vscale x 4 x i8> %0,
- <vscale x 4 x i8> %1,
- <vscale x 4 x i8> %2,
- <vscale x 4 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 4 x i8> %a
-}
-
-declare <vscale x 8 x i8> @llvm.riscv.vaadd.nxv8i8.nxv8i8(
- <vscale x 8 x i8>,
- <vscale x 8 x i8>,
- <vscale x 8 x i8>,
- i64);
-
-define <vscale x 8 x i8> @intrinsic_vaadd_vv_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vaadd_vv_nxv8i8_nxv8i8_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
-; CHECK-NEXT: vaadd.vv v8, v8, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i8> @llvm.riscv.vaadd.nxv8i8.nxv8i8(
- <vscale x 8 x i8> undef,
- <vscale x 8 x i8> %0,
- <vscale x 8 x i8> %1,
- i64 %2)
-
- ret <vscale x 8 x i8> %a
-}
-
-declare <vscale x 8 x i8> @llvm.riscv.vaadd.mask.nxv8i8.nxv8i8(
- <vscale x 8 x i8>,
- <vscale x 8 x i8>,
- <vscale x 8 x i8>,
- <vscale x 8 x i1>,
- i64,
- i64);
-
-define <vscale x 8 x i8> @intrinsic_vaadd_mask_vv_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv8i8_nxv8i8_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
-; CHECK-NEXT: vaadd.vv v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i8> @llvm.riscv.vaadd.mask.nxv8i8.nxv8i8(
- <vscale x 8 x i8> %0,
- <vscale x 8 x i8> %1,
- <vscale x 8 x i8> %2,
- <vscale x 8 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 8 x i8> %a
-}
-
-declare <vscale x 16 x i8> @llvm.riscv.vaadd.nxv16i8.nxv16i8(
- <vscale x 16 x i8>,
- <vscale x 16 x i8>,
- <vscale x 16 x i8>,
- i64);
-
-define <vscale x 16 x i8> @intrinsic_vaadd_vv_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vaadd_vv_nxv16i8_nxv16i8_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
-; CHECK-NEXT: vaadd.vv v8, v8, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i8> @llvm.riscv.vaadd.nxv16i8.nxv16i8(
- <vscale x 16 x i8> undef,
- <vscale x 16 x i8> %0,
- <vscale x 16 x i8> %1,
- i64 %2)
-
- ret <vscale x 16 x i8> %a
-}
-
-declare <vscale x 16 x i8> @llvm.riscv.vaadd.mask.nxv16i8.nxv16i8(
- <vscale x 16 x i8>,
- <vscale x 16 x i8>,
- <vscale x 16 x i8>,
- <vscale x 16 x i1>,
- i64,
- i64);
-
-define <vscale x 16 x i8> @intrinsic_vaadd_mask_vv_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv16i8_nxv16i8_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
-; CHECK-NEXT: vaadd.vv v8, v10, v12, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i8> @llvm.riscv.vaadd.mask.nxv16i8.nxv16i8(
- <vscale x 16 x i8> %0,
- <vscale x 16 x i8> %1,
- <vscale x 16 x i8> %2,
- <vscale x 16 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 16 x i8> %a
-}
-
-declare <vscale x 32 x i8> @llvm.riscv.vaadd.nxv32i8.nxv32i8(
- <vscale x 32 x i8>,
- <vscale x 32 x i8>,
- <vscale x 32 x i8>,
- i64);
-
-define <vscale x 32 x i8> @intrinsic_vaadd_vv_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vaadd_vv_nxv32i8_nxv32i8_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
-; CHECK-NEXT: vaadd.vv v8, v8, v12
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 32 x i8> @llvm.riscv.vaadd.nxv32i8.nxv32i8(
- <vscale x 32 x i8> undef,
- <vscale x 32 x i8> %0,
- <vscale x 32 x i8> %1,
- i64 %2)
-
- ret <vscale x 32 x i8> %a
-}
-
-declare <vscale x 32 x i8> @llvm.riscv.vaadd.mask.nxv32i8.nxv32i8(
- <vscale x 32 x i8>,
- <vscale x 32 x i8>,
- <vscale x 32 x i8>,
- <vscale x 32 x i1>,
- i64,
- i64);
-
-define <vscale x 32 x i8> @intrinsic_vaadd_mask_vv_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv32i8_nxv32i8_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
-; CHECK-NEXT: vaadd.vv v8, v12, v16, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 32 x i8> @llvm.riscv.vaadd.mask.nxv32i8.nxv32i8(
- <vscale x 32 x i8> %0,
- <vscale x 32 x i8> %1,
- <vscale x 32 x i8> %2,
- <vscale x 32 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 32 x i8> %a
-}
-
-declare <vscale x 64 x i8> @llvm.riscv.vaadd.nxv64i8.nxv64i8(
- <vscale x 64 x i8>,
- <vscale x 64 x i8>,
- <vscale x 64 x i8>,
- i64);
-
-define <vscale x 64 x i8> @intrinsic_vaadd_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vaadd_vv_nxv64i8_nxv64i8_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, mu
-; CHECK-NEXT: vaadd.vv v8, v8, v16
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 64 x i8> @llvm.riscv.vaadd.nxv64i8.nxv64i8(
- <vscale x 64 x i8> undef,
- <vscale x 64 x i8> %0,
- <vscale x 64 x i8> %1,
- i64 %2)
-
- ret <vscale x 64 x i8> %a
-}
-
-declare <vscale x 64 x i8> @llvm.riscv.vaadd.mask.nxv64i8.nxv64i8(
- <vscale x 64 x i8>,
- <vscale x 64 x i8>,
- <vscale x 64 x i8>,
- <vscale x 64 x i1>,
- i64,
- i64);
-
-define <vscale x 64 x i8> @intrinsic_vaadd_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv64i8_nxv64i8_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vl8r.v v24, (a0)
-; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu
-; CHECK-NEXT: vaadd.vv v8, v16, v24, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 64 x i8> @llvm.riscv.vaadd.mask.nxv64i8.nxv64i8(
- <vscale x 64 x i8> %0,
- <vscale x 64 x i8> %1,
- <vscale x 64 x i8> %2,
- <vscale x 64 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 64 x i8> %a
-}
-
-declare <vscale x 1 x i16> @llvm.riscv.vaadd.nxv1i16.nxv1i16(
- <vscale x 1 x i16>,
- <vscale x 1 x i16>,
- <vscale x 1 x i16>,
- i64);
-
-define <vscale x 1 x i16> @intrinsic_vaadd_vv_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vaadd_vv_nxv1i16_nxv1i16_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vaadd.vv v8, v8, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i16> @llvm.riscv.vaadd.nxv1i16.nxv1i16(
- <vscale x 1 x i16> undef,
- <vscale x 1 x i16> %0,
- <vscale x 1 x i16> %1,
- i64 %2)
-
- ret <vscale x 1 x i16> %a
-}
-
-declare <vscale x 1 x i16> @llvm.riscv.vaadd.mask.nxv1i16.nxv1i16(
- <vscale x 1 x i16>,
- <vscale x 1 x i16>,
- <vscale x 1 x i16>,
- <vscale x 1 x i1>,
- i64,
- i64);
-
-define <vscale x 1 x i16> @intrinsic_vaadd_mask_vv_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv1i16_nxv1i16_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vaadd.vv v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i16> @llvm.riscv.vaadd.mask.nxv1i16.nxv1i16(
- <vscale x 1 x i16> %0,
- <vscale x 1 x i16> %1,
- <vscale x 1 x i16> %2,
- <vscale x 1 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 1 x i16> %a
-}
-
-declare <vscale x 2 x i16> @llvm.riscv.vaadd.nxv2i16.nxv2i16(
- <vscale x 2 x i16>,
- <vscale x 2 x i16>,
- <vscale x 2 x i16>,
- i64);
-
-define <vscale x 2 x i16> @intrinsic_vaadd_vv_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vaadd_vv_nxv2i16_nxv2i16_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vaadd.vv v8, v8, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i16> @llvm.riscv.vaadd.nxv2i16.nxv2i16(
- <vscale x 2 x i16> undef,
- <vscale x 2 x i16> %0,
- <vscale x 2 x i16> %1,
- i64 %2)
-
- ret <vscale x 2 x i16> %a
-}
-
-declare <vscale x 2 x i16> @llvm.riscv.vaadd.mask.nxv2i16.nxv2i16(
- <vscale x 2 x i16>,
- <vscale x 2 x i16>,
- <vscale x 2 x i16>,
- <vscale x 2 x i1>,
- i64,
- i64);
-
-define <vscale x 2 x i16> @intrinsic_vaadd_mask_vv_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv2i16_nxv2i16_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vaadd.vv v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i16> @llvm.riscv.vaadd.mask.nxv2i16.nxv2i16(
- <vscale x 2 x i16> %0,
- <vscale x 2 x i16> %1,
- <vscale x 2 x i16> %2,
- <vscale x 2 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 2 x i16> %a
-}
-
-declare <vscale x 4 x i16> @llvm.riscv.vaadd.nxv4i16.nxv4i16(
- <vscale x 4 x i16>,
- <vscale x 4 x i16>,
- <vscale x 4 x i16>,
- i64);
-
-define <vscale x 4 x i16> @intrinsic_vaadd_vv_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vaadd_vv_nxv4i16_nxv4i16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vaadd.vv v8, v8, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i16> @llvm.riscv.vaadd.nxv4i16.nxv4i16(
- <vscale x 4 x i16> undef,
- <vscale x 4 x i16> %0,
- <vscale x 4 x i16> %1,
- i64 %2)
-
- ret <vscale x 4 x i16> %a
-}
-
-declare <vscale x 4 x i16> @llvm.riscv.vaadd.mask.nxv4i16.nxv4i16(
- <vscale x 4 x i16>,
- <vscale x 4 x i16>,
- <vscale x 4 x i16>,
- <vscale x 4 x i1>,
- i64,
- i64);
-
-define <vscale x 4 x i16> @intrinsic_vaadd_mask_vv_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv4i16_nxv4i16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vaadd.vv v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i16> @llvm.riscv.vaadd.mask.nxv4i16.nxv4i16(
- <vscale x 4 x i16> %0,
- <vscale x 4 x i16> %1,
- <vscale x 4 x i16> %2,
- <vscale x 4 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 4 x i16> %a
-}
-
-declare <vscale x 8 x i16> @llvm.riscv.vaadd.nxv8i16.nxv8i16(
- <vscale x 8 x i16>,
- <vscale x 8 x i16>,
- <vscale x 8 x i16>,
- i64);
-
-define <vscale x 8 x i16> @intrinsic_vaadd_vv_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vaadd_vv_nxv8i16_nxv8i16_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vaadd.vv v8, v8, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i16> @llvm.riscv.vaadd.nxv8i16.nxv8i16(
- <vscale x 8 x i16> undef,
- <vscale x 8 x i16> %0,
- <vscale x 8 x i16> %1,
- i64 %2)
-
- ret <vscale x 8 x i16> %a
-}
-
-declare <vscale x 8 x i16> @llvm.riscv.vaadd.mask.nxv8i16.nxv8i16(
- <vscale x 8 x i16>,
- <vscale x 8 x i16>,
- <vscale x 8 x i16>,
- <vscale x 8 x i1>,
- i64,
- i64);
-
-define <vscale x 8 x i16> @intrinsic_vaadd_mask_vv_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv8i16_nxv8i16_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vaadd.vv v8, v10, v12, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i16> @llvm.riscv.vaadd.mask.nxv8i16.nxv8i16(
- <vscale x 8 x i16> %0,
- <vscale x 8 x i16> %1,
- <vscale x 8 x i16> %2,
- <vscale x 8 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 8 x i16> %a
-}
-
-declare <vscale x 16 x i16> @llvm.riscv.vaadd.nxv16i16.nxv16i16(
- <vscale x 16 x i16>,
- <vscale x 16 x i16>,
- <vscale x 16 x i16>,
- i64);
-
-define <vscale x 16 x i16> @intrinsic_vaadd_vv_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vaadd_vv_nxv16i16_nxv16i16_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
-; CHECK-NEXT: vaadd.vv v8, v8, v12
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i16> @llvm.riscv.vaadd.nxv16i16.nxv16i16(
- <vscale x 16 x i16> undef,
- <vscale x 16 x i16> %0,
- <vscale x 16 x i16> %1,
- i64 %2)
-
- ret <vscale x 16 x i16> %a
-}
-
-declare <vscale x 16 x i16> @llvm.riscv.vaadd.mask.nxv16i16.nxv16i16(
- <vscale x 16 x i16>,
- <vscale x 16 x i16>,
- <vscale x 16 x i16>,
- <vscale x 16 x i1>,
- i64,
- i64);
-
-define <vscale x 16 x i16> @intrinsic_vaadd_mask_vv_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv16i16_nxv16i16_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
-; CHECK-NEXT: vaadd.vv v8, v12, v16, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i16> @llvm.riscv.vaadd.mask.nxv16i16.nxv16i16(
- <vscale x 16 x i16> %0,
- <vscale x 16 x i16> %1,
- <vscale x 16 x i16> %2,
- <vscale x 16 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 16 x i16> %a
-}
-
-declare <vscale x 32 x i16> @llvm.riscv.vaadd.nxv32i16.nxv32i16(
- <vscale x 32 x i16>,
- <vscale x 32 x i16>,
- <vscale x 32 x i16>,
- i64);
-
-define <vscale x 32 x i16> @intrinsic_vaadd_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vaadd_vv_nxv32i16_nxv32i16_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, mu
-; CHECK-NEXT: vaadd.vv v8, v8, v16
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 32 x i16> @llvm.riscv.vaadd.nxv32i16.nxv32i16(
- <vscale x 32 x i16> undef,
- <vscale x 32 x i16> %0,
- <vscale x 32 x i16> %1,
- i64 %2)
-
- ret <vscale x 32 x i16> %a
-}
-
-declare <vscale x 32 x i16> @llvm.riscv.vaadd.mask.nxv32i16.nxv32i16(
- <vscale x 32 x i16>,
- <vscale x 32 x i16>,
- <vscale x 32 x i16>,
- <vscale x 32 x i1>,
- i64,
- i64);
-
-define <vscale x 32 x i16> @intrinsic_vaadd_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv32i16_nxv32i16_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vl8re16.v v24, (a0)
-; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu
-; CHECK-NEXT: vaadd.vv v8, v16, v24, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 32 x i16> @llvm.riscv.vaadd.mask.nxv32i16.nxv32i16(
- <vscale x 32 x i16> %0,
- <vscale x 32 x i16> %1,
- <vscale x 32 x i16> %2,
- <vscale x 32 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 32 x i16> %a
-}
-
-declare <vscale x 1 x i32> @llvm.riscv.vaadd.nxv1i32.nxv1i32(
- <vscale x 1 x i32>,
- <vscale x 1 x i32>,
- <vscale x 1 x i32>,
- i64);
-
-define <vscale x 1 x i32> @intrinsic_vaadd_vv_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vaadd_vv_nxv1i32_nxv1i32_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vaadd.vv v8, v8, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i32> @llvm.riscv.vaadd.nxv1i32.nxv1i32(
- <vscale x 1 x i32> undef,
- <vscale x 1 x i32> %0,
- <vscale x 1 x i32> %1,
- i64 %2)
-
- ret <vscale x 1 x i32> %a
-}
-
-declare <vscale x 1 x i32> @llvm.riscv.vaadd.mask.nxv1i32.nxv1i32(
- <vscale x 1 x i32>,
- <vscale x 1 x i32>,
- <vscale x 1 x i32>,
- <vscale x 1 x i1>,
- i64,
- i64);
-
-define <vscale x 1 x i32> @intrinsic_vaadd_mask_vv_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv1i32_nxv1i32_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vaadd.vv v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i32> @llvm.riscv.vaadd.mask.nxv1i32.nxv1i32(
- <vscale x 1 x i32> %0,
- <vscale x 1 x i32> %1,
- <vscale x 1 x i32> %2,
- <vscale x 1 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 1 x i32> %a
-}
-
-declare <vscale x 2 x i32> @llvm.riscv.vaadd.nxv2i32.nxv2i32(
- <vscale x 2 x i32>,
- <vscale x 2 x i32>,
- <vscale x 2 x i32>,
- i64);
-
-define <vscale x 2 x i32> @intrinsic_vaadd_vv_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vaadd_vv_nxv2i32_nxv2i32_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vaadd.vv v8, v8, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i32> @llvm.riscv.vaadd.nxv2i32.nxv2i32(
- <vscale x 2 x i32> undef,
- <vscale x 2 x i32> %0,
- <vscale x 2 x i32> %1,
- i64 %2)
-
- ret <vscale x 2 x i32> %a
-}
-
-declare <vscale x 2 x i32> @llvm.riscv.vaadd.mask.nxv2i32.nxv2i32(
- <vscale x 2 x i32>,
- <vscale x 2 x i32>,
- <vscale x 2 x i32>,
- <vscale x 2 x i1>,
- i64,
- i64);
-
-define <vscale x 2 x i32> @intrinsic_vaadd_mask_vv_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv2i32_nxv2i32_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vaadd.vv v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i32> @llvm.riscv.vaadd.mask.nxv2i32.nxv2i32(
- <vscale x 2 x i32> %0,
- <vscale x 2 x i32> %1,
- <vscale x 2 x i32> %2,
- <vscale x 2 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 2 x i32> %a
-}
-
-declare <vscale x 4 x i32> @llvm.riscv.vaadd.nxv4i32.nxv4i32(
- <vscale x 4 x i32>,
- <vscale x 4 x i32>,
- <vscale x 4 x i32>,
- i64);
-
-define <vscale x 4 x i32> @intrinsic_vaadd_vv_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vaadd_vv_nxv4i32_nxv4i32_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vaadd.vv v8, v8, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i32> @llvm.riscv.vaadd.nxv4i32.nxv4i32(
- <vscale x 4 x i32> undef,
- <vscale x 4 x i32> %0,
- <vscale x 4 x i32> %1,
- i64 %2)
-
- ret <vscale x 4 x i32> %a
-}
-
-declare <vscale x 4 x i32> @llvm.riscv.vaadd.mask.nxv4i32.nxv4i32(
- <vscale x 4 x i32>,
- <vscale x 4 x i32>,
- <vscale x 4 x i32>,
- <vscale x 4 x i1>,
- i64,
- i64);
-
-define <vscale x 4 x i32> @intrinsic_vaadd_mask_vv_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv4i32_nxv4i32_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vaadd.vv v8, v10, v12, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i32> @llvm.riscv.vaadd.mask.nxv4i32.nxv4i32(
- <vscale x 4 x i32> %0,
- <vscale x 4 x i32> %1,
- <vscale x 4 x i32> %2,
- <vscale x 4 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 4 x i32> %a
-}
-
-declare <vscale x 8 x i32> @llvm.riscv.vaadd.nxv8i32.nxv8i32(
- <vscale x 8 x i32>,
- <vscale x 8 x i32>,
- <vscale x 8 x i32>,
- i64);
-
-define <vscale x 8 x i32> @intrinsic_vaadd_vv_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vaadd_vv_nxv8i32_nxv8i32_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
-; CHECK-NEXT: vaadd.vv v8, v8, v12
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i32> @llvm.riscv.vaadd.nxv8i32.nxv8i32(
- <vscale x 8 x i32> undef,
- <vscale x 8 x i32> %0,
- <vscale x 8 x i32> %1,
- i64 %2)
-
- ret <vscale x 8 x i32> %a
-}
-
-declare <vscale x 8 x i32> @llvm.riscv.vaadd.mask.nxv8i32.nxv8i32(
- <vscale x 8 x i32>,
- <vscale x 8 x i32>,
- <vscale x 8 x i32>,
- <vscale x 8 x i1>,
- i64,
- i64);
-
-define <vscale x 8 x i32> @intrinsic_vaadd_mask_vv_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv8i32_nxv8i32_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
-; CHECK-NEXT: vaadd.vv v8, v12, v16, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i32> @llvm.riscv.vaadd.mask.nxv8i32.nxv8i32(
- <vscale x 8 x i32> %0,
- <vscale x 8 x i32> %1,
- <vscale x 8 x i32> %2,
- <vscale x 8 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 8 x i32> %a
-}
-
-declare <vscale x 16 x i32> @llvm.riscv.vaadd.nxv16i32.nxv16i32(
- <vscale x 16 x i32>,
- <vscale x 16 x i32>,
- <vscale x 16 x i32>,
- i64);
-
-define <vscale x 16 x i32> @intrinsic_vaadd_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vaadd_vv_nxv16i32_nxv16i32_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu
-; CHECK-NEXT: vaadd.vv v8, v8, v16
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i32> @llvm.riscv.vaadd.nxv16i32.nxv16i32(
- <vscale x 16 x i32> undef,
- <vscale x 16 x i32> %0,
- <vscale x 16 x i32> %1,
- i64 %2)
-
- ret <vscale x 16 x i32> %a
-}
-
-declare <vscale x 16 x i32> @llvm.riscv.vaadd.mask.nxv16i32.nxv16i32(
- <vscale x 16 x i32>,
- <vscale x 16 x i32>,
- <vscale x 16 x i32>,
- <vscale x 16 x i1>,
- i64,
- i64);
-
-define <vscale x 16 x i32> @intrinsic_vaadd_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv16i32_nxv16i32_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vl8re32.v v24, (a0)
-; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu
-; CHECK-NEXT: vaadd.vv v8, v16, v24, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i32> @llvm.riscv.vaadd.mask.nxv16i32.nxv16i32(
- <vscale x 16 x i32> %0,
- <vscale x 16 x i32> %1,
- <vscale x 16 x i32> %2,
- <vscale x 16 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 16 x i32> %a
-}
-
-declare <vscale x 1 x i64> @llvm.riscv.vaadd.nxv1i64.nxv1i64(
- <vscale x 1 x i64>,
- <vscale x 1 x i64>,
- <vscale x 1 x i64>,
- i64);
-
-define <vscale x 1 x i64> @intrinsic_vaadd_vv_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vaadd_vv_nxv1i64_nxv1i64_nxv1i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
-; CHECK-NEXT: vaadd.vv v8, v8, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i64> @llvm.riscv.vaadd.nxv1i64.nxv1i64(
- <vscale x 1 x i64> undef,
- <vscale x 1 x i64> %0,
- <vscale x 1 x i64> %1,
- i64 %2)
-
- ret <vscale x 1 x i64> %a
-}
-
-declare <vscale x 1 x i64> @llvm.riscv.vaadd.mask.nxv1i64.nxv1i64(
- <vscale x 1 x i64>,
- <vscale x 1 x i64>,
- <vscale x 1 x i64>,
- <vscale x 1 x i1>,
- i64,
- i64);
-
-define <vscale x 1 x i64> @intrinsic_vaadd_mask_vv_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv1i64_nxv1i64_nxv1i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
-; CHECK-NEXT: vaadd.vv v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i64> @llvm.riscv.vaadd.mask.nxv1i64.nxv1i64(
- <vscale x 1 x i64> %0,
- <vscale x 1 x i64> %1,
- <vscale x 1 x i64> %2,
- <vscale x 1 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 1 x i64> %a
-}
-
-declare <vscale x 2 x i64> @llvm.riscv.vaadd.nxv2i64.nxv2i64(
- <vscale x 2 x i64>,
- <vscale x 2 x i64>,
- <vscale x 2 x i64>,
- i64);
-
-define <vscale x 2 x i64> @intrinsic_vaadd_vv_nxv2i64_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vaadd_vv_nxv2i64_nxv2i64_nxv2i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
-; CHECK-NEXT: vaadd.vv v8, v8, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i64> @llvm.riscv.vaadd.nxv2i64.nxv2i64(
- <vscale x 2 x i64> undef,
- <vscale x 2 x i64> %0,
- <vscale x 2 x i64> %1,
- i64 %2)
-
- ret <vscale x 2 x i64> %a
-}
-
-declare <vscale x 2 x i64> @llvm.riscv.vaadd.mask.nxv2i64.nxv2i64(
- <vscale x 2 x i64>,
- <vscale x 2 x i64>,
- <vscale x 2 x i64>,
- <vscale x 2 x i1>,
- i64,
- i64);
-
-define <vscale x 2 x i64> @intrinsic_vaadd_mask_vv_nxv2i64_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv2i64_nxv2i64_nxv2i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
-; CHECK-NEXT: vaadd.vv v8, v10, v12, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i64> @llvm.riscv.vaadd.mask.nxv2i64.nxv2i64(
- <vscale x 2 x i64> %0,
- <vscale x 2 x i64> %1,
- <vscale x 2 x i64> %2,
- <vscale x 2 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 2 x i64> %a
-}
-
-declare <vscale x 4 x i64> @llvm.riscv.vaadd.nxv4i64.nxv4i64(
- <vscale x 4 x i64>,
- <vscale x 4 x i64>,
- <vscale x 4 x i64>,
- i64);
-
-define <vscale x 4 x i64> @intrinsic_vaadd_vv_nxv4i64_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vaadd_vv_nxv4i64_nxv4i64_nxv4i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
-; CHECK-NEXT: vaadd.vv v8, v8, v12
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i64> @llvm.riscv.vaadd.nxv4i64.nxv4i64(
- <vscale x 4 x i64> undef,
- <vscale x 4 x i64> %0,
- <vscale x 4 x i64> %1,
- i64 %2)
-
- ret <vscale x 4 x i64> %a
-}
-
-declare <vscale x 4 x i64> @llvm.riscv.vaadd.mask.nxv4i64.nxv4i64(
- <vscale x 4 x i64>,
- <vscale x 4 x i64>,
- <vscale x 4 x i64>,
- <vscale x 4 x i1>,
- i64,
- i64);
-
-define <vscale x 4 x i64> @intrinsic_vaadd_mask_vv_nxv4i64_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv4i64_nxv4i64_nxv4i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
-; CHECK-NEXT: vaadd.vv v8, v12, v16, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i64> @llvm.riscv.vaadd.mask.nxv4i64.nxv4i64(
- <vscale x 4 x i64> %0,
- <vscale x 4 x i64> %1,
- <vscale x 4 x i64> %2,
- <vscale x 4 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 4 x i64> %a
-}
-
-declare <vscale x 8 x i64> @llvm.riscv.vaadd.nxv8i64.nxv8i64(
- <vscale x 8 x i64>,
- <vscale x 8 x i64>,
- <vscale x 8 x i64>,
- i64);
-
-define <vscale x 8 x i64> @intrinsic_vaadd_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vaadd_vv_nxv8i64_nxv8i64_nxv8i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu
-; CHECK-NEXT: vaadd.vv v8, v8, v16
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i64> @llvm.riscv.vaadd.nxv8i64.nxv8i64(
- <vscale x 8 x i64> undef,
- <vscale x 8 x i64> %0,
- <vscale x 8 x i64> %1,
- i64 %2)
-
- ret <vscale x 8 x i64> %a
-}
-
-declare <vscale x 8 x i64> @llvm.riscv.vaadd.mask.nxv8i64.nxv8i64(
- <vscale x 8 x i64>,
- <vscale x 8 x i64>,
- <vscale x 8 x i64>,
- <vscale x 8 x i1>,
- i64,
- i64);
-
-define <vscale x 8 x i64> @intrinsic_vaadd_mask_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv8i64_nxv8i64_nxv8i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vl8re64.v v24, (a0)
-; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu
-; CHECK-NEXT: vaadd.vv v8, v16, v24, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i64> @llvm.riscv.vaadd.mask.nxv8i64.nxv8i64(
- <vscale x 8 x i64> %0,
- <vscale x 8 x i64> %1,
- <vscale x 8 x i64> %2,
- <vscale x 8 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 8 x i64> %a
-}
-
-declare <vscale x 1 x i8> @llvm.riscv.vaadd.nxv1i8.i8(
- <vscale x 1 x i8>,
- <vscale x 1 x i8>,
- i8,
- i64);
-
-define <vscale x 1 x i8> @intrinsic_vaadd_vx_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, i8 %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vaadd_vx_nxv1i8_nxv1i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
-; CHECK-NEXT: vaadd.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i8> @llvm.riscv.vaadd.nxv1i8.i8(
- <vscale x 1 x i8> undef,
- <vscale x 1 x i8> %0,
- i8 %1,
- i64 %2)
-
- ret <vscale x 1 x i8> %a
-}
-
-declare <vscale x 1 x i8> @llvm.riscv.vaadd.mask.nxv1i8.i8(
- <vscale x 1 x i8>,
- <vscale x 1 x i8>,
- i8,
- <vscale x 1 x i1>,
- i64,
- i64);
-
-define <vscale x 1 x i8> @intrinsic_vaadd_mask_vx_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vaadd_mask_vx_nxv1i8_nxv1i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
-; CHECK-NEXT: vaadd.vx v8, v9, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i8> @llvm.riscv.vaadd.mask.nxv1i8.i8(
- <vscale x 1 x i8> %0,
- <vscale x 1 x i8> %1,
- i8 %2,
- <vscale x 1 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 1 x i8> %a
-}
-
-declare <vscale x 2 x i8> @llvm.riscv.vaadd.nxv2i8.i8(
- <vscale x 2 x i8>,
- <vscale x 2 x i8>,
- i8,
- i64);
-
-define <vscale x 2 x i8> @intrinsic_vaadd_vx_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, i8 %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vaadd_vx_nxv2i8_nxv2i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
-; CHECK-NEXT: vaadd.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i8> @llvm.riscv.vaadd.nxv2i8.i8(
- <vscale x 2 x i8> undef,
- <vscale x 2 x i8> %0,
- i8 %1,
- i64 %2)
-
- ret <vscale x 2 x i8> %a
-}
-
-declare <vscale x 2 x i8> @llvm.riscv.vaadd.mask.nxv2i8.i8(
- <vscale x 2 x i8>,
- <vscale x 2 x i8>,
- i8,
- <vscale x 2 x i1>,
- i64,
- i64);
-
-define <vscale x 2 x i8> @intrinsic_vaadd_mask_vx_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vaadd_mask_vx_nxv2i8_nxv2i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
-; CHECK-NEXT: vaadd.vx v8, v9, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i8> @llvm.riscv.vaadd.mask.nxv2i8.i8(
- <vscale x 2 x i8> %0,
- <vscale x 2 x i8> %1,
- i8 %2,
- <vscale x 2 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 2 x i8> %a
-}
-
-declare <vscale x 4 x i8> @llvm.riscv.vaadd.nxv4i8.i8(
- <vscale x 4 x i8>,
- <vscale x 4 x i8>,
- i8,
- i64);
-
-define <vscale x 4 x i8> @intrinsic_vaadd_vx_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, i8 %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vaadd_vx_nxv4i8_nxv4i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
-; CHECK-NEXT: vaadd.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i8> @llvm.riscv.vaadd.nxv4i8.i8(
- <vscale x 4 x i8> undef,
- <vscale x 4 x i8> %0,
- i8 %1,
- i64 %2)
-
- ret <vscale x 4 x i8> %a
-}
-
-declare <vscale x 4 x i8> @llvm.riscv.vaadd.mask.nxv4i8.i8(
- <vscale x 4 x i8>,
- <vscale x 4 x i8>,
- i8,
- <vscale x 4 x i1>,
- i64,
- i64);
-
-define <vscale x 4 x i8> @intrinsic_vaadd_mask_vx_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vaadd_mask_vx_nxv4i8_nxv4i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
-; CHECK-NEXT: vaadd.vx v8, v9, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i8> @llvm.riscv.vaadd.mask.nxv4i8.i8(
- <vscale x 4 x i8> %0,
- <vscale x 4 x i8> %1,
- i8 %2,
- <vscale x 4 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 4 x i8> %a
-}
-
-declare <vscale x 8 x i8> @llvm.riscv.vaadd.nxv8i8.i8(
- <vscale x 8 x i8>,
- <vscale x 8 x i8>,
- i8,
- i64);
-
-define <vscale x 8 x i8> @intrinsic_vaadd_vx_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, i8 %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vaadd_vx_nxv8i8_nxv8i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
-; CHECK-NEXT: vaadd.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i8> @llvm.riscv.vaadd.nxv8i8.i8(
- <vscale x 8 x i8> undef,
- <vscale x 8 x i8> %0,
- i8 %1,
- i64 %2)
-
- ret <vscale x 8 x i8> %a
-}
-
-declare <vscale x 8 x i8> @llvm.riscv.vaadd.mask.nxv8i8.i8(
- <vscale x 8 x i8>,
- <vscale x 8 x i8>,
- i8,
- <vscale x 8 x i1>,
- i64,
- i64);
-
-define <vscale x 8 x i8> @intrinsic_vaadd_mask_vx_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vaadd_mask_vx_nxv8i8_nxv8i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
-; CHECK-NEXT: vaadd.vx v8, v9, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i8> @llvm.riscv.vaadd.mask.nxv8i8.i8(
- <vscale x 8 x i8> %0,
- <vscale x 8 x i8> %1,
- i8 %2,
- <vscale x 8 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 8 x i8> %a
-}
-
-declare <vscale x 16 x i8> @llvm.riscv.vaadd.nxv16i8.i8(
- <vscale x 16 x i8>,
- <vscale x 16 x i8>,
- i8,
- i64);
-
-define <vscale x 16 x i8> @intrinsic_vaadd_vx_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, i8 %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vaadd_vx_nxv16i8_nxv16i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
-; CHECK-NEXT: vaadd.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i8> @llvm.riscv.vaadd.nxv16i8.i8(
- <vscale x 16 x i8> undef,
- <vscale x 16 x i8> %0,
- i8 %1,
- i64 %2)
-
- ret <vscale x 16 x i8> %a
-}
-
-declare <vscale x 16 x i8> @llvm.riscv.vaadd.mask.nxv16i8.i8(
- <vscale x 16 x i8>,
- <vscale x 16 x i8>,
- i8,
- <vscale x 16 x i1>,
- i64,
- i64);
-
-define <vscale x 16 x i8> @intrinsic_vaadd_mask_vx_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vaadd_mask_vx_nxv16i8_nxv16i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
-; CHECK-NEXT: vaadd.vx v8, v10, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i8> @llvm.riscv.vaadd.mask.nxv16i8.i8(
- <vscale x 16 x i8> %0,
- <vscale x 16 x i8> %1,
- i8 %2,
- <vscale x 16 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 16 x i8> %a
-}
-
-declare <vscale x 32 x i8> @llvm.riscv.vaadd.nxv32i8.i8(
- <vscale x 32 x i8>,
- <vscale x 32 x i8>,
- i8,
- i64);
-
-define <vscale x 32 x i8> @intrinsic_vaadd_vx_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, i8 %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vaadd_vx_nxv32i8_nxv32i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
-; CHECK-NEXT: vaadd.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 32 x i8> @llvm.riscv.vaadd.nxv32i8.i8(
- <vscale x 32 x i8> undef,
- <vscale x 32 x i8> %0,
- i8 %1,
- i64 %2)
-
- ret <vscale x 32 x i8> %a
-}
-
-declare <vscale x 32 x i8> @llvm.riscv.vaadd.mask.nxv32i8.i8(
- <vscale x 32 x i8>,
- <vscale x 32 x i8>,
- i8,
- <vscale x 32 x i1>,
- i64,
- i64);
-
-define <vscale x 32 x i8> @intrinsic_vaadd_mask_vx_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vaadd_mask_vx_nxv32i8_nxv32i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
-; CHECK-NEXT: vaadd.vx v8, v12, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 32 x i8> @llvm.riscv.vaadd.mask.nxv32i8.i8(
- <vscale x 32 x i8> %0,
- <vscale x 32 x i8> %1,
- i8 %2,
- <vscale x 32 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 32 x i8> %a
-}
-
-declare <vscale x 64 x i8> @llvm.riscv.vaadd.nxv64i8.i8(
- <vscale x 64 x i8>,
- <vscale x 64 x i8>,
- i8,
- i64);
-
-define <vscale x 64 x i8> @intrinsic_vaadd_vx_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, i8 %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vaadd_vx_nxv64i8_nxv64i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu
-; CHECK-NEXT: vaadd.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 64 x i8> @llvm.riscv.vaadd.nxv64i8.i8(
- <vscale x 64 x i8> undef,
- <vscale x 64 x i8> %0,
- i8 %1,
- i64 %2)
-
- ret <vscale x 64 x i8> %a
-}
-
-declare <vscale x 64 x i8> @llvm.riscv.vaadd.mask.nxv64i8.i8(
- <vscale x 64 x i8>,
- <vscale x 64 x i8>,
- i8,
- <vscale x 64 x i1>,
- i64,
- i64);
-
-define <vscale x 64 x i8> @intrinsic_vaadd_mask_vx_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i8 %2, <vscale x 64 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vaadd_mask_vx_nxv64i8_nxv64i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu
-; CHECK-NEXT: vaadd.vx v8, v16, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 64 x i8> @llvm.riscv.vaadd.mask.nxv64i8.i8(
- <vscale x 64 x i8> %0,
- <vscale x 64 x i8> %1,
- i8 %2,
- <vscale x 64 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 64 x i8> %a
-}
-
-declare <vscale x 1 x i16> @llvm.riscv.vaadd.nxv1i16.i16(
- <vscale x 1 x i16>,
- <vscale x 1 x i16>,
- i16,
- i64);
-
-define <vscale x 1 x i16> @intrinsic_vaadd_vx_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, i16 %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vaadd_vx_nxv1i16_nxv1i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
-; CHECK-NEXT: vaadd.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i16> @llvm.riscv.vaadd.nxv1i16.i16(
- <vscale x 1 x i16> undef,
- <vscale x 1 x i16> %0,
- i16 %1,
- i64 %2)
-
- ret <vscale x 1 x i16> %a
-}
-
-declare <vscale x 1 x i16> @llvm.riscv.vaadd.mask.nxv1i16.i16(
- <vscale x 1 x i16>,
- <vscale x 1 x i16>,
- i16,
- <vscale x 1 x i1>,
- i64,
- i64);
-
-define <vscale x 1 x i16> @intrinsic_vaadd_mask_vx_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vaadd_mask_vx_nxv1i16_nxv1i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
-; CHECK-NEXT: vaadd.vx v8, v9, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i16> @llvm.riscv.vaadd.mask.nxv1i16.i16(
- <vscale x 1 x i16> %0,
- <vscale x 1 x i16> %1,
- i16 %2,
- <vscale x 1 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 1 x i16> %a
-}
-
-declare <vscale x 2 x i16> @llvm.riscv.vaadd.nxv2i16.i16(
- <vscale x 2 x i16>,
- <vscale x 2 x i16>,
- i16,
- i64);
-
-define <vscale x 2 x i16> @intrinsic_vaadd_vx_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, i16 %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vaadd_vx_nxv2i16_nxv2i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
-; CHECK-NEXT: vaadd.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i16> @llvm.riscv.vaadd.nxv2i16.i16(
- <vscale x 2 x i16> undef,
- <vscale x 2 x i16> %0,
- i16 %1,
- i64 %2)
-
- ret <vscale x 2 x i16> %a
-}
-
-declare <vscale x 2 x i16> @llvm.riscv.vaadd.mask.nxv2i16.i16(
- <vscale x 2 x i16>,
- <vscale x 2 x i16>,
- i16,
- <vscale x 2 x i1>,
- i64,
- i64);
-
-define <vscale x 2 x i16> @intrinsic_vaadd_mask_vx_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vaadd_mask_vx_nxv2i16_nxv2i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
-; CHECK-NEXT: vaadd.vx v8, v9, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i16> @llvm.riscv.vaadd.mask.nxv2i16.i16(
- <vscale x 2 x i16> %0,
- <vscale x 2 x i16> %1,
- i16 %2,
- <vscale x 2 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 2 x i16> %a
-}
-
-declare <vscale x 4 x i16> @llvm.riscv.vaadd.nxv4i16.i16(
- <vscale x 4 x i16>,
- <vscale x 4 x i16>,
- i16,
- i64);
-
-define <vscale x 4 x i16> @intrinsic_vaadd_vx_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, i16 %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vaadd_vx_nxv4i16_nxv4i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
-; CHECK-NEXT: vaadd.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i16> @llvm.riscv.vaadd.nxv4i16.i16(
- <vscale x 4 x i16> undef,
- <vscale x 4 x i16> %0,
- i16 %1,
- i64 %2)
-
- ret <vscale x 4 x i16> %a
-}
-
-declare <vscale x 4 x i16> @llvm.riscv.vaadd.mask.nxv4i16.i16(
- <vscale x 4 x i16>,
- <vscale x 4 x i16>,
- i16,
- <vscale x 4 x i1>,
- i64,
- i64);
-
-define <vscale x 4 x i16> @intrinsic_vaadd_mask_vx_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vaadd_mask_vx_nxv4i16_nxv4i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
-; CHECK-NEXT: vaadd.vx v8, v9, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i16> @llvm.riscv.vaadd.mask.nxv4i16.i16(
- <vscale x 4 x i16> %0,
- <vscale x 4 x i16> %1,
- i16 %2,
- <vscale x 4 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 4 x i16> %a
-}
-
-declare <vscale x 8 x i16> @llvm.riscv.vaadd.nxv8i16.i16(
- <vscale x 8 x i16>,
- <vscale x 8 x i16>,
- i16,
- i64);
-
-define <vscale x 8 x i16> @intrinsic_vaadd_vx_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, i16 %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vaadd_vx_nxv8i16_nxv8i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
-; CHECK-NEXT: vaadd.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i16> @llvm.riscv.vaadd.nxv8i16.i16(
- <vscale x 8 x i16> undef,
- <vscale x 8 x i16> %0,
- i16 %1,
- i64 %2)
-
- ret <vscale x 8 x i16> %a
-}
-
-declare <vscale x 8 x i16> @llvm.riscv.vaadd.mask.nxv8i16.i16(
- <vscale x 8 x i16>,
- <vscale x 8 x i16>,
- i16,
- <vscale x 8 x i1>,
- i64,
- i64);
-
-define <vscale x 8 x i16> @intrinsic_vaadd_mask_vx_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vaadd_mask_vx_nxv8i16_nxv8i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
-; CHECK-NEXT: vaadd.vx v8, v10, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i16> @llvm.riscv.vaadd.mask.nxv8i16.i16(
- <vscale x 8 x i16> %0,
- <vscale x 8 x i16> %1,
- i16 %2,
- <vscale x 8 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 8 x i16> %a
-}
-
-declare <vscale x 16 x i16> @llvm.riscv.vaadd.nxv16i16.i16(
- <vscale x 16 x i16>,
- <vscale x 16 x i16>,
- i16,
- i64);
-
-define <vscale x 16 x i16> @intrinsic_vaadd_vx_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, i16 %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vaadd_vx_nxv16i16_nxv16i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
-; CHECK-NEXT: vaadd.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i16> @llvm.riscv.vaadd.nxv16i16.i16(
- <vscale x 16 x i16> undef,
- <vscale x 16 x i16> %0,
- i16 %1,
- i64 %2)
-
- ret <vscale x 16 x i16> %a
-}
-
-declare <vscale x 16 x i16> @llvm.riscv.vaadd.mask.nxv16i16.i16(
- <vscale x 16 x i16>,
- <vscale x 16 x i16>,
- i16,
- <vscale x 16 x i1>,
- i64,
- i64);
-
-define <vscale x 16 x i16> @intrinsic_vaadd_mask_vx_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vaadd_mask_vx_nxv16i16_nxv16i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
-; CHECK-NEXT: vaadd.vx v8, v12, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i16> @llvm.riscv.vaadd.mask.nxv16i16.i16(
- <vscale x 16 x i16> %0,
- <vscale x 16 x i16> %1,
- i16 %2,
- <vscale x 16 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 16 x i16> %a
-}
-
-declare <vscale x 32 x i16> @llvm.riscv.vaadd.nxv32i16.i16(
- <vscale x 32 x i16>,
- <vscale x 32 x i16>,
- i16,
- i64);
-
-define <vscale x 32 x i16> @intrinsic_vaadd_vx_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, i16 %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vaadd_vx_nxv32i16_nxv32i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu
-; CHECK-NEXT: vaadd.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 32 x i16> @llvm.riscv.vaadd.nxv32i16.i16(
- <vscale x 32 x i16> undef,
- <vscale x 32 x i16> %0,
- i16 %1,
- i64 %2)
-
- ret <vscale x 32 x i16> %a
-}
-
-declare <vscale x 32 x i16> @llvm.riscv.vaadd.mask.nxv32i16.i16(
- <vscale x 32 x i16>,
- <vscale x 32 x i16>,
- i16,
- <vscale x 32 x i1>,
- i64,
- i64);
-
-define <vscale x 32 x i16> @intrinsic_vaadd_mask_vx_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, i16 %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vaadd_mask_vx_nxv32i16_nxv32i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu
-; CHECK-NEXT: vaadd.vx v8, v16, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 32 x i16> @llvm.riscv.vaadd.mask.nxv32i16.i16(
- <vscale x 32 x i16> %0,
- <vscale x 32 x i16> %1,
- i16 %2,
- <vscale x 32 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 32 x i16> %a
-}
-
-declare <vscale x 1 x i32> @llvm.riscv.vaadd.nxv1i32.i32(
- <vscale x 1 x i32>,
- <vscale x 1 x i32>,
- i32,
- i64);
-
-define <vscale x 1 x i32> @intrinsic_vaadd_vx_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, i32 %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vaadd_vx_nxv1i32_nxv1i32_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
-; CHECK-NEXT: vaadd.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i32> @llvm.riscv.vaadd.nxv1i32.i32(
- <vscale x 1 x i32> undef,
- <vscale x 1 x i32> %0,
- i32 %1,
- i64 %2)
-
- ret <vscale x 1 x i32> %a
-}
-
-declare <vscale x 1 x i32> @llvm.riscv.vaadd.mask.nxv1i32.i32(
- <vscale x 1 x i32>,
- <vscale x 1 x i32>,
- i32,
- <vscale x 1 x i1>,
- i64,
- i64);
-
-define <vscale x 1 x i32> @intrinsic_vaadd_mask_vx_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vaadd_mask_vx_nxv1i32_nxv1i32_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
-; CHECK-NEXT: vaadd.vx v8, v9, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i32> @llvm.riscv.vaadd.mask.nxv1i32.i32(
- <vscale x 1 x i32> %0,
- <vscale x 1 x i32> %1,
- i32 %2,
- <vscale x 1 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 1 x i32> %a
-}
-
-declare <vscale x 2 x i32> @llvm.riscv.vaadd.nxv2i32.i32(
- <vscale x 2 x i32>,
- <vscale x 2 x i32>,
- i32,
- i64);
-
-define <vscale x 2 x i32> @intrinsic_vaadd_vx_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, i32 %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vaadd_vx_nxv2i32_nxv2i32_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
-; CHECK-NEXT: vaadd.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i32> @llvm.riscv.vaadd.nxv2i32.i32(
- <vscale x 2 x i32> undef,
- <vscale x 2 x i32> %0,
- i32 %1,
- i64 %2)
-
- ret <vscale x 2 x i32> %a
-}
-
-declare <vscale x 2 x i32> @llvm.riscv.vaadd.mask.nxv2i32.i32(
- <vscale x 2 x i32>,
- <vscale x 2 x i32>,
- i32,
- <vscale x 2 x i1>,
- i64,
- i64);
-
-define <vscale x 2 x i32> @intrinsic_vaadd_mask_vx_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vaadd_mask_vx_nxv2i32_nxv2i32_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
-; CHECK-NEXT: vaadd.vx v8, v9, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i32> @llvm.riscv.vaadd.mask.nxv2i32.i32(
- <vscale x 2 x i32> %0,
- <vscale x 2 x i32> %1,
- i32 %2,
- <vscale x 2 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 2 x i32> %a
-}
-
-declare <vscale x 4 x i32> @llvm.riscv.vaadd.nxv4i32.i32(
- <vscale x 4 x i32>,
- <vscale x 4 x i32>,
- i32,
- i64);
-
-define <vscale x 4 x i32> @intrinsic_vaadd_vx_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, i32 %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vaadd_vx_nxv4i32_nxv4i32_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; CHECK-NEXT: vaadd.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i32> @llvm.riscv.vaadd.nxv4i32.i32(
- <vscale x 4 x i32> undef,
- <vscale x 4 x i32> %0,
- i32 %1,
- i64 %2)
-
- ret <vscale x 4 x i32> %a
-}
-
-declare <vscale x 4 x i32> @llvm.riscv.vaadd.mask.nxv4i32.i32(
- <vscale x 4 x i32>,
- <vscale x 4 x i32>,
- i32,
- <vscale x 4 x i1>,
- i64,
- i64);
-
-define <vscale x 4 x i32> @intrinsic_vaadd_mask_vx_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vaadd_mask_vx_nxv4i32_nxv4i32_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; CHECK-NEXT: vaadd.vx v8, v10, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i32> @llvm.riscv.vaadd.mask.nxv4i32.i32(
- <vscale x 4 x i32> %0,
- <vscale x 4 x i32> %1,
- i32 %2,
- <vscale x 4 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 4 x i32> %a
-}
-
-declare <vscale x 8 x i32> @llvm.riscv.vaadd.nxv8i32.i32(
- <vscale x 8 x i32>,
- <vscale x 8 x i32>,
- i32,
- i64);
-
-define <vscale x 8 x i32> @intrinsic_vaadd_vx_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, i32 %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vaadd_vx_nxv8i32_nxv8i32_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
-; CHECK-NEXT: vaadd.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i32> @llvm.riscv.vaadd.nxv8i32.i32(
- <vscale x 8 x i32> undef,
- <vscale x 8 x i32> %0,
- i32 %1,
- i64 %2)
-
- ret <vscale x 8 x i32> %a
-}
-
-declare <vscale x 8 x i32> @llvm.riscv.vaadd.mask.nxv8i32.i32(
- <vscale x 8 x i32>,
- <vscale x 8 x i32>,
- i32,
- <vscale x 8 x i1>,
- i64,
- i64);
-
-define <vscale x 8 x i32> @intrinsic_vaadd_mask_vx_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vaadd_mask_vx_nxv8i32_nxv8i32_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
-; CHECK-NEXT: vaadd.vx v8, v12, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i32> @llvm.riscv.vaadd.mask.nxv8i32.i32(
- <vscale x 8 x i32> %0,
- <vscale x 8 x i32> %1,
- i32 %2,
- <vscale x 8 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 8 x i32> %a
-}
-
-declare <vscale x 16 x i32> @llvm.riscv.vaadd.nxv16i32.i32(
- <vscale x 16 x i32>,
- <vscale x 16 x i32>,
- i32,
- i64);
-
-define <vscale x 16 x i32> @intrinsic_vaadd_vx_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, i32 %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vaadd_vx_nxv16i32_nxv16i32_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu
-; CHECK-NEXT: vaadd.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i32> @llvm.riscv.vaadd.nxv16i32.i32(
- <vscale x 16 x i32> undef,
- <vscale x 16 x i32> %0,
- i32 %1,
- i64 %2)
-
- ret <vscale x 16 x i32> %a
-}
-
-declare <vscale x 16 x i32> @llvm.riscv.vaadd.mask.nxv16i32.i32(
- <vscale x 16 x i32>,
- <vscale x 16 x i32>,
- i32,
- <vscale x 16 x i1>,
- i64,
- i64);
-
-define <vscale x 16 x i32> @intrinsic_vaadd_mask_vx_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vaadd_mask_vx_nxv16i32_nxv16i32_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu
-; CHECK-NEXT: vaadd.vx v8, v16, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i32> @llvm.riscv.vaadd.mask.nxv16i32.i32(
- <vscale x 16 x i32> %0,
- <vscale x 16 x i32> %1,
- i32 %2,
- <vscale x 16 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 16 x i32> %a
-}
-
-declare <vscale x 1 x i64> @llvm.riscv.vaadd.nxv1i64.i64(
- <vscale x 1 x i64>,
- <vscale x 1 x i64>,
- i64,
- i64);
-
-define <vscale x 1 x i64> @intrinsic_vaadd_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vaadd_vx_nxv1i64_nxv1i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
-; CHECK-NEXT: vaadd.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i64> @llvm.riscv.vaadd.nxv1i64.i64(
- <vscale x 1 x i64> undef,
- <vscale x 1 x i64> %0,
- i64 %1,
- i64 %2)
-
- ret <vscale x 1 x i64> %a
-}
-
-declare <vscale x 1 x i64> @llvm.riscv.vaadd.mask.nxv1i64.i64(
- <vscale x 1 x i64>,
- <vscale x 1 x i64>,
- i64,
- <vscale x 1 x i1>,
- i64,
- i64);
-
-define <vscale x 1 x i64> @intrinsic_vaadd_mask_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vaadd_mask_vx_nxv1i64_nxv1i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
-; CHECK-NEXT: vaadd.vx v8, v9, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i64> @llvm.riscv.vaadd.mask.nxv1i64.i64(
- <vscale x 1 x i64> %0,
- <vscale x 1 x i64> %1,
- i64 %2,
- <vscale x 1 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 1 x i64> %a
-}
-
-declare <vscale x 2 x i64> @llvm.riscv.vaadd.nxv2i64.i64(
- <vscale x 2 x i64>,
- <vscale x 2 x i64>,
- i64,
- i64);
-
-define <vscale x 2 x i64> @intrinsic_vaadd_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vaadd_vx_nxv2i64_nxv2i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
-; CHECK-NEXT: vaadd.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i64> @llvm.riscv.vaadd.nxv2i64.i64(
- <vscale x 2 x i64> undef,
- <vscale x 2 x i64> %0,
- i64 %1,
- i64 %2)
-
- ret <vscale x 2 x i64> %a
-}
-
-declare <vscale x 2 x i64> @llvm.riscv.vaadd.mask.nxv2i64.i64(
- <vscale x 2 x i64>,
- <vscale x 2 x i64>,
- i64,
- <vscale x 2 x i1>,
- i64,
- i64);
-
-define <vscale x 2 x i64> @intrinsic_vaadd_mask_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vaadd_mask_vx_nxv2i64_nxv2i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
-; CHECK-NEXT: vaadd.vx v8, v10, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i64> @llvm.riscv.vaadd.mask.nxv2i64.i64(
- <vscale x 2 x i64> %0,
- <vscale x 2 x i64> %1,
- i64 %2,
- <vscale x 2 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 2 x i64> %a
-}
-
-declare <vscale x 4 x i64> @llvm.riscv.vaadd.nxv4i64.i64(
- <vscale x 4 x i64>,
- <vscale x 4 x i64>,
- i64,
- i64);
-
-define <vscale x 4 x i64> @intrinsic_vaadd_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vaadd_vx_nxv4i64_nxv4i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
-; CHECK-NEXT: vaadd.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i64> @llvm.riscv.vaadd.nxv4i64.i64(
- <vscale x 4 x i64> undef,
- <vscale x 4 x i64> %0,
- i64 %1,
- i64 %2)
-
- ret <vscale x 4 x i64> %a
-}
-
-declare <vscale x 4 x i64> @llvm.riscv.vaadd.mask.nxv4i64.i64(
- <vscale x 4 x i64>,
- <vscale x 4 x i64>,
- i64,
- <vscale x 4 x i1>,
- i64,
- i64);
-
-define <vscale x 4 x i64> @intrinsic_vaadd_mask_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vaadd_mask_vx_nxv4i64_nxv4i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
-; CHECK-NEXT: vaadd.vx v8, v12, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i64> @llvm.riscv.vaadd.mask.nxv4i64.i64(
- <vscale x 4 x i64> %0,
- <vscale x 4 x i64> %1,
- i64 %2,
- <vscale x 4 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 4 x i64> %a
-}
-
-declare <vscale x 8 x i64> @llvm.riscv.vaadd.nxv8i64.i64(
- <vscale x 8 x i64>,
- <vscale x 8 x i64>,
- i64,
- i64);
-
-define <vscale x 8 x i64> @intrinsic_vaadd_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, i64 %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vaadd_vx_nxv8i64_nxv8i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu
-; CHECK-NEXT: vaadd.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i64> @llvm.riscv.vaadd.nxv8i64.i64(
- <vscale x 8 x i64> undef,
- <vscale x 8 x i64> %0,
- i64 %1,
- i64 %2)
-
- ret <vscale x 8 x i64> %a
-}
-
-declare <vscale x 8 x i64> @llvm.riscv.vaadd.mask.nxv8i64.i64(
- <vscale x 8 x i64>,
- <vscale x 8 x i64>,
- i64,
- <vscale x 8 x i1>,
- i64,
- i64);
-
-define <vscale x 8 x i64> @intrinsic_vaadd_mask_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vaadd_mask_vx_nxv8i64_nxv8i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu
-; CHECK-NEXT: vaadd.vx v8, v16, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i64> @llvm.riscv.vaadd.mask.nxv8i64.i64(
- <vscale x 8 x i64> %0,
- <vscale x 8 x i64> %1,
- i64 %2,
- <vscale x 8 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 8 x i64> %a
-}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vaadd-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vaadd.ll
similarity index 80%
rename from llvm/test/CodeGen/RISCV/rvv/vaadd-rv32.ll
rename to llvm/test/CodeGen/RISCV/rvv/vaadd.ll
index 2d9f005c0d373..5b90ded320cec 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vaadd-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vaadd.ll
@@ -1,13 +1,15 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs \
-; RUN: < %s | FileCheck %s
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v \
+; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,RV32
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v \
+; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,RV64
declare <vscale x 1 x i8> @llvm.riscv.vaadd.nxv1i8.nxv1i8(
<vscale x 1 x i8>,
<vscale x 1 x i8>,
<vscale x 1 x i8>,
- i32);
+ iXLen);
-define <vscale x 1 x i8> @intrinsic_vaadd_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i32 %2) nounwind {
+define <vscale x 1 x i8> @intrinsic_vaadd_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vaadd_vv_nxv1i8_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
@@ -18,7 +20,7 @@ entry:
<vscale x 1 x i8> undef,
<vscale x 1 x i8> %0,
<vscale x 1 x i8> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 1 x i8> %a
}
@@ -28,10 +30,9 @@ declare <vscale x 1 x i8> @llvm.riscv.vaadd.mask.nxv1i8.nxv1i8(
<vscale x 1 x i8>,
<vscale x 1 x i8>,
<vscale x 1 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 1 x i8> @intrinsic_vaadd_mask_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+define <vscale x 1 x i8> @intrinsic_vaadd_mask_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv1i8_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
@@ -43,7 +44,7 @@ entry:
<vscale x 1 x i8> %1,
<vscale x 1 x i8> %2,
<vscale x 1 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 1 x i8> %a
}
@@ -52,9 +53,9 @@ declare <vscale x 2 x i8> @llvm.riscv.vaadd.nxv2i8.nxv2i8(
<vscale x 2 x i8>,
<vscale x 2 x i8>,
<vscale x 2 x i8>,
- i32);
+ iXLen);
-define <vscale x 2 x i8> @intrinsic_vaadd_vv_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i32 %2) nounwind {
+define <vscale x 2 x i8> @intrinsic_vaadd_vv_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vaadd_vv_nxv2i8_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
@@ -65,7 +66,7 @@ entry:
<vscale x 2 x i8> undef,
<vscale x 2 x i8> %0,
<vscale x 2 x i8> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 2 x i8> %a
}
@@ -75,10 +76,9 @@ declare <vscale x 2 x i8> @llvm.riscv.vaadd.mask.nxv2i8.nxv2i8(
<vscale x 2 x i8>,
<vscale x 2 x i8>,
<vscale x 2 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 2 x i8> @intrinsic_vaadd_mask_vv_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+define <vscale x 2 x i8> @intrinsic_vaadd_mask_vv_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv2i8_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
@@ -90,7 +90,7 @@ entry:
<vscale x 2 x i8> %1,
<vscale x 2 x i8> %2,
<vscale x 2 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 2 x i8> %a
}
@@ -99,9 +99,9 @@ declare <vscale x 4 x i8> @llvm.riscv.vaadd.nxv4i8.nxv4i8(
<vscale x 4 x i8>,
<vscale x 4 x i8>,
<vscale x 4 x i8>,
- i32);
+ iXLen);
-define <vscale x 4 x i8> @intrinsic_vaadd_vv_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i32 %2) nounwind {
+define <vscale x 4 x i8> @intrinsic_vaadd_vv_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vaadd_vv_nxv4i8_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
@@ -112,7 +112,7 @@ entry:
<vscale x 4 x i8> undef,
<vscale x 4 x i8> %0,
<vscale x 4 x i8> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 4 x i8> %a
}
@@ -122,10 +122,9 @@ declare <vscale x 4 x i8> @llvm.riscv.vaadd.mask.nxv4i8.nxv4i8(
<vscale x 4 x i8>,
<vscale x 4 x i8>,
<vscale x 4 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 4 x i8> @intrinsic_vaadd_mask_vv_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+define <vscale x 4 x i8> @intrinsic_vaadd_mask_vv_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv4i8_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
@@ -137,7 +136,7 @@ entry:
<vscale x 4 x i8> %1,
<vscale x 4 x i8> %2,
<vscale x 4 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 4 x i8> %a
}
@@ -146,9 +145,9 @@ declare <vscale x 8 x i8> @llvm.riscv.vaadd.nxv8i8.nxv8i8(
<vscale x 8 x i8>,
<vscale x 8 x i8>,
<vscale x 8 x i8>,
- i32);
+ iXLen);
-define <vscale x 8 x i8> @intrinsic_vaadd_vv_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i32 %2) nounwind {
+define <vscale x 8 x i8> @intrinsic_vaadd_vv_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vaadd_vv_nxv8i8_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
@@ -159,7 +158,7 @@ entry:
<vscale x 8 x i8> undef,
<vscale x 8 x i8> %0,
<vscale x 8 x i8> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 8 x i8> %a
}
@@ -169,10 +168,9 @@ declare <vscale x 8 x i8> @llvm.riscv.vaadd.mask.nxv8i8.nxv8i8(
<vscale x 8 x i8>,
<vscale x 8 x i8>,
<vscale x 8 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 8 x i8> @intrinsic_vaadd_mask_vv_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+define <vscale x 8 x i8> @intrinsic_vaadd_mask_vv_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv8i8_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
@@ -184,7 +182,7 @@ entry:
<vscale x 8 x i8> %1,
<vscale x 8 x i8> %2,
<vscale x 8 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 8 x i8> %a
}
@@ -193,9 +191,9 @@ declare <vscale x 16 x i8> @llvm.riscv.vaadd.nxv16i8.nxv16i8(
<vscale x 16 x i8>,
<vscale x 16 x i8>,
<vscale x 16 x i8>,
- i32);
+ iXLen);
-define <vscale x 16 x i8> @intrinsic_vaadd_vv_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i32 %2) nounwind {
+define <vscale x 16 x i8> @intrinsic_vaadd_vv_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vaadd_vv_nxv16i8_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
@@ -206,7 +204,7 @@ entry:
<vscale x 16 x i8> undef,
<vscale x 16 x i8> %0,
<vscale x 16 x i8> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 16 x i8> %a
}
@@ -216,10 +214,9 @@ declare <vscale x 16 x i8> @llvm.riscv.vaadd.mask.nxv16i8.nxv16i8(
<vscale x 16 x i8>,
<vscale x 16 x i8>,
<vscale x 16 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 16 x i8> @intrinsic_vaadd_mask_vv_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+define <vscale x 16 x i8> @intrinsic_vaadd_mask_vv_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv16i8_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
@@ -231,7 +228,7 @@ entry:
<vscale x 16 x i8> %1,
<vscale x 16 x i8> %2,
<vscale x 16 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 16 x i8> %a
}
@@ -240,9 +237,9 @@ declare <vscale x 32 x i8> @llvm.riscv.vaadd.nxv32i8.nxv32i8(
<vscale x 32 x i8>,
<vscale x 32 x i8>,
<vscale x 32 x i8>,
- i32);
+ iXLen);
-define <vscale x 32 x i8> @intrinsic_vaadd_vv_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i32 %2) nounwind {
+define <vscale x 32 x i8> @intrinsic_vaadd_vv_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vaadd_vv_nxv32i8_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
@@ -253,7 +250,7 @@ entry:
<vscale x 32 x i8> undef,
<vscale x 32 x i8> %0,
<vscale x 32 x i8> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 32 x i8> %a
}
@@ -263,10 +260,9 @@ declare <vscale x 32 x i8> @llvm.riscv.vaadd.mask.nxv32i8.nxv32i8(
<vscale x 32 x i8>,
<vscale x 32 x i8>,
<vscale x 32 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 32 x i8> @intrinsic_vaadd_mask_vv_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
+define <vscale x 32 x i8> @intrinsic_vaadd_mask_vv_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv32i8_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
@@ -278,7 +274,7 @@ entry:
<vscale x 32 x i8> %1,
<vscale x 32 x i8> %2,
<vscale x 32 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 32 x i8> %a
}
@@ -287,9 +283,9 @@ declare <vscale x 64 x i8> @llvm.riscv.vaadd.nxv64i8.nxv64i8(
<vscale x 64 x i8>,
<vscale x 64 x i8>,
<vscale x 64 x i8>,
- i32);
+ iXLen);
-define <vscale x 64 x i8> @intrinsic_vaadd_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i32 %2) nounwind {
+define <vscale x 64 x i8> @intrinsic_vaadd_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vaadd_vv_nxv64i8_nxv64i8_nxv64i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, mu
@@ -300,7 +296,7 @@ entry:
<vscale x 64 x i8> undef,
<vscale x 64 x i8> %0,
<vscale x 64 x i8> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 64 x i8> %a
}
@@ -310,10 +306,9 @@ declare <vscale x 64 x i8> @llvm.riscv.vaadd.mask.nxv64i8.nxv64i8(
<vscale x 64 x i8>,
<vscale x 64 x i8>,
<vscale x 64 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 64 x i8> @intrinsic_vaadd_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, i32 %4) nounwind {
+define <vscale x 64 x i8> @intrinsic_vaadd_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv64i8_nxv64i8_nxv64i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vl8r.v v24, (a0)
@@ -326,7 +321,7 @@ entry:
<vscale x 64 x i8> %1,
<vscale x 64 x i8> %2,
<vscale x 64 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 64 x i8> %a
}
@@ -335,9 +330,9 @@ declare <vscale x 1 x i16> @llvm.riscv.vaadd.nxv1i16.nxv1i16(
<vscale x 1 x i16>,
<vscale x 1 x i16>,
<vscale x 1 x i16>,
- i32);
+ iXLen);
-define <vscale x 1 x i16> @intrinsic_vaadd_vv_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i32 %2) nounwind {
+define <vscale x 1 x i16> @intrinsic_vaadd_vv_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vaadd_vv_nxv1i16_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
@@ -348,7 +343,7 @@ entry:
<vscale x 1 x i16> undef,
<vscale x 1 x i16> %0,
<vscale x 1 x i16> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 1 x i16> %a
}
@@ -358,10 +353,9 @@ declare <vscale x 1 x i16> @llvm.riscv.vaadd.mask.nxv1i16.nxv1i16(
<vscale x 1 x i16>,
<vscale x 1 x i16>,
<vscale x 1 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 1 x i16> @intrinsic_vaadd_mask_vv_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+define <vscale x 1 x i16> @intrinsic_vaadd_mask_vv_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv1i16_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
@@ -373,7 +367,7 @@ entry:
<vscale x 1 x i16> %1,
<vscale x 1 x i16> %2,
<vscale x 1 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 1 x i16> %a
}
@@ -382,9 +376,9 @@ declare <vscale x 2 x i16> @llvm.riscv.vaadd.nxv2i16.nxv2i16(
<vscale x 2 x i16>,
<vscale x 2 x i16>,
<vscale x 2 x i16>,
- i32);
+ iXLen);
-define <vscale x 2 x i16> @intrinsic_vaadd_vv_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i32 %2) nounwind {
+define <vscale x 2 x i16> @intrinsic_vaadd_vv_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vaadd_vv_nxv2i16_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
@@ -395,7 +389,7 @@ entry:
<vscale x 2 x i16> undef,
<vscale x 2 x i16> %0,
<vscale x 2 x i16> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 2 x i16> %a
}
@@ -405,10 +399,9 @@ declare <vscale x 2 x i16> @llvm.riscv.vaadd.mask.nxv2i16.nxv2i16(
<vscale x 2 x i16>,
<vscale x 2 x i16>,
<vscale x 2 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 2 x i16> @intrinsic_vaadd_mask_vv_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+define <vscale x 2 x i16> @intrinsic_vaadd_mask_vv_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv2i16_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
@@ -420,7 +413,7 @@ entry:
<vscale x 2 x i16> %1,
<vscale x 2 x i16> %2,
<vscale x 2 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 2 x i16> %a
}
@@ -429,9 +422,9 @@ declare <vscale x 4 x i16> @llvm.riscv.vaadd.nxv4i16.nxv4i16(
<vscale x 4 x i16>,
<vscale x 4 x i16>,
<vscale x 4 x i16>,
- i32);
+ iXLen);
-define <vscale x 4 x i16> @intrinsic_vaadd_vv_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i32 %2) nounwind {
+define <vscale x 4 x i16> @intrinsic_vaadd_vv_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vaadd_vv_nxv4i16_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
@@ -442,7 +435,7 @@ entry:
<vscale x 4 x i16> undef,
<vscale x 4 x i16> %0,
<vscale x 4 x i16> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 4 x i16> %a
}
@@ -452,10 +445,9 @@ declare <vscale x 4 x i16> @llvm.riscv.vaadd.mask.nxv4i16.nxv4i16(
<vscale x 4 x i16>,
<vscale x 4 x i16>,
<vscale x 4 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 4 x i16> @intrinsic_vaadd_mask_vv_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+define <vscale x 4 x i16> @intrinsic_vaadd_mask_vv_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv4i16_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
@@ -467,7 +459,7 @@ entry:
<vscale x 4 x i16> %1,
<vscale x 4 x i16> %2,
<vscale x 4 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 4 x i16> %a
}
@@ -476,9 +468,9 @@ declare <vscale x 8 x i16> @llvm.riscv.vaadd.nxv8i16.nxv8i16(
<vscale x 8 x i16>,
<vscale x 8 x i16>,
<vscale x 8 x i16>,
- i32);
+ iXLen);
-define <vscale x 8 x i16> @intrinsic_vaadd_vv_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i32 %2) nounwind {
+define <vscale x 8 x i16> @intrinsic_vaadd_vv_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vaadd_vv_nxv8i16_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
@@ -489,7 +481,7 @@ entry:
<vscale x 8 x i16> undef,
<vscale x 8 x i16> %0,
<vscale x 8 x i16> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 8 x i16> %a
}
@@ -499,10 +491,9 @@ declare <vscale x 8 x i16> @llvm.riscv.vaadd.mask.nxv8i16.nxv8i16(
<vscale x 8 x i16>,
<vscale x 8 x i16>,
<vscale x 8 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 8 x i16> @intrinsic_vaadd_mask_vv_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+define <vscale x 8 x i16> @intrinsic_vaadd_mask_vv_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv8i16_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
@@ -514,7 +505,7 @@ entry:
<vscale x 8 x i16> %1,
<vscale x 8 x i16> %2,
<vscale x 8 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 8 x i16> %a
}
@@ -523,9 +514,9 @@ declare <vscale x 16 x i16> @llvm.riscv.vaadd.nxv16i16.nxv16i16(
<vscale x 16 x i16>,
<vscale x 16 x i16>,
<vscale x 16 x i16>,
- i32);
+ iXLen);
-define <vscale x 16 x i16> @intrinsic_vaadd_vv_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i32 %2) nounwind {
+define <vscale x 16 x i16> @intrinsic_vaadd_vv_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vaadd_vv_nxv16i16_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
@@ -536,7 +527,7 @@ entry:
<vscale x 16 x i16> undef,
<vscale x 16 x i16> %0,
<vscale x 16 x i16> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 16 x i16> %a
}
@@ -546,10 +537,9 @@ declare <vscale x 16 x i16> @llvm.riscv.vaadd.mask.nxv16i16.nxv16i16(
<vscale x 16 x i16>,
<vscale x 16 x i16>,
<vscale x 16 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 16 x i16> @intrinsic_vaadd_mask_vv_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+define <vscale x 16 x i16> @intrinsic_vaadd_mask_vv_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv16i16_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
@@ -561,7 +551,7 @@ entry:
<vscale x 16 x i16> %1,
<vscale x 16 x i16> %2,
<vscale x 16 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 16 x i16> %a
}
@@ -570,9 +560,9 @@ declare <vscale x 32 x i16> @llvm.riscv.vaadd.nxv32i16.nxv32i16(
<vscale x 32 x i16>,
<vscale x 32 x i16>,
<vscale x 32 x i16>,
- i32);
+ iXLen);
-define <vscale x 32 x i16> @intrinsic_vaadd_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, i32 %2) nounwind {
+define <vscale x 32 x i16> @intrinsic_vaadd_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vaadd_vv_nxv32i16_nxv32i16_nxv32i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, mu
@@ -583,7 +573,7 @@ entry:
<vscale x 32 x i16> undef,
<vscale x 32 x i16> %0,
<vscale x 32 x i16> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 32 x i16> %a
}
@@ -593,10 +583,9 @@ declare <vscale x 32 x i16> @llvm.riscv.vaadd.mask.nxv32i16.nxv32i16(
<vscale x 32 x i16>,
<vscale x 32 x i16>,
<vscale x 32 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 32 x i16> @intrinsic_vaadd_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
+define <vscale x 32 x i16> @intrinsic_vaadd_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv32i16_nxv32i16_nxv32i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vl8re16.v v24, (a0)
@@ -609,7 +598,7 @@ entry:
<vscale x 32 x i16> %1,
<vscale x 32 x i16> %2,
<vscale x 32 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 32 x i16> %a
}
@@ -618,9 +607,9 @@ declare <vscale x 1 x i32> @llvm.riscv.vaadd.nxv1i32.nxv1i32(
<vscale x 1 x i32>,
<vscale x 1 x i32>,
<vscale x 1 x i32>,
- i32);
+ iXLen);
-define <vscale x 1 x i32> @intrinsic_vaadd_vv_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2) nounwind {
+define <vscale x 1 x i32> @intrinsic_vaadd_vv_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vaadd_vv_nxv1i32_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
@@ -631,7 +620,7 @@ entry:
<vscale x 1 x i32> undef,
<vscale x 1 x i32> %0,
<vscale x 1 x i32> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 1 x i32> %a
}
@@ -641,10 +630,9 @@ declare <vscale x 1 x i32> @llvm.riscv.vaadd.mask.nxv1i32.nxv1i32(
<vscale x 1 x i32>,
<vscale x 1 x i32>,
<vscale x 1 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 1 x i32> @intrinsic_vaadd_mask_vv_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+define <vscale x 1 x i32> @intrinsic_vaadd_mask_vv_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv1i32_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
@@ -656,7 +644,7 @@ entry:
<vscale x 1 x i32> %1,
<vscale x 1 x i32> %2,
<vscale x 1 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 1 x i32> %a
}
@@ -665,9 +653,9 @@ declare <vscale x 2 x i32> @llvm.riscv.vaadd.nxv2i32.nxv2i32(
<vscale x 2 x i32>,
<vscale x 2 x i32>,
<vscale x 2 x i32>,
- i32);
+ iXLen);
-define <vscale x 2 x i32> @intrinsic_vaadd_vv_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2) nounwind {
+define <vscale x 2 x i32> @intrinsic_vaadd_vv_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vaadd_vv_nxv2i32_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
@@ -678,7 +666,7 @@ entry:
<vscale x 2 x i32> undef,
<vscale x 2 x i32> %0,
<vscale x 2 x i32> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 2 x i32> %a
}
@@ -688,10 +676,9 @@ declare <vscale x 2 x i32> @llvm.riscv.vaadd.mask.nxv2i32.nxv2i32(
<vscale x 2 x i32>,
<vscale x 2 x i32>,
<vscale x 2 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 2 x i32> @intrinsic_vaadd_mask_vv_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+define <vscale x 2 x i32> @intrinsic_vaadd_mask_vv_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv2i32_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
@@ -703,7 +690,7 @@ entry:
<vscale x 2 x i32> %1,
<vscale x 2 x i32> %2,
<vscale x 2 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 2 x i32> %a
}
@@ -712,9 +699,9 @@ declare <vscale x 4 x i32> @llvm.riscv.vaadd.nxv4i32.nxv4i32(
<vscale x 4 x i32>,
<vscale x 4 x i32>,
<vscale x 4 x i32>,
- i32);
+ iXLen);
-define <vscale x 4 x i32> @intrinsic_vaadd_vv_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2) nounwind {
+define <vscale x 4 x i32> @intrinsic_vaadd_vv_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vaadd_vv_nxv4i32_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
@@ -725,7 +712,7 @@ entry:
<vscale x 4 x i32> undef,
<vscale x 4 x i32> %0,
<vscale x 4 x i32> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 4 x i32> %a
}
@@ -735,10 +722,9 @@ declare <vscale x 4 x i32> @llvm.riscv.vaadd.mask.nxv4i32.nxv4i32(
<vscale x 4 x i32>,
<vscale x 4 x i32>,
<vscale x 4 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 4 x i32> @intrinsic_vaadd_mask_vv_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+define <vscale x 4 x i32> @intrinsic_vaadd_mask_vv_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv4i32_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
@@ -750,7 +736,7 @@ entry:
<vscale x 4 x i32> %1,
<vscale x 4 x i32> %2,
<vscale x 4 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 4 x i32> %a
}
@@ -759,9 +745,9 @@ declare <vscale x 8 x i32> @llvm.riscv.vaadd.nxv8i32.nxv8i32(
<vscale x 8 x i32>,
<vscale x 8 x i32>,
<vscale x 8 x i32>,
- i32);
+ iXLen);
-define <vscale x 8 x i32> @intrinsic_vaadd_vv_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2) nounwind {
+define <vscale x 8 x i32> @intrinsic_vaadd_vv_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vaadd_vv_nxv8i32_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
@@ -772,7 +758,7 @@ entry:
<vscale x 8 x i32> undef,
<vscale x 8 x i32> %0,
<vscale x 8 x i32> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 8 x i32> %a
}
@@ -782,10 +768,9 @@ declare <vscale x 8 x i32> @llvm.riscv.vaadd.mask.nxv8i32.nxv8i32(
<vscale x 8 x i32>,
<vscale x 8 x i32>,
<vscale x 8 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 8 x i32> @intrinsic_vaadd_mask_vv_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+define <vscale x 8 x i32> @intrinsic_vaadd_mask_vv_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv8i32_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
@@ -797,7 +782,7 @@ entry:
<vscale x 8 x i32> %1,
<vscale x 8 x i32> %2,
<vscale x 8 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 8 x i32> %a
}
@@ -806,9 +791,9 @@ declare <vscale x 16 x i32> @llvm.riscv.vaadd.nxv16i32.nxv16i32(
<vscale x 16 x i32>,
<vscale x 16 x i32>,
<vscale x 16 x i32>,
- i32);
+ iXLen);
-define <vscale x 16 x i32> @intrinsic_vaadd_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2) nounwind {
+define <vscale x 16 x i32> @intrinsic_vaadd_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vaadd_vv_nxv16i32_nxv16i32_nxv16i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu
@@ -819,7 +804,7 @@ entry:
<vscale x 16 x i32> undef,
<vscale x 16 x i32> %0,
<vscale x 16 x i32> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 16 x i32> %a
}
@@ -829,10 +814,9 @@ declare <vscale x 16 x i32> @llvm.riscv.vaadd.mask.nxv16i32.nxv16i32(
<vscale x 16 x i32>,
<vscale x 16 x i32>,
<vscale x 16 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 16 x i32> @intrinsic_vaadd_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+define <vscale x 16 x i32> @intrinsic_vaadd_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv16i32_nxv16i32_nxv16i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vl8re32.v v24, (a0)
@@ -845,7 +829,7 @@ entry:
<vscale x 16 x i32> %1,
<vscale x 16 x i32> %2,
<vscale x 16 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 16 x i32> %a
}
@@ -854,9 +838,9 @@ declare <vscale x 1 x i64> @llvm.riscv.vaadd.nxv1i64.nxv1i64(
<vscale x 1 x i64>,
<vscale x 1 x i64>,
<vscale x 1 x i64>,
- i32);
+ iXLen);
-define <vscale x 1 x i64> @intrinsic_vaadd_vv_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i32 %2) nounwind {
+define <vscale x 1 x i64> @intrinsic_vaadd_vv_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vaadd_vv_nxv1i64_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
@@ -867,7 +851,7 @@ entry:
<vscale x 1 x i64> undef,
<vscale x 1 x i64> %0,
<vscale x 1 x i64> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 1 x i64> %a
}
@@ -877,10 +861,9 @@ declare <vscale x 1 x i64> @llvm.riscv.vaadd.mask.nxv1i64.nxv1i64(
<vscale x 1 x i64>,
<vscale x 1 x i64>,
<vscale x 1 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 1 x i64> @intrinsic_vaadd_mask_vv_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+define <vscale x 1 x i64> @intrinsic_vaadd_mask_vv_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv1i64_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
@@ -892,7 +875,7 @@ entry:
<vscale x 1 x i64> %1,
<vscale x 1 x i64> %2,
<vscale x 1 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 1 x i64> %a
}
@@ -901,9 +884,9 @@ declare <vscale x 2 x i64> @llvm.riscv.vaadd.nxv2i64.nxv2i64(
<vscale x 2 x i64>,
<vscale x 2 x i64>,
<vscale x 2 x i64>,
- i32);
+ iXLen);
-define <vscale x 2 x i64> @intrinsic_vaadd_vv_nxv2i64_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i32 %2) nounwind {
+define <vscale x 2 x i64> @intrinsic_vaadd_vv_nxv2i64_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vaadd_vv_nxv2i64_nxv2i64_nxv2i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
@@ -914,7 +897,7 @@ entry:
<vscale x 2 x i64> undef,
<vscale x 2 x i64> %0,
<vscale x 2 x i64> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 2 x i64> %a
}
@@ -924,10 +907,9 @@ declare <vscale x 2 x i64> @llvm.riscv.vaadd.mask.nxv2i64.nxv2i64(
<vscale x 2 x i64>,
<vscale x 2 x i64>,
<vscale x 2 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 2 x i64> @intrinsic_vaadd_mask_vv_nxv2i64_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+define <vscale x 2 x i64> @intrinsic_vaadd_mask_vv_nxv2i64_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv2i64_nxv2i64_nxv2i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
@@ -939,7 +921,7 @@ entry:
<vscale x 2 x i64> %1,
<vscale x 2 x i64> %2,
<vscale x 2 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 2 x i64> %a
}
@@ -948,9 +930,9 @@ declare <vscale x 4 x i64> @llvm.riscv.vaadd.nxv4i64.nxv4i64(
<vscale x 4 x i64>,
<vscale x 4 x i64>,
<vscale x 4 x i64>,
- i32);
+ iXLen);
-define <vscale x 4 x i64> @intrinsic_vaadd_vv_nxv4i64_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i32 %2) nounwind {
+define <vscale x 4 x i64> @intrinsic_vaadd_vv_nxv4i64_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vaadd_vv_nxv4i64_nxv4i64_nxv4i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
@@ -961,7 +943,7 @@ entry:
<vscale x 4 x i64> undef,
<vscale x 4 x i64> %0,
<vscale x 4 x i64> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 4 x i64> %a
}
@@ -971,10 +953,9 @@ declare <vscale x 4 x i64> @llvm.riscv.vaadd.mask.nxv4i64.nxv4i64(
<vscale x 4 x i64>,
<vscale x 4 x i64>,
<vscale x 4 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 4 x i64> @intrinsic_vaadd_mask_vv_nxv4i64_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+define <vscale x 4 x i64> @intrinsic_vaadd_mask_vv_nxv4i64_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv4i64_nxv4i64_nxv4i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
@@ -986,7 +967,7 @@ entry:
<vscale x 4 x i64> %1,
<vscale x 4 x i64> %2,
<vscale x 4 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 4 x i64> %a
}
@@ -995,9 +976,9 @@ declare <vscale x 8 x i64> @llvm.riscv.vaadd.nxv8i64.nxv8i64(
<vscale x 8 x i64>,
<vscale x 8 x i64>,
<vscale x 8 x i64>,
- i32);
+ iXLen);
-define <vscale x 8 x i64> @intrinsic_vaadd_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i32 %2) nounwind {
+define <vscale x 8 x i64> @intrinsic_vaadd_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vaadd_vv_nxv8i64_nxv8i64_nxv8i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu
@@ -1008,7 +989,7 @@ entry:
<vscale x 8 x i64> undef,
<vscale x 8 x i64> %0,
<vscale x 8 x i64> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 8 x i64> %a
}
@@ -1018,10 +999,9 @@ declare <vscale x 8 x i64> @llvm.riscv.vaadd.mask.nxv8i64.nxv8i64(
<vscale x 8 x i64>,
<vscale x 8 x i64>,
<vscale x 8 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 8 x i64> @intrinsic_vaadd_mask_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+define <vscale x 8 x i64> @intrinsic_vaadd_mask_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv8i64_nxv8i64_nxv8i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vl8re64.v v24, (a0)
@@ -1034,7 +1014,7 @@ entry:
<vscale x 8 x i64> %1,
<vscale x 8 x i64> %2,
<vscale x 8 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 8 x i64> %a
}
@@ -1043,9 +1023,9 @@ declare <vscale x 1 x i8> @llvm.riscv.vaadd.nxv1i8.i8(
<vscale x 1 x i8>,
<vscale x 1 x i8>,
i8,
- i32);
+ iXLen);
-define <vscale x 1 x i8> @intrinsic_vaadd_vx_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, i8 %1, i32 %2) nounwind {
+define <vscale x 1 x i8> @intrinsic_vaadd_vx_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, i8 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vaadd_vx_nxv1i8_nxv1i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
@@ -1056,7 +1036,7 @@ entry:
<vscale x 1 x i8> undef,
<vscale x 1 x i8> %0,
i8 %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 1 x i8> %a
}
@@ -1066,10 +1046,9 @@ declare <vscale x 1 x i8> @llvm.riscv.vaadd.mask.nxv1i8.i8(
<vscale x 1 x i8>,
i8,
<vscale x 1 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 1 x i8> @intrinsic_vaadd_mask_vx_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+define <vscale x 1 x i8> @intrinsic_vaadd_mask_vx_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vaadd_mask_vx_nxv1i8_nxv1i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
@@ -1081,7 +1060,7 @@ entry:
<vscale x 1 x i8> %1,
i8 %2,
<vscale x 1 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 1 x i8> %a
}
@@ -1090,9 +1069,9 @@ declare <vscale x 2 x i8> @llvm.riscv.vaadd.nxv2i8.i8(
<vscale x 2 x i8>,
<vscale x 2 x i8>,
i8,
- i32);
+ iXLen);
-define <vscale x 2 x i8> @intrinsic_vaadd_vx_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, i8 %1, i32 %2) nounwind {
+define <vscale x 2 x i8> @intrinsic_vaadd_vx_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, i8 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vaadd_vx_nxv2i8_nxv2i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
@@ -1103,7 +1082,7 @@ entry:
<vscale x 2 x i8> undef,
<vscale x 2 x i8> %0,
i8 %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 2 x i8> %a
}
@@ -1113,10 +1092,9 @@ declare <vscale x 2 x i8> @llvm.riscv.vaadd.mask.nxv2i8.i8(
<vscale x 2 x i8>,
i8,
<vscale x 2 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 2 x i8> @intrinsic_vaadd_mask_vx_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+define <vscale x 2 x i8> @intrinsic_vaadd_mask_vx_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vaadd_mask_vx_nxv2i8_nxv2i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
@@ -1128,7 +1106,7 @@ entry:
<vscale x 2 x i8> %1,
i8 %2,
<vscale x 2 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 2 x i8> %a
}
@@ -1137,9 +1115,9 @@ declare <vscale x 4 x i8> @llvm.riscv.vaadd.nxv4i8.i8(
<vscale x 4 x i8>,
<vscale x 4 x i8>,
i8,
- i32);
+ iXLen);
-define <vscale x 4 x i8> @intrinsic_vaadd_vx_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, i8 %1, i32 %2) nounwind {
+define <vscale x 4 x i8> @intrinsic_vaadd_vx_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, i8 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vaadd_vx_nxv4i8_nxv4i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
@@ -1150,7 +1128,7 @@ entry:
<vscale x 4 x i8> undef,
<vscale x 4 x i8> %0,
i8 %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 4 x i8> %a
}
@@ -1160,10 +1138,9 @@ declare <vscale x 4 x i8> @llvm.riscv.vaadd.mask.nxv4i8.i8(
<vscale x 4 x i8>,
i8,
<vscale x 4 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 4 x i8> @intrinsic_vaadd_mask_vx_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+define <vscale x 4 x i8> @intrinsic_vaadd_mask_vx_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vaadd_mask_vx_nxv4i8_nxv4i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
@@ -1175,7 +1152,7 @@ entry:
<vscale x 4 x i8> %1,
i8 %2,
<vscale x 4 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 4 x i8> %a
}
@@ -1184,9 +1161,9 @@ declare <vscale x 8 x i8> @llvm.riscv.vaadd.nxv8i8.i8(
<vscale x 8 x i8>,
<vscale x 8 x i8>,
i8,
- i32);
+ iXLen);
-define <vscale x 8 x i8> @intrinsic_vaadd_vx_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, i8 %1, i32 %2) nounwind {
+define <vscale x 8 x i8> @intrinsic_vaadd_vx_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, i8 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vaadd_vx_nxv8i8_nxv8i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
@@ -1197,7 +1174,7 @@ entry:
<vscale x 8 x i8> undef,
<vscale x 8 x i8> %0,
i8 %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 8 x i8> %a
}
@@ -1207,10 +1184,9 @@ declare <vscale x 8 x i8> @llvm.riscv.vaadd.mask.nxv8i8.i8(
<vscale x 8 x i8>,
i8,
<vscale x 8 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 8 x i8> @intrinsic_vaadd_mask_vx_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+define <vscale x 8 x i8> @intrinsic_vaadd_mask_vx_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vaadd_mask_vx_nxv8i8_nxv8i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
@@ -1222,7 +1198,7 @@ entry:
<vscale x 8 x i8> %1,
i8 %2,
<vscale x 8 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 8 x i8> %a
}
@@ -1231,9 +1207,9 @@ declare <vscale x 16 x i8> @llvm.riscv.vaadd.nxv16i8.i8(
<vscale x 16 x i8>,
<vscale x 16 x i8>,
i8,
- i32);
+ iXLen);
-define <vscale x 16 x i8> @intrinsic_vaadd_vx_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, i8 %1, i32 %2) nounwind {
+define <vscale x 16 x i8> @intrinsic_vaadd_vx_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, i8 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vaadd_vx_nxv16i8_nxv16i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
@@ -1244,7 +1220,7 @@ entry:
<vscale x 16 x i8> undef,
<vscale x 16 x i8> %0,
i8 %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 16 x i8> %a
}
@@ -1254,10 +1230,9 @@ declare <vscale x 16 x i8> @llvm.riscv.vaadd.mask.nxv16i8.i8(
<vscale x 16 x i8>,
i8,
<vscale x 16 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 16 x i8> @intrinsic_vaadd_mask_vx_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+define <vscale x 16 x i8> @intrinsic_vaadd_mask_vx_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vaadd_mask_vx_nxv16i8_nxv16i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
@@ -1269,7 +1244,7 @@ entry:
<vscale x 16 x i8> %1,
i8 %2,
<vscale x 16 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 16 x i8> %a
}
@@ -1278,9 +1253,9 @@ declare <vscale x 32 x i8> @llvm.riscv.vaadd.nxv32i8.i8(
<vscale x 32 x i8>,
<vscale x 32 x i8>,
i8,
- i32);
+ iXLen);
-define <vscale x 32 x i8> @intrinsic_vaadd_vx_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, i8 %1, i32 %2) nounwind {
+define <vscale x 32 x i8> @intrinsic_vaadd_vx_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, i8 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vaadd_vx_nxv32i8_nxv32i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
@@ -1291,7 +1266,7 @@ entry:
<vscale x 32 x i8> undef,
<vscale x 32 x i8> %0,
i8 %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 32 x i8> %a
}
@@ -1301,10 +1276,9 @@ declare <vscale x 32 x i8> @llvm.riscv.vaadd.mask.nxv32i8.i8(
<vscale x 32 x i8>,
i8,
<vscale x 32 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 32 x i8> @intrinsic_vaadd_mask_vx_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
+define <vscale x 32 x i8> @intrinsic_vaadd_mask_vx_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vaadd_mask_vx_nxv32i8_nxv32i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
@@ -1316,7 +1290,7 @@ entry:
<vscale x 32 x i8> %1,
i8 %2,
<vscale x 32 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 32 x i8> %a
}
@@ -1325,9 +1299,9 @@ declare <vscale x 64 x i8> @llvm.riscv.vaadd.nxv64i8.i8(
<vscale x 64 x i8>,
<vscale x 64 x i8>,
i8,
- i32);
+ iXLen);
-define <vscale x 64 x i8> @intrinsic_vaadd_vx_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, i8 %1, i32 %2) nounwind {
+define <vscale x 64 x i8> @intrinsic_vaadd_vx_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, i8 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vaadd_vx_nxv64i8_nxv64i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu
@@ -1338,7 +1312,7 @@ entry:
<vscale x 64 x i8> undef,
<vscale x 64 x i8> %0,
i8 %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 64 x i8> %a
}
@@ -1348,10 +1322,9 @@ declare <vscale x 64 x i8> @llvm.riscv.vaadd.mask.nxv64i8.i8(
<vscale x 64 x i8>,
i8,
<vscale x 64 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 64 x i8> @intrinsic_vaadd_mask_vx_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i8 %2, <vscale x 64 x i1> %3, i32 %4) nounwind {
+define <vscale x 64 x i8> @intrinsic_vaadd_mask_vx_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i8 %2, <vscale x 64 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vaadd_mask_vx_nxv64i8_nxv64i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu
@@ -1363,7 +1336,7 @@ entry:
<vscale x 64 x i8> %1,
i8 %2,
<vscale x 64 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 64 x i8> %a
}
@@ -1372,9 +1345,9 @@ declare <vscale x 1 x i16> @llvm.riscv.vaadd.nxv1i16.i16(
<vscale x 1 x i16>,
<vscale x 1 x i16>,
i16,
- i32);
+ iXLen);
-define <vscale x 1 x i16> @intrinsic_vaadd_vx_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, i16 %1, i32 %2) nounwind {
+define <vscale x 1 x i16> @intrinsic_vaadd_vx_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, i16 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vaadd_vx_nxv1i16_nxv1i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
@@ -1385,7 +1358,7 @@ entry:
<vscale x 1 x i16> undef,
<vscale x 1 x i16> %0,
i16 %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 1 x i16> %a
}
@@ -1395,10 +1368,9 @@ declare <vscale x 1 x i16> @llvm.riscv.vaadd.mask.nxv1i16.i16(
<vscale x 1 x i16>,
i16,
<vscale x 1 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 1 x i16> @intrinsic_vaadd_mask_vx_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+define <vscale x 1 x i16> @intrinsic_vaadd_mask_vx_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vaadd_mask_vx_nxv1i16_nxv1i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
@@ -1410,7 +1382,7 @@ entry:
<vscale x 1 x i16> %1,
i16 %2,
<vscale x 1 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 1 x i16> %a
}
@@ -1419,9 +1391,9 @@ declare <vscale x 2 x i16> @llvm.riscv.vaadd.nxv2i16.i16(
<vscale x 2 x i16>,
<vscale x 2 x i16>,
i16,
- i32);
+ iXLen);
-define <vscale x 2 x i16> @intrinsic_vaadd_vx_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, i16 %1, i32 %2) nounwind {
+define <vscale x 2 x i16> @intrinsic_vaadd_vx_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, i16 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vaadd_vx_nxv2i16_nxv2i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
@@ -1432,7 +1404,7 @@ entry:
<vscale x 2 x i16> undef,
<vscale x 2 x i16> %0,
i16 %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 2 x i16> %a
}
@@ -1442,10 +1414,9 @@ declare <vscale x 2 x i16> @llvm.riscv.vaadd.mask.nxv2i16.i16(
<vscale x 2 x i16>,
i16,
<vscale x 2 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 2 x i16> @intrinsic_vaadd_mask_vx_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+define <vscale x 2 x i16> @intrinsic_vaadd_mask_vx_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vaadd_mask_vx_nxv2i16_nxv2i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
@@ -1457,7 +1428,7 @@ entry:
<vscale x 2 x i16> %1,
i16 %2,
<vscale x 2 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 2 x i16> %a
}
@@ -1466,9 +1437,9 @@ declare <vscale x 4 x i16> @llvm.riscv.vaadd.nxv4i16.i16(
<vscale x 4 x i16>,
<vscale x 4 x i16>,
i16,
- i32);
+ iXLen);
-define <vscale x 4 x i16> @intrinsic_vaadd_vx_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, i16 %1, i32 %2) nounwind {
+define <vscale x 4 x i16> @intrinsic_vaadd_vx_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, i16 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vaadd_vx_nxv4i16_nxv4i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
@@ -1479,7 +1450,7 @@ entry:
<vscale x 4 x i16> undef,
<vscale x 4 x i16> %0,
i16 %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 4 x i16> %a
}
@@ -1489,10 +1460,9 @@ declare <vscale x 4 x i16> @llvm.riscv.vaadd.mask.nxv4i16.i16(
<vscale x 4 x i16>,
i16,
<vscale x 4 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 4 x i16> @intrinsic_vaadd_mask_vx_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+define <vscale x 4 x i16> @intrinsic_vaadd_mask_vx_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vaadd_mask_vx_nxv4i16_nxv4i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
@@ -1504,7 +1474,7 @@ entry:
<vscale x 4 x i16> %1,
i16 %2,
<vscale x 4 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 4 x i16> %a
}
@@ -1513,9 +1483,9 @@ declare <vscale x 8 x i16> @llvm.riscv.vaadd.nxv8i16.i16(
<vscale x 8 x i16>,
<vscale x 8 x i16>,
i16,
- i32);
+ iXLen);
-define <vscale x 8 x i16> @intrinsic_vaadd_vx_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, i16 %1, i32 %2) nounwind {
+define <vscale x 8 x i16> @intrinsic_vaadd_vx_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, i16 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vaadd_vx_nxv8i16_nxv8i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
@@ -1526,7 +1496,7 @@ entry:
<vscale x 8 x i16> undef,
<vscale x 8 x i16> %0,
i16 %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 8 x i16> %a
}
@@ -1536,10 +1506,9 @@ declare <vscale x 8 x i16> @llvm.riscv.vaadd.mask.nxv8i16.i16(
<vscale x 8 x i16>,
i16,
<vscale x 8 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 8 x i16> @intrinsic_vaadd_mask_vx_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+define <vscale x 8 x i16> @intrinsic_vaadd_mask_vx_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vaadd_mask_vx_nxv8i16_nxv8i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
@@ -1551,7 +1520,7 @@ entry:
<vscale x 8 x i16> %1,
i16 %2,
<vscale x 8 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 8 x i16> %a
}
@@ -1560,9 +1529,9 @@ declare <vscale x 16 x i16> @llvm.riscv.vaadd.nxv16i16.i16(
<vscale x 16 x i16>,
<vscale x 16 x i16>,
i16,
- i32);
+ iXLen);
-define <vscale x 16 x i16> @intrinsic_vaadd_vx_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, i16 %1, i32 %2) nounwind {
+define <vscale x 16 x i16> @intrinsic_vaadd_vx_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, i16 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vaadd_vx_nxv16i16_nxv16i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
@@ -1573,7 +1542,7 @@ entry:
<vscale x 16 x i16> undef,
<vscale x 16 x i16> %0,
i16 %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 16 x i16> %a
}
@@ -1583,10 +1552,9 @@ declare <vscale x 16 x i16> @llvm.riscv.vaadd.mask.nxv16i16.i16(
<vscale x 16 x i16>,
i16,
<vscale x 16 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 16 x i16> @intrinsic_vaadd_mask_vx_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+define <vscale x 16 x i16> @intrinsic_vaadd_mask_vx_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vaadd_mask_vx_nxv16i16_nxv16i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
@@ -1598,7 +1566,7 @@ entry:
<vscale x 16 x i16> %1,
i16 %2,
<vscale x 16 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 16 x i16> %a
}
@@ -1607,9 +1575,9 @@ declare <vscale x 32 x i16> @llvm.riscv.vaadd.nxv32i16.i16(
<vscale x 32 x i16>,
<vscale x 32 x i16>,
i16,
- i32);
+ iXLen);
-define <vscale x 32 x i16> @intrinsic_vaadd_vx_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, i16 %1, i32 %2) nounwind {
+define <vscale x 32 x i16> @intrinsic_vaadd_vx_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, i16 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vaadd_vx_nxv32i16_nxv32i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu
@@ -1620,7 +1588,7 @@ entry:
<vscale x 32 x i16> undef,
<vscale x 32 x i16> %0,
i16 %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 32 x i16> %a
}
@@ -1630,10 +1598,9 @@ declare <vscale x 32 x i16> @llvm.riscv.vaadd.mask.nxv32i16.i16(
<vscale x 32 x i16>,
i16,
<vscale x 32 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 32 x i16> @intrinsic_vaadd_mask_vx_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, i16 %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
+define <vscale x 32 x i16> @intrinsic_vaadd_mask_vx_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, i16 %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vaadd_mask_vx_nxv32i16_nxv32i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu
@@ -1645,7 +1612,7 @@ entry:
<vscale x 32 x i16> %1,
i16 %2,
<vscale x 32 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 32 x i16> %a
}
@@ -1654,9 +1621,9 @@ declare <vscale x 1 x i32> @llvm.riscv.vaadd.nxv1i32.i32(
<vscale x 1 x i32>,
<vscale x 1 x i32>,
i32,
- i32);
+ iXLen);
-define <vscale x 1 x i32> @intrinsic_vaadd_vx_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, i32 %1, i32 %2) nounwind {
+define <vscale x 1 x i32> @intrinsic_vaadd_vx_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, i32 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vaadd_vx_nxv1i32_nxv1i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
@@ -1667,7 +1634,7 @@ entry:
<vscale x 1 x i32> undef,
<vscale x 1 x i32> %0,
i32 %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 1 x i32> %a
}
@@ -1677,10 +1644,9 @@ declare <vscale x 1 x i32> @llvm.riscv.vaadd.mask.nxv1i32.i32(
<vscale x 1 x i32>,
i32,
<vscale x 1 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 1 x i32> @intrinsic_vaadd_mask_vx_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+define <vscale x 1 x i32> @intrinsic_vaadd_mask_vx_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vaadd_mask_vx_nxv1i32_nxv1i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
@@ -1692,7 +1658,7 @@ entry:
<vscale x 1 x i32> %1,
i32 %2,
<vscale x 1 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 1 x i32> %a
}
@@ -1701,9 +1667,9 @@ declare <vscale x 2 x i32> @llvm.riscv.vaadd.nxv2i32.i32(
<vscale x 2 x i32>,
<vscale x 2 x i32>,
i32,
- i32);
+ iXLen);
-define <vscale x 2 x i32> @intrinsic_vaadd_vx_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, i32 %1, i32 %2) nounwind {
+define <vscale x 2 x i32> @intrinsic_vaadd_vx_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, i32 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vaadd_vx_nxv2i32_nxv2i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
@@ -1714,7 +1680,7 @@ entry:
<vscale x 2 x i32> undef,
<vscale x 2 x i32> %0,
i32 %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 2 x i32> %a
}
@@ -1724,10 +1690,9 @@ declare <vscale x 2 x i32> @llvm.riscv.vaadd.mask.nxv2i32.i32(
<vscale x 2 x i32>,
i32,
<vscale x 2 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 2 x i32> @intrinsic_vaadd_mask_vx_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+define <vscale x 2 x i32> @intrinsic_vaadd_mask_vx_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vaadd_mask_vx_nxv2i32_nxv2i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
@@ -1739,7 +1704,7 @@ entry:
<vscale x 2 x i32> %1,
i32 %2,
<vscale x 2 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 2 x i32> %a
}
@@ -1748,9 +1713,9 @@ declare <vscale x 4 x i32> @llvm.riscv.vaadd.nxv4i32.i32(
<vscale x 4 x i32>,
<vscale x 4 x i32>,
i32,
- i32);
+ iXLen);
-define <vscale x 4 x i32> @intrinsic_vaadd_vx_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, i32 %1, i32 %2) nounwind {
+define <vscale x 4 x i32> @intrinsic_vaadd_vx_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, i32 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vaadd_vx_nxv4i32_nxv4i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
@@ -1761,7 +1726,7 @@ entry:
<vscale x 4 x i32> undef,
<vscale x 4 x i32> %0,
i32 %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 4 x i32> %a
}
@@ -1771,10 +1736,9 @@ declare <vscale x 4 x i32> @llvm.riscv.vaadd.mask.nxv4i32.i32(
<vscale x 4 x i32>,
i32,
<vscale x 4 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 4 x i32> @intrinsic_vaadd_mask_vx_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+define <vscale x 4 x i32> @intrinsic_vaadd_mask_vx_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vaadd_mask_vx_nxv4i32_nxv4i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
@@ -1786,7 +1750,7 @@ entry:
<vscale x 4 x i32> %1,
i32 %2,
<vscale x 4 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 4 x i32> %a
}
@@ -1795,9 +1759,9 @@ declare <vscale x 8 x i32> @llvm.riscv.vaadd.nxv8i32.i32(
<vscale x 8 x i32>,
<vscale x 8 x i32>,
i32,
- i32);
+ iXLen);
-define <vscale x 8 x i32> @intrinsic_vaadd_vx_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, i32 %1, i32 %2) nounwind {
+define <vscale x 8 x i32> @intrinsic_vaadd_vx_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, i32 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vaadd_vx_nxv8i32_nxv8i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
@@ -1808,7 +1772,7 @@ entry:
<vscale x 8 x i32> undef,
<vscale x 8 x i32> %0,
i32 %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 8 x i32> %a
}
@@ -1818,10 +1782,9 @@ declare <vscale x 8 x i32> @llvm.riscv.vaadd.mask.nxv8i32.i32(
<vscale x 8 x i32>,
i32,
<vscale x 8 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 8 x i32> @intrinsic_vaadd_mask_vx_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+define <vscale x 8 x i32> @intrinsic_vaadd_mask_vx_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vaadd_mask_vx_nxv8i32_nxv8i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
@@ -1833,7 +1796,7 @@ entry:
<vscale x 8 x i32> %1,
i32 %2,
<vscale x 8 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 8 x i32> %a
}
@@ -1842,9 +1805,9 @@ declare <vscale x 16 x i32> @llvm.riscv.vaadd.nxv16i32.i32(
<vscale x 16 x i32>,
<vscale x 16 x i32>,
i32,
- i32);
+ iXLen);
-define <vscale x 16 x i32> @intrinsic_vaadd_vx_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, i32 %1, i32 %2) nounwind {
+define <vscale x 16 x i32> @intrinsic_vaadd_vx_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, i32 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vaadd_vx_nxv16i32_nxv16i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu
@@ -1855,7 +1818,7 @@ entry:
<vscale x 16 x i32> undef,
<vscale x 16 x i32> %0,
i32 %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 16 x i32> %a
}
@@ -1865,10 +1828,9 @@ declare <vscale x 16 x i32> @llvm.riscv.vaadd.mask.nxv16i32.i32(
<vscale x 16 x i32>,
i32,
<vscale x 16 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 16 x i32> @intrinsic_vaadd_mask_vx_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+define <vscale x 16 x i32> @intrinsic_vaadd_mask_vx_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vaadd_mask_vx_nxv16i32_nxv16i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu
@@ -1880,7 +1842,7 @@ entry:
<vscale x 16 x i32> %1,
i32 %2,
<vscale x 16 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 16 x i32> %a
}
@@ -1889,26 +1851,32 @@ declare <vscale x 1 x i64> @llvm.riscv.vaadd.nxv1i64.i64(
<vscale x 1 x i64>,
<vscale x 1 x i64>,
i64,
- i32);
-
-define <vscale x 1 x i64> @intrinsic_vaadd_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vaadd_vx_nxv1i64_nxv1i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addi sp, sp, -16
-; CHECK-NEXT: sw a1, 12(sp)
-; CHECK-NEXT: sw a0, 8(sp)
-; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
-; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v9, (a0), zero
-; CHECK-NEXT: vaadd.vv v8, v8, v9
-; CHECK-NEXT: addi sp, sp, 16
-; CHECK-NEXT: ret
+ iXLen);
+
+define <vscale x 1 x i64> @intrinsic_vaadd_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, iXLen %2) nounwind {
+; RV32-LABEL: intrinsic_vaadd_vx_nxv1i64_nxv1i64_i64:
+; RV32: # %bb.0: # %entry
+; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: sw a1, 12(sp)
+; RV32-NEXT: sw a0, 8(sp)
+; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
+; RV32-NEXT: addi a0, sp, 8
+; RV32-NEXT: vlse64.v v9, (a0), zero
+; RV32-NEXT: vaadd.vv v8, v8, v9
+; RV32-NEXT: addi sp, sp, 16
+; RV32-NEXT: ret
+;
+; RV64-LABEL: intrinsic_vaadd_vx_nxv1i64_nxv1i64_i64:
+; RV64: # %bb.0: # %entry
+; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, mu
+; RV64-NEXT: vaadd.vx v8, v8, a0
+; RV64-NEXT: ret
entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vaadd.nxv1i64.i64(
<vscale x 1 x i64> undef,
<vscale x 1 x i64> %0,
i64 %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 1 x i64> %a
}
@@ -1918,28 +1886,33 @@ declare <vscale x 1 x i64> @llvm.riscv.vaadd.mask.nxv1i64.i64(
<vscale x 1 x i64>,
i64,
<vscale x 1 x i1>,
- i32,
- i32);
-
-define <vscale x 1 x i64> @intrinsic_vaadd_mask_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vaadd_mask_vx_nxv1i64_nxv1i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addi sp, sp, -16
-; CHECK-NEXT: sw a1, 12(sp)
-; CHECK-NEXT: sw a0, 8(sp)
-; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
-; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v10, (a0), zero
-; CHECK-NEXT: vaadd.vv v8, v9, v10, v0.t
-; CHECK-NEXT: addi sp, sp, 16
-; CHECK-NEXT: ret
+ iXLen, iXLen);
+
+define <vscale x 1 x i64> @intrinsic_vaadd_mask_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
+; RV32-LABEL: intrinsic_vaadd_mask_vx_nxv1i64_nxv1i64_i64:
+; RV32: # %bb.0: # %entry
+; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: sw a1, 12(sp)
+; RV32-NEXT: sw a0, 8(sp)
+; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
+; RV32-NEXT: addi a0, sp, 8
+; RV32-NEXT: vlse64.v v10, (a0), zero
+; RV32-NEXT: vaadd.vv v8, v9, v10, v0.t
+; RV32-NEXT: addi sp, sp, 16
+; RV32-NEXT: ret
+;
+; RV64-LABEL: intrinsic_vaadd_mask_vx_nxv1i64_nxv1i64_i64:
+; RV64: # %bb.0: # %entry
+; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, mu
+; RV64-NEXT: vaadd.vx v8, v9, a0, v0.t
+; RV64-NEXT: ret
entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vaadd.mask.nxv1i64.i64(
<vscale x 1 x i64> %0,
<vscale x 1 x i64> %1,
i64 %2,
<vscale x 1 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 1 x i64> %a
}
@@ -1948,26 +1921,32 @@ declare <vscale x 2 x i64> @llvm.riscv.vaadd.nxv2i64.i64(
<vscale x 2 x i64>,
<vscale x 2 x i64>,
i64,
- i32);
-
-define <vscale x 2 x i64> @intrinsic_vaadd_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vaadd_vx_nxv2i64_nxv2i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addi sp, sp, -16
-; CHECK-NEXT: sw a1, 12(sp)
-; CHECK-NEXT: sw a0, 8(sp)
-; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
-; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v10, (a0), zero
-; CHECK-NEXT: vaadd.vv v8, v8, v10
-; CHECK-NEXT: addi sp, sp, 16
-; CHECK-NEXT: ret
+ iXLen);
+
+define <vscale x 2 x i64> @intrinsic_vaadd_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, iXLen %2) nounwind {
+; RV32-LABEL: intrinsic_vaadd_vx_nxv2i64_nxv2i64_i64:
+; RV32: # %bb.0: # %entry
+; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: sw a1, 12(sp)
+; RV32-NEXT: sw a0, 8(sp)
+; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
+; RV32-NEXT: addi a0, sp, 8
+; RV32-NEXT: vlse64.v v10, (a0), zero
+; RV32-NEXT: vaadd.vv v8, v8, v10
+; RV32-NEXT: addi sp, sp, 16
+; RV32-NEXT: ret
+;
+; RV64-LABEL: intrinsic_vaadd_vx_nxv2i64_nxv2i64_i64:
+; RV64: # %bb.0: # %entry
+; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, mu
+; RV64-NEXT: vaadd.vx v8, v8, a0
+; RV64-NEXT: ret
entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vaadd.nxv2i64.i64(
<vscale x 2 x i64> undef,
<vscale x 2 x i64> %0,
i64 %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 2 x i64> %a
}
@@ -1977,28 +1956,33 @@ declare <vscale x 2 x i64> @llvm.riscv.vaadd.mask.nxv2i64.i64(
<vscale x 2 x i64>,
i64,
<vscale x 2 x i1>,
- i32,
- i32);
-
-define <vscale x 2 x i64> @intrinsic_vaadd_mask_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vaadd_mask_vx_nxv2i64_nxv2i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addi sp, sp, -16
-; CHECK-NEXT: sw a1, 12(sp)
-; CHECK-NEXT: sw a0, 8(sp)
-; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
-; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v12, (a0), zero
-; CHECK-NEXT: vaadd.vv v8, v10, v12, v0.t
-; CHECK-NEXT: addi sp, sp, 16
-; CHECK-NEXT: ret
+ iXLen, iXLen);
+
+define <vscale x 2 x i64> @intrinsic_vaadd_mask_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
+; RV32-LABEL: intrinsic_vaadd_mask_vx_nxv2i64_nxv2i64_i64:
+; RV32: # %bb.0: # %entry
+; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: sw a1, 12(sp)
+; RV32-NEXT: sw a0, 8(sp)
+; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
+; RV32-NEXT: addi a0, sp, 8
+; RV32-NEXT: vlse64.v v12, (a0), zero
+; RV32-NEXT: vaadd.vv v8, v10, v12, v0.t
+; RV32-NEXT: addi sp, sp, 16
+; RV32-NEXT: ret
+;
+; RV64-LABEL: intrinsic_vaadd_mask_vx_nxv2i64_nxv2i64_i64:
+; RV64: # %bb.0: # %entry
+; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, mu
+; RV64-NEXT: vaadd.vx v8, v10, a0, v0.t
+; RV64-NEXT: ret
entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vaadd.mask.nxv2i64.i64(
<vscale x 2 x i64> %0,
<vscale x 2 x i64> %1,
i64 %2,
<vscale x 2 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 2 x i64> %a
}
@@ -2007,26 +1991,32 @@ declare <vscale x 4 x i64> @llvm.riscv.vaadd.nxv4i64.i64(
<vscale x 4 x i64>,
<vscale x 4 x i64>,
i64,
- i32);
-
-define <vscale x 4 x i64> @intrinsic_vaadd_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vaadd_vx_nxv4i64_nxv4i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addi sp, sp, -16
-; CHECK-NEXT: sw a1, 12(sp)
-; CHECK-NEXT: sw a0, 8(sp)
-; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
-; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v12, (a0), zero
-; CHECK-NEXT: vaadd.vv v8, v8, v12
-; CHECK-NEXT: addi sp, sp, 16
-; CHECK-NEXT: ret
+ iXLen);
+
+define <vscale x 4 x i64> @intrinsic_vaadd_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, iXLen %2) nounwind {
+; RV32-LABEL: intrinsic_vaadd_vx_nxv4i64_nxv4i64_i64:
+; RV32: # %bb.0: # %entry
+; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: sw a1, 12(sp)
+; RV32-NEXT: sw a0, 8(sp)
+; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
+; RV32-NEXT: addi a0, sp, 8
+; RV32-NEXT: vlse64.v v12, (a0), zero
+; RV32-NEXT: vaadd.vv v8, v8, v12
+; RV32-NEXT: addi sp, sp, 16
+; RV32-NEXT: ret
+;
+; RV64-LABEL: intrinsic_vaadd_vx_nxv4i64_nxv4i64_i64:
+; RV64: # %bb.0: # %entry
+; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu
+; RV64-NEXT: vaadd.vx v8, v8, a0
+; RV64-NEXT: ret
entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vaadd.nxv4i64.i64(
<vscale x 4 x i64> undef,
<vscale x 4 x i64> %0,
i64 %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 4 x i64> %a
}
@@ -2036,28 +2026,33 @@ declare <vscale x 4 x i64> @llvm.riscv.vaadd.mask.nxv4i64.i64(
<vscale x 4 x i64>,
i64,
<vscale x 4 x i1>,
- i32,
- i32);
-
-define <vscale x 4 x i64> @intrinsic_vaadd_mask_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vaadd_mask_vx_nxv4i64_nxv4i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addi sp, sp, -16
-; CHECK-NEXT: sw a1, 12(sp)
-; CHECK-NEXT: sw a0, 8(sp)
-; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
-; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v16, (a0), zero
-; CHECK-NEXT: vaadd.vv v8, v12, v16, v0.t
-; CHECK-NEXT: addi sp, sp, 16
-; CHECK-NEXT: ret
+ iXLen, iXLen);
+
+define <vscale x 4 x i64> @intrinsic_vaadd_mask_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
+; RV32-LABEL: intrinsic_vaadd_mask_vx_nxv4i64_nxv4i64_i64:
+; RV32: # %bb.0: # %entry
+; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: sw a1, 12(sp)
+; RV32-NEXT: sw a0, 8(sp)
+; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
+; RV32-NEXT: addi a0, sp, 8
+; RV32-NEXT: vlse64.v v16, (a0), zero
+; RV32-NEXT: vaadd.vv v8, v12, v16, v0.t
+; RV32-NEXT: addi sp, sp, 16
+; RV32-NEXT: ret
+;
+; RV64-LABEL: intrinsic_vaadd_mask_vx_nxv4i64_nxv4i64_i64:
+; RV64: # %bb.0: # %entry
+; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu
+; RV64-NEXT: vaadd.vx v8, v12, a0, v0.t
+; RV64-NEXT: ret
entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vaadd.mask.nxv4i64.i64(
<vscale x 4 x i64> %0,
<vscale x 4 x i64> %1,
i64 %2,
<vscale x 4 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 4 x i64> %a
}
@@ -2066,26 +2061,32 @@ declare <vscale x 8 x i64> @llvm.riscv.vaadd.nxv8i64.i64(
<vscale x 8 x i64>,
<vscale x 8 x i64>,
i64,
- i32);
-
-define <vscale x 8 x i64> @intrinsic_vaadd_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, i64 %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vaadd_vx_nxv8i64_nxv8i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addi sp, sp, -16
-; CHECK-NEXT: sw a1, 12(sp)
-; CHECK-NEXT: sw a0, 8(sp)
-; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, mu
-; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v16, (a0), zero
-; CHECK-NEXT: vaadd.vv v8, v8, v16
-; CHECK-NEXT: addi sp, sp, 16
-; CHECK-NEXT: ret
+ iXLen);
+
+define <vscale x 8 x i64> @intrinsic_vaadd_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, i64 %1, iXLen %2) nounwind {
+; RV32-LABEL: intrinsic_vaadd_vx_nxv8i64_nxv8i64_i64:
+; RV32: # %bb.0: # %entry
+; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: sw a1, 12(sp)
+; RV32-NEXT: sw a0, 8(sp)
+; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu
+; RV32-NEXT: addi a0, sp, 8
+; RV32-NEXT: vlse64.v v16, (a0), zero
+; RV32-NEXT: vaadd.vv v8, v8, v16
+; RV32-NEXT: addi sp, sp, 16
+; RV32-NEXT: ret
+;
+; RV64-LABEL: intrinsic_vaadd_vx_nxv8i64_nxv8i64_i64:
+; RV64: # %bb.0: # %entry
+; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, mu
+; RV64-NEXT: vaadd.vx v8, v8, a0
+; RV64-NEXT: ret
entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vaadd.nxv8i64.i64(
<vscale x 8 x i64> undef,
<vscale x 8 x i64> %0,
i64 %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 8 x i64> %a
}
@@ -2095,28 +2096,33 @@ declare <vscale x 8 x i64> @llvm.riscv.vaadd.mask.nxv8i64.i64(
<vscale x 8 x i64>,
i64,
<vscale x 8 x i1>,
- i32,
- i32);
-
-define <vscale x 8 x i64> @intrinsic_vaadd_mask_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vaadd_mask_vx_nxv8i64_nxv8i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addi sp, sp, -16
-; CHECK-NEXT: sw a1, 12(sp)
-; CHECK-NEXT: sw a0, 8(sp)
-; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, mu
-; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v24, (a0), zero
-; CHECK-NEXT: vaadd.vv v8, v16, v24, v0.t
-; CHECK-NEXT: addi sp, sp, 16
-; CHECK-NEXT: ret
+ iXLen, iXLen);
+
+define <vscale x 8 x i64> @intrinsic_vaadd_mask_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
+; RV32-LABEL: intrinsic_vaadd_mask_vx_nxv8i64_nxv8i64_i64:
+; RV32: # %bb.0: # %entry
+; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: sw a1, 12(sp)
+; RV32-NEXT: sw a0, 8(sp)
+; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu
+; RV32-NEXT: addi a0, sp, 8
+; RV32-NEXT: vlse64.v v24, (a0), zero
+; RV32-NEXT: vaadd.vv v8, v16, v24, v0.t
+; RV32-NEXT: addi sp, sp, 16
+; RV32-NEXT: ret
+;
+; RV64-LABEL: intrinsic_vaadd_mask_vx_nxv8i64_nxv8i64_i64:
+; RV64: # %bb.0: # %entry
+; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, mu
+; RV64-NEXT: vaadd.vx v8, v16, a0, v0.t
+; RV64-NEXT: ret
entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vaadd.mask.nxv8i64.i64(
<vscale x 8 x i64> %0,
<vscale x 8 x i64> %1,
i64 %2,
<vscale x 8 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 8 x i64> %a
}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vaaddu-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vaaddu-rv32.ll
deleted file mode 100644
index 5d8b24ed84866..0000000000000
--- a/llvm/test/CodeGen/RISCV/rvv/vaaddu-rv32.ll
+++ /dev/null
@@ -1,2122 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs \
-; RUN: < %s | FileCheck %s
-declare <vscale x 1 x i8> @llvm.riscv.vaaddu.nxv1i8.nxv1i8(
- <vscale x 1 x i8>,
- <vscale x 1 x i8>,
- <vscale x 1 x i8>,
- i32);
-
-define <vscale x 1 x i8> @intrinsic_vaaddu_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vaaddu_vv_nxv1i8_nxv1i8_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
-; CHECK-NEXT: vaaddu.vv v8, v8, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i8> @llvm.riscv.vaaddu.nxv1i8.nxv1i8(
- <vscale x 1 x i8> undef,
- <vscale x 1 x i8> %0,
- <vscale x 1 x i8> %1,
- i32 %2)
-
- ret <vscale x 1 x i8> %a
-}
-
-declare <vscale x 1 x i8> @llvm.riscv.vaaddu.mask.nxv1i8.nxv1i8(
- <vscale x 1 x i8>,
- <vscale x 1 x i8>,
- <vscale x 1 x i8>,
- <vscale x 1 x i1>,
- i32,
- i32);
-
-define <vscale x 1 x i8> @intrinsic_vaaddu_mask_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv1i8_nxv1i8_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
-; CHECK-NEXT: vaaddu.vv v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i8> @llvm.riscv.vaaddu.mask.nxv1i8.nxv1i8(
- <vscale x 1 x i8> %0,
- <vscale x 1 x i8> %1,
- <vscale x 1 x i8> %2,
- <vscale x 1 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 1 x i8> %a
-}
-
-declare <vscale x 2 x i8> @llvm.riscv.vaaddu.nxv2i8.nxv2i8(
- <vscale x 2 x i8>,
- <vscale x 2 x i8>,
- <vscale x 2 x i8>,
- i32);
-
-define <vscale x 2 x i8> @intrinsic_vaaddu_vv_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vaaddu_vv_nxv2i8_nxv2i8_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
-; CHECK-NEXT: vaaddu.vv v8, v8, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i8> @llvm.riscv.vaaddu.nxv2i8.nxv2i8(
- <vscale x 2 x i8> undef,
- <vscale x 2 x i8> %0,
- <vscale x 2 x i8> %1,
- i32 %2)
-
- ret <vscale x 2 x i8> %a
-}
-
-declare <vscale x 2 x i8> @llvm.riscv.vaaddu.mask.nxv2i8.nxv2i8(
- <vscale x 2 x i8>,
- <vscale x 2 x i8>,
- <vscale x 2 x i8>,
- <vscale x 2 x i1>,
- i32,
- i32);
-
-define <vscale x 2 x i8> @intrinsic_vaaddu_mask_vv_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv2i8_nxv2i8_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
-; CHECK-NEXT: vaaddu.vv v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i8> @llvm.riscv.vaaddu.mask.nxv2i8.nxv2i8(
- <vscale x 2 x i8> %0,
- <vscale x 2 x i8> %1,
- <vscale x 2 x i8> %2,
- <vscale x 2 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 2 x i8> %a
-}
-
-declare <vscale x 4 x i8> @llvm.riscv.vaaddu.nxv4i8.nxv4i8(
- <vscale x 4 x i8>,
- <vscale x 4 x i8>,
- <vscale x 4 x i8>,
- i32);
-
-define <vscale x 4 x i8> @intrinsic_vaaddu_vv_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vaaddu_vv_nxv4i8_nxv4i8_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
-; CHECK-NEXT: vaaddu.vv v8, v8, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i8> @llvm.riscv.vaaddu.nxv4i8.nxv4i8(
- <vscale x 4 x i8> undef,
- <vscale x 4 x i8> %0,
- <vscale x 4 x i8> %1,
- i32 %2)
-
- ret <vscale x 4 x i8> %a
-}
-
-declare <vscale x 4 x i8> @llvm.riscv.vaaddu.mask.nxv4i8.nxv4i8(
- <vscale x 4 x i8>,
- <vscale x 4 x i8>,
- <vscale x 4 x i8>,
- <vscale x 4 x i1>,
- i32,
- i32);
-
-define <vscale x 4 x i8> @intrinsic_vaaddu_mask_vv_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv4i8_nxv4i8_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
-; CHECK-NEXT: vaaddu.vv v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i8> @llvm.riscv.vaaddu.mask.nxv4i8.nxv4i8(
- <vscale x 4 x i8> %0,
- <vscale x 4 x i8> %1,
- <vscale x 4 x i8> %2,
- <vscale x 4 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 4 x i8> %a
-}
-
-declare <vscale x 8 x i8> @llvm.riscv.vaaddu.nxv8i8.nxv8i8(
- <vscale x 8 x i8>,
- <vscale x 8 x i8>,
- <vscale x 8 x i8>,
- i32);
-
-define <vscale x 8 x i8> @intrinsic_vaaddu_vv_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vaaddu_vv_nxv8i8_nxv8i8_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
-; CHECK-NEXT: vaaddu.vv v8, v8, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i8> @llvm.riscv.vaaddu.nxv8i8.nxv8i8(
- <vscale x 8 x i8> undef,
- <vscale x 8 x i8> %0,
- <vscale x 8 x i8> %1,
- i32 %2)
-
- ret <vscale x 8 x i8> %a
-}
-
-declare <vscale x 8 x i8> @llvm.riscv.vaaddu.mask.nxv8i8.nxv8i8(
- <vscale x 8 x i8>,
- <vscale x 8 x i8>,
- <vscale x 8 x i8>,
- <vscale x 8 x i1>,
- i32,
- i32);
-
-define <vscale x 8 x i8> @intrinsic_vaaddu_mask_vv_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv8i8_nxv8i8_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
-; CHECK-NEXT: vaaddu.vv v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i8> @llvm.riscv.vaaddu.mask.nxv8i8.nxv8i8(
- <vscale x 8 x i8> %0,
- <vscale x 8 x i8> %1,
- <vscale x 8 x i8> %2,
- <vscale x 8 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 8 x i8> %a
-}
-
-declare <vscale x 16 x i8> @llvm.riscv.vaaddu.nxv16i8.nxv16i8(
- <vscale x 16 x i8>,
- <vscale x 16 x i8>,
- <vscale x 16 x i8>,
- i32);
-
-define <vscale x 16 x i8> @intrinsic_vaaddu_vv_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vaaddu_vv_nxv16i8_nxv16i8_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
-; CHECK-NEXT: vaaddu.vv v8, v8, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i8> @llvm.riscv.vaaddu.nxv16i8.nxv16i8(
- <vscale x 16 x i8> undef,
- <vscale x 16 x i8> %0,
- <vscale x 16 x i8> %1,
- i32 %2)
-
- ret <vscale x 16 x i8> %a
-}
-
-declare <vscale x 16 x i8> @llvm.riscv.vaaddu.mask.nxv16i8.nxv16i8(
- <vscale x 16 x i8>,
- <vscale x 16 x i8>,
- <vscale x 16 x i8>,
- <vscale x 16 x i1>,
- i32,
- i32);
-
-define <vscale x 16 x i8> @intrinsic_vaaddu_mask_vv_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv16i8_nxv16i8_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
-; CHECK-NEXT: vaaddu.vv v8, v10, v12, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i8> @llvm.riscv.vaaddu.mask.nxv16i8.nxv16i8(
- <vscale x 16 x i8> %0,
- <vscale x 16 x i8> %1,
- <vscale x 16 x i8> %2,
- <vscale x 16 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 16 x i8> %a
-}
-
-declare <vscale x 32 x i8> @llvm.riscv.vaaddu.nxv32i8.nxv32i8(
- <vscale x 32 x i8>,
- <vscale x 32 x i8>,
- <vscale x 32 x i8>,
- i32);
-
-define <vscale x 32 x i8> @intrinsic_vaaddu_vv_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vaaddu_vv_nxv32i8_nxv32i8_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
-; CHECK-NEXT: vaaddu.vv v8, v8, v12
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 32 x i8> @llvm.riscv.vaaddu.nxv32i8.nxv32i8(
- <vscale x 32 x i8> undef,
- <vscale x 32 x i8> %0,
- <vscale x 32 x i8> %1,
- i32 %2)
-
- ret <vscale x 32 x i8> %a
-}
-
-declare <vscale x 32 x i8> @llvm.riscv.vaaddu.mask.nxv32i8.nxv32i8(
- <vscale x 32 x i8>,
- <vscale x 32 x i8>,
- <vscale x 32 x i8>,
- <vscale x 32 x i1>,
- i32,
- i32);
-
-define <vscale x 32 x i8> @intrinsic_vaaddu_mask_vv_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv32i8_nxv32i8_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
-; CHECK-NEXT: vaaddu.vv v8, v12, v16, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 32 x i8> @llvm.riscv.vaaddu.mask.nxv32i8.nxv32i8(
- <vscale x 32 x i8> %0,
- <vscale x 32 x i8> %1,
- <vscale x 32 x i8> %2,
- <vscale x 32 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 32 x i8> %a
-}
-
-declare <vscale x 64 x i8> @llvm.riscv.vaaddu.nxv64i8.nxv64i8(
- <vscale x 64 x i8>,
- <vscale x 64 x i8>,
- <vscale x 64 x i8>,
- i32);
-
-define <vscale x 64 x i8> @intrinsic_vaaddu_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vaaddu_vv_nxv64i8_nxv64i8_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, mu
-; CHECK-NEXT: vaaddu.vv v8, v8, v16
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 64 x i8> @llvm.riscv.vaaddu.nxv64i8.nxv64i8(
- <vscale x 64 x i8> undef,
- <vscale x 64 x i8> %0,
- <vscale x 64 x i8> %1,
- i32 %2)
-
- ret <vscale x 64 x i8> %a
-}
-
-declare <vscale x 64 x i8> @llvm.riscv.vaaddu.mask.nxv64i8.nxv64i8(
- <vscale x 64 x i8>,
- <vscale x 64 x i8>,
- <vscale x 64 x i8>,
- <vscale x 64 x i1>,
- i32,
- i32);
-
-define <vscale x 64 x i8> @intrinsic_vaaddu_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv64i8_nxv64i8_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vl8r.v v24, (a0)
-; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu
-; CHECK-NEXT: vaaddu.vv v8, v16, v24, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 64 x i8> @llvm.riscv.vaaddu.mask.nxv64i8.nxv64i8(
- <vscale x 64 x i8> %0,
- <vscale x 64 x i8> %1,
- <vscale x 64 x i8> %2,
- <vscale x 64 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 64 x i8> %a
-}
-
-declare <vscale x 1 x i16> @llvm.riscv.vaaddu.nxv1i16.nxv1i16(
- <vscale x 1 x i16>,
- <vscale x 1 x i16>,
- <vscale x 1 x i16>,
- i32);
-
-define <vscale x 1 x i16> @intrinsic_vaaddu_vv_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vaaddu_vv_nxv1i16_nxv1i16_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vaaddu.vv v8, v8, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i16> @llvm.riscv.vaaddu.nxv1i16.nxv1i16(
- <vscale x 1 x i16> undef,
- <vscale x 1 x i16> %0,
- <vscale x 1 x i16> %1,
- i32 %2)
-
- ret <vscale x 1 x i16> %a
-}
-
-declare <vscale x 1 x i16> @llvm.riscv.vaaddu.mask.nxv1i16.nxv1i16(
- <vscale x 1 x i16>,
- <vscale x 1 x i16>,
- <vscale x 1 x i16>,
- <vscale x 1 x i1>,
- i32,
- i32);
-
-define <vscale x 1 x i16> @intrinsic_vaaddu_mask_vv_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv1i16_nxv1i16_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vaaddu.vv v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i16> @llvm.riscv.vaaddu.mask.nxv1i16.nxv1i16(
- <vscale x 1 x i16> %0,
- <vscale x 1 x i16> %1,
- <vscale x 1 x i16> %2,
- <vscale x 1 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 1 x i16> %a
-}
-
-declare <vscale x 2 x i16> @llvm.riscv.vaaddu.nxv2i16.nxv2i16(
- <vscale x 2 x i16>,
- <vscale x 2 x i16>,
- <vscale x 2 x i16>,
- i32);
-
-define <vscale x 2 x i16> @intrinsic_vaaddu_vv_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vaaddu_vv_nxv2i16_nxv2i16_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vaaddu.vv v8, v8, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i16> @llvm.riscv.vaaddu.nxv2i16.nxv2i16(
- <vscale x 2 x i16> undef,
- <vscale x 2 x i16> %0,
- <vscale x 2 x i16> %1,
- i32 %2)
-
- ret <vscale x 2 x i16> %a
-}
-
-declare <vscale x 2 x i16> @llvm.riscv.vaaddu.mask.nxv2i16.nxv2i16(
- <vscale x 2 x i16>,
- <vscale x 2 x i16>,
- <vscale x 2 x i16>,
- <vscale x 2 x i1>,
- i32,
- i32);
-
-define <vscale x 2 x i16> @intrinsic_vaaddu_mask_vv_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv2i16_nxv2i16_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vaaddu.vv v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i16> @llvm.riscv.vaaddu.mask.nxv2i16.nxv2i16(
- <vscale x 2 x i16> %0,
- <vscale x 2 x i16> %1,
- <vscale x 2 x i16> %2,
- <vscale x 2 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 2 x i16> %a
-}
-
-declare <vscale x 4 x i16> @llvm.riscv.vaaddu.nxv4i16.nxv4i16(
- <vscale x 4 x i16>,
- <vscale x 4 x i16>,
- <vscale x 4 x i16>,
- i32);
-
-define <vscale x 4 x i16> @intrinsic_vaaddu_vv_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vaaddu_vv_nxv4i16_nxv4i16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vaaddu.vv v8, v8, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i16> @llvm.riscv.vaaddu.nxv4i16.nxv4i16(
- <vscale x 4 x i16> undef,
- <vscale x 4 x i16> %0,
- <vscale x 4 x i16> %1,
- i32 %2)
-
- ret <vscale x 4 x i16> %a
-}
-
-declare <vscale x 4 x i16> @llvm.riscv.vaaddu.mask.nxv4i16.nxv4i16(
- <vscale x 4 x i16>,
- <vscale x 4 x i16>,
- <vscale x 4 x i16>,
- <vscale x 4 x i1>,
- i32,
- i32);
-
-define <vscale x 4 x i16> @intrinsic_vaaddu_mask_vv_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv4i16_nxv4i16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vaaddu.vv v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i16> @llvm.riscv.vaaddu.mask.nxv4i16.nxv4i16(
- <vscale x 4 x i16> %0,
- <vscale x 4 x i16> %1,
- <vscale x 4 x i16> %2,
- <vscale x 4 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 4 x i16> %a
-}
-
-declare <vscale x 8 x i16> @llvm.riscv.vaaddu.nxv8i16.nxv8i16(
- <vscale x 8 x i16>,
- <vscale x 8 x i16>,
- <vscale x 8 x i16>,
- i32);
-
-define <vscale x 8 x i16> @intrinsic_vaaddu_vv_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vaaddu_vv_nxv8i16_nxv8i16_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vaaddu.vv v8, v8, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i16> @llvm.riscv.vaaddu.nxv8i16.nxv8i16(
- <vscale x 8 x i16> undef,
- <vscale x 8 x i16> %0,
- <vscale x 8 x i16> %1,
- i32 %2)
-
- ret <vscale x 8 x i16> %a
-}
-
-declare <vscale x 8 x i16> @llvm.riscv.vaaddu.mask.nxv8i16.nxv8i16(
- <vscale x 8 x i16>,
- <vscale x 8 x i16>,
- <vscale x 8 x i16>,
- <vscale x 8 x i1>,
- i32,
- i32);
-
-define <vscale x 8 x i16> @intrinsic_vaaddu_mask_vv_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv8i16_nxv8i16_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vaaddu.vv v8, v10, v12, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i16> @llvm.riscv.vaaddu.mask.nxv8i16.nxv8i16(
- <vscale x 8 x i16> %0,
- <vscale x 8 x i16> %1,
- <vscale x 8 x i16> %2,
- <vscale x 8 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 8 x i16> %a
-}
-
-declare <vscale x 16 x i16> @llvm.riscv.vaaddu.nxv16i16.nxv16i16(
- <vscale x 16 x i16>,
- <vscale x 16 x i16>,
- <vscale x 16 x i16>,
- i32);
-
-define <vscale x 16 x i16> @intrinsic_vaaddu_vv_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vaaddu_vv_nxv16i16_nxv16i16_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
-; CHECK-NEXT: vaaddu.vv v8, v8, v12
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i16> @llvm.riscv.vaaddu.nxv16i16.nxv16i16(
- <vscale x 16 x i16> undef,
- <vscale x 16 x i16> %0,
- <vscale x 16 x i16> %1,
- i32 %2)
-
- ret <vscale x 16 x i16> %a
-}
-
-declare <vscale x 16 x i16> @llvm.riscv.vaaddu.mask.nxv16i16.nxv16i16(
- <vscale x 16 x i16>,
- <vscale x 16 x i16>,
- <vscale x 16 x i16>,
- <vscale x 16 x i1>,
- i32,
- i32);
-
-define <vscale x 16 x i16> @intrinsic_vaaddu_mask_vv_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv16i16_nxv16i16_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
-; CHECK-NEXT: vaaddu.vv v8, v12, v16, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i16> @llvm.riscv.vaaddu.mask.nxv16i16.nxv16i16(
- <vscale x 16 x i16> %0,
- <vscale x 16 x i16> %1,
- <vscale x 16 x i16> %2,
- <vscale x 16 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 16 x i16> %a
-}
-
-declare <vscale x 32 x i16> @llvm.riscv.vaaddu.nxv32i16.nxv32i16(
- <vscale x 32 x i16>,
- <vscale x 32 x i16>,
- <vscale x 32 x i16>,
- i32);
-
-define <vscale x 32 x i16> @intrinsic_vaaddu_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vaaddu_vv_nxv32i16_nxv32i16_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, mu
-; CHECK-NEXT: vaaddu.vv v8, v8, v16
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 32 x i16> @llvm.riscv.vaaddu.nxv32i16.nxv32i16(
- <vscale x 32 x i16> undef,
- <vscale x 32 x i16> %0,
- <vscale x 32 x i16> %1,
- i32 %2)
-
- ret <vscale x 32 x i16> %a
-}
-
-declare <vscale x 32 x i16> @llvm.riscv.vaaddu.mask.nxv32i16.nxv32i16(
- <vscale x 32 x i16>,
- <vscale x 32 x i16>,
- <vscale x 32 x i16>,
- <vscale x 32 x i1>,
- i32,
- i32);
-
-define <vscale x 32 x i16> @intrinsic_vaaddu_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv32i16_nxv32i16_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vl8re16.v v24, (a0)
-; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu
-; CHECK-NEXT: vaaddu.vv v8, v16, v24, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 32 x i16> @llvm.riscv.vaaddu.mask.nxv32i16.nxv32i16(
- <vscale x 32 x i16> %0,
- <vscale x 32 x i16> %1,
- <vscale x 32 x i16> %2,
- <vscale x 32 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 32 x i16> %a
-}
-
-declare <vscale x 1 x i32> @llvm.riscv.vaaddu.nxv1i32.nxv1i32(
- <vscale x 1 x i32>,
- <vscale x 1 x i32>,
- <vscale x 1 x i32>,
- i32);
-
-define <vscale x 1 x i32> @intrinsic_vaaddu_vv_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vaaddu_vv_nxv1i32_nxv1i32_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vaaddu.vv v8, v8, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i32> @llvm.riscv.vaaddu.nxv1i32.nxv1i32(
- <vscale x 1 x i32> undef,
- <vscale x 1 x i32> %0,
- <vscale x 1 x i32> %1,
- i32 %2)
-
- ret <vscale x 1 x i32> %a
-}
-
-declare <vscale x 1 x i32> @llvm.riscv.vaaddu.mask.nxv1i32.nxv1i32(
- <vscale x 1 x i32>,
- <vscale x 1 x i32>,
- <vscale x 1 x i32>,
- <vscale x 1 x i1>,
- i32,
- i32);
-
-define <vscale x 1 x i32> @intrinsic_vaaddu_mask_vv_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv1i32_nxv1i32_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vaaddu.vv v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i32> @llvm.riscv.vaaddu.mask.nxv1i32.nxv1i32(
- <vscale x 1 x i32> %0,
- <vscale x 1 x i32> %1,
- <vscale x 1 x i32> %2,
- <vscale x 1 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 1 x i32> %a
-}
-
-declare <vscale x 2 x i32> @llvm.riscv.vaaddu.nxv2i32.nxv2i32(
- <vscale x 2 x i32>,
- <vscale x 2 x i32>,
- <vscale x 2 x i32>,
- i32);
-
-define <vscale x 2 x i32> @intrinsic_vaaddu_vv_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vaaddu_vv_nxv2i32_nxv2i32_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vaaddu.vv v8, v8, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i32> @llvm.riscv.vaaddu.nxv2i32.nxv2i32(
- <vscale x 2 x i32> undef,
- <vscale x 2 x i32> %0,
- <vscale x 2 x i32> %1,
- i32 %2)
-
- ret <vscale x 2 x i32> %a
-}
-
-declare <vscale x 2 x i32> @llvm.riscv.vaaddu.mask.nxv2i32.nxv2i32(
- <vscale x 2 x i32>,
- <vscale x 2 x i32>,
- <vscale x 2 x i32>,
- <vscale x 2 x i1>,
- i32,
- i32);
-
-define <vscale x 2 x i32> @intrinsic_vaaddu_mask_vv_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv2i32_nxv2i32_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vaaddu.vv v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i32> @llvm.riscv.vaaddu.mask.nxv2i32.nxv2i32(
- <vscale x 2 x i32> %0,
- <vscale x 2 x i32> %1,
- <vscale x 2 x i32> %2,
- <vscale x 2 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 2 x i32> %a
-}
-
-declare <vscale x 4 x i32> @llvm.riscv.vaaddu.nxv4i32.nxv4i32(
- <vscale x 4 x i32>,
- <vscale x 4 x i32>,
- <vscale x 4 x i32>,
- i32);
-
-define <vscale x 4 x i32> @intrinsic_vaaddu_vv_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vaaddu_vv_nxv4i32_nxv4i32_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vaaddu.vv v8, v8, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i32> @llvm.riscv.vaaddu.nxv4i32.nxv4i32(
- <vscale x 4 x i32> undef,
- <vscale x 4 x i32> %0,
- <vscale x 4 x i32> %1,
- i32 %2)
-
- ret <vscale x 4 x i32> %a
-}
-
-declare <vscale x 4 x i32> @llvm.riscv.vaaddu.mask.nxv4i32.nxv4i32(
- <vscale x 4 x i32>,
- <vscale x 4 x i32>,
- <vscale x 4 x i32>,
- <vscale x 4 x i1>,
- i32,
- i32);
-
-define <vscale x 4 x i32> @intrinsic_vaaddu_mask_vv_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv4i32_nxv4i32_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vaaddu.vv v8, v10, v12, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i32> @llvm.riscv.vaaddu.mask.nxv4i32.nxv4i32(
- <vscale x 4 x i32> %0,
- <vscale x 4 x i32> %1,
- <vscale x 4 x i32> %2,
- <vscale x 4 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 4 x i32> %a
-}
-
-declare <vscale x 8 x i32> @llvm.riscv.vaaddu.nxv8i32.nxv8i32(
- <vscale x 8 x i32>,
- <vscale x 8 x i32>,
- <vscale x 8 x i32>,
- i32);
-
-define <vscale x 8 x i32> @intrinsic_vaaddu_vv_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vaaddu_vv_nxv8i32_nxv8i32_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
-; CHECK-NEXT: vaaddu.vv v8, v8, v12
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i32> @llvm.riscv.vaaddu.nxv8i32.nxv8i32(
- <vscale x 8 x i32> undef,
- <vscale x 8 x i32> %0,
- <vscale x 8 x i32> %1,
- i32 %2)
-
- ret <vscale x 8 x i32> %a
-}
-
-declare <vscale x 8 x i32> @llvm.riscv.vaaddu.mask.nxv8i32.nxv8i32(
- <vscale x 8 x i32>,
- <vscale x 8 x i32>,
- <vscale x 8 x i32>,
- <vscale x 8 x i1>,
- i32,
- i32);
-
-define <vscale x 8 x i32> @intrinsic_vaaddu_mask_vv_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv8i32_nxv8i32_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
-; CHECK-NEXT: vaaddu.vv v8, v12, v16, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i32> @llvm.riscv.vaaddu.mask.nxv8i32.nxv8i32(
- <vscale x 8 x i32> %0,
- <vscale x 8 x i32> %1,
- <vscale x 8 x i32> %2,
- <vscale x 8 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 8 x i32> %a
-}
-
-declare <vscale x 16 x i32> @llvm.riscv.vaaddu.nxv16i32.nxv16i32(
- <vscale x 16 x i32>,
- <vscale x 16 x i32>,
- <vscale x 16 x i32>,
- i32);
-
-define <vscale x 16 x i32> @intrinsic_vaaddu_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vaaddu_vv_nxv16i32_nxv16i32_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu
-; CHECK-NEXT: vaaddu.vv v8, v8, v16
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i32> @llvm.riscv.vaaddu.nxv16i32.nxv16i32(
- <vscale x 16 x i32> undef,
- <vscale x 16 x i32> %0,
- <vscale x 16 x i32> %1,
- i32 %2)
-
- ret <vscale x 16 x i32> %a
-}
-
-declare <vscale x 16 x i32> @llvm.riscv.vaaddu.mask.nxv16i32.nxv16i32(
- <vscale x 16 x i32>,
- <vscale x 16 x i32>,
- <vscale x 16 x i32>,
- <vscale x 16 x i1>,
- i32,
- i32);
-
-define <vscale x 16 x i32> @intrinsic_vaaddu_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv16i32_nxv16i32_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vl8re32.v v24, (a0)
-; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu
-; CHECK-NEXT: vaaddu.vv v8, v16, v24, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i32> @llvm.riscv.vaaddu.mask.nxv16i32.nxv16i32(
- <vscale x 16 x i32> %0,
- <vscale x 16 x i32> %1,
- <vscale x 16 x i32> %2,
- <vscale x 16 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 16 x i32> %a
-}
-
-declare <vscale x 1 x i64> @llvm.riscv.vaaddu.nxv1i64.nxv1i64(
- <vscale x 1 x i64>,
- <vscale x 1 x i64>,
- <vscale x 1 x i64>,
- i32);
-
-define <vscale x 1 x i64> @intrinsic_vaaddu_vv_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vaaddu_vv_nxv1i64_nxv1i64_nxv1i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
-; CHECK-NEXT: vaaddu.vv v8, v8, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i64> @llvm.riscv.vaaddu.nxv1i64.nxv1i64(
- <vscale x 1 x i64> undef,
- <vscale x 1 x i64> %0,
- <vscale x 1 x i64> %1,
- i32 %2)
-
- ret <vscale x 1 x i64> %a
-}
-
-declare <vscale x 1 x i64> @llvm.riscv.vaaddu.mask.nxv1i64.nxv1i64(
- <vscale x 1 x i64>,
- <vscale x 1 x i64>,
- <vscale x 1 x i64>,
- <vscale x 1 x i1>,
- i32,
- i32);
-
-define <vscale x 1 x i64> @intrinsic_vaaddu_mask_vv_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv1i64_nxv1i64_nxv1i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
-; CHECK-NEXT: vaaddu.vv v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i64> @llvm.riscv.vaaddu.mask.nxv1i64.nxv1i64(
- <vscale x 1 x i64> %0,
- <vscale x 1 x i64> %1,
- <vscale x 1 x i64> %2,
- <vscale x 1 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 1 x i64> %a
-}
-
-declare <vscale x 2 x i64> @llvm.riscv.vaaddu.nxv2i64.nxv2i64(
- <vscale x 2 x i64>,
- <vscale x 2 x i64>,
- <vscale x 2 x i64>,
- i32);
-
-define <vscale x 2 x i64> @intrinsic_vaaddu_vv_nxv2i64_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vaaddu_vv_nxv2i64_nxv2i64_nxv2i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
-; CHECK-NEXT: vaaddu.vv v8, v8, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i64> @llvm.riscv.vaaddu.nxv2i64.nxv2i64(
- <vscale x 2 x i64> undef,
- <vscale x 2 x i64> %0,
- <vscale x 2 x i64> %1,
- i32 %2)
-
- ret <vscale x 2 x i64> %a
-}
-
-declare <vscale x 2 x i64> @llvm.riscv.vaaddu.mask.nxv2i64.nxv2i64(
- <vscale x 2 x i64>,
- <vscale x 2 x i64>,
- <vscale x 2 x i64>,
- <vscale x 2 x i1>,
- i32,
- i32);
-
-define <vscale x 2 x i64> @intrinsic_vaaddu_mask_vv_nxv2i64_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv2i64_nxv2i64_nxv2i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
-; CHECK-NEXT: vaaddu.vv v8, v10, v12, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i64> @llvm.riscv.vaaddu.mask.nxv2i64.nxv2i64(
- <vscale x 2 x i64> %0,
- <vscale x 2 x i64> %1,
- <vscale x 2 x i64> %2,
- <vscale x 2 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 2 x i64> %a
-}
-
-declare <vscale x 4 x i64> @llvm.riscv.vaaddu.nxv4i64.nxv4i64(
- <vscale x 4 x i64>,
- <vscale x 4 x i64>,
- <vscale x 4 x i64>,
- i32);
-
-define <vscale x 4 x i64> @intrinsic_vaaddu_vv_nxv4i64_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vaaddu_vv_nxv4i64_nxv4i64_nxv4i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
-; CHECK-NEXT: vaaddu.vv v8, v8, v12
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i64> @llvm.riscv.vaaddu.nxv4i64.nxv4i64(
- <vscale x 4 x i64> undef,
- <vscale x 4 x i64> %0,
- <vscale x 4 x i64> %1,
- i32 %2)
-
- ret <vscale x 4 x i64> %a
-}
-
-declare <vscale x 4 x i64> @llvm.riscv.vaaddu.mask.nxv4i64.nxv4i64(
- <vscale x 4 x i64>,
- <vscale x 4 x i64>,
- <vscale x 4 x i64>,
- <vscale x 4 x i1>,
- i32,
- i32);
-
-define <vscale x 4 x i64> @intrinsic_vaaddu_mask_vv_nxv4i64_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv4i64_nxv4i64_nxv4i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
-; CHECK-NEXT: vaaddu.vv v8, v12, v16, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i64> @llvm.riscv.vaaddu.mask.nxv4i64.nxv4i64(
- <vscale x 4 x i64> %0,
- <vscale x 4 x i64> %1,
- <vscale x 4 x i64> %2,
- <vscale x 4 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 4 x i64> %a
-}
-
-declare <vscale x 8 x i64> @llvm.riscv.vaaddu.nxv8i64.nxv8i64(
- <vscale x 8 x i64>,
- <vscale x 8 x i64>,
- <vscale x 8 x i64>,
- i32);
-
-define <vscale x 8 x i64> @intrinsic_vaaddu_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vaaddu_vv_nxv8i64_nxv8i64_nxv8i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu
-; CHECK-NEXT: vaaddu.vv v8, v8, v16
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i64> @llvm.riscv.vaaddu.nxv8i64.nxv8i64(
- <vscale x 8 x i64> undef,
- <vscale x 8 x i64> %0,
- <vscale x 8 x i64> %1,
- i32 %2)
-
- ret <vscale x 8 x i64> %a
-}
-
-declare <vscale x 8 x i64> @llvm.riscv.vaaddu.mask.nxv8i64.nxv8i64(
- <vscale x 8 x i64>,
- <vscale x 8 x i64>,
- <vscale x 8 x i64>,
- <vscale x 8 x i1>,
- i32,
- i32);
-
-define <vscale x 8 x i64> @intrinsic_vaaddu_mask_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv8i64_nxv8i64_nxv8i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vl8re64.v v24, (a0)
-; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu
-; CHECK-NEXT: vaaddu.vv v8, v16, v24, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i64> @llvm.riscv.vaaddu.mask.nxv8i64.nxv8i64(
- <vscale x 8 x i64> %0,
- <vscale x 8 x i64> %1,
- <vscale x 8 x i64> %2,
- <vscale x 8 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 8 x i64> %a
-}
-
-declare <vscale x 1 x i8> @llvm.riscv.vaaddu.nxv1i8.i8(
- <vscale x 1 x i8>,
- <vscale x 1 x i8>,
- i8,
- i32);
-
-define <vscale x 1 x i8> @intrinsic_vaaddu_vx_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, i8 %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vaaddu_vx_nxv1i8_nxv1i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
-; CHECK-NEXT: vaaddu.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i8> @llvm.riscv.vaaddu.nxv1i8.i8(
- <vscale x 1 x i8> undef,
- <vscale x 1 x i8> %0,
- i8 %1,
- i32 %2)
-
- ret <vscale x 1 x i8> %a
-}
-
-declare <vscale x 1 x i8> @llvm.riscv.vaaddu.mask.nxv1i8.i8(
- <vscale x 1 x i8>,
- <vscale x 1 x i8>,
- i8,
- <vscale x 1 x i1>,
- i32,
- i32);
-
-define <vscale x 1 x i8> @intrinsic_vaaddu_mask_vx_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vaaddu_mask_vx_nxv1i8_nxv1i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
-; CHECK-NEXT: vaaddu.vx v8, v9, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i8> @llvm.riscv.vaaddu.mask.nxv1i8.i8(
- <vscale x 1 x i8> %0,
- <vscale x 1 x i8> %1,
- i8 %2,
- <vscale x 1 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 1 x i8> %a
-}
-
-declare <vscale x 2 x i8> @llvm.riscv.vaaddu.nxv2i8.i8(
- <vscale x 2 x i8>,
- <vscale x 2 x i8>,
- i8,
- i32);
-
-define <vscale x 2 x i8> @intrinsic_vaaddu_vx_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, i8 %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vaaddu_vx_nxv2i8_nxv2i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
-; CHECK-NEXT: vaaddu.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i8> @llvm.riscv.vaaddu.nxv2i8.i8(
- <vscale x 2 x i8> undef,
- <vscale x 2 x i8> %0,
- i8 %1,
- i32 %2)
-
- ret <vscale x 2 x i8> %a
-}
-
-declare <vscale x 2 x i8> @llvm.riscv.vaaddu.mask.nxv2i8.i8(
- <vscale x 2 x i8>,
- <vscale x 2 x i8>,
- i8,
- <vscale x 2 x i1>,
- i32,
- i32);
-
-define <vscale x 2 x i8> @intrinsic_vaaddu_mask_vx_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vaaddu_mask_vx_nxv2i8_nxv2i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
-; CHECK-NEXT: vaaddu.vx v8, v9, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i8> @llvm.riscv.vaaddu.mask.nxv2i8.i8(
- <vscale x 2 x i8> %0,
- <vscale x 2 x i8> %1,
- i8 %2,
- <vscale x 2 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 2 x i8> %a
-}
-
-declare <vscale x 4 x i8> @llvm.riscv.vaaddu.nxv4i8.i8(
- <vscale x 4 x i8>,
- <vscale x 4 x i8>,
- i8,
- i32);
-
-define <vscale x 4 x i8> @intrinsic_vaaddu_vx_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, i8 %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vaaddu_vx_nxv4i8_nxv4i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
-; CHECK-NEXT: vaaddu.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i8> @llvm.riscv.vaaddu.nxv4i8.i8(
- <vscale x 4 x i8> undef,
- <vscale x 4 x i8> %0,
- i8 %1,
- i32 %2)
-
- ret <vscale x 4 x i8> %a
-}
-
-declare <vscale x 4 x i8> @llvm.riscv.vaaddu.mask.nxv4i8.i8(
- <vscale x 4 x i8>,
- <vscale x 4 x i8>,
- i8,
- <vscale x 4 x i1>,
- i32,
- i32);
-
-define <vscale x 4 x i8> @intrinsic_vaaddu_mask_vx_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vaaddu_mask_vx_nxv4i8_nxv4i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
-; CHECK-NEXT: vaaddu.vx v8, v9, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i8> @llvm.riscv.vaaddu.mask.nxv4i8.i8(
- <vscale x 4 x i8> %0,
- <vscale x 4 x i8> %1,
- i8 %2,
- <vscale x 4 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 4 x i8> %a
-}
-
-declare <vscale x 8 x i8> @llvm.riscv.vaaddu.nxv8i8.i8(
- <vscale x 8 x i8>,
- <vscale x 8 x i8>,
- i8,
- i32);
-
-define <vscale x 8 x i8> @intrinsic_vaaddu_vx_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, i8 %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vaaddu_vx_nxv8i8_nxv8i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
-; CHECK-NEXT: vaaddu.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i8> @llvm.riscv.vaaddu.nxv8i8.i8(
- <vscale x 8 x i8> undef,
- <vscale x 8 x i8> %0,
- i8 %1,
- i32 %2)
-
- ret <vscale x 8 x i8> %a
-}
-
-declare <vscale x 8 x i8> @llvm.riscv.vaaddu.mask.nxv8i8.i8(
- <vscale x 8 x i8>,
- <vscale x 8 x i8>,
- i8,
- <vscale x 8 x i1>,
- i32,
- i32);
-
-define <vscale x 8 x i8> @intrinsic_vaaddu_mask_vx_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vaaddu_mask_vx_nxv8i8_nxv8i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
-; CHECK-NEXT: vaaddu.vx v8, v9, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i8> @llvm.riscv.vaaddu.mask.nxv8i8.i8(
- <vscale x 8 x i8> %0,
- <vscale x 8 x i8> %1,
- i8 %2,
- <vscale x 8 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 8 x i8> %a
-}
-
-declare <vscale x 16 x i8> @llvm.riscv.vaaddu.nxv16i8.i8(
- <vscale x 16 x i8>,
- <vscale x 16 x i8>,
- i8,
- i32);
-
-define <vscale x 16 x i8> @intrinsic_vaaddu_vx_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, i8 %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vaaddu_vx_nxv16i8_nxv16i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
-; CHECK-NEXT: vaaddu.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i8> @llvm.riscv.vaaddu.nxv16i8.i8(
- <vscale x 16 x i8> undef,
- <vscale x 16 x i8> %0,
- i8 %1,
- i32 %2)
-
- ret <vscale x 16 x i8> %a
-}
-
-declare <vscale x 16 x i8> @llvm.riscv.vaaddu.mask.nxv16i8.i8(
- <vscale x 16 x i8>,
- <vscale x 16 x i8>,
- i8,
- <vscale x 16 x i1>,
- i32,
- i32);
-
-define <vscale x 16 x i8> @intrinsic_vaaddu_mask_vx_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vaaddu_mask_vx_nxv16i8_nxv16i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
-; CHECK-NEXT: vaaddu.vx v8, v10, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i8> @llvm.riscv.vaaddu.mask.nxv16i8.i8(
- <vscale x 16 x i8> %0,
- <vscale x 16 x i8> %1,
- i8 %2,
- <vscale x 16 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 16 x i8> %a
-}
-
-declare <vscale x 32 x i8> @llvm.riscv.vaaddu.nxv32i8.i8(
- <vscale x 32 x i8>,
- <vscale x 32 x i8>,
- i8,
- i32);
-
-define <vscale x 32 x i8> @intrinsic_vaaddu_vx_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, i8 %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vaaddu_vx_nxv32i8_nxv32i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
-; CHECK-NEXT: vaaddu.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 32 x i8> @llvm.riscv.vaaddu.nxv32i8.i8(
- <vscale x 32 x i8> undef,
- <vscale x 32 x i8> %0,
- i8 %1,
- i32 %2)
-
- ret <vscale x 32 x i8> %a
-}
-
-declare <vscale x 32 x i8> @llvm.riscv.vaaddu.mask.nxv32i8.i8(
- <vscale x 32 x i8>,
- <vscale x 32 x i8>,
- i8,
- <vscale x 32 x i1>,
- i32,
- i32);
-
-define <vscale x 32 x i8> @intrinsic_vaaddu_mask_vx_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vaaddu_mask_vx_nxv32i8_nxv32i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
-; CHECK-NEXT: vaaddu.vx v8, v12, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 32 x i8> @llvm.riscv.vaaddu.mask.nxv32i8.i8(
- <vscale x 32 x i8> %0,
- <vscale x 32 x i8> %1,
- i8 %2,
- <vscale x 32 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 32 x i8> %a
-}
-
-declare <vscale x 64 x i8> @llvm.riscv.vaaddu.nxv64i8.i8(
- <vscale x 64 x i8>,
- <vscale x 64 x i8>,
- i8,
- i32);
-
-define <vscale x 64 x i8> @intrinsic_vaaddu_vx_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, i8 %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vaaddu_vx_nxv64i8_nxv64i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu
-; CHECK-NEXT: vaaddu.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 64 x i8> @llvm.riscv.vaaddu.nxv64i8.i8(
- <vscale x 64 x i8> undef,
- <vscale x 64 x i8> %0,
- i8 %1,
- i32 %2)
-
- ret <vscale x 64 x i8> %a
-}
-
-declare <vscale x 64 x i8> @llvm.riscv.vaaddu.mask.nxv64i8.i8(
- <vscale x 64 x i8>,
- <vscale x 64 x i8>,
- i8,
- <vscale x 64 x i1>,
- i32,
- i32);
-
-define <vscale x 64 x i8> @intrinsic_vaaddu_mask_vx_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i8 %2, <vscale x 64 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vaaddu_mask_vx_nxv64i8_nxv64i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu
-; CHECK-NEXT: vaaddu.vx v8, v16, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 64 x i8> @llvm.riscv.vaaddu.mask.nxv64i8.i8(
- <vscale x 64 x i8> %0,
- <vscale x 64 x i8> %1,
- i8 %2,
- <vscale x 64 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 64 x i8> %a
-}
-
-declare <vscale x 1 x i16> @llvm.riscv.vaaddu.nxv1i16.i16(
- <vscale x 1 x i16>,
- <vscale x 1 x i16>,
- i16,
- i32);
-
-define <vscale x 1 x i16> @intrinsic_vaaddu_vx_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, i16 %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vaaddu_vx_nxv1i16_nxv1i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
-; CHECK-NEXT: vaaddu.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i16> @llvm.riscv.vaaddu.nxv1i16.i16(
- <vscale x 1 x i16> undef,
- <vscale x 1 x i16> %0,
- i16 %1,
- i32 %2)
-
- ret <vscale x 1 x i16> %a
-}
-
-declare <vscale x 1 x i16> @llvm.riscv.vaaddu.mask.nxv1i16.i16(
- <vscale x 1 x i16>,
- <vscale x 1 x i16>,
- i16,
- <vscale x 1 x i1>,
- i32,
- i32);
-
-define <vscale x 1 x i16> @intrinsic_vaaddu_mask_vx_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vaaddu_mask_vx_nxv1i16_nxv1i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
-; CHECK-NEXT: vaaddu.vx v8, v9, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i16> @llvm.riscv.vaaddu.mask.nxv1i16.i16(
- <vscale x 1 x i16> %0,
- <vscale x 1 x i16> %1,
- i16 %2,
- <vscale x 1 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 1 x i16> %a
-}
-
-declare <vscale x 2 x i16> @llvm.riscv.vaaddu.nxv2i16.i16(
- <vscale x 2 x i16>,
- <vscale x 2 x i16>,
- i16,
- i32);
-
-define <vscale x 2 x i16> @intrinsic_vaaddu_vx_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, i16 %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vaaddu_vx_nxv2i16_nxv2i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
-; CHECK-NEXT: vaaddu.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i16> @llvm.riscv.vaaddu.nxv2i16.i16(
- <vscale x 2 x i16> undef,
- <vscale x 2 x i16> %0,
- i16 %1,
- i32 %2)
-
- ret <vscale x 2 x i16> %a
-}
-
-declare <vscale x 2 x i16> @llvm.riscv.vaaddu.mask.nxv2i16.i16(
- <vscale x 2 x i16>,
- <vscale x 2 x i16>,
- i16,
- <vscale x 2 x i1>,
- i32,
- i32);
-
-define <vscale x 2 x i16> @intrinsic_vaaddu_mask_vx_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vaaddu_mask_vx_nxv2i16_nxv2i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
-; CHECK-NEXT: vaaddu.vx v8, v9, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i16> @llvm.riscv.vaaddu.mask.nxv2i16.i16(
- <vscale x 2 x i16> %0,
- <vscale x 2 x i16> %1,
- i16 %2,
- <vscale x 2 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 2 x i16> %a
-}
-
-declare <vscale x 4 x i16> @llvm.riscv.vaaddu.nxv4i16.i16(
- <vscale x 4 x i16>,
- <vscale x 4 x i16>,
- i16,
- i32);
-
-define <vscale x 4 x i16> @intrinsic_vaaddu_vx_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, i16 %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vaaddu_vx_nxv4i16_nxv4i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
-; CHECK-NEXT: vaaddu.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i16> @llvm.riscv.vaaddu.nxv4i16.i16(
- <vscale x 4 x i16> undef,
- <vscale x 4 x i16> %0,
- i16 %1,
- i32 %2)
-
- ret <vscale x 4 x i16> %a
-}
-
-declare <vscale x 4 x i16> @llvm.riscv.vaaddu.mask.nxv4i16.i16(
- <vscale x 4 x i16>,
- <vscale x 4 x i16>,
- i16,
- <vscale x 4 x i1>,
- i32,
- i32);
-
-define <vscale x 4 x i16> @intrinsic_vaaddu_mask_vx_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vaaddu_mask_vx_nxv4i16_nxv4i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
-; CHECK-NEXT: vaaddu.vx v8, v9, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i16> @llvm.riscv.vaaddu.mask.nxv4i16.i16(
- <vscale x 4 x i16> %0,
- <vscale x 4 x i16> %1,
- i16 %2,
- <vscale x 4 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 4 x i16> %a
-}
-
-declare <vscale x 8 x i16> @llvm.riscv.vaaddu.nxv8i16.i16(
- <vscale x 8 x i16>,
- <vscale x 8 x i16>,
- i16,
- i32);
-
-define <vscale x 8 x i16> @intrinsic_vaaddu_vx_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, i16 %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vaaddu_vx_nxv8i16_nxv8i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
-; CHECK-NEXT: vaaddu.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i16> @llvm.riscv.vaaddu.nxv8i16.i16(
- <vscale x 8 x i16> undef,
- <vscale x 8 x i16> %0,
- i16 %1,
- i32 %2)
-
- ret <vscale x 8 x i16> %a
-}
-
-declare <vscale x 8 x i16> @llvm.riscv.vaaddu.mask.nxv8i16.i16(
- <vscale x 8 x i16>,
- <vscale x 8 x i16>,
- i16,
- <vscale x 8 x i1>,
- i32,
- i32);
-
-define <vscale x 8 x i16> @intrinsic_vaaddu_mask_vx_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vaaddu_mask_vx_nxv8i16_nxv8i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
-; CHECK-NEXT: vaaddu.vx v8, v10, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i16> @llvm.riscv.vaaddu.mask.nxv8i16.i16(
- <vscale x 8 x i16> %0,
- <vscale x 8 x i16> %1,
- i16 %2,
- <vscale x 8 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 8 x i16> %a
-}
-
-declare <vscale x 16 x i16> @llvm.riscv.vaaddu.nxv16i16.i16(
- <vscale x 16 x i16>,
- <vscale x 16 x i16>,
- i16,
- i32);
-
-define <vscale x 16 x i16> @intrinsic_vaaddu_vx_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, i16 %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vaaddu_vx_nxv16i16_nxv16i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
-; CHECK-NEXT: vaaddu.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i16> @llvm.riscv.vaaddu.nxv16i16.i16(
- <vscale x 16 x i16> undef,
- <vscale x 16 x i16> %0,
- i16 %1,
- i32 %2)
-
- ret <vscale x 16 x i16> %a
-}
-
-declare <vscale x 16 x i16> @llvm.riscv.vaaddu.mask.nxv16i16.i16(
- <vscale x 16 x i16>,
- <vscale x 16 x i16>,
- i16,
- <vscale x 16 x i1>,
- i32,
- i32);
-
-define <vscale x 16 x i16> @intrinsic_vaaddu_mask_vx_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vaaddu_mask_vx_nxv16i16_nxv16i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
-; CHECK-NEXT: vaaddu.vx v8, v12, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i16> @llvm.riscv.vaaddu.mask.nxv16i16.i16(
- <vscale x 16 x i16> %0,
- <vscale x 16 x i16> %1,
- i16 %2,
- <vscale x 16 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 16 x i16> %a
-}
-
-declare <vscale x 32 x i16> @llvm.riscv.vaaddu.nxv32i16.i16(
- <vscale x 32 x i16>,
- <vscale x 32 x i16>,
- i16,
- i32);
-
-define <vscale x 32 x i16> @intrinsic_vaaddu_vx_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, i16 %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vaaddu_vx_nxv32i16_nxv32i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu
-; CHECK-NEXT: vaaddu.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 32 x i16> @llvm.riscv.vaaddu.nxv32i16.i16(
- <vscale x 32 x i16> undef,
- <vscale x 32 x i16> %0,
- i16 %1,
- i32 %2)
-
- ret <vscale x 32 x i16> %a
-}
-
-declare <vscale x 32 x i16> @llvm.riscv.vaaddu.mask.nxv32i16.i16(
- <vscale x 32 x i16>,
- <vscale x 32 x i16>,
- i16,
- <vscale x 32 x i1>,
- i32,
- i32);
-
-define <vscale x 32 x i16> @intrinsic_vaaddu_mask_vx_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, i16 %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vaaddu_mask_vx_nxv32i16_nxv32i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu
-; CHECK-NEXT: vaaddu.vx v8, v16, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 32 x i16> @llvm.riscv.vaaddu.mask.nxv32i16.i16(
- <vscale x 32 x i16> %0,
- <vscale x 32 x i16> %1,
- i16 %2,
- <vscale x 32 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 32 x i16> %a
-}
-
-declare <vscale x 1 x i32> @llvm.riscv.vaaddu.nxv1i32.i32(
- <vscale x 1 x i32>,
- <vscale x 1 x i32>,
- i32,
- i32);
-
-define <vscale x 1 x i32> @intrinsic_vaaddu_vx_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, i32 %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vaaddu_vx_nxv1i32_nxv1i32_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
-; CHECK-NEXT: vaaddu.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i32> @llvm.riscv.vaaddu.nxv1i32.i32(
- <vscale x 1 x i32> undef,
- <vscale x 1 x i32> %0,
- i32 %1,
- i32 %2)
-
- ret <vscale x 1 x i32> %a
-}
-
-declare <vscale x 1 x i32> @llvm.riscv.vaaddu.mask.nxv1i32.i32(
- <vscale x 1 x i32>,
- <vscale x 1 x i32>,
- i32,
- <vscale x 1 x i1>,
- i32,
- i32);
-
-define <vscale x 1 x i32> @intrinsic_vaaddu_mask_vx_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vaaddu_mask_vx_nxv1i32_nxv1i32_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
-; CHECK-NEXT: vaaddu.vx v8, v9, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i32> @llvm.riscv.vaaddu.mask.nxv1i32.i32(
- <vscale x 1 x i32> %0,
- <vscale x 1 x i32> %1,
- i32 %2,
- <vscale x 1 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 1 x i32> %a
-}
-
-declare <vscale x 2 x i32> @llvm.riscv.vaaddu.nxv2i32.i32(
- <vscale x 2 x i32>,
- <vscale x 2 x i32>,
- i32,
- i32);
-
-define <vscale x 2 x i32> @intrinsic_vaaddu_vx_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, i32 %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vaaddu_vx_nxv2i32_nxv2i32_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
-; CHECK-NEXT: vaaddu.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i32> @llvm.riscv.vaaddu.nxv2i32.i32(
- <vscale x 2 x i32> undef,
- <vscale x 2 x i32> %0,
- i32 %1,
- i32 %2)
-
- ret <vscale x 2 x i32> %a
-}
-
-declare <vscale x 2 x i32> @llvm.riscv.vaaddu.mask.nxv2i32.i32(
- <vscale x 2 x i32>,
- <vscale x 2 x i32>,
- i32,
- <vscale x 2 x i1>,
- i32,
- i32);
-
-define <vscale x 2 x i32> @intrinsic_vaaddu_mask_vx_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vaaddu_mask_vx_nxv2i32_nxv2i32_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
-; CHECK-NEXT: vaaddu.vx v8, v9, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i32> @llvm.riscv.vaaddu.mask.nxv2i32.i32(
- <vscale x 2 x i32> %0,
- <vscale x 2 x i32> %1,
- i32 %2,
- <vscale x 2 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 2 x i32> %a
-}
-
-declare <vscale x 4 x i32> @llvm.riscv.vaaddu.nxv4i32.i32(
- <vscale x 4 x i32>,
- <vscale x 4 x i32>,
- i32,
- i32);
-
-define <vscale x 4 x i32> @intrinsic_vaaddu_vx_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, i32 %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vaaddu_vx_nxv4i32_nxv4i32_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; CHECK-NEXT: vaaddu.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i32> @llvm.riscv.vaaddu.nxv4i32.i32(
- <vscale x 4 x i32> undef,
- <vscale x 4 x i32> %0,
- i32 %1,
- i32 %2)
-
- ret <vscale x 4 x i32> %a
-}
-
-declare <vscale x 4 x i32> @llvm.riscv.vaaddu.mask.nxv4i32.i32(
- <vscale x 4 x i32>,
- <vscale x 4 x i32>,
- i32,
- <vscale x 4 x i1>,
- i32,
- i32);
-
-define <vscale x 4 x i32> @intrinsic_vaaddu_mask_vx_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vaaddu_mask_vx_nxv4i32_nxv4i32_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; CHECK-NEXT: vaaddu.vx v8, v10, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i32> @llvm.riscv.vaaddu.mask.nxv4i32.i32(
- <vscale x 4 x i32> %0,
- <vscale x 4 x i32> %1,
- i32 %2,
- <vscale x 4 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 4 x i32> %a
-}
-
-declare <vscale x 8 x i32> @llvm.riscv.vaaddu.nxv8i32.i32(
- <vscale x 8 x i32>,
- <vscale x 8 x i32>,
- i32,
- i32);
-
-define <vscale x 8 x i32> @intrinsic_vaaddu_vx_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, i32 %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vaaddu_vx_nxv8i32_nxv8i32_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
-; CHECK-NEXT: vaaddu.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i32> @llvm.riscv.vaaddu.nxv8i32.i32(
- <vscale x 8 x i32> undef,
- <vscale x 8 x i32> %0,
- i32 %1,
- i32 %2)
-
- ret <vscale x 8 x i32> %a
-}
-
-declare <vscale x 8 x i32> @llvm.riscv.vaaddu.mask.nxv8i32.i32(
- <vscale x 8 x i32>,
- <vscale x 8 x i32>,
- i32,
- <vscale x 8 x i1>,
- i32,
- i32);
-
-define <vscale x 8 x i32> @intrinsic_vaaddu_mask_vx_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vaaddu_mask_vx_nxv8i32_nxv8i32_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
-; CHECK-NEXT: vaaddu.vx v8, v12, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i32> @llvm.riscv.vaaddu.mask.nxv8i32.i32(
- <vscale x 8 x i32> %0,
- <vscale x 8 x i32> %1,
- i32 %2,
- <vscale x 8 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 8 x i32> %a
-}
-
-declare <vscale x 16 x i32> @llvm.riscv.vaaddu.nxv16i32.i32(
- <vscale x 16 x i32>,
- <vscale x 16 x i32>,
- i32,
- i32);
-
-define <vscale x 16 x i32> @intrinsic_vaaddu_vx_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, i32 %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vaaddu_vx_nxv16i32_nxv16i32_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu
-; CHECK-NEXT: vaaddu.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i32> @llvm.riscv.vaaddu.nxv16i32.i32(
- <vscale x 16 x i32> undef,
- <vscale x 16 x i32> %0,
- i32 %1,
- i32 %2)
-
- ret <vscale x 16 x i32> %a
-}
-
-declare <vscale x 16 x i32> @llvm.riscv.vaaddu.mask.nxv16i32.i32(
- <vscale x 16 x i32>,
- <vscale x 16 x i32>,
- i32,
- <vscale x 16 x i1>,
- i32,
- i32);
-
-define <vscale x 16 x i32> @intrinsic_vaaddu_mask_vx_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vaaddu_mask_vx_nxv16i32_nxv16i32_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu
-; CHECK-NEXT: vaaddu.vx v8, v16, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i32> @llvm.riscv.vaaddu.mask.nxv16i32.i32(
- <vscale x 16 x i32> %0,
- <vscale x 16 x i32> %1,
- i32 %2,
- <vscale x 16 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 16 x i32> %a
-}
-
-declare <vscale x 1 x i64> @llvm.riscv.vaaddu.nxv1i64.i64(
- <vscale x 1 x i64>,
- <vscale x 1 x i64>,
- i64,
- i32);
-
-define <vscale x 1 x i64> @intrinsic_vaaddu_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vaaddu_vx_nxv1i64_nxv1i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addi sp, sp, -16
-; CHECK-NEXT: sw a1, 12(sp)
-; CHECK-NEXT: sw a0, 8(sp)
-; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
-; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v9, (a0), zero
-; CHECK-NEXT: vaaddu.vv v8, v8, v9
-; CHECK-NEXT: addi sp, sp, 16
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i64> @llvm.riscv.vaaddu.nxv1i64.i64(
- <vscale x 1 x i64> undef,
- <vscale x 1 x i64> %0,
- i64 %1,
- i32 %2)
-
- ret <vscale x 1 x i64> %a
-}
-
-declare <vscale x 1 x i64> @llvm.riscv.vaaddu.mask.nxv1i64.i64(
- <vscale x 1 x i64>,
- <vscale x 1 x i64>,
- i64,
- <vscale x 1 x i1>,
- i32,
- i32);
-
-define <vscale x 1 x i64> @intrinsic_vaaddu_mask_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vaaddu_mask_vx_nxv1i64_nxv1i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addi sp, sp, -16
-; CHECK-NEXT: sw a1, 12(sp)
-; CHECK-NEXT: sw a0, 8(sp)
-; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
-; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v10, (a0), zero
-; CHECK-NEXT: vaaddu.vv v8, v9, v10, v0.t
-; CHECK-NEXT: addi sp, sp, 16
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i64> @llvm.riscv.vaaddu.mask.nxv1i64.i64(
- <vscale x 1 x i64> %0,
- <vscale x 1 x i64> %1,
- i64 %2,
- <vscale x 1 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 1 x i64> %a
-}
-
-declare <vscale x 2 x i64> @llvm.riscv.vaaddu.nxv2i64.i64(
- <vscale x 2 x i64>,
- <vscale x 2 x i64>,
- i64,
- i32);
-
-define <vscale x 2 x i64> @intrinsic_vaaddu_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vaaddu_vx_nxv2i64_nxv2i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addi sp, sp, -16
-; CHECK-NEXT: sw a1, 12(sp)
-; CHECK-NEXT: sw a0, 8(sp)
-; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
-; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v10, (a0), zero
-; CHECK-NEXT: vaaddu.vv v8, v8, v10
-; CHECK-NEXT: addi sp, sp, 16
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i64> @llvm.riscv.vaaddu.nxv2i64.i64(
- <vscale x 2 x i64> undef,
- <vscale x 2 x i64> %0,
- i64 %1,
- i32 %2)
-
- ret <vscale x 2 x i64> %a
-}
-
-declare <vscale x 2 x i64> @llvm.riscv.vaaddu.mask.nxv2i64.i64(
- <vscale x 2 x i64>,
- <vscale x 2 x i64>,
- i64,
- <vscale x 2 x i1>,
- i32,
- i32);
-
-define <vscale x 2 x i64> @intrinsic_vaaddu_mask_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vaaddu_mask_vx_nxv2i64_nxv2i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addi sp, sp, -16
-; CHECK-NEXT: sw a1, 12(sp)
-; CHECK-NEXT: sw a0, 8(sp)
-; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
-; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v12, (a0), zero
-; CHECK-NEXT: vaaddu.vv v8, v10, v12, v0.t
-; CHECK-NEXT: addi sp, sp, 16
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i64> @llvm.riscv.vaaddu.mask.nxv2i64.i64(
- <vscale x 2 x i64> %0,
- <vscale x 2 x i64> %1,
- i64 %2,
- <vscale x 2 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 2 x i64> %a
-}
-
-declare <vscale x 4 x i64> @llvm.riscv.vaaddu.nxv4i64.i64(
- <vscale x 4 x i64>,
- <vscale x 4 x i64>,
- i64,
- i32);
-
-define <vscale x 4 x i64> @intrinsic_vaaddu_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vaaddu_vx_nxv4i64_nxv4i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addi sp, sp, -16
-; CHECK-NEXT: sw a1, 12(sp)
-; CHECK-NEXT: sw a0, 8(sp)
-; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
-; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v12, (a0), zero
-; CHECK-NEXT: vaaddu.vv v8, v8, v12
-; CHECK-NEXT: addi sp, sp, 16
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i64> @llvm.riscv.vaaddu.nxv4i64.i64(
- <vscale x 4 x i64> undef,
- <vscale x 4 x i64> %0,
- i64 %1,
- i32 %2)
-
- ret <vscale x 4 x i64> %a
-}
-
-declare <vscale x 4 x i64> @llvm.riscv.vaaddu.mask.nxv4i64.i64(
- <vscale x 4 x i64>,
- <vscale x 4 x i64>,
- i64,
- <vscale x 4 x i1>,
- i32,
- i32);
-
-define <vscale x 4 x i64> @intrinsic_vaaddu_mask_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vaaddu_mask_vx_nxv4i64_nxv4i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addi sp, sp, -16
-; CHECK-NEXT: sw a1, 12(sp)
-; CHECK-NEXT: sw a0, 8(sp)
-; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
-; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v16, (a0), zero
-; CHECK-NEXT: vaaddu.vv v8, v12, v16, v0.t
-; CHECK-NEXT: addi sp, sp, 16
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i64> @llvm.riscv.vaaddu.mask.nxv4i64.i64(
- <vscale x 4 x i64> %0,
- <vscale x 4 x i64> %1,
- i64 %2,
- <vscale x 4 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 4 x i64> %a
-}
-
-declare <vscale x 8 x i64> @llvm.riscv.vaaddu.nxv8i64.i64(
- <vscale x 8 x i64>,
- <vscale x 8 x i64>,
- i64,
- i32);
-
-define <vscale x 8 x i64> @intrinsic_vaaddu_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, i64 %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vaaddu_vx_nxv8i64_nxv8i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addi sp, sp, -16
-; CHECK-NEXT: sw a1, 12(sp)
-; CHECK-NEXT: sw a0, 8(sp)
-; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, mu
-; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v16, (a0), zero
-; CHECK-NEXT: vaaddu.vv v8, v8, v16
-; CHECK-NEXT: addi sp, sp, 16
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i64> @llvm.riscv.vaaddu.nxv8i64.i64(
- <vscale x 8 x i64> undef,
- <vscale x 8 x i64> %0,
- i64 %1,
- i32 %2)
-
- ret <vscale x 8 x i64> %a
-}
-
-declare <vscale x 8 x i64> @llvm.riscv.vaaddu.mask.nxv8i64.i64(
- <vscale x 8 x i64>,
- <vscale x 8 x i64>,
- i64,
- <vscale x 8 x i1>,
- i32,
- i32);
-
-define <vscale x 8 x i64> @intrinsic_vaaddu_mask_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vaaddu_mask_vx_nxv8i64_nxv8i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addi sp, sp, -16
-; CHECK-NEXT: sw a1, 12(sp)
-; CHECK-NEXT: sw a0, 8(sp)
-; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, mu
-; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v24, (a0), zero
-; CHECK-NEXT: vaaddu.vv v8, v16, v24, v0.t
-; CHECK-NEXT: addi sp, sp, 16
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i64> @llvm.riscv.vaaddu.mask.nxv8i64.i64(
- <vscale x 8 x i64> %0,
- <vscale x 8 x i64> %1,
- i64 %2,
- <vscale x 8 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 8 x i64> %a
-}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vaaddu-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vaaddu.ll
similarity index 80%
rename from llvm/test/CodeGen/RISCV/rvv/vaaddu-rv64.ll
rename to llvm/test/CodeGen/RISCV/rvv/vaaddu.ll
index 4fad38c164c72..95c70db78b6bc 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vaaddu-rv64.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vaaddu.ll
@@ -1,13 +1,15 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs \
-; RUN: < %s | FileCheck %s
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v \
+; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,RV32
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v \
+; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,RV64
declare <vscale x 1 x i8> @llvm.riscv.vaaddu.nxv1i8.nxv1i8(
<vscale x 1 x i8>,
<vscale x 1 x i8>,
<vscale x 1 x i8>,
- i64);
+ iXLen);
-define <vscale x 1 x i8> @intrinsic_vaaddu_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2) nounwind {
+define <vscale x 1 x i8> @intrinsic_vaaddu_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vaaddu_vv_nxv1i8_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
@@ -18,7 +20,7 @@ entry:
<vscale x 1 x i8> undef,
<vscale x 1 x i8> %0,
<vscale x 1 x i8> %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 1 x i8> %a
}
@@ -28,10 +30,9 @@ declare <vscale x 1 x i8> @llvm.riscv.vaaddu.mask.nxv1i8.nxv1i8(
<vscale x 1 x i8>,
<vscale x 1 x i8>,
<vscale x 1 x i1>,
- i64,
- i64);
+ iXLen, iXLen);
-define <vscale x 1 x i8> @intrinsic_vaaddu_mask_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+define <vscale x 1 x i8> @intrinsic_vaaddu_mask_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv1i8_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
@@ -43,7 +44,7 @@ entry:
<vscale x 1 x i8> %1,
<vscale x 1 x i8> %2,
<vscale x 1 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 1 x i8> %a
}
@@ -52,9 +53,9 @@ declare <vscale x 2 x i8> @llvm.riscv.vaaddu.nxv2i8.nxv2i8(
<vscale x 2 x i8>,
<vscale x 2 x i8>,
<vscale x 2 x i8>,
- i64);
+ iXLen);
-define <vscale x 2 x i8> @intrinsic_vaaddu_vv_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2) nounwind {
+define <vscale x 2 x i8> @intrinsic_vaaddu_vv_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vaaddu_vv_nxv2i8_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
@@ -65,7 +66,7 @@ entry:
<vscale x 2 x i8> undef,
<vscale x 2 x i8> %0,
<vscale x 2 x i8> %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 2 x i8> %a
}
@@ -75,10 +76,9 @@ declare <vscale x 2 x i8> @llvm.riscv.vaaddu.mask.nxv2i8.nxv2i8(
<vscale x 2 x i8>,
<vscale x 2 x i8>,
<vscale x 2 x i1>,
- i64,
- i64);
+ iXLen, iXLen);
-define <vscale x 2 x i8> @intrinsic_vaaddu_mask_vv_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+define <vscale x 2 x i8> @intrinsic_vaaddu_mask_vv_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv2i8_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
@@ -90,7 +90,7 @@ entry:
<vscale x 2 x i8> %1,
<vscale x 2 x i8> %2,
<vscale x 2 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 2 x i8> %a
}
@@ -99,9 +99,9 @@ declare <vscale x 4 x i8> @llvm.riscv.vaaddu.nxv4i8.nxv4i8(
<vscale x 4 x i8>,
<vscale x 4 x i8>,
<vscale x 4 x i8>,
- i64);
+ iXLen);
-define <vscale x 4 x i8> @intrinsic_vaaddu_vv_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2) nounwind {
+define <vscale x 4 x i8> @intrinsic_vaaddu_vv_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vaaddu_vv_nxv4i8_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
@@ -112,7 +112,7 @@ entry:
<vscale x 4 x i8> undef,
<vscale x 4 x i8> %0,
<vscale x 4 x i8> %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 4 x i8> %a
}
@@ -122,10 +122,9 @@ declare <vscale x 4 x i8> @llvm.riscv.vaaddu.mask.nxv4i8.nxv4i8(
<vscale x 4 x i8>,
<vscale x 4 x i8>,
<vscale x 4 x i1>,
- i64,
- i64);
+ iXLen, iXLen);
-define <vscale x 4 x i8> @intrinsic_vaaddu_mask_vv_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+define <vscale x 4 x i8> @intrinsic_vaaddu_mask_vv_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv4i8_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
@@ -137,7 +136,7 @@ entry:
<vscale x 4 x i8> %1,
<vscale x 4 x i8> %2,
<vscale x 4 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 4 x i8> %a
}
@@ -146,9 +145,9 @@ declare <vscale x 8 x i8> @llvm.riscv.vaaddu.nxv8i8.nxv8i8(
<vscale x 8 x i8>,
<vscale x 8 x i8>,
<vscale x 8 x i8>,
- i64);
+ iXLen);
-define <vscale x 8 x i8> @intrinsic_vaaddu_vv_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2) nounwind {
+define <vscale x 8 x i8> @intrinsic_vaaddu_vv_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vaaddu_vv_nxv8i8_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
@@ -159,7 +158,7 @@ entry:
<vscale x 8 x i8> undef,
<vscale x 8 x i8> %0,
<vscale x 8 x i8> %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 8 x i8> %a
}
@@ -169,10 +168,9 @@ declare <vscale x 8 x i8> @llvm.riscv.vaaddu.mask.nxv8i8.nxv8i8(
<vscale x 8 x i8>,
<vscale x 8 x i8>,
<vscale x 8 x i1>,
- i64,
- i64);
+ iXLen, iXLen);
-define <vscale x 8 x i8> @intrinsic_vaaddu_mask_vv_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+define <vscale x 8 x i8> @intrinsic_vaaddu_mask_vv_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv8i8_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
@@ -184,7 +182,7 @@ entry:
<vscale x 8 x i8> %1,
<vscale x 8 x i8> %2,
<vscale x 8 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 8 x i8> %a
}
@@ -193,9 +191,9 @@ declare <vscale x 16 x i8> @llvm.riscv.vaaddu.nxv16i8.nxv16i8(
<vscale x 16 x i8>,
<vscale x 16 x i8>,
<vscale x 16 x i8>,
- i64);
+ iXLen);
-define <vscale x 16 x i8> @intrinsic_vaaddu_vv_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2) nounwind {
+define <vscale x 16 x i8> @intrinsic_vaaddu_vv_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vaaddu_vv_nxv16i8_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
@@ -206,7 +204,7 @@ entry:
<vscale x 16 x i8> undef,
<vscale x 16 x i8> %0,
<vscale x 16 x i8> %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 16 x i8> %a
}
@@ -216,10 +214,9 @@ declare <vscale x 16 x i8> @llvm.riscv.vaaddu.mask.nxv16i8.nxv16i8(
<vscale x 16 x i8>,
<vscale x 16 x i8>,
<vscale x 16 x i1>,
- i64,
- i64);
+ iXLen, iXLen);
-define <vscale x 16 x i8> @intrinsic_vaaddu_mask_vv_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+define <vscale x 16 x i8> @intrinsic_vaaddu_mask_vv_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv16i8_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
@@ -231,7 +228,7 @@ entry:
<vscale x 16 x i8> %1,
<vscale x 16 x i8> %2,
<vscale x 16 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 16 x i8> %a
}
@@ -240,9 +237,9 @@ declare <vscale x 32 x i8> @llvm.riscv.vaaddu.nxv32i8.nxv32i8(
<vscale x 32 x i8>,
<vscale x 32 x i8>,
<vscale x 32 x i8>,
- i64);
+ iXLen);
-define <vscale x 32 x i8> @intrinsic_vaaddu_vv_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i64 %2) nounwind {
+define <vscale x 32 x i8> @intrinsic_vaaddu_vv_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vaaddu_vv_nxv32i8_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
@@ -253,7 +250,7 @@ entry:
<vscale x 32 x i8> undef,
<vscale x 32 x i8> %0,
<vscale x 32 x i8> %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 32 x i8> %a
}
@@ -263,10 +260,9 @@ declare <vscale x 32 x i8> @llvm.riscv.vaaddu.mask.nxv32i8.nxv32i8(
<vscale x 32 x i8>,
<vscale x 32 x i8>,
<vscale x 32 x i1>,
- i64,
- i64);
+ iXLen, iXLen);
-define <vscale x 32 x i8> @intrinsic_vaaddu_mask_vv_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
+define <vscale x 32 x i8> @intrinsic_vaaddu_mask_vv_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv32i8_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
@@ -278,7 +274,7 @@ entry:
<vscale x 32 x i8> %1,
<vscale x 32 x i8> %2,
<vscale x 32 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 32 x i8> %a
}
@@ -287,9 +283,9 @@ declare <vscale x 64 x i8> @llvm.riscv.vaaddu.nxv64i8.nxv64i8(
<vscale x 64 x i8>,
<vscale x 64 x i8>,
<vscale x 64 x i8>,
- i64);
+ iXLen);
-define <vscale x 64 x i8> @intrinsic_vaaddu_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i64 %2) nounwind {
+define <vscale x 64 x i8> @intrinsic_vaaddu_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vaaddu_vv_nxv64i8_nxv64i8_nxv64i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, mu
@@ -300,7 +296,7 @@ entry:
<vscale x 64 x i8> undef,
<vscale x 64 x i8> %0,
<vscale x 64 x i8> %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 64 x i8> %a
}
@@ -310,10 +306,9 @@ declare <vscale x 64 x i8> @llvm.riscv.vaaddu.mask.nxv64i8.nxv64i8(
<vscale x 64 x i8>,
<vscale x 64 x i8>,
<vscale x 64 x i1>,
- i64,
- i64);
+ iXLen, iXLen);
-define <vscale x 64 x i8> @intrinsic_vaaddu_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, i64 %4) nounwind {
+define <vscale x 64 x i8> @intrinsic_vaaddu_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv64i8_nxv64i8_nxv64i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vl8r.v v24, (a0)
@@ -326,7 +321,7 @@ entry:
<vscale x 64 x i8> %1,
<vscale x 64 x i8> %2,
<vscale x 64 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 64 x i8> %a
}
@@ -335,9 +330,9 @@ declare <vscale x 1 x i16> @llvm.riscv.vaaddu.nxv1i16.nxv1i16(
<vscale x 1 x i16>,
<vscale x 1 x i16>,
<vscale x 1 x i16>,
- i64);
+ iXLen);
-define <vscale x 1 x i16> @intrinsic_vaaddu_vv_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i64 %2) nounwind {
+define <vscale x 1 x i16> @intrinsic_vaaddu_vv_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vaaddu_vv_nxv1i16_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
@@ -348,7 +343,7 @@ entry:
<vscale x 1 x i16> undef,
<vscale x 1 x i16> %0,
<vscale x 1 x i16> %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 1 x i16> %a
}
@@ -358,10 +353,9 @@ declare <vscale x 1 x i16> @llvm.riscv.vaaddu.mask.nxv1i16.nxv1i16(
<vscale x 1 x i16>,
<vscale x 1 x i16>,
<vscale x 1 x i1>,
- i64,
- i64);
+ iXLen, iXLen);
-define <vscale x 1 x i16> @intrinsic_vaaddu_mask_vv_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+define <vscale x 1 x i16> @intrinsic_vaaddu_mask_vv_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv1i16_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
@@ -373,7 +367,7 @@ entry:
<vscale x 1 x i16> %1,
<vscale x 1 x i16> %2,
<vscale x 1 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 1 x i16> %a
}
@@ -382,9 +376,9 @@ declare <vscale x 2 x i16> @llvm.riscv.vaaddu.nxv2i16.nxv2i16(
<vscale x 2 x i16>,
<vscale x 2 x i16>,
<vscale x 2 x i16>,
- i64);
+ iXLen);
-define <vscale x 2 x i16> @intrinsic_vaaddu_vv_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i64 %2) nounwind {
+define <vscale x 2 x i16> @intrinsic_vaaddu_vv_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vaaddu_vv_nxv2i16_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
@@ -395,7 +389,7 @@ entry:
<vscale x 2 x i16> undef,
<vscale x 2 x i16> %0,
<vscale x 2 x i16> %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 2 x i16> %a
}
@@ -405,10 +399,9 @@ declare <vscale x 2 x i16> @llvm.riscv.vaaddu.mask.nxv2i16.nxv2i16(
<vscale x 2 x i16>,
<vscale x 2 x i16>,
<vscale x 2 x i1>,
- i64,
- i64);
+ iXLen, iXLen);
-define <vscale x 2 x i16> @intrinsic_vaaddu_mask_vv_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+define <vscale x 2 x i16> @intrinsic_vaaddu_mask_vv_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv2i16_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
@@ -420,7 +413,7 @@ entry:
<vscale x 2 x i16> %1,
<vscale x 2 x i16> %2,
<vscale x 2 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 2 x i16> %a
}
@@ -429,9 +422,9 @@ declare <vscale x 4 x i16> @llvm.riscv.vaaddu.nxv4i16.nxv4i16(
<vscale x 4 x i16>,
<vscale x 4 x i16>,
<vscale x 4 x i16>,
- i64);
+ iXLen);
-define <vscale x 4 x i16> @intrinsic_vaaddu_vv_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i64 %2) nounwind {
+define <vscale x 4 x i16> @intrinsic_vaaddu_vv_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vaaddu_vv_nxv4i16_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
@@ -442,7 +435,7 @@ entry:
<vscale x 4 x i16> undef,
<vscale x 4 x i16> %0,
<vscale x 4 x i16> %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 4 x i16> %a
}
@@ -452,10 +445,9 @@ declare <vscale x 4 x i16> @llvm.riscv.vaaddu.mask.nxv4i16.nxv4i16(
<vscale x 4 x i16>,
<vscale x 4 x i16>,
<vscale x 4 x i1>,
- i64,
- i64);
+ iXLen, iXLen);
-define <vscale x 4 x i16> @intrinsic_vaaddu_mask_vv_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+define <vscale x 4 x i16> @intrinsic_vaaddu_mask_vv_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv4i16_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
@@ -467,7 +459,7 @@ entry:
<vscale x 4 x i16> %1,
<vscale x 4 x i16> %2,
<vscale x 4 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 4 x i16> %a
}
@@ -476,9 +468,9 @@ declare <vscale x 8 x i16> @llvm.riscv.vaaddu.nxv8i16.nxv8i16(
<vscale x 8 x i16>,
<vscale x 8 x i16>,
<vscale x 8 x i16>,
- i64);
+ iXLen);
-define <vscale x 8 x i16> @intrinsic_vaaddu_vv_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i64 %2) nounwind {
+define <vscale x 8 x i16> @intrinsic_vaaddu_vv_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vaaddu_vv_nxv8i16_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
@@ -489,7 +481,7 @@ entry:
<vscale x 8 x i16> undef,
<vscale x 8 x i16> %0,
<vscale x 8 x i16> %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 8 x i16> %a
}
@@ -499,10 +491,9 @@ declare <vscale x 8 x i16> @llvm.riscv.vaaddu.mask.nxv8i16.nxv8i16(
<vscale x 8 x i16>,
<vscale x 8 x i16>,
<vscale x 8 x i1>,
- i64,
- i64);
+ iXLen, iXLen);
-define <vscale x 8 x i16> @intrinsic_vaaddu_mask_vv_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+define <vscale x 8 x i16> @intrinsic_vaaddu_mask_vv_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv8i16_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
@@ -514,7 +505,7 @@ entry:
<vscale x 8 x i16> %1,
<vscale x 8 x i16> %2,
<vscale x 8 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 8 x i16> %a
}
@@ -523,9 +514,9 @@ declare <vscale x 16 x i16> @llvm.riscv.vaaddu.nxv16i16.nxv16i16(
<vscale x 16 x i16>,
<vscale x 16 x i16>,
<vscale x 16 x i16>,
- i64);
+ iXLen);
-define <vscale x 16 x i16> @intrinsic_vaaddu_vv_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i64 %2) nounwind {
+define <vscale x 16 x i16> @intrinsic_vaaddu_vv_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vaaddu_vv_nxv16i16_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
@@ -536,7 +527,7 @@ entry:
<vscale x 16 x i16> undef,
<vscale x 16 x i16> %0,
<vscale x 16 x i16> %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 16 x i16> %a
}
@@ -546,10 +537,9 @@ declare <vscale x 16 x i16> @llvm.riscv.vaaddu.mask.nxv16i16.nxv16i16(
<vscale x 16 x i16>,
<vscale x 16 x i16>,
<vscale x 16 x i1>,
- i64,
- i64);
+ iXLen, iXLen);
-define <vscale x 16 x i16> @intrinsic_vaaddu_mask_vv_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+define <vscale x 16 x i16> @intrinsic_vaaddu_mask_vv_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv16i16_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
@@ -561,7 +551,7 @@ entry:
<vscale x 16 x i16> %1,
<vscale x 16 x i16> %2,
<vscale x 16 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 16 x i16> %a
}
@@ -570,9 +560,9 @@ declare <vscale x 32 x i16> @llvm.riscv.vaaddu.nxv32i16.nxv32i16(
<vscale x 32 x i16>,
<vscale x 32 x i16>,
<vscale x 32 x i16>,
- i64);
+ iXLen);
-define <vscale x 32 x i16> @intrinsic_vaaddu_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, i64 %2) nounwind {
+define <vscale x 32 x i16> @intrinsic_vaaddu_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vaaddu_vv_nxv32i16_nxv32i16_nxv32i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, mu
@@ -583,7 +573,7 @@ entry:
<vscale x 32 x i16> undef,
<vscale x 32 x i16> %0,
<vscale x 32 x i16> %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 32 x i16> %a
}
@@ -593,10 +583,9 @@ declare <vscale x 32 x i16> @llvm.riscv.vaaddu.mask.nxv32i16.nxv32i16(
<vscale x 32 x i16>,
<vscale x 32 x i16>,
<vscale x 32 x i1>,
- i64,
- i64);
+ iXLen, iXLen);
-define <vscale x 32 x i16> @intrinsic_vaaddu_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
+define <vscale x 32 x i16> @intrinsic_vaaddu_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv32i16_nxv32i16_nxv32i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vl8re16.v v24, (a0)
@@ -609,7 +598,7 @@ entry:
<vscale x 32 x i16> %1,
<vscale x 32 x i16> %2,
<vscale x 32 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 32 x i16> %a
}
@@ -618,9 +607,9 @@ declare <vscale x 1 x i32> @llvm.riscv.vaaddu.nxv1i32.nxv1i32(
<vscale x 1 x i32>,
<vscale x 1 x i32>,
<vscale x 1 x i32>,
- i64);
+ iXLen);
-define <vscale x 1 x i32> @intrinsic_vaaddu_vv_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2) nounwind {
+define <vscale x 1 x i32> @intrinsic_vaaddu_vv_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vaaddu_vv_nxv1i32_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
@@ -631,7 +620,7 @@ entry:
<vscale x 1 x i32> undef,
<vscale x 1 x i32> %0,
<vscale x 1 x i32> %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 1 x i32> %a
}
@@ -641,10 +630,9 @@ declare <vscale x 1 x i32> @llvm.riscv.vaaddu.mask.nxv1i32.nxv1i32(
<vscale x 1 x i32>,
<vscale x 1 x i32>,
<vscale x 1 x i1>,
- i64,
- i64);
+ iXLen, iXLen);
-define <vscale x 1 x i32> @intrinsic_vaaddu_mask_vv_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+define <vscale x 1 x i32> @intrinsic_vaaddu_mask_vv_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv1i32_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
@@ -656,7 +644,7 @@ entry:
<vscale x 1 x i32> %1,
<vscale x 1 x i32> %2,
<vscale x 1 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 1 x i32> %a
}
@@ -665,9 +653,9 @@ declare <vscale x 2 x i32> @llvm.riscv.vaaddu.nxv2i32.nxv2i32(
<vscale x 2 x i32>,
<vscale x 2 x i32>,
<vscale x 2 x i32>,
- i64);
+ iXLen);
-define <vscale x 2 x i32> @intrinsic_vaaddu_vv_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2) nounwind {
+define <vscale x 2 x i32> @intrinsic_vaaddu_vv_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vaaddu_vv_nxv2i32_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
@@ -678,7 +666,7 @@ entry:
<vscale x 2 x i32> undef,
<vscale x 2 x i32> %0,
<vscale x 2 x i32> %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 2 x i32> %a
}
@@ -688,10 +676,9 @@ declare <vscale x 2 x i32> @llvm.riscv.vaaddu.mask.nxv2i32.nxv2i32(
<vscale x 2 x i32>,
<vscale x 2 x i32>,
<vscale x 2 x i1>,
- i64,
- i64);
+ iXLen, iXLen);
-define <vscale x 2 x i32> @intrinsic_vaaddu_mask_vv_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+define <vscale x 2 x i32> @intrinsic_vaaddu_mask_vv_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv2i32_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
@@ -703,7 +690,7 @@ entry:
<vscale x 2 x i32> %1,
<vscale x 2 x i32> %2,
<vscale x 2 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 2 x i32> %a
}
@@ -712,9 +699,9 @@ declare <vscale x 4 x i32> @llvm.riscv.vaaddu.nxv4i32.nxv4i32(
<vscale x 4 x i32>,
<vscale x 4 x i32>,
<vscale x 4 x i32>,
- i64);
+ iXLen);
-define <vscale x 4 x i32> @intrinsic_vaaddu_vv_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i64 %2) nounwind {
+define <vscale x 4 x i32> @intrinsic_vaaddu_vv_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vaaddu_vv_nxv4i32_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
@@ -725,7 +712,7 @@ entry:
<vscale x 4 x i32> undef,
<vscale x 4 x i32> %0,
<vscale x 4 x i32> %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 4 x i32> %a
}
@@ -735,10 +722,9 @@ declare <vscale x 4 x i32> @llvm.riscv.vaaddu.mask.nxv4i32.nxv4i32(
<vscale x 4 x i32>,
<vscale x 4 x i32>,
<vscale x 4 x i1>,
- i64,
- i64);
+ iXLen, iXLen);
-define <vscale x 4 x i32> @intrinsic_vaaddu_mask_vv_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+define <vscale x 4 x i32> @intrinsic_vaaddu_mask_vv_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv4i32_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
@@ -750,7 +736,7 @@ entry:
<vscale x 4 x i32> %1,
<vscale x 4 x i32> %2,
<vscale x 4 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 4 x i32> %a
}
@@ -759,9 +745,9 @@ declare <vscale x 8 x i32> @llvm.riscv.vaaddu.nxv8i32.nxv8i32(
<vscale x 8 x i32>,
<vscale x 8 x i32>,
<vscale x 8 x i32>,
- i64);
+ iXLen);
-define <vscale x 8 x i32> @intrinsic_vaaddu_vv_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i64 %2) nounwind {
+define <vscale x 8 x i32> @intrinsic_vaaddu_vv_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vaaddu_vv_nxv8i32_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
@@ -772,7 +758,7 @@ entry:
<vscale x 8 x i32> undef,
<vscale x 8 x i32> %0,
<vscale x 8 x i32> %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 8 x i32> %a
}
@@ -782,10 +768,9 @@ declare <vscale x 8 x i32> @llvm.riscv.vaaddu.mask.nxv8i32.nxv8i32(
<vscale x 8 x i32>,
<vscale x 8 x i32>,
<vscale x 8 x i1>,
- i64,
- i64);
+ iXLen, iXLen);
-define <vscale x 8 x i32> @intrinsic_vaaddu_mask_vv_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+define <vscale x 8 x i32> @intrinsic_vaaddu_mask_vv_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv8i32_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
@@ -797,7 +782,7 @@ entry:
<vscale x 8 x i32> %1,
<vscale x 8 x i32> %2,
<vscale x 8 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 8 x i32> %a
}
@@ -806,9 +791,9 @@ declare <vscale x 16 x i32> @llvm.riscv.vaaddu.nxv16i32.nxv16i32(
<vscale x 16 x i32>,
<vscale x 16 x i32>,
<vscale x 16 x i32>,
- i64);
+ iXLen);
-define <vscale x 16 x i32> @intrinsic_vaaddu_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i64 %2) nounwind {
+define <vscale x 16 x i32> @intrinsic_vaaddu_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vaaddu_vv_nxv16i32_nxv16i32_nxv16i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu
@@ -819,7 +804,7 @@ entry:
<vscale x 16 x i32> undef,
<vscale x 16 x i32> %0,
<vscale x 16 x i32> %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 16 x i32> %a
}
@@ -829,10 +814,9 @@ declare <vscale x 16 x i32> @llvm.riscv.vaaddu.mask.nxv16i32.nxv16i32(
<vscale x 16 x i32>,
<vscale x 16 x i32>,
<vscale x 16 x i1>,
- i64,
- i64);
+ iXLen, iXLen);
-define <vscale x 16 x i32> @intrinsic_vaaddu_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+define <vscale x 16 x i32> @intrinsic_vaaddu_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv16i32_nxv16i32_nxv16i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vl8re32.v v24, (a0)
@@ -845,7 +829,7 @@ entry:
<vscale x 16 x i32> %1,
<vscale x 16 x i32> %2,
<vscale x 16 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 16 x i32> %a
}
@@ -854,9 +838,9 @@ declare <vscale x 1 x i64> @llvm.riscv.vaaddu.nxv1i64.nxv1i64(
<vscale x 1 x i64>,
<vscale x 1 x i64>,
<vscale x 1 x i64>,
- i64);
+ iXLen);
-define <vscale x 1 x i64> @intrinsic_vaaddu_vv_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2) nounwind {
+define <vscale x 1 x i64> @intrinsic_vaaddu_vv_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vaaddu_vv_nxv1i64_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
@@ -867,7 +851,7 @@ entry:
<vscale x 1 x i64> undef,
<vscale x 1 x i64> %0,
<vscale x 1 x i64> %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 1 x i64> %a
}
@@ -877,10 +861,9 @@ declare <vscale x 1 x i64> @llvm.riscv.vaaddu.mask.nxv1i64.nxv1i64(
<vscale x 1 x i64>,
<vscale x 1 x i64>,
<vscale x 1 x i1>,
- i64,
- i64);
+ iXLen, iXLen);
-define <vscale x 1 x i64> @intrinsic_vaaddu_mask_vv_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+define <vscale x 1 x i64> @intrinsic_vaaddu_mask_vv_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv1i64_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
@@ -892,7 +875,7 @@ entry:
<vscale x 1 x i64> %1,
<vscale x 1 x i64> %2,
<vscale x 1 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 1 x i64> %a
}
@@ -901,9 +884,9 @@ declare <vscale x 2 x i64> @llvm.riscv.vaaddu.nxv2i64.nxv2i64(
<vscale x 2 x i64>,
<vscale x 2 x i64>,
<vscale x 2 x i64>,
- i64);
+ iXLen);
-define <vscale x 2 x i64> @intrinsic_vaaddu_vv_nxv2i64_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2) nounwind {
+define <vscale x 2 x i64> @intrinsic_vaaddu_vv_nxv2i64_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vaaddu_vv_nxv2i64_nxv2i64_nxv2i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
@@ -914,7 +897,7 @@ entry:
<vscale x 2 x i64> undef,
<vscale x 2 x i64> %0,
<vscale x 2 x i64> %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 2 x i64> %a
}
@@ -924,10 +907,9 @@ declare <vscale x 2 x i64> @llvm.riscv.vaaddu.mask.nxv2i64.nxv2i64(
<vscale x 2 x i64>,
<vscale x 2 x i64>,
<vscale x 2 x i1>,
- i64,
- i64);
+ iXLen, iXLen);
-define <vscale x 2 x i64> @intrinsic_vaaddu_mask_vv_nxv2i64_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+define <vscale x 2 x i64> @intrinsic_vaaddu_mask_vv_nxv2i64_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv2i64_nxv2i64_nxv2i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
@@ -939,7 +921,7 @@ entry:
<vscale x 2 x i64> %1,
<vscale x 2 x i64> %2,
<vscale x 2 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 2 x i64> %a
}
@@ -948,9 +930,9 @@ declare <vscale x 4 x i64> @llvm.riscv.vaaddu.nxv4i64.nxv4i64(
<vscale x 4 x i64>,
<vscale x 4 x i64>,
<vscale x 4 x i64>,
- i64);
+ iXLen);
-define <vscale x 4 x i64> @intrinsic_vaaddu_vv_nxv4i64_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2) nounwind {
+define <vscale x 4 x i64> @intrinsic_vaaddu_vv_nxv4i64_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vaaddu_vv_nxv4i64_nxv4i64_nxv4i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
@@ -961,7 +943,7 @@ entry:
<vscale x 4 x i64> undef,
<vscale x 4 x i64> %0,
<vscale x 4 x i64> %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 4 x i64> %a
}
@@ -971,10 +953,9 @@ declare <vscale x 4 x i64> @llvm.riscv.vaaddu.mask.nxv4i64.nxv4i64(
<vscale x 4 x i64>,
<vscale x 4 x i64>,
<vscale x 4 x i1>,
- i64,
- i64);
+ iXLen, iXLen);
-define <vscale x 4 x i64> @intrinsic_vaaddu_mask_vv_nxv4i64_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+define <vscale x 4 x i64> @intrinsic_vaaddu_mask_vv_nxv4i64_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv4i64_nxv4i64_nxv4i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
@@ -986,7 +967,7 @@ entry:
<vscale x 4 x i64> %1,
<vscale x 4 x i64> %2,
<vscale x 4 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 4 x i64> %a
}
@@ -995,9 +976,9 @@ declare <vscale x 8 x i64> @llvm.riscv.vaaddu.nxv8i64.nxv8i64(
<vscale x 8 x i64>,
<vscale x 8 x i64>,
<vscale x 8 x i64>,
- i64);
+ iXLen);
-define <vscale x 8 x i64> @intrinsic_vaaddu_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2) nounwind {
+define <vscale x 8 x i64> @intrinsic_vaaddu_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vaaddu_vv_nxv8i64_nxv8i64_nxv8i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu
@@ -1008,7 +989,7 @@ entry:
<vscale x 8 x i64> undef,
<vscale x 8 x i64> %0,
<vscale x 8 x i64> %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 8 x i64> %a
}
@@ -1018,10 +999,9 @@ declare <vscale x 8 x i64> @llvm.riscv.vaaddu.mask.nxv8i64.nxv8i64(
<vscale x 8 x i64>,
<vscale x 8 x i64>,
<vscale x 8 x i1>,
- i64,
- i64);
+ iXLen, iXLen);
-define <vscale x 8 x i64> @intrinsic_vaaddu_mask_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+define <vscale x 8 x i64> @intrinsic_vaaddu_mask_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv8i64_nxv8i64_nxv8i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vl8re64.v v24, (a0)
@@ -1034,7 +1014,7 @@ entry:
<vscale x 8 x i64> %1,
<vscale x 8 x i64> %2,
<vscale x 8 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 8 x i64> %a
}
@@ -1043,9 +1023,9 @@ declare <vscale x 1 x i8> @llvm.riscv.vaaddu.nxv1i8.i8(
<vscale x 1 x i8>,
<vscale x 1 x i8>,
i8,
- i64);
+ iXLen);
-define <vscale x 1 x i8> @intrinsic_vaaddu_vx_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, i8 %1, i64 %2) nounwind {
+define <vscale x 1 x i8> @intrinsic_vaaddu_vx_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, i8 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vaaddu_vx_nxv1i8_nxv1i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
@@ -1056,7 +1036,7 @@ entry:
<vscale x 1 x i8> undef,
<vscale x 1 x i8> %0,
i8 %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 1 x i8> %a
}
@@ -1066,10 +1046,9 @@ declare <vscale x 1 x i8> @llvm.riscv.vaaddu.mask.nxv1i8.i8(
<vscale x 1 x i8>,
i8,
<vscale x 1 x i1>,
- i64,
- i64);
+ iXLen, iXLen);
-define <vscale x 1 x i8> @intrinsic_vaaddu_mask_vx_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+define <vscale x 1 x i8> @intrinsic_vaaddu_mask_vx_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vaaddu_mask_vx_nxv1i8_nxv1i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
@@ -1081,7 +1060,7 @@ entry:
<vscale x 1 x i8> %1,
i8 %2,
<vscale x 1 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 1 x i8> %a
}
@@ -1090,9 +1069,9 @@ declare <vscale x 2 x i8> @llvm.riscv.vaaddu.nxv2i8.i8(
<vscale x 2 x i8>,
<vscale x 2 x i8>,
i8,
- i64);
+ iXLen);
-define <vscale x 2 x i8> @intrinsic_vaaddu_vx_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, i8 %1, i64 %2) nounwind {
+define <vscale x 2 x i8> @intrinsic_vaaddu_vx_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, i8 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vaaddu_vx_nxv2i8_nxv2i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
@@ -1103,7 +1082,7 @@ entry:
<vscale x 2 x i8> undef,
<vscale x 2 x i8> %0,
i8 %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 2 x i8> %a
}
@@ -1113,10 +1092,9 @@ declare <vscale x 2 x i8> @llvm.riscv.vaaddu.mask.nxv2i8.i8(
<vscale x 2 x i8>,
i8,
<vscale x 2 x i1>,
- i64,
- i64);
+ iXLen, iXLen);
-define <vscale x 2 x i8> @intrinsic_vaaddu_mask_vx_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+define <vscale x 2 x i8> @intrinsic_vaaddu_mask_vx_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vaaddu_mask_vx_nxv2i8_nxv2i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
@@ -1128,7 +1106,7 @@ entry:
<vscale x 2 x i8> %1,
i8 %2,
<vscale x 2 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 2 x i8> %a
}
@@ -1137,9 +1115,9 @@ declare <vscale x 4 x i8> @llvm.riscv.vaaddu.nxv4i8.i8(
<vscale x 4 x i8>,
<vscale x 4 x i8>,
i8,
- i64);
+ iXLen);
-define <vscale x 4 x i8> @intrinsic_vaaddu_vx_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, i8 %1, i64 %2) nounwind {
+define <vscale x 4 x i8> @intrinsic_vaaddu_vx_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, i8 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vaaddu_vx_nxv4i8_nxv4i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
@@ -1150,7 +1128,7 @@ entry:
<vscale x 4 x i8> undef,
<vscale x 4 x i8> %0,
i8 %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 4 x i8> %a
}
@@ -1160,10 +1138,9 @@ declare <vscale x 4 x i8> @llvm.riscv.vaaddu.mask.nxv4i8.i8(
<vscale x 4 x i8>,
i8,
<vscale x 4 x i1>,
- i64,
- i64);
+ iXLen, iXLen);
-define <vscale x 4 x i8> @intrinsic_vaaddu_mask_vx_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+define <vscale x 4 x i8> @intrinsic_vaaddu_mask_vx_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vaaddu_mask_vx_nxv4i8_nxv4i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
@@ -1175,7 +1152,7 @@ entry:
<vscale x 4 x i8> %1,
i8 %2,
<vscale x 4 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 4 x i8> %a
}
@@ -1184,9 +1161,9 @@ declare <vscale x 8 x i8> @llvm.riscv.vaaddu.nxv8i8.i8(
<vscale x 8 x i8>,
<vscale x 8 x i8>,
i8,
- i64);
+ iXLen);
-define <vscale x 8 x i8> @intrinsic_vaaddu_vx_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, i8 %1, i64 %2) nounwind {
+define <vscale x 8 x i8> @intrinsic_vaaddu_vx_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, i8 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vaaddu_vx_nxv8i8_nxv8i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
@@ -1197,7 +1174,7 @@ entry:
<vscale x 8 x i8> undef,
<vscale x 8 x i8> %0,
i8 %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 8 x i8> %a
}
@@ -1207,10 +1184,9 @@ declare <vscale x 8 x i8> @llvm.riscv.vaaddu.mask.nxv8i8.i8(
<vscale x 8 x i8>,
i8,
<vscale x 8 x i1>,
- i64,
- i64);
+ iXLen, iXLen);
-define <vscale x 8 x i8> @intrinsic_vaaddu_mask_vx_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+define <vscale x 8 x i8> @intrinsic_vaaddu_mask_vx_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vaaddu_mask_vx_nxv8i8_nxv8i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
@@ -1222,7 +1198,7 @@ entry:
<vscale x 8 x i8> %1,
i8 %2,
<vscale x 8 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 8 x i8> %a
}
@@ -1231,9 +1207,9 @@ declare <vscale x 16 x i8> @llvm.riscv.vaaddu.nxv16i8.i8(
<vscale x 16 x i8>,
<vscale x 16 x i8>,
i8,
- i64);
+ iXLen);
-define <vscale x 16 x i8> @intrinsic_vaaddu_vx_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, i8 %1, i64 %2) nounwind {
+define <vscale x 16 x i8> @intrinsic_vaaddu_vx_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, i8 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vaaddu_vx_nxv16i8_nxv16i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
@@ -1244,7 +1220,7 @@ entry:
<vscale x 16 x i8> undef,
<vscale x 16 x i8> %0,
i8 %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 16 x i8> %a
}
@@ -1254,10 +1230,9 @@ declare <vscale x 16 x i8> @llvm.riscv.vaaddu.mask.nxv16i8.i8(
<vscale x 16 x i8>,
i8,
<vscale x 16 x i1>,
- i64,
- i64);
+ iXLen, iXLen);
-define <vscale x 16 x i8> @intrinsic_vaaddu_mask_vx_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+define <vscale x 16 x i8> @intrinsic_vaaddu_mask_vx_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vaaddu_mask_vx_nxv16i8_nxv16i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
@@ -1269,7 +1244,7 @@ entry:
<vscale x 16 x i8> %1,
i8 %2,
<vscale x 16 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 16 x i8> %a
}
@@ -1278,9 +1253,9 @@ declare <vscale x 32 x i8> @llvm.riscv.vaaddu.nxv32i8.i8(
<vscale x 32 x i8>,
<vscale x 32 x i8>,
i8,
- i64);
+ iXLen);
-define <vscale x 32 x i8> @intrinsic_vaaddu_vx_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, i8 %1, i64 %2) nounwind {
+define <vscale x 32 x i8> @intrinsic_vaaddu_vx_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, i8 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vaaddu_vx_nxv32i8_nxv32i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
@@ -1291,7 +1266,7 @@ entry:
<vscale x 32 x i8> undef,
<vscale x 32 x i8> %0,
i8 %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 32 x i8> %a
}
@@ -1301,10 +1276,9 @@ declare <vscale x 32 x i8> @llvm.riscv.vaaddu.mask.nxv32i8.i8(
<vscale x 32 x i8>,
i8,
<vscale x 32 x i1>,
- i64,
- i64);
+ iXLen, iXLen);
-define <vscale x 32 x i8> @intrinsic_vaaddu_mask_vx_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
+define <vscale x 32 x i8> @intrinsic_vaaddu_mask_vx_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vaaddu_mask_vx_nxv32i8_nxv32i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
@@ -1316,7 +1290,7 @@ entry:
<vscale x 32 x i8> %1,
i8 %2,
<vscale x 32 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 32 x i8> %a
}
@@ -1325,9 +1299,9 @@ declare <vscale x 64 x i8> @llvm.riscv.vaaddu.nxv64i8.i8(
<vscale x 64 x i8>,
<vscale x 64 x i8>,
i8,
- i64);
+ iXLen);
-define <vscale x 64 x i8> @intrinsic_vaaddu_vx_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, i8 %1, i64 %2) nounwind {
+define <vscale x 64 x i8> @intrinsic_vaaddu_vx_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, i8 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vaaddu_vx_nxv64i8_nxv64i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu
@@ -1338,7 +1312,7 @@ entry:
<vscale x 64 x i8> undef,
<vscale x 64 x i8> %0,
i8 %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 64 x i8> %a
}
@@ -1348,10 +1322,9 @@ declare <vscale x 64 x i8> @llvm.riscv.vaaddu.mask.nxv64i8.i8(
<vscale x 64 x i8>,
i8,
<vscale x 64 x i1>,
- i64,
- i64);
+ iXLen, iXLen);
-define <vscale x 64 x i8> @intrinsic_vaaddu_mask_vx_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i8 %2, <vscale x 64 x i1> %3, i64 %4) nounwind {
+define <vscale x 64 x i8> @intrinsic_vaaddu_mask_vx_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i8 %2, <vscale x 64 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vaaddu_mask_vx_nxv64i8_nxv64i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu
@@ -1363,7 +1336,7 @@ entry:
<vscale x 64 x i8> %1,
i8 %2,
<vscale x 64 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 64 x i8> %a
}
@@ -1372,9 +1345,9 @@ declare <vscale x 1 x i16> @llvm.riscv.vaaddu.nxv1i16.i16(
<vscale x 1 x i16>,
<vscale x 1 x i16>,
i16,
- i64);
+ iXLen);
-define <vscale x 1 x i16> @intrinsic_vaaddu_vx_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, i16 %1, i64 %2) nounwind {
+define <vscale x 1 x i16> @intrinsic_vaaddu_vx_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, i16 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vaaddu_vx_nxv1i16_nxv1i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
@@ -1385,7 +1358,7 @@ entry:
<vscale x 1 x i16> undef,
<vscale x 1 x i16> %0,
i16 %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 1 x i16> %a
}
@@ -1395,10 +1368,9 @@ declare <vscale x 1 x i16> @llvm.riscv.vaaddu.mask.nxv1i16.i16(
<vscale x 1 x i16>,
i16,
<vscale x 1 x i1>,
- i64,
- i64);
+ iXLen, iXLen);
-define <vscale x 1 x i16> @intrinsic_vaaddu_mask_vx_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+define <vscale x 1 x i16> @intrinsic_vaaddu_mask_vx_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vaaddu_mask_vx_nxv1i16_nxv1i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
@@ -1410,7 +1382,7 @@ entry:
<vscale x 1 x i16> %1,
i16 %2,
<vscale x 1 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 1 x i16> %a
}
@@ -1419,9 +1391,9 @@ declare <vscale x 2 x i16> @llvm.riscv.vaaddu.nxv2i16.i16(
<vscale x 2 x i16>,
<vscale x 2 x i16>,
i16,
- i64);
+ iXLen);
-define <vscale x 2 x i16> @intrinsic_vaaddu_vx_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, i16 %1, i64 %2) nounwind {
+define <vscale x 2 x i16> @intrinsic_vaaddu_vx_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, i16 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vaaddu_vx_nxv2i16_nxv2i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
@@ -1432,7 +1404,7 @@ entry:
<vscale x 2 x i16> undef,
<vscale x 2 x i16> %0,
i16 %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 2 x i16> %a
}
@@ -1442,10 +1414,9 @@ declare <vscale x 2 x i16> @llvm.riscv.vaaddu.mask.nxv2i16.i16(
<vscale x 2 x i16>,
i16,
<vscale x 2 x i1>,
- i64,
- i64);
+ iXLen, iXLen);
-define <vscale x 2 x i16> @intrinsic_vaaddu_mask_vx_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+define <vscale x 2 x i16> @intrinsic_vaaddu_mask_vx_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vaaddu_mask_vx_nxv2i16_nxv2i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
@@ -1457,7 +1428,7 @@ entry:
<vscale x 2 x i16> %1,
i16 %2,
<vscale x 2 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 2 x i16> %a
}
@@ -1466,9 +1437,9 @@ declare <vscale x 4 x i16> @llvm.riscv.vaaddu.nxv4i16.i16(
<vscale x 4 x i16>,
<vscale x 4 x i16>,
i16,
- i64);
+ iXLen);
-define <vscale x 4 x i16> @intrinsic_vaaddu_vx_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, i16 %1, i64 %2) nounwind {
+define <vscale x 4 x i16> @intrinsic_vaaddu_vx_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, i16 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vaaddu_vx_nxv4i16_nxv4i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
@@ -1479,7 +1450,7 @@ entry:
<vscale x 4 x i16> undef,
<vscale x 4 x i16> %0,
i16 %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 4 x i16> %a
}
@@ -1489,10 +1460,9 @@ declare <vscale x 4 x i16> @llvm.riscv.vaaddu.mask.nxv4i16.i16(
<vscale x 4 x i16>,
i16,
<vscale x 4 x i1>,
- i64,
- i64);
+ iXLen, iXLen);
-define <vscale x 4 x i16> @intrinsic_vaaddu_mask_vx_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+define <vscale x 4 x i16> @intrinsic_vaaddu_mask_vx_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vaaddu_mask_vx_nxv4i16_nxv4i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
@@ -1504,7 +1474,7 @@ entry:
<vscale x 4 x i16> %1,
i16 %2,
<vscale x 4 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 4 x i16> %a
}
@@ -1513,9 +1483,9 @@ declare <vscale x 8 x i16> @llvm.riscv.vaaddu.nxv8i16.i16(
<vscale x 8 x i16>,
<vscale x 8 x i16>,
i16,
- i64);
+ iXLen);
-define <vscale x 8 x i16> @intrinsic_vaaddu_vx_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, i16 %1, i64 %2) nounwind {
+define <vscale x 8 x i16> @intrinsic_vaaddu_vx_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, i16 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vaaddu_vx_nxv8i16_nxv8i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
@@ -1526,7 +1496,7 @@ entry:
<vscale x 8 x i16> undef,
<vscale x 8 x i16> %0,
i16 %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 8 x i16> %a
}
@@ -1536,10 +1506,9 @@ declare <vscale x 8 x i16> @llvm.riscv.vaaddu.mask.nxv8i16.i16(
<vscale x 8 x i16>,
i16,
<vscale x 8 x i1>,
- i64,
- i64);
+ iXLen, iXLen);
-define <vscale x 8 x i16> @intrinsic_vaaddu_mask_vx_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+define <vscale x 8 x i16> @intrinsic_vaaddu_mask_vx_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vaaddu_mask_vx_nxv8i16_nxv8i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
@@ -1551,7 +1520,7 @@ entry:
<vscale x 8 x i16> %1,
i16 %2,
<vscale x 8 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 8 x i16> %a
}
@@ -1560,9 +1529,9 @@ declare <vscale x 16 x i16> @llvm.riscv.vaaddu.nxv16i16.i16(
<vscale x 16 x i16>,
<vscale x 16 x i16>,
i16,
- i64);
+ iXLen);
-define <vscale x 16 x i16> @intrinsic_vaaddu_vx_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, i16 %1, i64 %2) nounwind {
+define <vscale x 16 x i16> @intrinsic_vaaddu_vx_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, i16 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vaaddu_vx_nxv16i16_nxv16i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
@@ -1573,7 +1542,7 @@ entry:
<vscale x 16 x i16> undef,
<vscale x 16 x i16> %0,
i16 %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 16 x i16> %a
}
@@ -1583,10 +1552,9 @@ declare <vscale x 16 x i16> @llvm.riscv.vaaddu.mask.nxv16i16.i16(
<vscale x 16 x i16>,
i16,
<vscale x 16 x i1>,
- i64,
- i64);
+ iXLen, iXLen);
-define <vscale x 16 x i16> @intrinsic_vaaddu_mask_vx_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+define <vscale x 16 x i16> @intrinsic_vaaddu_mask_vx_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vaaddu_mask_vx_nxv16i16_nxv16i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
@@ -1598,7 +1566,7 @@ entry:
<vscale x 16 x i16> %1,
i16 %2,
<vscale x 16 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 16 x i16> %a
}
@@ -1607,9 +1575,9 @@ declare <vscale x 32 x i16> @llvm.riscv.vaaddu.nxv32i16.i16(
<vscale x 32 x i16>,
<vscale x 32 x i16>,
i16,
- i64);
+ iXLen);
-define <vscale x 32 x i16> @intrinsic_vaaddu_vx_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, i16 %1, i64 %2) nounwind {
+define <vscale x 32 x i16> @intrinsic_vaaddu_vx_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, i16 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vaaddu_vx_nxv32i16_nxv32i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu
@@ -1620,7 +1588,7 @@ entry:
<vscale x 32 x i16> undef,
<vscale x 32 x i16> %0,
i16 %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 32 x i16> %a
}
@@ -1630,10 +1598,9 @@ declare <vscale x 32 x i16> @llvm.riscv.vaaddu.mask.nxv32i16.i16(
<vscale x 32 x i16>,
i16,
<vscale x 32 x i1>,
- i64,
- i64);
+ iXLen, iXLen);
-define <vscale x 32 x i16> @intrinsic_vaaddu_mask_vx_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, i16 %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
+define <vscale x 32 x i16> @intrinsic_vaaddu_mask_vx_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, i16 %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vaaddu_mask_vx_nxv32i16_nxv32i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu
@@ -1645,7 +1612,7 @@ entry:
<vscale x 32 x i16> %1,
i16 %2,
<vscale x 32 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 32 x i16> %a
}
@@ -1654,9 +1621,9 @@ declare <vscale x 1 x i32> @llvm.riscv.vaaddu.nxv1i32.i32(
<vscale x 1 x i32>,
<vscale x 1 x i32>,
i32,
- i64);
+ iXLen);
-define <vscale x 1 x i32> @intrinsic_vaaddu_vx_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, i32 %1, i64 %2) nounwind {
+define <vscale x 1 x i32> @intrinsic_vaaddu_vx_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, i32 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vaaddu_vx_nxv1i32_nxv1i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
@@ -1667,7 +1634,7 @@ entry:
<vscale x 1 x i32> undef,
<vscale x 1 x i32> %0,
i32 %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 1 x i32> %a
}
@@ -1677,10 +1644,9 @@ declare <vscale x 1 x i32> @llvm.riscv.vaaddu.mask.nxv1i32.i32(
<vscale x 1 x i32>,
i32,
<vscale x 1 x i1>,
- i64,
- i64);
+ iXLen, iXLen);
-define <vscale x 1 x i32> @intrinsic_vaaddu_mask_vx_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+define <vscale x 1 x i32> @intrinsic_vaaddu_mask_vx_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vaaddu_mask_vx_nxv1i32_nxv1i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
@@ -1692,7 +1658,7 @@ entry:
<vscale x 1 x i32> %1,
i32 %2,
<vscale x 1 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 1 x i32> %a
}
@@ -1701,9 +1667,9 @@ declare <vscale x 2 x i32> @llvm.riscv.vaaddu.nxv2i32.i32(
<vscale x 2 x i32>,
<vscale x 2 x i32>,
i32,
- i64);
+ iXLen);
-define <vscale x 2 x i32> @intrinsic_vaaddu_vx_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, i32 %1, i64 %2) nounwind {
+define <vscale x 2 x i32> @intrinsic_vaaddu_vx_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, i32 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vaaddu_vx_nxv2i32_nxv2i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
@@ -1714,7 +1680,7 @@ entry:
<vscale x 2 x i32> undef,
<vscale x 2 x i32> %0,
i32 %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 2 x i32> %a
}
@@ -1724,10 +1690,9 @@ declare <vscale x 2 x i32> @llvm.riscv.vaaddu.mask.nxv2i32.i32(
<vscale x 2 x i32>,
i32,
<vscale x 2 x i1>,
- i64,
- i64);
+ iXLen, iXLen);
-define <vscale x 2 x i32> @intrinsic_vaaddu_mask_vx_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+define <vscale x 2 x i32> @intrinsic_vaaddu_mask_vx_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vaaddu_mask_vx_nxv2i32_nxv2i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
@@ -1739,7 +1704,7 @@ entry:
<vscale x 2 x i32> %1,
i32 %2,
<vscale x 2 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 2 x i32> %a
}
@@ -1748,9 +1713,9 @@ declare <vscale x 4 x i32> @llvm.riscv.vaaddu.nxv4i32.i32(
<vscale x 4 x i32>,
<vscale x 4 x i32>,
i32,
- i64);
+ iXLen);
-define <vscale x 4 x i32> @intrinsic_vaaddu_vx_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, i32 %1, i64 %2) nounwind {
+define <vscale x 4 x i32> @intrinsic_vaaddu_vx_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, i32 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vaaddu_vx_nxv4i32_nxv4i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
@@ -1761,7 +1726,7 @@ entry:
<vscale x 4 x i32> undef,
<vscale x 4 x i32> %0,
i32 %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 4 x i32> %a
}
@@ -1771,10 +1736,9 @@ declare <vscale x 4 x i32> @llvm.riscv.vaaddu.mask.nxv4i32.i32(
<vscale x 4 x i32>,
i32,
<vscale x 4 x i1>,
- i64,
- i64);
+ iXLen, iXLen);
-define <vscale x 4 x i32> @intrinsic_vaaddu_mask_vx_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+define <vscale x 4 x i32> @intrinsic_vaaddu_mask_vx_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vaaddu_mask_vx_nxv4i32_nxv4i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
@@ -1786,7 +1750,7 @@ entry:
<vscale x 4 x i32> %1,
i32 %2,
<vscale x 4 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 4 x i32> %a
}
@@ -1795,9 +1759,9 @@ declare <vscale x 8 x i32> @llvm.riscv.vaaddu.nxv8i32.i32(
<vscale x 8 x i32>,
<vscale x 8 x i32>,
i32,
- i64);
+ iXLen);
-define <vscale x 8 x i32> @intrinsic_vaaddu_vx_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, i32 %1, i64 %2) nounwind {
+define <vscale x 8 x i32> @intrinsic_vaaddu_vx_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, i32 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vaaddu_vx_nxv8i32_nxv8i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
@@ -1808,7 +1772,7 @@ entry:
<vscale x 8 x i32> undef,
<vscale x 8 x i32> %0,
i32 %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 8 x i32> %a
}
@@ -1818,10 +1782,9 @@ declare <vscale x 8 x i32> @llvm.riscv.vaaddu.mask.nxv8i32.i32(
<vscale x 8 x i32>,
i32,
<vscale x 8 x i1>,
- i64,
- i64);
+ iXLen, iXLen);
-define <vscale x 8 x i32> @intrinsic_vaaddu_mask_vx_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+define <vscale x 8 x i32> @intrinsic_vaaddu_mask_vx_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vaaddu_mask_vx_nxv8i32_nxv8i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
@@ -1833,7 +1796,7 @@ entry:
<vscale x 8 x i32> %1,
i32 %2,
<vscale x 8 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 8 x i32> %a
}
@@ -1842,9 +1805,9 @@ declare <vscale x 16 x i32> @llvm.riscv.vaaddu.nxv16i32.i32(
<vscale x 16 x i32>,
<vscale x 16 x i32>,
i32,
- i64);
+ iXLen);
-define <vscale x 16 x i32> @intrinsic_vaaddu_vx_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, i32 %1, i64 %2) nounwind {
+define <vscale x 16 x i32> @intrinsic_vaaddu_vx_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, i32 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vaaddu_vx_nxv16i32_nxv16i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu
@@ -1855,7 +1818,7 @@ entry:
<vscale x 16 x i32> undef,
<vscale x 16 x i32> %0,
i32 %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 16 x i32> %a
}
@@ -1865,10 +1828,9 @@ declare <vscale x 16 x i32> @llvm.riscv.vaaddu.mask.nxv16i32.i32(
<vscale x 16 x i32>,
i32,
<vscale x 16 x i1>,
- i64,
- i64);
+ iXLen, iXLen);
-define <vscale x 16 x i32> @intrinsic_vaaddu_mask_vx_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+define <vscale x 16 x i32> @intrinsic_vaaddu_mask_vx_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vaaddu_mask_vx_nxv16i32_nxv16i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu
@@ -1880,7 +1842,7 @@ entry:
<vscale x 16 x i32> %1,
i32 %2,
<vscale x 16 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 16 x i32> %a
}
@@ -1889,20 +1851,32 @@ declare <vscale x 1 x i64> @llvm.riscv.vaaddu.nxv1i64.i64(
<vscale x 1 x i64>,
<vscale x 1 x i64>,
i64,
- i64);
-
-define <vscale x 1 x i64> @intrinsic_vaaddu_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vaaddu_vx_nxv1i64_nxv1i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
-; CHECK-NEXT: vaaddu.vx v8, v8, a0
-; CHECK-NEXT: ret
+ iXLen);
+
+define <vscale x 1 x i64> @intrinsic_vaaddu_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, iXLen %2) nounwind {
+; RV32-LABEL: intrinsic_vaaddu_vx_nxv1i64_nxv1i64_i64:
+; RV32: # %bb.0: # %entry
+; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: sw a1, 12(sp)
+; RV32-NEXT: sw a0, 8(sp)
+; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
+; RV32-NEXT: addi a0, sp, 8
+; RV32-NEXT: vlse64.v v9, (a0), zero
+; RV32-NEXT: vaaddu.vv v8, v8, v9
+; RV32-NEXT: addi sp, sp, 16
+; RV32-NEXT: ret
+;
+; RV64-LABEL: intrinsic_vaaddu_vx_nxv1i64_nxv1i64_i64:
+; RV64: # %bb.0: # %entry
+; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, mu
+; RV64-NEXT: vaaddu.vx v8, v8, a0
+; RV64-NEXT: ret
entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vaaddu.nxv1i64.i64(
<vscale x 1 x i64> undef,
<vscale x 1 x i64> %0,
i64 %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 1 x i64> %a
}
@@ -1912,22 +1886,33 @@ declare <vscale x 1 x i64> @llvm.riscv.vaaddu.mask.nxv1i64.i64(
<vscale x 1 x i64>,
i64,
<vscale x 1 x i1>,
- i64,
- i64);
-
-define <vscale x 1 x i64> @intrinsic_vaaddu_mask_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vaaddu_mask_vx_nxv1i64_nxv1i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
-; CHECK-NEXT: vaaddu.vx v8, v9, a0, v0.t
-; CHECK-NEXT: ret
+ iXLen, iXLen);
+
+define <vscale x 1 x i64> @intrinsic_vaaddu_mask_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
+; RV32-LABEL: intrinsic_vaaddu_mask_vx_nxv1i64_nxv1i64_i64:
+; RV32: # %bb.0: # %entry
+; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: sw a1, 12(sp)
+; RV32-NEXT: sw a0, 8(sp)
+; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
+; RV32-NEXT: addi a0, sp, 8
+; RV32-NEXT: vlse64.v v10, (a0), zero
+; RV32-NEXT: vaaddu.vv v8, v9, v10, v0.t
+; RV32-NEXT: addi sp, sp, 16
+; RV32-NEXT: ret
+;
+; RV64-LABEL: intrinsic_vaaddu_mask_vx_nxv1i64_nxv1i64_i64:
+; RV64: # %bb.0: # %entry
+; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, mu
+; RV64-NEXT: vaaddu.vx v8, v9, a0, v0.t
+; RV64-NEXT: ret
entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vaaddu.mask.nxv1i64.i64(
<vscale x 1 x i64> %0,
<vscale x 1 x i64> %1,
i64 %2,
<vscale x 1 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 1 x i64> %a
}
@@ -1936,20 +1921,32 @@ declare <vscale x 2 x i64> @llvm.riscv.vaaddu.nxv2i64.i64(
<vscale x 2 x i64>,
<vscale x 2 x i64>,
i64,
- i64);
-
-define <vscale x 2 x i64> @intrinsic_vaaddu_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vaaddu_vx_nxv2i64_nxv2i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
-; CHECK-NEXT: vaaddu.vx v8, v8, a0
-; CHECK-NEXT: ret
+ iXLen);
+
+define <vscale x 2 x i64> @intrinsic_vaaddu_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, iXLen %2) nounwind {
+; RV32-LABEL: intrinsic_vaaddu_vx_nxv2i64_nxv2i64_i64:
+; RV32: # %bb.0: # %entry
+; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: sw a1, 12(sp)
+; RV32-NEXT: sw a0, 8(sp)
+; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
+; RV32-NEXT: addi a0, sp, 8
+; RV32-NEXT: vlse64.v v10, (a0), zero
+; RV32-NEXT: vaaddu.vv v8, v8, v10
+; RV32-NEXT: addi sp, sp, 16
+; RV32-NEXT: ret
+;
+; RV64-LABEL: intrinsic_vaaddu_vx_nxv2i64_nxv2i64_i64:
+; RV64: # %bb.0: # %entry
+; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, mu
+; RV64-NEXT: vaaddu.vx v8, v8, a0
+; RV64-NEXT: ret
entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vaaddu.nxv2i64.i64(
<vscale x 2 x i64> undef,
<vscale x 2 x i64> %0,
i64 %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 2 x i64> %a
}
@@ -1959,22 +1956,33 @@ declare <vscale x 2 x i64> @llvm.riscv.vaaddu.mask.nxv2i64.i64(
<vscale x 2 x i64>,
i64,
<vscale x 2 x i1>,
- i64,
- i64);
-
-define <vscale x 2 x i64> @intrinsic_vaaddu_mask_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vaaddu_mask_vx_nxv2i64_nxv2i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
-; CHECK-NEXT: vaaddu.vx v8, v10, a0, v0.t
-; CHECK-NEXT: ret
+ iXLen, iXLen);
+
+define <vscale x 2 x i64> @intrinsic_vaaddu_mask_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
+; RV32-LABEL: intrinsic_vaaddu_mask_vx_nxv2i64_nxv2i64_i64:
+; RV32: # %bb.0: # %entry
+; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: sw a1, 12(sp)
+; RV32-NEXT: sw a0, 8(sp)
+; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
+; RV32-NEXT: addi a0, sp, 8
+; RV32-NEXT: vlse64.v v12, (a0), zero
+; RV32-NEXT: vaaddu.vv v8, v10, v12, v0.t
+; RV32-NEXT: addi sp, sp, 16
+; RV32-NEXT: ret
+;
+; RV64-LABEL: intrinsic_vaaddu_mask_vx_nxv2i64_nxv2i64_i64:
+; RV64: # %bb.0: # %entry
+; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, mu
+; RV64-NEXT: vaaddu.vx v8, v10, a0, v0.t
+; RV64-NEXT: ret
entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vaaddu.mask.nxv2i64.i64(
<vscale x 2 x i64> %0,
<vscale x 2 x i64> %1,
i64 %2,
<vscale x 2 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 2 x i64> %a
}
@@ -1983,20 +1991,32 @@ declare <vscale x 4 x i64> @llvm.riscv.vaaddu.nxv4i64.i64(
<vscale x 4 x i64>,
<vscale x 4 x i64>,
i64,
- i64);
-
-define <vscale x 4 x i64> @intrinsic_vaaddu_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vaaddu_vx_nxv4i64_nxv4i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
-; CHECK-NEXT: vaaddu.vx v8, v8, a0
-; CHECK-NEXT: ret
+ iXLen);
+
+define <vscale x 4 x i64> @intrinsic_vaaddu_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, iXLen %2) nounwind {
+; RV32-LABEL: intrinsic_vaaddu_vx_nxv4i64_nxv4i64_i64:
+; RV32: # %bb.0: # %entry
+; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: sw a1, 12(sp)
+; RV32-NEXT: sw a0, 8(sp)
+; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
+; RV32-NEXT: addi a0, sp, 8
+; RV32-NEXT: vlse64.v v12, (a0), zero
+; RV32-NEXT: vaaddu.vv v8, v8, v12
+; RV32-NEXT: addi sp, sp, 16
+; RV32-NEXT: ret
+;
+; RV64-LABEL: intrinsic_vaaddu_vx_nxv4i64_nxv4i64_i64:
+; RV64: # %bb.0: # %entry
+; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu
+; RV64-NEXT: vaaddu.vx v8, v8, a0
+; RV64-NEXT: ret
entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vaaddu.nxv4i64.i64(
<vscale x 4 x i64> undef,
<vscale x 4 x i64> %0,
i64 %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 4 x i64> %a
}
@@ -2006,22 +2026,33 @@ declare <vscale x 4 x i64> @llvm.riscv.vaaddu.mask.nxv4i64.i64(
<vscale x 4 x i64>,
i64,
<vscale x 4 x i1>,
- i64,
- i64);
-
-define <vscale x 4 x i64> @intrinsic_vaaddu_mask_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vaaddu_mask_vx_nxv4i64_nxv4i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
-; CHECK-NEXT: vaaddu.vx v8, v12, a0, v0.t
-; CHECK-NEXT: ret
+ iXLen, iXLen);
+
+define <vscale x 4 x i64> @intrinsic_vaaddu_mask_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
+; RV32-LABEL: intrinsic_vaaddu_mask_vx_nxv4i64_nxv4i64_i64:
+; RV32: # %bb.0: # %entry
+; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: sw a1, 12(sp)
+; RV32-NEXT: sw a0, 8(sp)
+; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
+; RV32-NEXT: addi a0, sp, 8
+; RV32-NEXT: vlse64.v v16, (a0), zero
+; RV32-NEXT: vaaddu.vv v8, v12, v16, v0.t
+; RV32-NEXT: addi sp, sp, 16
+; RV32-NEXT: ret
+;
+; RV64-LABEL: intrinsic_vaaddu_mask_vx_nxv4i64_nxv4i64_i64:
+; RV64: # %bb.0: # %entry
+; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu
+; RV64-NEXT: vaaddu.vx v8, v12, a0, v0.t
+; RV64-NEXT: ret
entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vaaddu.mask.nxv4i64.i64(
<vscale x 4 x i64> %0,
<vscale x 4 x i64> %1,
i64 %2,
<vscale x 4 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 4 x i64> %a
}
@@ -2030,20 +2061,32 @@ declare <vscale x 8 x i64> @llvm.riscv.vaaddu.nxv8i64.i64(
<vscale x 8 x i64>,
<vscale x 8 x i64>,
i64,
- i64);
-
-define <vscale x 8 x i64> @intrinsic_vaaddu_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, i64 %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vaaddu_vx_nxv8i64_nxv8i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu
-; CHECK-NEXT: vaaddu.vx v8, v8, a0
-; CHECK-NEXT: ret
+ iXLen);
+
+define <vscale x 8 x i64> @intrinsic_vaaddu_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, i64 %1, iXLen %2) nounwind {
+; RV32-LABEL: intrinsic_vaaddu_vx_nxv8i64_nxv8i64_i64:
+; RV32: # %bb.0: # %entry
+; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: sw a1, 12(sp)
+; RV32-NEXT: sw a0, 8(sp)
+; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu
+; RV32-NEXT: addi a0, sp, 8
+; RV32-NEXT: vlse64.v v16, (a0), zero
+; RV32-NEXT: vaaddu.vv v8, v8, v16
+; RV32-NEXT: addi sp, sp, 16
+; RV32-NEXT: ret
+;
+; RV64-LABEL: intrinsic_vaaddu_vx_nxv8i64_nxv8i64_i64:
+; RV64: # %bb.0: # %entry
+; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, mu
+; RV64-NEXT: vaaddu.vx v8, v8, a0
+; RV64-NEXT: ret
entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vaaddu.nxv8i64.i64(
<vscale x 8 x i64> undef,
<vscale x 8 x i64> %0,
i64 %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 8 x i64> %a
}
@@ -2053,22 +2096,33 @@ declare <vscale x 8 x i64> @llvm.riscv.vaaddu.mask.nxv8i64.i64(
<vscale x 8 x i64>,
i64,
<vscale x 8 x i1>,
- i64,
- i64);
-
-define <vscale x 8 x i64> @intrinsic_vaaddu_mask_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vaaddu_mask_vx_nxv8i64_nxv8i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu
-; CHECK-NEXT: vaaddu.vx v8, v16, a0, v0.t
-; CHECK-NEXT: ret
+ iXLen, iXLen);
+
+define <vscale x 8 x i64> @intrinsic_vaaddu_mask_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
+; RV32-LABEL: intrinsic_vaaddu_mask_vx_nxv8i64_nxv8i64_i64:
+; RV32: # %bb.0: # %entry
+; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: sw a1, 12(sp)
+; RV32-NEXT: sw a0, 8(sp)
+; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu
+; RV32-NEXT: addi a0, sp, 8
+; RV32-NEXT: vlse64.v v24, (a0), zero
+; RV32-NEXT: vaaddu.vv v8, v16, v24, v0.t
+; RV32-NEXT: addi sp, sp, 16
+; RV32-NEXT: ret
+;
+; RV64-LABEL: intrinsic_vaaddu_mask_vx_nxv8i64_nxv8i64_i64:
+; RV64: # %bb.0: # %entry
+; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, mu
+; RV64-NEXT: vaaddu.vx v8, v16, a0, v0.t
+; RV64-NEXT: ret
entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vaaddu.mask.nxv8i64.i64(
<vscale x 8 x i64> %0,
<vscale x 8 x i64> %1,
i64 %2,
<vscale x 8 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 8 x i64> %a
}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vadd-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vadd-rv64.ll
deleted file mode 100644
index 5f1bd6842cc29..0000000000000
--- a/llvm/test/CodeGen/RISCV/rvv/vadd-rv64.ll
+++ /dev/null
@@ -1,2800 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs \
-; RUN: < %s | FileCheck %s
-declare <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.nxv1i8(
- <vscale x 1 x i8>,
- <vscale x 1 x i8>,
- <vscale x 1 x i8>,
- i64);
-
-define <vscale x 1 x i8> @intrinsic_vadd_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vadd_vv_nxv1i8_nxv1i8_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
-; CHECK-NEXT: vadd.vv v8, v8, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.nxv1i8(
- <vscale x 1 x i8> undef,
- <vscale x 1 x i8> %0,
- <vscale x 1 x i8> %1,
- i64 %2)
-
- ret <vscale x 1 x i8> %a
-}
-
-declare <vscale x 1 x i8> @llvm.riscv.vadd.mask.nxv1i8.nxv1i8(
- <vscale x 1 x i8>,
- <vscale x 1 x i8>,
- <vscale x 1 x i8>,
- <vscale x 1 x i1>,
- i64,
- i64);
-
-define <vscale x 1 x i8> @intrinsic_vadd_mask_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv1i8_nxv1i8_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
-; CHECK-NEXT: vadd.vv v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i8> @llvm.riscv.vadd.mask.nxv1i8.nxv1i8(
- <vscale x 1 x i8> %0,
- <vscale x 1 x i8> %1,
- <vscale x 1 x i8> %2,
- <vscale x 1 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 1 x i8> %a
-}
-
-declare <vscale x 2 x i8> @llvm.riscv.vadd.nxv2i8.nxv2i8(
- <vscale x 2 x i8>,
- <vscale x 2 x i8>,
- <vscale x 2 x i8>,
- i64);
-
-define <vscale x 2 x i8> @intrinsic_vadd_vv_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vadd_vv_nxv2i8_nxv2i8_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
-; CHECK-NEXT: vadd.vv v8, v8, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i8> @llvm.riscv.vadd.nxv2i8.nxv2i8(
- <vscale x 2 x i8> undef,
- <vscale x 2 x i8> %0,
- <vscale x 2 x i8> %1,
- i64 %2)
-
- ret <vscale x 2 x i8> %a
-}
-
-declare <vscale x 2 x i8> @llvm.riscv.vadd.mask.nxv2i8.nxv2i8(
- <vscale x 2 x i8>,
- <vscale x 2 x i8>,
- <vscale x 2 x i8>,
- <vscale x 2 x i1>,
- i64,
- i64);
-
-define <vscale x 2 x i8> @intrinsic_vadd_mask_vv_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv2i8_nxv2i8_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
-; CHECK-NEXT: vadd.vv v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i8> @llvm.riscv.vadd.mask.nxv2i8.nxv2i8(
- <vscale x 2 x i8> %0,
- <vscale x 2 x i8> %1,
- <vscale x 2 x i8> %2,
- <vscale x 2 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 2 x i8> %a
-}
-
-declare <vscale x 4 x i8> @llvm.riscv.vadd.nxv4i8.nxv4i8(
- <vscale x 4 x i8>,
- <vscale x 4 x i8>,
- <vscale x 4 x i8>,
- i64);
-
-define <vscale x 4 x i8> @intrinsic_vadd_vv_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vadd_vv_nxv4i8_nxv4i8_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
-; CHECK-NEXT: vadd.vv v8, v8, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i8> @llvm.riscv.vadd.nxv4i8.nxv4i8(
- <vscale x 4 x i8> undef,
- <vscale x 4 x i8> %0,
- <vscale x 4 x i8> %1,
- i64 %2)
-
- ret <vscale x 4 x i8> %a
-}
-
-declare <vscale x 4 x i8> @llvm.riscv.vadd.mask.nxv4i8.nxv4i8(
- <vscale x 4 x i8>,
- <vscale x 4 x i8>,
- <vscale x 4 x i8>,
- <vscale x 4 x i1>,
- i64,
- i64);
-
-define <vscale x 4 x i8> @intrinsic_vadd_mask_vv_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv4i8_nxv4i8_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
-; CHECK-NEXT: vadd.vv v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i8> @llvm.riscv.vadd.mask.nxv4i8.nxv4i8(
- <vscale x 4 x i8> %0,
- <vscale x 4 x i8> %1,
- <vscale x 4 x i8> %2,
- <vscale x 4 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 4 x i8> %a
-}
-
-declare <vscale x 8 x i8> @llvm.riscv.vadd.nxv8i8.nxv8i8(
- <vscale x 8 x i8>,
- <vscale x 8 x i8>,
- <vscale x 8 x i8>,
- i64);
-
-define <vscale x 8 x i8> @intrinsic_vadd_vv_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vadd_vv_nxv8i8_nxv8i8_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
-; CHECK-NEXT: vadd.vv v8, v8, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i8> @llvm.riscv.vadd.nxv8i8.nxv8i8(
- <vscale x 8 x i8> undef,
- <vscale x 8 x i8> %0,
- <vscale x 8 x i8> %1,
- i64 %2)
-
- ret <vscale x 8 x i8> %a
-}
-
-declare <vscale x 8 x i8> @llvm.riscv.vadd.mask.nxv8i8.nxv8i8(
- <vscale x 8 x i8>,
- <vscale x 8 x i8>,
- <vscale x 8 x i8>,
- <vscale x 8 x i1>,
- i64,
- i64);
-
-define <vscale x 8 x i8> @intrinsic_vadd_mask_vv_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv8i8_nxv8i8_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
-; CHECK-NEXT: vadd.vv v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i8> @llvm.riscv.vadd.mask.nxv8i8.nxv8i8(
- <vscale x 8 x i8> %0,
- <vscale x 8 x i8> %1,
- <vscale x 8 x i8> %2,
- <vscale x 8 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 8 x i8> %a
-}
-
-declare <vscale x 16 x i8> @llvm.riscv.vadd.nxv16i8.nxv16i8(
- <vscale x 16 x i8>,
- <vscale x 16 x i8>,
- <vscale x 16 x i8>,
- i64);
-
-define <vscale x 16 x i8> @intrinsic_vadd_vv_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vadd_vv_nxv16i8_nxv16i8_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
-; CHECK-NEXT: vadd.vv v8, v8, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i8> @llvm.riscv.vadd.nxv16i8.nxv16i8(
- <vscale x 16 x i8> undef,
- <vscale x 16 x i8> %0,
- <vscale x 16 x i8> %1,
- i64 %2)
-
- ret <vscale x 16 x i8> %a
-}
-
-declare <vscale x 16 x i8> @llvm.riscv.vadd.mask.nxv16i8.nxv16i8(
- <vscale x 16 x i8>,
- <vscale x 16 x i8>,
- <vscale x 16 x i8>,
- <vscale x 16 x i1>,
- i64,
- i64);
-
-define <vscale x 16 x i8> @intrinsic_vadd_mask_vv_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv16i8_nxv16i8_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
-; CHECK-NEXT: vadd.vv v8, v10, v12, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i8> @llvm.riscv.vadd.mask.nxv16i8.nxv16i8(
- <vscale x 16 x i8> %0,
- <vscale x 16 x i8> %1,
- <vscale x 16 x i8> %2,
- <vscale x 16 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 16 x i8> %a
-}
-
-declare <vscale x 32 x i8> @llvm.riscv.vadd.nxv32i8.nxv32i8(
- <vscale x 32 x i8>,
- <vscale x 32 x i8>,
- <vscale x 32 x i8>,
- i64);
-
-define <vscale x 32 x i8> @intrinsic_vadd_vv_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vadd_vv_nxv32i8_nxv32i8_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
-; CHECK-NEXT: vadd.vv v8, v8, v12
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 32 x i8> @llvm.riscv.vadd.nxv32i8.nxv32i8(
- <vscale x 32 x i8> undef,
- <vscale x 32 x i8> %0,
- <vscale x 32 x i8> %1,
- i64 %2)
-
- ret <vscale x 32 x i8> %a
-}
-
-declare <vscale x 32 x i8> @llvm.riscv.vadd.mask.nxv32i8.nxv32i8(
- <vscale x 32 x i8>,
- <vscale x 32 x i8>,
- <vscale x 32 x i8>,
- <vscale x 32 x i1>,
- i64,
- i64);
-
-define <vscale x 32 x i8> @intrinsic_vadd_mask_vv_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv32i8_nxv32i8_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
-; CHECK-NEXT: vadd.vv v8, v12, v16, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 32 x i8> @llvm.riscv.vadd.mask.nxv32i8.nxv32i8(
- <vscale x 32 x i8> %0,
- <vscale x 32 x i8> %1,
- <vscale x 32 x i8> %2,
- <vscale x 32 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 32 x i8> %a
-}
-
-declare <vscale x 64 x i8> @llvm.riscv.vadd.nxv64i8.nxv64i8(
- <vscale x 64 x i8>,
- <vscale x 64 x i8>,
- <vscale x 64 x i8>,
- i64);
-
-define <vscale x 64 x i8> @intrinsic_vadd_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vadd_vv_nxv64i8_nxv64i8_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, mu
-; CHECK-NEXT: vadd.vv v8, v8, v16
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 64 x i8> @llvm.riscv.vadd.nxv64i8.nxv64i8(
- <vscale x 64 x i8> undef,
- <vscale x 64 x i8> %0,
- <vscale x 64 x i8> %1,
- i64 %2)
-
- ret <vscale x 64 x i8> %a
-}
-
-declare <vscale x 64 x i8> @llvm.riscv.vadd.mask.nxv64i8.nxv64i8(
- <vscale x 64 x i8>,
- <vscale x 64 x i8>,
- <vscale x 64 x i8>,
- <vscale x 64 x i1>,
- i64,
- i64);
-
-define <vscale x 64 x i8> @intrinsic_vadd_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv64i8_nxv64i8_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vl8r.v v24, (a0)
-; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu
-; CHECK-NEXT: vadd.vv v8, v16, v24, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 64 x i8> @llvm.riscv.vadd.mask.nxv64i8.nxv64i8(
- <vscale x 64 x i8> %0,
- <vscale x 64 x i8> %1,
- <vscale x 64 x i8> %2,
- <vscale x 64 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 64 x i8> %a
-}
-
-declare <vscale x 1 x i16> @llvm.riscv.vadd.nxv1i16.nxv1i16(
- <vscale x 1 x i16>,
- <vscale x 1 x i16>,
- <vscale x 1 x i16>,
- i64);
-
-define <vscale x 1 x i16> @intrinsic_vadd_vv_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vadd_vv_nxv1i16_nxv1i16_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vadd.vv v8, v8, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i16> @llvm.riscv.vadd.nxv1i16.nxv1i16(
- <vscale x 1 x i16> undef,
- <vscale x 1 x i16> %0,
- <vscale x 1 x i16> %1,
- i64 %2)
-
- ret <vscale x 1 x i16> %a
-}
-
-declare <vscale x 1 x i16> @llvm.riscv.vadd.mask.nxv1i16.nxv1i16(
- <vscale x 1 x i16>,
- <vscale x 1 x i16>,
- <vscale x 1 x i16>,
- <vscale x 1 x i1>,
- i64,
- i64);
-
-define <vscale x 1 x i16> @intrinsic_vadd_mask_vv_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv1i16_nxv1i16_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vadd.vv v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i16> @llvm.riscv.vadd.mask.nxv1i16.nxv1i16(
- <vscale x 1 x i16> %0,
- <vscale x 1 x i16> %1,
- <vscale x 1 x i16> %2,
- <vscale x 1 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 1 x i16> %a
-}
-
-declare <vscale x 2 x i16> @llvm.riscv.vadd.nxv2i16.nxv2i16(
- <vscale x 2 x i16>,
- <vscale x 2 x i16>,
- <vscale x 2 x i16>,
- i64);
-
-define <vscale x 2 x i16> @intrinsic_vadd_vv_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vadd_vv_nxv2i16_nxv2i16_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vadd.vv v8, v8, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i16> @llvm.riscv.vadd.nxv2i16.nxv2i16(
- <vscale x 2 x i16> undef,
- <vscale x 2 x i16> %0,
- <vscale x 2 x i16> %1,
- i64 %2)
-
- ret <vscale x 2 x i16> %a
-}
-
-declare <vscale x 2 x i16> @llvm.riscv.vadd.mask.nxv2i16.nxv2i16(
- <vscale x 2 x i16>,
- <vscale x 2 x i16>,
- <vscale x 2 x i16>,
- <vscale x 2 x i1>,
- i64,
- i64);
-
-define <vscale x 2 x i16> @intrinsic_vadd_mask_vv_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv2i16_nxv2i16_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vadd.vv v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i16> @llvm.riscv.vadd.mask.nxv2i16.nxv2i16(
- <vscale x 2 x i16> %0,
- <vscale x 2 x i16> %1,
- <vscale x 2 x i16> %2,
- <vscale x 2 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 2 x i16> %a
-}
-
-declare <vscale x 4 x i16> @llvm.riscv.vadd.nxv4i16.nxv4i16(
- <vscale x 4 x i16>,
- <vscale x 4 x i16>,
- <vscale x 4 x i16>,
- i64);
-
-define <vscale x 4 x i16> @intrinsic_vadd_vv_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vadd_vv_nxv4i16_nxv4i16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vadd.vv v8, v8, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i16> @llvm.riscv.vadd.nxv4i16.nxv4i16(
- <vscale x 4 x i16> undef,
- <vscale x 4 x i16> %0,
- <vscale x 4 x i16> %1,
- i64 %2)
-
- ret <vscale x 4 x i16> %a
-}
-
-declare <vscale x 4 x i16> @llvm.riscv.vadd.mask.nxv4i16.nxv4i16(
- <vscale x 4 x i16>,
- <vscale x 4 x i16>,
- <vscale x 4 x i16>,
- <vscale x 4 x i1>,
- i64,
- i64);
-
-define <vscale x 4 x i16> @intrinsic_vadd_mask_vv_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv4i16_nxv4i16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vadd.vv v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i16> @llvm.riscv.vadd.mask.nxv4i16.nxv4i16(
- <vscale x 4 x i16> %0,
- <vscale x 4 x i16> %1,
- <vscale x 4 x i16> %2,
- <vscale x 4 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 4 x i16> %a
-}
-
-declare <vscale x 8 x i16> @llvm.riscv.vadd.nxv8i16.nxv8i16(
- <vscale x 8 x i16>,
- <vscale x 8 x i16>,
- <vscale x 8 x i16>,
- i64);
-
-define <vscale x 8 x i16> @intrinsic_vadd_vv_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vadd_vv_nxv8i16_nxv8i16_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vadd.vv v8, v8, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i16> @llvm.riscv.vadd.nxv8i16.nxv8i16(
- <vscale x 8 x i16> undef,
- <vscale x 8 x i16> %0,
- <vscale x 8 x i16> %1,
- i64 %2)
-
- ret <vscale x 8 x i16> %a
-}
-
-declare <vscale x 8 x i16> @llvm.riscv.vadd.mask.nxv8i16.nxv8i16(
- <vscale x 8 x i16>,
- <vscale x 8 x i16>,
- <vscale x 8 x i16>,
- <vscale x 8 x i1>,
- i64,
- i64);
-
-define <vscale x 8 x i16> @intrinsic_vadd_mask_vv_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv8i16_nxv8i16_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vadd.vv v8, v10, v12, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i16> @llvm.riscv.vadd.mask.nxv8i16.nxv8i16(
- <vscale x 8 x i16> %0,
- <vscale x 8 x i16> %1,
- <vscale x 8 x i16> %2,
- <vscale x 8 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 8 x i16> %a
-}
-
-declare <vscale x 16 x i16> @llvm.riscv.vadd.nxv16i16.nxv16i16(
- <vscale x 16 x i16>,
- <vscale x 16 x i16>,
- <vscale x 16 x i16>,
- i64);
-
-define <vscale x 16 x i16> @intrinsic_vadd_vv_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vadd_vv_nxv16i16_nxv16i16_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
-; CHECK-NEXT: vadd.vv v8, v8, v12
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i16> @llvm.riscv.vadd.nxv16i16.nxv16i16(
- <vscale x 16 x i16> undef,
- <vscale x 16 x i16> %0,
- <vscale x 16 x i16> %1,
- i64 %2)
-
- ret <vscale x 16 x i16> %a
-}
-
-declare <vscale x 16 x i16> @llvm.riscv.vadd.mask.nxv16i16.nxv16i16(
- <vscale x 16 x i16>,
- <vscale x 16 x i16>,
- <vscale x 16 x i16>,
- <vscale x 16 x i1>,
- i64,
- i64);
-
-define <vscale x 16 x i16> @intrinsic_vadd_mask_vv_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv16i16_nxv16i16_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
-; CHECK-NEXT: vadd.vv v8, v12, v16, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i16> @llvm.riscv.vadd.mask.nxv16i16.nxv16i16(
- <vscale x 16 x i16> %0,
- <vscale x 16 x i16> %1,
- <vscale x 16 x i16> %2,
- <vscale x 16 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 16 x i16> %a
-}
-
-declare <vscale x 32 x i16> @llvm.riscv.vadd.nxv32i16.nxv32i16(
- <vscale x 32 x i16>,
- <vscale x 32 x i16>,
- <vscale x 32 x i16>,
- i64);
-
-define <vscale x 32 x i16> @intrinsic_vadd_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vadd_vv_nxv32i16_nxv32i16_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, mu
-; CHECK-NEXT: vadd.vv v8, v8, v16
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 32 x i16> @llvm.riscv.vadd.nxv32i16.nxv32i16(
- <vscale x 32 x i16> undef,
- <vscale x 32 x i16> %0,
- <vscale x 32 x i16> %1,
- i64 %2)
-
- ret <vscale x 32 x i16> %a
-}
-
-declare <vscale x 32 x i16> @llvm.riscv.vadd.mask.nxv32i16.nxv32i16(
- <vscale x 32 x i16>,
- <vscale x 32 x i16>,
- <vscale x 32 x i16>,
- <vscale x 32 x i1>,
- i64,
- i64);
-
-define <vscale x 32 x i16> @intrinsic_vadd_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv32i16_nxv32i16_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vl8re16.v v24, (a0)
-; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu
-; CHECK-NEXT: vadd.vv v8, v16, v24, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 32 x i16> @llvm.riscv.vadd.mask.nxv32i16.nxv32i16(
- <vscale x 32 x i16> %0,
- <vscale x 32 x i16> %1,
- <vscale x 32 x i16> %2,
- <vscale x 32 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 32 x i16> %a
-}
-
-declare <vscale x 1 x i32> @llvm.riscv.vadd.nxv1i32.nxv1i32(
- <vscale x 1 x i32>,
- <vscale x 1 x i32>,
- <vscale x 1 x i32>,
- i64);
-
-define <vscale x 1 x i32> @intrinsic_vadd_vv_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vadd_vv_nxv1i32_nxv1i32_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vadd.vv v8, v8, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i32> @llvm.riscv.vadd.nxv1i32.nxv1i32(
- <vscale x 1 x i32> undef,
- <vscale x 1 x i32> %0,
- <vscale x 1 x i32> %1,
- i64 %2)
-
- ret <vscale x 1 x i32> %a
-}
-
-declare <vscale x 1 x i32> @llvm.riscv.vadd.mask.nxv1i32.nxv1i32(
- <vscale x 1 x i32>,
- <vscale x 1 x i32>,
- <vscale x 1 x i32>,
- <vscale x 1 x i1>,
- i64,
- i64);
-
-define <vscale x 1 x i32> @intrinsic_vadd_mask_vv_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv1i32_nxv1i32_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vadd.vv v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i32> @llvm.riscv.vadd.mask.nxv1i32.nxv1i32(
- <vscale x 1 x i32> %0,
- <vscale x 1 x i32> %1,
- <vscale x 1 x i32> %2,
- <vscale x 1 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 1 x i32> %a
-}
-
-declare <vscale x 2 x i32> @llvm.riscv.vadd.nxv2i32.nxv2i32(
- <vscale x 2 x i32>,
- <vscale x 2 x i32>,
- <vscale x 2 x i32>,
- i64);
-
-define <vscale x 2 x i32> @intrinsic_vadd_vv_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vadd_vv_nxv2i32_nxv2i32_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vadd.vv v8, v8, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i32> @llvm.riscv.vadd.nxv2i32.nxv2i32(
- <vscale x 2 x i32> undef,
- <vscale x 2 x i32> %0,
- <vscale x 2 x i32> %1,
- i64 %2)
-
- ret <vscale x 2 x i32> %a
-}
-
-declare <vscale x 2 x i32> @llvm.riscv.vadd.mask.nxv2i32.nxv2i32(
- <vscale x 2 x i32>,
- <vscale x 2 x i32>,
- <vscale x 2 x i32>,
- <vscale x 2 x i1>,
- i64,
- i64);
-
-define <vscale x 2 x i32> @intrinsic_vadd_mask_vv_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv2i32_nxv2i32_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vadd.vv v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i32> @llvm.riscv.vadd.mask.nxv2i32.nxv2i32(
- <vscale x 2 x i32> %0,
- <vscale x 2 x i32> %1,
- <vscale x 2 x i32> %2,
- <vscale x 2 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 2 x i32> %a
-}
-
-declare <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(
- <vscale x 4 x i32>,
- <vscale x 4 x i32>,
- <vscale x 4 x i32>,
- i64);
-
-define <vscale x 4 x i32> @intrinsic_vadd_vv_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vadd_vv_nxv4i32_nxv4i32_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vadd.vv v8, v8, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(
- <vscale x 4 x i32> undef,
- <vscale x 4 x i32> %0,
- <vscale x 4 x i32> %1,
- i64 %2)
-
- ret <vscale x 4 x i32> %a
-}
-
-declare <vscale x 4 x i32> @llvm.riscv.vadd.mask.nxv4i32.nxv4i32(
- <vscale x 4 x i32>,
- <vscale x 4 x i32>,
- <vscale x 4 x i32>,
- <vscale x 4 x i1>,
- i64,
- i64);
-
-define <vscale x 4 x i32> @intrinsic_vadd_mask_vv_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv4i32_nxv4i32_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vadd.vv v8, v10, v12, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i32> @llvm.riscv.vadd.mask.nxv4i32.nxv4i32(
- <vscale x 4 x i32> %0,
- <vscale x 4 x i32> %1,
- <vscale x 4 x i32> %2,
- <vscale x 4 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 4 x i32> %a
-}
-
-declare <vscale x 8 x i32> @llvm.riscv.vadd.nxv8i32.nxv8i32(
- <vscale x 8 x i32>,
- <vscale x 8 x i32>,
- <vscale x 8 x i32>,
- i64);
-
-define <vscale x 8 x i32> @intrinsic_vadd_vv_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vadd_vv_nxv8i32_nxv8i32_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
-; CHECK-NEXT: vadd.vv v8, v8, v12
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i32> @llvm.riscv.vadd.nxv8i32.nxv8i32(
- <vscale x 8 x i32> undef,
- <vscale x 8 x i32> %0,
- <vscale x 8 x i32> %1,
- i64 %2)
-
- ret <vscale x 8 x i32> %a
-}
-
-declare <vscale x 8 x i32> @llvm.riscv.vadd.mask.nxv8i32.nxv8i32(
- <vscale x 8 x i32>,
- <vscale x 8 x i32>,
- <vscale x 8 x i32>,
- <vscale x 8 x i1>,
- i64,
- i64);
-
-define <vscale x 8 x i32> @intrinsic_vadd_mask_vv_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv8i32_nxv8i32_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
-; CHECK-NEXT: vadd.vv v8, v12, v16, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i32> @llvm.riscv.vadd.mask.nxv8i32.nxv8i32(
- <vscale x 8 x i32> %0,
- <vscale x 8 x i32> %1,
- <vscale x 8 x i32> %2,
- <vscale x 8 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 8 x i32> %a
-}
-
-declare <vscale x 16 x i32> @llvm.riscv.vadd.nxv16i32.nxv16i32(
- <vscale x 16 x i32>,
- <vscale x 16 x i32>,
- <vscale x 16 x i32>,
- i64);
-
-define <vscale x 16 x i32> @intrinsic_vadd_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vadd_vv_nxv16i32_nxv16i32_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu
-; CHECK-NEXT: vadd.vv v8, v8, v16
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i32> @llvm.riscv.vadd.nxv16i32.nxv16i32(
- <vscale x 16 x i32> undef,
- <vscale x 16 x i32> %0,
- <vscale x 16 x i32> %1,
- i64 %2)
-
- ret <vscale x 16 x i32> %a
-}
-
-declare <vscale x 16 x i32> @llvm.riscv.vadd.mask.nxv16i32.nxv16i32(
- <vscale x 16 x i32>,
- <vscale x 16 x i32>,
- <vscale x 16 x i32>,
- <vscale x 16 x i1>,
- i64,
- i64);
-
-define <vscale x 16 x i32> @intrinsic_vadd_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv16i32_nxv16i32_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vl8re32.v v24, (a0)
-; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu
-; CHECK-NEXT: vadd.vv v8, v16, v24, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i32> @llvm.riscv.vadd.mask.nxv16i32.nxv16i32(
- <vscale x 16 x i32> %0,
- <vscale x 16 x i32> %1,
- <vscale x 16 x i32> %2,
- <vscale x 16 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 16 x i32> %a
-}
-
-declare <vscale x 1 x i64> @llvm.riscv.vadd.nxv1i64.nxv1i64(
- <vscale x 1 x i64>,
- <vscale x 1 x i64>,
- <vscale x 1 x i64>,
- i64);
-
-define <vscale x 1 x i64> @intrinsic_vadd_vv_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vadd_vv_nxv1i64_nxv1i64_nxv1i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
-; CHECK-NEXT: vadd.vv v8, v8, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i64> @llvm.riscv.vadd.nxv1i64.nxv1i64(
- <vscale x 1 x i64> undef,
- <vscale x 1 x i64> %0,
- <vscale x 1 x i64> %1,
- i64 %2)
-
- ret <vscale x 1 x i64> %a
-}
-
-declare <vscale x 1 x i64> @llvm.riscv.vadd.mask.nxv1i64.nxv1i64(
- <vscale x 1 x i64>,
- <vscale x 1 x i64>,
- <vscale x 1 x i64>,
- <vscale x 1 x i1>,
- i64,
- i64);
-
-define <vscale x 1 x i64> @intrinsic_vadd_mask_vv_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv1i64_nxv1i64_nxv1i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
-; CHECK-NEXT: vadd.vv v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i64> @llvm.riscv.vadd.mask.nxv1i64.nxv1i64(
- <vscale x 1 x i64> %0,
- <vscale x 1 x i64> %1,
- <vscale x 1 x i64> %2,
- <vscale x 1 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 1 x i64> %a
-}
-
-declare <vscale x 2 x i64> @llvm.riscv.vadd.nxv2i64.nxv2i64(
- <vscale x 2 x i64>,
- <vscale x 2 x i64>,
- <vscale x 2 x i64>,
- i64);
-
-define <vscale x 2 x i64> @intrinsic_vadd_vv_nxv2i64_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vadd_vv_nxv2i64_nxv2i64_nxv2i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
-; CHECK-NEXT: vadd.vv v8, v8, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i64> @llvm.riscv.vadd.nxv2i64.nxv2i64(
- <vscale x 2 x i64> undef,
- <vscale x 2 x i64> %0,
- <vscale x 2 x i64> %1,
- i64 %2)
-
- ret <vscale x 2 x i64> %a
-}
-
-declare <vscale x 2 x i64> @llvm.riscv.vadd.mask.nxv2i64.nxv2i64(
- <vscale x 2 x i64>,
- <vscale x 2 x i64>,
- <vscale x 2 x i64>,
- <vscale x 2 x i1>,
- i64,
- i64);
-
-define <vscale x 2 x i64> @intrinsic_vadd_mask_vv_nxv2i64_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv2i64_nxv2i64_nxv2i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
-; CHECK-NEXT: vadd.vv v8, v10, v12, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i64> @llvm.riscv.vadd.mask.nxv2i64.nxv2i64(
- <vscale x 2 x i64> %0,
- <vscale x 2 x i64> %1,
- <vscale x 2 x i64> %2,
- <vscale x 2 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 2 x i64> %a
-}
-
-declare <vscale x 4 x i64> @llvm.riscv.vadd.nxv4i64.nxv4i64(
- <vscale x 4 x i64>,
- <vscale x 4 x i64>,
- <vscale x 4 x i64>,
- i64);
-
-define <vscale x 4 x i64> @intrinsic_vadd_vv_nxv4i64_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vadd_vv_nxv4i64_nxv4i64_nxv4i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
-; CHECK-NEXT: vadd.vv v8, v8, v12
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i64> @llvm.riscv.vadd.nxv4i64.nxv4i64(
- <vscale x 4 x i64> undef,
- <vscale x 4 x i64> %0,
- <vscale x 4 x i64> %1,
- i64 %2)
-
- ret <vscale x 4 x i64> %a
-}
-
-declare <vscale x 4 x i64> @llvm.riscv.vadd.mask.nxv4i64.nxv4i64(
- <vscale x 4 x i64>,
- <vscale x 4 x i64>,
- <vscale x 4 x i64>,
- <vscale x 4 x i1>,
- i64,
- i64);
-
-define <vscale x 4 x i64> @intrinsic_vadd_mask_vv_nxv4i64_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv4i64_nxv4i64_nxv4i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
-; CHECK-NEXT: vadd.vv v8, v12, v16, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i64> @llvm.riscv.vadd.mask.nxv4i64.nxv4i64(
- <vscale x 4 x i64> %0,
- <vscale x 4 x i64> %1,
- <vscale x 4 x i64> %2,
- <vscale x 4 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 4 x i64> %a
-}
-
-declare <vscale x 8 x i64> @llvm.riscv.vadd.nxv8i64.nxv8i64(
- <vscale x 8 x i64>,
- <vscale x 8 x i64>,
- <vscale x 8 x i64>,
- i64);
-
-define <vscale x 8 x i64> @intrinsic_vadd_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vadd_vv_nxv8i64_nxv8i64_nxv8i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu
-; CHECK-NEXT: vadd.vv v8, v8, v16
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i64> @llvm.riscv.vadd.nxv8i64.nxv8i64(
- <vscale x 8 x i64> undef,
- <vscale x 8 x i64> %0,
- <vscale x 8 x i64> %1,
- i64 %2)
-
- ret <vscale x 8 x i64> %a
-}
-
-declare <vscale x 8 x i64> @llvm.riscv.vadd.mask.nxv8i64.nxv8i64(
- <vscale x 8 x i64>,
- <vscale x 8 x i64>,
- <vscale x 8 x i64>,
- <vscale x 8 x i1>,
- i64,
- i64);
-
-define <vscale x 8 x i64> @intrinsic_vadd_mask_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv8i64_nxv8i64_nxv8i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vl8re64.v v24, (a0)
-; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu
-; CHECK-NEXT: vadd.vv v8, v16, v24, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i64> @llvm.riscv.vadd.mask.nxv8i64.nxv8i64(
- <vscale x 8 x i64> %0,
- <vscale x 8 x i64> %1,
- <vscale x 8 x i64> %2,
- <vscale x 8 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 8 x i64> %a
-}
-
-declare <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.i8(
- <vscale x 1 x i8>,
- <vscale x 1 x i8>,
- i8,
- i64);
-
-define <vscale x 1 x i8> @intrinsic_vadd_vx_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, i8 %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vadd_vx_nxv1i8_nxv1i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
-; CHECK-NEXT: vadd.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.i8(
- <vscale x 1 x i8> undef,
- <vscale x 1 x i8> %0,
- i8 %1,
- i64 %2)
-
- ret <vscale x 1 x i8> %a
-}
-
-declare <vscale x 1 x i8> @llvm.riscv.vadd.mask.nxv1i8.i8(
- <vscale x 1 x i8>,
- <vscale x 1 x i8>,
- i8,
- <vscale x 1 x i1>,
- i64,
- i64);
-
-define <vscale x 1 x i8> @intrinsic_vadd_mask_vx_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv1i8_nxv1i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
-; CHECK-NEXT: vadd.vx v8, v9, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i8> @llvm.riscv.vadd.mask.nxv1i8.i8(
- <vscale x 1 x i8> %0,
- <vscale x 1 x i8> %1,
- i8 %2,
- <vscale x 1 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 1 x i8> %a
-}
-
-declare <vscale x 2 x i8> @llvm.riscv.vadd.nxv2i8.i8(
- <vscale x 2 x i8>,
- <vscale x 2 x i8>,
- i8,
- i64);
-
-define <vscale x 2 x i8> @intrinsic_vadd_vx_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, i8 %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vadd_vx_nxv2i8_nxv2i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
-; CHECK-NEXT: vadd.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i8> @llvm.riscv.vadd.nxv2i8.i8(
- <vscale x 2 x i8> undef,
- <vscale x 2 x i8> %0,
- i8 %1,
- i64 %2)
-
- ret <vscale x 2 x i8> %a
-}
-
-declare <vscale x 2 x i8> @llvm.riscv.vadd.mask.nxv2i8.i8(
- <vscale x 2 x i8>,
- <vscale x 2 x i8>,
- i8,
- <vscale x 2 x i1>,
- i64,
- i64);
-
-define <vscale x 2 x i8> @intrinsic_vadd_mask_vx_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv2i8_nxv2i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
-; CHECK-NEXT: vadd.vx v8, v9, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i8> @llvm.riscv.vadd.mask.nxv2i8.i8(
- <vscale x 2 x i8> %0,
- <vscale x 2 x i8> %1,
- i8 %2,
- <vscale x 2 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 2 x i8> %a
-}
-
-declare <vscale x 4 x i8> @llvm.riscv.vadd.nxv4i8.i8(
- <vscale x 4 x i8>,
- <vscale x 4 x i8>,
- i8,
- i64);
-
-define <vscale x 4 x i8> @intrinsic_vadd_vx_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, i8 %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vadd_vx_nxv4i8_nxv4i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
-; CHECK-NEXT: vadd.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i8> @llvm.riscv.vadd.nxv4i8.i8(
- <vscale x 4 x i8> undef,
- <vscale x 4 x i8> %0,
- i8 %1,
- i64 %2)
-
- ret <vscale x 4 x i8> %a
-}
-
-declare <vscale x 4 x i8> @llvm.riscv.vadd.mask.nxv4i8.i8(
- <vscale x 4 x i8>,
- <vscale x 4 x i8>,
- i8,
- <vscale x 4 x i1>,
- i64,
- i64);
-
-define <vscale x 4 x i8> @intrinsic_vadd_mask_vx_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv4i8_nxv4i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
-; CHECK-NEXT: vadd.vx v8, v9, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i8> @llvm.riscv.vadd.mask.nxv4i8.i8(
- <vscale x 4 x i8> %0,
- <vscale x 4 x i8> %1,
- i8 %2,
- <vscale x 4 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 4 x i8> %a
-}
-
-declare <vscale x 8 x i8> @llvm.riscv.vadd.nxv8i8.i8(
- <vscale x 8 x i8>,
- <vscale x 8 x i8>,
- i8,
- i64);
-
-define <vscale x 8 x i8> @intrinsic_vadd_vx_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, i8 %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vadd_vx_nxv8i8_nxv8i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
-; CHECK-NEXT: vadd.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i8> @llvm.riscv.vadd.nxv8i8.i8(
- <vscale x 8 x i8> undef,
- <vscale x 8 x i8> %0,
- i8 %1,
- i64 %2)
-
- ret <vscale x 8 x i8> %a
-}
-
-declare <vscale x 8 x i8> @llvm.riscv.vadd.mask.nxv8i8.i8(
- <vscale x 8 x i8>,
- <vscale x 8 x i8>,
- i8,
- <vscale x 8 x i1>,
- i64,
- i64);
-
-define <vscale x 8 x i8> @intrinsic_vadd_mask_vx_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv8i8_nxv8i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
-; CHECK-NEXT: vadd.vx v8, v9, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i8> @llvm.riscv.vadd.mask.nxv8i8.i8(
- <vscale x 8 x i8> %0,
- <vscale x 8 x i8> %1,
- i8 %2,
- <vscale x 8 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 8 x i8> %a
-}
-
-declare <vscale x 16 x i8> @llvm.riscv.vadd.nxv16i8.i8(
- <vscale x 16 x i8>,
- <vscale x 16 x i8>,
- i8,
- i64);
-
-define <vscale x 16 x i8> @intrinsic_vadd_vx_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, i8 %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vadd_vx_nxv16i8_nxv16i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
-; CHECK-NEXT: vadd.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i8> @llvm.riscv.vadd.nxv16i8.i8(
- <vscale x 16 x i8> undef,
- <vscale x 16 x i8> %0,
- i8 %1,
- i64 %2)
-
- ret <vscale x 16 x i8> %a
-}
-
-declare <vscale x 16 x i8> @llvm.riscv.vadd.mask.nxv16i8.i8(
- <vscale x 16 x i8>,
- <vscale x 16 x i8>,
- i8,
- <vscale x 16 x i1>,
- i64,
- i64);
-
-define <vscale x 16 x i8> @intrinsic_vadd_mask_vx_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv16i8_nxv16i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
-; CHECK-NEXT: vadd.vx v8, v10, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i8> @llvm.riscv.vadd.mask.nxv16i8.i8(
- <vscale x 16 x i8> %0,
- <vscale x 16 x i8> %1,
- i8 %2,
- <vscale x 16 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 16 x i8> %a
-}
-
-declare <vscale x 32 x i8> @llvm.riscv.vadd.nxv32i8.i8(
- <vscale x 32 x i8>,
- <vscale x 32 x i8>,
- i8,
- i64);
-
-define <vscale x 32 x i8> @intrinsic_vadd_vx_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, i8 %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vadd_vx_nxv32i8_nxv32i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
-; CHECK-NEXT: vadd.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 32 x i8> @llvm.riscv.vadd.nxv32i8.i8(
- <vscale x 32 x i8> undef,
- <vscale x 32 x i8> %0,
- i8 %1,
- i64 %2)
-
- ret <vscale x 32 x i8> %a
-}
-
-declare <vscale x 32 x i8> @llvm.riscv.vadd.mask.nxv32i8.i8(
- <vscale x 32 x i8>,
- <vscale x 32 x i8>,
- i8,
- <vscale x 32 x i1>,
- i64,
- i64);
-
-define <vscale x 32 x i8> @intrinsic_vadd_mask_vx_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv32i8_nxv32i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
-; CHECK-NEXT: vadd.vx v8, v12, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 32 x i8> @llvm.riscv.vadd.mask.nxv32i8.i8(
- <vscale x 32 x i8> %0,
- <vscale x 32 x i8> %1,
- i8 %2,
- <vscale x 32 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 32 x i8> %a
-}
-
-declare <vscale x 64 x i8> @llvm.riscv.vadd.nxv64i8.i8(
- <vscale x 64 x i8>,
- <vscale x 64 x i8>,
- i8,
- i64);
-
-define <vscale x 64 x i8> @intrinsic_vadd_vx_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, i8 %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vadd_vx_nxv64i8_nxv64i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu
-; CHECK-NEXT: vadd.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 64 x i8> @llvm.riscv.vadd.nxv64i8.i8(
- <vscale x 64 x i8> undef,
- <vscale x 64 x i8> %0,
- i8 %1,
- i64 %2)
-
- ret <vscale x 64 x i8> %a
-}
-
-declare <vscale x 64 x i8> @llvm.riscv.vadd.mask.nxv64i8.i8(
- <vscale x 64 x i8>,
- <vscale x 64 x i8>,
- i8,
- <vscale x 64 x i1>,
- i64,
- i64);
-
-define <vscale x 64 x i8> @intrinsic_vadd_mask_vx_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i8 %2, <vscale x 64 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv64i8_nxv64i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu
-; CHECK-NEXT: vadd.vx v8, v16, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 64 x i8> @llvm.riscv.vadd.mask.nxv64i8.i8(
- <vscale x 64 x i8> %0,
- <vscale x 64 x i8> %1,
- i8 %2,
- <vscale x 64 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 64 x i8> %a
-}
-
-declare <vscale x 1 x i16> @llvm.riscv.vadd.nxv1i16.i16(
- <vscale x 1 x i16>,
- <vscale x 1 x i16>,
- i16,
- i64);
-
-define <vscale x 1 x i16> @intrinsic_vadd_vx_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, i16 %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vadd_vx_nxv1i16_nxv1i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
-; CHECK-NEXT: vadd.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i16> @llvm.riscv.vadd.nxv1i16.i16(
- <vscale x 1 x i16> undef,
- <vscale x 1 x i16> %0,
- i16 %1,
- i64 %2)
-
- ret <vscale x 1 x i16> %a
-}
-
-declare <vscale x 1 x i16> @llvm.riscv.vadd.mask.nxv1i16.i16(
- <vscale x 1 x i16>,
- <vscale x 1 x i16>,
- i16,
- <vscale x 1 x i1>,
- i64,
- i64);
-
-define <vscale x 1 x i16> @intrinsic_vadd_mask_vx_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv1i16_nxv1i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
-; CHECK-NEXT: vadd.vx v8, v9, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i16> @llvm.riscv.vadd.mask.nxv1i16.i16(
- <vscale x 1 x i16> %0,
- <vscale x 1 x i16> %1,
- i16 %2,
- <vscale x 1 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 1 x i16> %a
-}
-
-declare <vscale x 2 x i16> @llvm.riscv.vadd.nxv2i16.i16(
- <vscale x 2 x i16>,
- <vscale x 2 x i16>,
- i16,
- i64);
-
-define <vscale x 2 x i16> @intrinsic_vadd_vx_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, i16 %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vadd_vx_nxv2i16_nxv2i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
-; CHECK-NEXT: vadd.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i16> @llvm.riscv.vadd.nxv2i16.i16(
- <vscale x 2 x i16> undef,
- <vscale x 2 x i16> %0,
- i16 %1,
- i64 %2)
-
- ret <vscale x 2 x i16> %a
-}
-
-declare <vscale x 2 x i16> @llvm.riscv.vadd.mask.nxv2i16.i16(
- <vscale x 2 x i16>,
- <vscale x 2 x i16>,
- i16,
- <vscale x 2 x i1>,
- i64,
- i64);
-
-define <vscale x 2 x i16> @intrinsic_vadd_mask_vx_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv2i16_nxv2i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
-; CHECK-NEXT: vadd.vx v8, v9, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i16> @llvm.riscv.vadd.mask.nxv2i16.i16(
- <vscale x 2 x i16> %0,
- <vscale x 2 x i16> %1,
- i16 %2,
- <vscale x 2 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 2 x i16> %a
-}
-
-declare <vscale x 4 x i16> @llvm.riscv.vadd.nxv4i16.i16(
- <vscale x 4 x i16>,
- <vscale x 4 x i16>,
- i16,
- i64);
-
-define <vscale x 4 x i16> @intrinsic_vadd_vx_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, i16 %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vadd_vx_nxv4i16_nxv4i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
-; CHECK-NEXT: vadd.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i16> @llvm.riscv.vadd.nxv4i16.i16(
- <vscale x 4 x i16> undef,
- <vscale x 4 x i16> %0,
- i16 %1,
- i64 %2)
-
- ret <vscale x 4 x i16> %a
-}
-
-declare <vscale x 4 x i16> @llvm.riscv.vadd.mask.nxv4i16.i16(
- <vscale x 4 x i16>,
- <vscale x 4 x i16>,
- i16,
- <vscale x 4 x i1>,
- i64,
- i64);
-
-define <vscale x 4 x i16> @intrinsic_vadd_mask_vx_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv4i16_nxv4i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
-; CHECK-NEXT: vadd.vx v8, v9, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i16> @llvm.riscv.vadd.mask.nxv4i16.i16(
- <vscale x 4 x i16> %0,
- <vscale x 4 x i16> %1,
- i16 %2,
- <vscale x 4 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 4 x i16> %a
-}
-
-declare <vscale x 8 x i16> @llvm.riscv.vadd.nxv8i16.i16(
- <vscale x 8 x i16>,
- <vscale x 8 x i16>,
- i16,
- i64);
-
-define <vscale x 8 x i16> @intrinsic_vadd_vx_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, i16 %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vadd_vx_nxv8i16_nxv8i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
-; CHECK-NEXT: vadd.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i16> @llvm.riscv.vadd.nxv8i16.i16(
- <vscale x 8 x i16> undef,
- <vscale x 8 x i16> %0,
- i16 %1,
- i64 %2)
-
- ret <vscale x 8 x i16> %a
-}
-
-declare <vscale x 8 x i16> @llvm.riscv.vadd.mask.nxv8i16.i16(
- <vscale x 8 x i16>,
- <vscale x 8 x i16>,
- i16,
- <vscale x 8 x i1>,
- i64,
- i64);
-
-define <vscale x 8 x i16> @intrinsic_vadd_mask_vx_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv8i16_nxv8i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
-; CHECK-NEXT: vadd.vx v8, v10, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i16> @llvm.riscv.vadd.mask.nxv8i16.i16(
- <vscale x 8 x i16> %0,
- <vscale x 8 x i16> %1,
- i16 %2,
- <vscale x 8 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 8 x i16> %a
-}
-
-declare <vscale x 16 x i16> @llvm.riscv.vadd.nxv16i16.i16(
- <vscale x 16 x i16>,
- <vscale x 16 x i16>,
- i16,
- i64);
-
-define <vscale x 16 x i16> @intrinsic_vadd_vx_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, i16 %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vadd_vx_nxv16i16_nxv16i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
-; CHECK-NEXT: vadd.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i16> @llvm.riscv.vadd.nxv16i16.i16(
- <vscale x 16 x i16> undef,
- <vscale x 16 x i16> %0,
- i16 %1,
- i64 %2)
-
- ret <vscale x 16 x i16> %a
-}
-
-declare <vscale x 16 x i16> @llvm.riscv.vadd.mask.nxv16i16.i16(
- <vscale x 16 x i16>,
- <vscale x 16 x i16>,
- i16,
- <vscale x 16 x i1>,
- i64,
- i64);
-
-define <vscale x 16 x i16> @intrinsic_vadd_mask_vx_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv16i16_nxv16i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
-; CHECK-NEXT: vadd.vx v8, v12, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i16> @llvm.riscv.vadd.mask.nxv16i16.i16(
- <vscale x 16 x i16> %0,
- <vscale x 16 x i16> %1,
- i16 %2,
- <vscale x 16 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 16 x i16> %a
-}
-
-declare <vscale x 32 x i16> @llvm.riscv.vadd.nxv32i16.i16(
- <vscale x 32 x i16>,
- <vscale x 32 x i16>,
- i16,
- i64);
-
-define <vscale x 32 x i16> @intrinsic_vadd_vx_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, i16 %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vadd_vx_nxv32i16_nxv32i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu
-; CHECK-NEXT: vadd.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 32 x i16> @llvm.riscv.vadd.nxv32i16.i16(
- <vscale x 32 x i16> undef,
- <vscale x 32 x i16> %0,
- i16 %1,
- i64 %2)
-
- ret <vscale x 32 x i16> %a
-}
-
-declare <vscale x 32 x i16> @llvm.riscv.vadd.mask.nxv32i16.i16(
- <vscale x 32 x i16>,
- <vscale x 32 x i16>,
- i16,
- <vscale x 32 x i1>,
- i64,
- i64);
-
-define <vscale x 32 x i16> @intrinsic_vadd_mask_vx_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, i16 %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv32i16_nxv32i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu
-; CHECK-NEXT: vadd.vx v8, v16, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 32 x i16> @llvm.riscv.vadd.mask.nxv32i16.i16(
- <vscale x 32 x i16> %0,
- <vscale x 32 x i16> %1,
- i16 %2,
- <vscale x 32 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 32 x i16> %a
-}
-
-declare <vscale x 1 x i32> @llvm.riscv.vadd.nxv1i32.i32(
- <vscale x 1 x i32>,
- <vscale x 1 x i32>,
- i32,
- i64);
-
-define <vscale x 1 x i32> @intrinsic_vadd_vx_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, i32 %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vadd_vx_nxv1i32_nxv1i32_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
-; CHECK-NEXT: vadd.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i32> @llvm.riscv.vadd.nxv1i32.i32(
- <vscale x 1 x i32> undef,
- <vscale x 1 x i32> %0,
- i32 %1,
- i64 %2)
-
- ret <vscale x 1 x i32> %a
-}
-
-declare <vscale x 1 x i32> @llvm.riscv.vadd.mask.nxv1i32.i32(
- <vscale x 1 x i32>,
- <vscale x 1 x i32>,
- i32,
- <vscale x 1 x i1>,
- i64,
- i64);
-
-define <vscale x 1 x i32> @intrinsic_vadd_mask_vx_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv1i32_nxv1i32_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
-; CHECK-NEXT: vadd.vx v8, v9, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i32> @llvm.riscv.vadd.mask.nxv1i32.i32(
- <vscale x 1 x i32> %0,
- <vscale x 1 x i32> %1,
- i32 %2,
- <vscale x 1 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 1 x i32> %a
-}
-
-declare <vscale x 2 x i32> @llvm.riscv.vadd.nxv2i32.i32(
- <vscale x 2 x i32>,
- <vscale x 2 x i32>,
- i32,
- i64);
-
-define <vscale x 2 x i32> @intrinsic_vadd_vx_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, i32 %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vadd_vx_nxv2i32_nxv2i32_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
-; CHECK-NEXT: vadd.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i32> @llvm.riscv.vadd.nxv2i32.i32(
- <vscale x 2 x i32> undef,
- <vscale x 2 x i32> %0,
- i32 %1,
- i64 %2)
-
- ret <vscale x 2 x i32> %a
-}
-
-declare <vscale x 2 x i32> @llvm.riscv.vadd.mask.nxv2i32.i32(
- <vscale x 2 x i32>,
- <vscale x 2 x i32>,
- i32,
- <vscale x 2 x i1>,
- i64,
- i64);
-
-define <vscale x 2 x i32> @intrinsic_vadd_mask_vx_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv2i32_nxv2i32_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
-; CHECK-NEXT: vadd.vx v8, v9, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i32> @llvm.riscv.vadd.mask.nxv2i32.i32(
- <vscale x 2 x i32> %0,
- <vscale x 2 x i32> %1,
- i32 %2,
- <vscale x 2 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 2 x i32> %a
-}
-
-declare <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.i32(
- <vscale x 4 x i32>,
- <vscale x 4 x i32>,
- i32,
- i64);
-
-define <vscale x 4 x i32> @intrinsic_vadd_vx_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, i32 %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vadd_vx_nxv4i32_nxv4i32_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; CHECK-NEXT: vadd.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.i32(
- <vscale x 4 x i32> undef,
- <vscale x 4 x i32> %0,
- i32 %1,
- i64 %2)
-
- ret <vscale x 4 x i32> %a
-}
-
-declare <vscale x 4 x i32> @llvm.riscv.vadd.mask.nxv4i32.i32(
- <vscale x 4 x i32>,
- <vscale x 4 x i32>,
- i32,
- <vscale x 4 x i1>,
- i64,
- i64);
-
-define <vscale x 4 x i32> @intrinsic_vadd_mask_vx_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv4i32_nxv4i32_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; CHECK-NEXT: vadd.vx v8, v10, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i32> @llvm.riscv.vadd.mask.nxv4i32.i32(
- <vscale x 4 x i32> %0,
- <vscale x 4 x i32> %1,
- i32 %2,
- <vscale x 4 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 4 x i32> %a
-}
-
-declare <vscale x 8 x i32> @llvm.riscv.vadd.nxv8i32.i32(
- <vscale x 8 x i32>,
- <vscale x 8 x i32>,
- i32,
- i64);
-
-define <vscale x 8 x i32> @intrinsic_vadd_vx_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, i32 %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vadd_vx_nxv8i32_nxv8i32_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
-; CHECK-NEXT: vadd.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i32> @llvm.riscv.vadd.nxv8i32.i32(
- <vscale x 8 x i32> undef,
- <vscale x 8 x i32> %0,
- i32 %1,
- i64 %2)
-
- ret <vscale x 8 x i32> %a
-}
-
-declare <vscale x 8 x i32> @llvm.riscv.vadd.mask.nxv8i32.i32(
- <vscale x 8 x i32>,
- <vscale x 8 x i32>,
- i32,
- <vscale x 8 x i1>,
- i64,
- i64);
-
-define <vscale x 8 x i32> @intrinsic_vadd_mask_vx_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv8i32_nxv8i32_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
-; CHECK-NEXT: vadd.vx v8, v12, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i32> @llvm.riscv.vadd.mask.nxv8i32.i32(
- <vscale x 8 x i32> %0,
- <vscale x 8 x i32> %1,
- i32 %2,
- <vscale x 8 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 8 x i32> %a
-}
-
-declare <vscale x 16 x i32> @llvm.riscv.vadd.nxv16i32.i32(
- <vscale x 16 x i32>,
- <vscale x 16 x i32>,
- i32,
- i64);
-
-define <vscale x 16 x i32> @intrinsic_vadd_vx_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, i32 %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vadd_vx_nxv16i32_nxv16i32_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu
-; CHECK-NEXT: vadd.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i32> @llvm.riscv.vadd.nxv16i32.i32(
- <vscale x 16 x i32> undef,
- <vscale x 16 x i32> %0,
- i32 %1,
- i64 %2)
-
- ret <vscale x 16 x i32> %a
-}
-
-declare <vscale x 16 x i32> @llvm.riscv.vadd.mask.nxv16i32.i32(
- <vscale x 16 x i32>,
- <vscale x 16 x i32>,
- i32,
- <vscale x 16 x i1>,
- i64,
- i64);
-
-define <vscale x 16 x i32> @intrinsic_vadd_mask_vx_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv16i32_nxv16i32_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu
-; CHECK-NEXT: vadd.vx v8, v16, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i32> @llvm.riscv.vadd.mask.nxv16i32.i32(
- <vscale x 16 x i32> %0,
- <vscale x 16 x i32> %1,
- i32 %2,
- <vscale x 16 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 16 x i32> %a
-}
-
-declare <vscale x 1 x i64> @llvm.riscv.vadd.nxv1i64.i64(
- <vscale x 1 x i64>,
- <vscale x 1 x i64>,
- i64,
- i64);
-
-define <vscale x 1 x i64> @intrinsic_vadd_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vadd_vx_nxv1i64_nxv1i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
-; CHECK-NEXT: vadd.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i64> @llvm.riscv.vadd.nxv1i64.i64(
- <vscale x 1 x i64> undef,
- <vscale x 1 x i64> %0,
- i64 %1,
- i64 %2)
-
- ret <vscale x 1 x i64> %a
-}
-
-declare <vscale x 1 x i64> @llvm.riscv.vadd.mask.nxv1i64.i64(
- <vscale x 1 x i64>,
- <vscale x 1 x i64>,
- i64,
- <vscale x 1 x i1>,
- i64,
- i64);
-
-define <vscale x 1 x i64> @intrinsic_vadd_mask_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv1i64_nxv1i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
-; CHECK-NEXT: vadd.vx v8, v9, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i64> @llvm.riscv.vadd.mask.nxv1i64.i64(
- <vscale x 1 x i64> %0,
- <vscale x 1 x i64> %1,
- i64 %2,
- <vscale x 1 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 1 x i64> %a
-}
-
-declare <vscale x 2 x i64> @llvm.riscv.vadd.nxv2i64.i64(
- <vscale x 2 x i64>,
- <vscale x 2 x i64>,
- i64,
- i64);
-
-define <vscale x 2 x i64> @intrinsic_vadd_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vadd_vx_nxv2i64_nxv2i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
-; CHECK-NEXT: vadd.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i64> @llvm.riscv.vadd.nxv2i64.i64(
- <vscale x 2 x i64> undef,
- <vscale x 2 x i64> %0,
- i64 %1,
- i64 %2)
-
- ret <vscale x 2 x i64> %a
-}
-
-declare <vscale x 2 x i64> @llvm.riscv.vadd.mask.nxv2i64.i64(
- <vscale x 2 x i64>,
- <vscale x 2 x i64>,
- i64,
- <vscale x 2 x i1>,
- i64,
- i64);
-
-define <vscale x 2 x i64> @intrinsic_vadd_mask_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv2i64_nxv2i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
-; CHECK-NEXT: vadd.vx v8, v10, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i64> @llvm.riscv.vadd.mask.nxv2i64.i64(
- <vscale x 2 x i64> %0,
- <vscale x 2 x i64> %1,
- i64 %2,
- <vscale x 2 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 2 x i64> %a
-}
-
-declare <vscale x 4 x i64> @llvm.riscv.vadd.nxv4i64.i64(
- <vscale x 4 x i64>,
- <vscale x 4 x i64>,
- i64,
- i64);
-
-define <vscale x 4 x i64> @intrinsic_vadd_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vadd_vx_nxv4i64_nxv4i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
-; CHECK-NEXT: vadd.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i64> @llvm.riscv.vadd.nxv4i64.i64(
- <vscale x 4 x i64> undef,
- <vscale x 4 x i64> %0,
- i64 %1,
- i64 %2)
-
- ret <vscale x 4 x i64> %a
-}
-
-declare <vscale x 4 x i64> @llvm.riscv.vadd.mask.nxv4i64.i64(
- <vscale x 4 x i64>,
- <vscale x 4 x i64>,
- i64,
- <vscale x 4 x i1>,
- i64,
- i64);
-
-define <vscale x 4 x i64> @intrinsic_vadd_mask_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv4i64_nxv4i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
-; CHECK-NEXT: vadd.vx v8, v12, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i64> @llvm.riscv.vadd.mask.nxv4i64.i64(
- <vscale x 4 x i64> %0,
- <vscale x 4 x i64> %1,
- i64 %2,
- <vscale x 4 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 4 x i64> %a
-}
-
-declare <vscale x 8 x i64> @llvm.riscv.vadd.nxv8i64.i64(
- <vscale x 8 x i64>,
- <vscale x 8 x i64>,
- i64,
- i64);
-
-define <vscale x 8 x i64> @intrinsic_vadd_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, i64 %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vadd_vx_nxv8i64_nxv8i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu
-; CHECK-NEXT: vadd.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i64> @llvm.riscv.vadd.nxv8i64.i64(
- <vscale x 8 x i64> undef,
- <vscale x 8 x i64> %0,
- i64 %1,
- i64 %2)
-
- ret <vscale x 8 x i64> %a
-}
-
-declare <vscale x 8 x i64> @llvm.riscv.vadd.mask.nxv8i64.i64(
- <vscale x 8 x i64>,
- <vscale x 8 x i64>,
- i64,
- <vscale x 8 x i1>,
- i64,
- i64);
-
-define <vscale x 8 x i64> @intrinsic_vadd_mask_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv8i64_nxv8i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu
-; CHECK-NEXT: vadd.vx v8, v16, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i64> @llvm.riscv.vadd.mask.nxv8i64.i64(
- <vscale x 8 x i64> %0,
- <vscale x 8 x i64> %1,
- i64 %2,
- <vscale x 8 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 8 x i64> %a
-}
-
-define <vscale x 1 x i8> @intrinsic_vadd_vi_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, i64 %1) nounwind {
-; CHECK-LABEL: intrinsic_vadd_vi_nxv1i8_nxv1i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
-; CHECK-NEXT: vadd.vi v8, v8, 9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.i8(
- <vscale x 1 x i8> undef,
- <vscale x 1 x i8> %0,
- i8 9,
- i64 %1)
-
- ret <vscale x 1 x i8> %a
-}
-
-define <vscale x 1 x i8> @intrinsic_vadd_mask_vi_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv1i8_nxv1i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
-; CHECK-NEXT: vadd.vi v8, v9, 9, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i8> @llvm.riscv.vadd.mask.nxv1i8.i8(
- <vscale x 1 x i8> %0,
- <vscale x 1 x i8> %1,
- i8 9,
- <vscale x 1 x i1> %2,
- i64 %3, i64 1)
-
- ret <vscale x 1 x i8> %a
-}
-
-define <vscale x 2 x i8> @intrinsic_vadd_vi_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, i64 %1) nounwind {
-; CHECK-LABEL: intrinsic_vadd_vi_nxv2i8_nxv2i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
-; CHECK-NEXT: vadd.vi v8, v8, 9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i8> @llvm.riscv.vadd.nxv2i8.i8(
- <vscale x 2 x i8> undef,
- <vscale x 2 x i8> %0,
- i8 9,
- i64 %1)
-
- ret <vscale x 2 x i8> %a
-}
-
-define <vscale x 2 x i8> @intrinsic_vadd_mask_vi_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv2i8_nxv2i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
-; CHECK-NEXT: vadd.vi v8, v9, 9, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i8> @llvm.riscv.vadd.mask.nxv2i8.i8(
- <vscale x 2 x i8> %0,
- <vscale x 2 x i8> %1,
- i8 9,
- <vscale x 2 x i1> %2,
- i64 %3, i64 1)
-
- ret <vscale x 2 x i8> %a
-}
-
-define <vscale x 4 x i8> @intrinsic_vadd_vi_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, i64 %1) nounwind {
-; CHECK-LABEL: intrinsic_vadd_vi_nxv4i8_nxv4i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
-; CHECK-NEXT: vadd.vi v8, v8, 9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i8> @llvm.riscv.vadd.nxv4i8.i8(
- <vscale x 4 x i8> undef,
- <vscale x 4 x i8> %0,
- i8 9,
- i64 %1)
-
- ret <vscale x 4 x i8> %a
-}
-
-define <vscale x 4 x i8> @intrinsic_vadd_mask_vi_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv4i8_nxv4i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
-; CHECK-NEXT: vadd.vi v8, v9, 9, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i8> @llvm.riscv.vadd.mask.nxv4i8.i8(
- <vscale x 4 x i8> %0,
- <vscale x 4 x i8> %1,
- i8 9,
- <vscale x 4 x i1> %2,
- i64 %3, i64 1)
-
- ret <vscale x 4 x i8> %a
-}
-
-define <vscale x 8 x i8> @intrinsic_vadd_vi_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, i64 %1) nounwind {
-; CHECK-LABEL: intrinsic_vadd_vi_nxv8i8_nxv8i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
-; CHECK-NEXT: vadd.vi v8, v8, 9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i8> @llvm.riscv.vadd.nxv8i8.i8(
- <vscale x 8 x i8> undef,
- <vscale x 8 x i8> %0,
- i8 9,
- i64 %1)
-
- ret <vscale x 8 x i8> %a
-}
-
-define <vscale x 8 x i8> @intrinsic_vadd_mask_vi_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv8i8_nxv8i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
-; CHECK-NEXT: vadd.vi v8, v9, 9, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i8> @llvm.riscv.vadd.mask.nxv8i8.i8(
- <vscale x 8 x i8> %0,
- <vscale x 8 x i8> %1,
- i8 9,
- <vscale x 8 x i1> %2,
- i64 %3, i64 1)
-
- ret <vscale x 8 x i8> %a
-}
-
-define <vscale x 16 x i8> @intrinsic_vadd_vi_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, i64 %1) nounwind {
-; CHECK-LABEL: intrinsic_vadd_vi_nxv16i8_nxv16i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
-; CHECK-NEXT: vadd.vi v8, v8, 9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i8> @llvm.riscv.vadd.nxv16i8.i8(
- <vscale x 16 x i8> undef,
- <vscale x 16 x i8> %0,
- i8 9,
- i64 %1)
-
- ret <vscale x 16 x i8> %a
-}
-
-define <vscale x 16 x i8> @intrinsic_vadd_mask_vi_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i1> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv16i8_nxv16i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
-; CHECK-NEXT: vadd.vi v8, v10, 9, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i8> @llvm.riscv.vadd.mask.nxv16i8.i8(
- <vscale x 16 x i8> %0,
- <vscale x 16 x i8> %1,
- i8 9,
- <vscale x 16 x i1> %2,
- i64 %3, i64 1)
-
- ret <vscale x 16 x i8> %a
-}
-
-define <vscale x 32 x i8> @intrinsic_vadd_vi_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, i64 %1) nounwind {
-; CHECK-LABEL: intrinsic_vadd_vi_nxv32i8_nxv32i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
-; CHECK-NEXT: vadd.vi v8, v8, 9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 32 x i8> @llvm.riscv.vadd.nxv32i8.i8(
- <vscale x 32 x i8> undef,
- <vscale x 32 x i8> %0,
- i8 9,
- i64 %1)
-
- ret <vscale x 32 x i8> %a
-}
-
-define <vscale x 32 x i8> @intrinsic_vadd_mask_vi_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i1> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv32i8_nxv32i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
-; CHECK-NEXT: vadd.vi v8, v12, 9, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 32 x i8> @llvm.riscv.vadd.mask.nxv32i8.i8(
- <vscale x 32 x i8> %0,
- <vscale x 32 x i8> %1,
- i8 9,
- <vscale x 32 x i1> %2,
- i64 %3, i64 1)
-
- ret <vscale x 32 x i8> %a
-}
-
-define <vscale x 64 x i8> @intrinsic_vadd_vi_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, i64 %1) nounwind {
-; CHECK-LABEL: intrinsic_vadd_vi_nxv64i8_nxv64i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, mu
-; CHECK-NEXT: vadd.vi v8, v8, 9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 64 x i8> @llvm.riscv.vadd.nxv64i8.i8(
- <vscale x 64 x i8> undef,
- <vscale x 64 x i8> %0,
- i8 9,
- i64 %1)
-
- ret <vscale x 64 x i8> %a
-}
-
-define <vscale x 64 x i8> @intrinsic_vadd_mask_vi_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i1> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv64i8_nxv64i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, mu
-; CHECK-NEXT: vadd.vi v8, v16, 9, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 64 x i8> @llvm.riscv.vadd.mask.nxv64i8.i8(
- <vscale x 64 x i8> %0,
- <vscale x 64 x i8> %1,
- i8 9,
- <vscale x 64 x i1> %2,
- i64 %3, i64 1)
-
- ret <vscale x 64 x i8> %a
-}
-
-define <vscale x 1 x i16> @intrinsic_vadd_vi_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, i64 %1) nounwind {
-; CHECK-LABEL: intrinsic_vadd_vi_nxv1i16_nxv1i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vadd.vi v8, v8, 9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i16> @llvm.riscv.vadd.nxv1i16.i16(
- <vscale x 1 x i16> undef,
- <vscale x 1 x i16> %0,
- i16 9,
- i64 %1)
-
- ret <vscale x 1 x i16> %a
-}
-
-define <vscale x 1 x i16> @intrinsic_vadd_mask_vi_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv1i16_nxv1i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vadd.vi v8, v9, 9, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i16> @llvm.riscv.vadd.mask.nxv1i16.i16(
- <vscale x 1 x i16> %0,
- <vscale x 1 x i16> %1,
- i16 9,
- <vscale x 1 x i1> %2,
- i64 %3, i64 1)
-
- ret <vscale x 1 x i16> %a
-}
-
-define <vscale x 2 x i16> @intrinsic_vadd_vi_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, i64 %1) nounwind {
-; CHECK-LABEL: intrinsic_vadd_vi_nxv2i16_nxv2i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vadd.vi v8, v8, 9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i16> @llvm.riscv.vadd.nxv2i16.i16(
- <vscale x 2 x i16> undef,
- <vscale x 2 x i16> %0,
- i16 9,
- i64 %1)
-
- ret <vscale x 2 x i16> %a
-}
-
-define <vscale x 2 x i16> @intrinsic_vadd_mask_vi_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv2i16_nxv2i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vadd.vi v8, v9, 9, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i16> @llvm.riscv.vadd.mask.nxv2i16.i16(
- <vscale x 2 x i16> %0,
- <vscale x 2 x i16> %1,
- i16 9,
- <vscale x 2 x i1> %2,
- i64 %3, i64 1)
-
- ret <vscale x 2 x i16> %a
-}
-
-define <vscale x 4 x i16> @intrinsic_vadd_vi_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, i64 %1) nounwind {
-; CHECK-LABEL: intrinsic_vadd_vi_nxv4i16_nxv4i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vadd.vi v8, v8, 9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i16> @llvm.riscv.vadd.nxv4i16.i16(
- <vscale x 4 x i16> undef,
- <vscale x 4 x i16> %0,
- i16 9,
- i64 %1)
-
- ret <vscale x 4 x i16> %a
-}
-
-define <vscale x 4 x i16> @intrinsic_vadd_mask_vi_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv4i16_nxv4i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vadd.vi v8, v9, 9, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i16> @llvm.riscv.vadd.mask.nxv4i16.i16(
- <vscale x 4 x i16> %0,
- <vscale x 4 x i16> %1,
- i16 9,
- <vscale x 4 x i1> %2,
- i64 %3, i64 1)
-
- ret <vscale x 4 x i16> %a
-}
-
-define <vscale x 8 x i16> @intrinsic_vadd_vi_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, i64 %1) nounwind {
-; CHECK-LABEL: intrinsic_vadd_vi_nxv8i16_nxv8i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vadd.vi v8, v8, 9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i16> @llvm.riscv.vadd.nxv8i16.i16(
- <vscale x 8 x i16> undef,
- <vscale x 8 x i16> %0,
- i16 9,
- i64 %1)
-
- ret <vscale x 8 x i16> %a
-}
-
-define <vscale x 8 x i16> @intrinsic_vadd_mask_vi_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv8i16_nxv8i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vadd.vi v8, v10, 9, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i16> @llvm.riscv.vadd.mask.nxv8i16.i16(
- <vscale x 8 x i16> %0,
- <vscale x 8 x i16> %1,
- i16 9,
- <vscale x 8 x i1> %2,
- i64 %3, i64 1)
-
- ret <vscale x 8 x i16> %a
-}
-
-define <vscale x 16 x i16> @intrinsic_vadd_vi_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, i64 %1) nounwind {
-; CHECK-LABEL: intrinsic_vadd_vi_nxv16i16_nxv16i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
-; CHECK-NEXT: vadd.vi v8, v8, 9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i16> @llvm.riscv.vadd.nxv16i16.i16(
- <vscale x 16 x i16> undef,
- <vscale x 16 x i16> %0,
- i16 9,
- i64 %1)
-
- ret <vscale x 16 x i16> %a
-}
-
-define <vscale x 16 x i16> @intrinsic_vadd_mask_vi_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i1> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv16i16_nxv16i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
-; CHECK-NEXT: vadd.vi v8, v12, 9, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i16> @llvm.riscv.vadd.mask.nxv16i16.i16(
- <vscale x 16 x i16> %0,
- <vscale x 16 x i16> %1,
- i16 9,
- <vscale x 16 x i1> %2,
- i64 %3, i64 1)
-
- ret <vscale x 16 x i16> %a
-}
-
-define <vscale x 32 x i16> @intrinsic_vadd_vi_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, i64 %1) nounwind {
-; CHECK-LABEL: intrinsic_vadd_vi_nxv32i16_nxv32i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, mu
-; CHECK-NEXT: vadd.vi v8, v8, 9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 32 x i16> @llvm.riscv.vadd.nxv32i16.i16(
- <vscale x 32 x i16> undef,
- <vscale x 32 x i16> %0,
- i16 9,
- i64 %1)
-
- ret <vscale x 32 x i16> %a
-}
-
-define <vscale x 32 x i16> @intrinsic_vadd_mask_vi_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i1> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv32i16_nxv32i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, mu
-; CHECK-NEXT: vadd.vi v8, v16, 9, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 32 x i16> @llvm.riscv.vadd.mask.nxv32i16.i16(
- <vscale x 32 x i16> %0,
- <vscale x 32 x i16> %1,
- i16 9,
- <vscale x 32 x i1> %2,
- i64 %3, i64 1)
-
- ret <vscale x 32 x i16> %a
-}
-
-define <vscale x 1 x i32> @intrinsic_vadd_vi_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, i64 %1) nounwind {
-; CHECK-LABEL: intrinsic_vadd_vi_nxv1i32_nxv1i32_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vadd.vi v8, v8, 9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i32> @llvm.riscv.vadd.nxv1i32.i32(
- <vscale x 1 x i32> undef,
- <vscale x 1 x i32> %0,
- i32 9,
- i64 %1)
-
- ret <vscale x 1 x i32> %a
-}
-
-define <vscale x 1 x i32> @intrinsic_vadd_mask_vi_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv1i32_nxv1i32_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vadd.vi v8, v9, 9, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i32> @llvm.riscv.vadd.mask.nxv1i32.i32(
- <vscale x 1 x i32> %0,
- <vscale x 1 x i32> %1,
- i32 9,
- <vscale x 1 x i1> %2,
- i64 %3, i64 1)
-
- ret <vscale x 1 x i32> %a
-}
-
-define <vscale x 2 x i32> @intrinsic_vadd_vi_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, i64 %1) nounwind {
-; CHECK-LABEL: intrinsic_vadd_vi_nxv2i32_nxv2i32_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vadd.vi v8, v8, 9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i32> @llvm.riscv.vadd.nxv2i32.i32(
- <vscale x 2 x i32> undef,
- <vscale x 2 x i32> %0,
- i32 9,
- i64 %1)
-
- ret <vscale x 2 x i32> %a
-}
-
-define <vscale x 2 x i32> @intrinsic_vadd_mask_vi_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv2i32_nxv2i32_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vadd.vi v8, v9, 9, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i32> @llvm.riscv.vadd.mask.nxv2i32.i32(
- <vscale x 2 x i32> %0,
- <vscale x 2 x i32> %1,
- i32 9,
- <vscale x 2 x i1> %2,
- i64 %3, i64 1)
-
- ret <vscale x 2 x i32> %a
-}
-
-define <vscale x 4 x i32> @intrinsic_vadd_vi_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, i64 %1) nounwind {
-; CHECK-LABEL: intrinsic_vadd_vi_nxv4i32_nxv4i32_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vadd.vi v8, v8, 9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.i32(
- <vscale x 4 x i32> undef,
- <vscale x 4 x i32> %0,
- i32 9,
- i64 %1)
-
- ret <vscale x 4 x i32> %a
-}
-
-define <vscale x 4 x i32> @intrinsic_vadd_mask_vi_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv4i32_nxv4i32_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vadd.vi v8, v10, 9, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i32> @llvm.riscv.vadd.mask.nxv4i32.i32(
- <vscale x 4 x i32> %0,
- <vscale x 4 x i32> %1,
- i32 9,
- <vscale x 4 x i1> %2,
- i64 %3, i64 1)
-
- ret <vscale x 4 x i32> %a
-}
-
-define <vscale x 8 x i32> @intrinsic_vadd_vi_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, i64 %1) nounwind {
-; CHECK-LABEL: intrinsic_vadd_vi_nxv8i32_nxv8i32_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
-; CHECK-NEXT: vadd.vi v8, v8, 9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i32> @llvm.riscv.vadd.nxv8i32.i32(
- <vscale x 8 x i32> undef,
- <vscale x 8 x i32> %0,
- i32 9,
- i64 %1)
-
- ret <vscale x 8 x i32> %a
-}
-
-define <vscale x 8 x i32> @intrinsic_vadd_mask_vi_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv8i32_nxv8i32_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
-; CHECK-NEXT: vadd.vi v8, v12, 9, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i32> @llvm.riscv.vadd.mask.nxv8i32.i32(
- <vscale x 8 x i32> %0,
- <vscale x 8 x i32> %1,
- i32 9,
- <vscale x 8 x i1> %2,
- i64 %3, i64 1)
-
- ret <vscale x 8 x i32> %a
-}
-
-define <vscale x 16 x i32> @intrinsic_vadd_vi_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, i64 %1) nounwind {
-; CHECK-LABEL: intrinsic_vadd_vi_nxv16i32_nxv16i32_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu
-; CHECK-NEXT: vadd.vi v8, v8, 9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i32> @llvm.riscv.vadd.nxv16i32.i32(
- <vscale x 16 x i32> undef,
- <vscale x 16 x i32> %0,
- i32 9,
- i64 %1)
-
- ret <vscale x 16 x i32> %a
-}
-
-define <vscale x 16 x i32> @intrinsic_vadd_mask_vi_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i1> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv16i32_nxv16i32_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu
-; CHECK-NEXT: vadd.vi v8, v16, 9, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i32> @llvm.riscv.vadd.mask.nxv16i32.i32(
- <vscale x 16 x i32> %0,
- <vscale x 16 x i32> %1,
- i32 9,
- <vscale x 16 x i1> %2,
- i64 %3, i64 1)
-
- ret <vscale x 16 x i32> %a
-}
-
-define <vscale x 1 x i64> @intrinsic_vadd_vi_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1) nounwind {
-; CHECK-LABEL: intrinsic_vadd_vi_nxv1i64_nxv1i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
-; CHECK-NEXT: vadd.vi v8, v8, 9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i64> @llvm.riscv.vadd.nxv1i64.i64(
- <vscale x 1 x i64> undef,
- <vscale x 1 x i64> %0,
- i64 9,
- i64 %1)
-
- ret <vscale x 1 x i64> %a
-}
-
-define <vscale x 1 x i64> @intrinsic_vadd_mask_vi_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv1i64_nxv1i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
-; CHECK-NEXT: vadd.vi v8, v9, 9, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i64> @llvm.riscv.vadd.mask.nxv1i64.i64(
- <vscale x 1 x i64> %0,
- <vscale x 1 x i64> %1,
- i64 9,
- <vscale x 1 x i1> %2,
- i64 %3, i64 1)
-
- ret <vscale x 1 x i64> %a
-}
-
-define <vscale x 2 x i64> @intrinsic_vadd_vi_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1) nounwind {
-; CHECK-LABEL: intrinsic_vadd_vi_nxv2i64_nxv2i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
-; CHECK-NEXT: vadd.vi v8, v8, 9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i64> @llvm.riscv.vadd.nxv2i64.i64(
- <vscale x 2 x i64> undef,
- <vscale x 2 x i64> %0,
- i64 9,
- i64 %1)
-
- ret <vscale x 2 x i64> %a
-}
-
-define <vscale x 2 x i64> @intrinsic_vadd_mask_vi_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv2i64_nxv2i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
-; CHECK-NEXT: vadd.vi v8, v10, 9, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i64> @llvm.riscv.vadd.mask.nxv2i64.i64(
- <vscale x 2 x i64> %0,
- <vscale x 2 x i64> %1,
- i64 9,
- <vscale x 2 x i1> %2,
- i64 %3, i64 1)
-
- ret <vscale x 2 x i64> %a
-}
-
-define <vscale x 4 x i64> @intrinsic_vadd_vi_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1) nounwind {
-; CHECK-LABEL: intrinsic_vadd_vi_nxv4i64_nxv4i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
-; CHECK-NEXT: vadd.vi v8, v8, 9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i64> @llvm.riscv.vadd.nxv4i64.i64(
- <vscale x 4 x i64> undef,
- <vscale x 4 x i64> %0,
- i64 9,
- i64 %1)
-
- ret <vscale x 4 x i64> %a
-}
-
-define <vscale x 4 x i64> @intrinsic_vadd_mask_vi_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv4i64_nxv4i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
-; CHECK-NEXT: vadd.vi v8, v12, 9, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i64> @llvm.riscv.vadd.mask.nxv4i64.i64(
- <vscale x 4 x i64> %0,
- <vscale x 4 x i64> %1,
- i64 9,
- <vscale x 4 x i1> %2,
- i64 %3, i64 1)
-
- ret <vscale x 4 x i64> %a
-}
-
-define <vscale x 8 x i64> @intrinsic_vadd_vi_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, i64 %1) nounwind {
-; CHECK-LABEL: intrinsic_vadd_vi_nxv8i64_nxv8i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu
-; CHECK-NEXT: vadd.vi v8, v8, 9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i64> @llvm.riscv.vadd.nxv8i64.i64(
- <vscale x 8 x i64> undef,
- <vscale x 8 x i64> %0,
- i64 9,
- i64 %1)
-
- ret <vscale x 8 x i64> %a
-}
-
-define <vscale x 8 x i64> @intrinsic_vadd_mask_vi_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv8i64_nxv8i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu
-; CHECK-NEXT: vadd.vi v8, v16, 9, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i64> @llvm.riscv.vadd.mask.nxv8i64.i64(
- <vscale x 8 x i64> %0,
- <vscale x 8 x i64> %1,
- i64 9,
- <vscale x 8 x i1> %2,
- i64 %3, i64 1)
-
- ret <vscale x 8 x i64> %a
-}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vadd-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vadd.ll
similarity index 83%
rename from llvm/test/CodeGen/RISCV/rvv/vadd-rv32.ll
rename to llvm/test/CodeGen/RISCV/rvv/vadd.ll
index 5f39548b45cc2..ac5dde5cb985d 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vadd-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vadd.ll
@@ -1,13 +1,15 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs \
-; RUN: < %s | FileCheck %s
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v \
+; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,RV32
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v \
+; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,RV64
declare <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.nxv1i8(
<vscale x 1 x i8>,
<vscale x 1 x i8>,
<vscale x 1 x i8>,
- i32);
+ iXLen);
-define <vscale x 1 x i8> @intrinsic_vadd_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i32 %2) nounwind {
+define <vscale x 1 x i8> @intrinsic_vadd_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vadd_vv_nxv1i8_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
@@ -18,7 +20,7 @@ entry:
<vscale x 1 x i8> undef,
<vscale x 1 x i8> %0,
<vscale x 1 x i8> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 1 x i8> %a
}
@@ -28,9 +30,9 @@ declare <vscale x 1 x i8> @llvm.riscv.vadd.mask.nxv1i8.nxv1i8(
<vscale x 1 x i8>,
<vscale x 1 x i8>,
<vscale x 1 x i1>,
- i32, i32);
+ iXLen, iXLen);
-define <vscale x 1 x i8> @intrinsic_vadd_mask_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+define <vscale x 1 x i8> @intrinsic_vadd_mask_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv1i8_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
@@ -42,7 +44,7 @@ entry:
<vscale x 1 x i8> %1,
<vscale x 1 x i8> %2,
<vscale x 1 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 1 x i8> %a
}
@@ -51,9 +53,9 @@ declare <vscale x 2 x i8> @llvm.riscv.vadd.nxv2i8.nxv2i8(
<vscale x 2 x i8>,
<vscale x 2 x i8>,
<vscale x 2 x i8>,
- i32);
+ iXLen);
-define <vscale x 2 x i8> @intrinsic_vadd_vv_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i32 %2) nounwind {
+define <vscale x 2 x i8> @intrinsic_vadd_vv_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vadd_vv_nxv2i8_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
@@ -64,7 +66,7 @@ entry:
<vscale x 2 x i8> undef,
<vscale x 2 x i8> %0,
<vscale x 2 x i8> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 2 x i8> %a
}
@@ -74,9 +76,9 @@ declare <vscale x 2 x i8> @llvm.riscv.vadd.mask.nxv2i8.nxv2i8(
<vscale x 2 x i8>,
<vscale x 2 x i8>,
<vscale x 2 x i1>,
- i32, i32);
+ iXLen, iXLen);
-define <vscale x 2 x i8> @intrinsic_vadd_mask_vv_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+define <vscale x 2 x i8> @intrinsic_vadd_mask_vv_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv2i8_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
@@ -88,7 +90,7 @@ entry:
<vscale x 2 x i8> %1,
<vscale x 2 x i8> %2,
<vscale x 2 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 2 x i8> %a
}
@@ -97,9 +99,9 @@ declare <vscale x 4 x i8> @llvm.riscv.vadd.nxv4i8.nxv4i8(
<vscale x 4 x i8>,
<vscale x 4 x i8>,
<vscale x 4 x i8>,
- i32);
+ iXLen);
-define <vscale x 4 x i8> @intrinsic_vadd_vv_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i32 %2) nounwind {
+define <vscale x 4 x i8> @intrinsic_vadd_vv_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vadd_vv_nxv4i8_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
@@ -110,7 +112,7 @@ entry:
<vscale x 4 x i8> undef,
<vscale x 4 x i8> %0,
<vscale x 4 x i8> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 4 x i8> %a
}
@@ -120,9 +122,9 @@ declare <vscale x 4 x i8> @llvm.riscv.vadd.mask.nxv4i8.nxv4i8(
<vscale x 4 x i8>,
<vscale x 4 x i8>,
<vscale x 4 x i1>,
- i32, i32);
+ iXLen, iXLen);
-define <vscale x 4 x i8> @intrinsic_vadd_mask_vv_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+define <vscale x 4 x i8> @intrinsic_vadd_mask_vv_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv4i8_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
@@ -134,7 +136,7 @@ entry:
<vscale x 4 x i8> %1,
<vscale x 4 x i8> %2,
<vscale x 4 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 4 x i8> %a
}
@@ -143,9 +145,9 @@ declare <vscale x 8 x i8> @llvm.riscv.vadd.nxv8i8.nxv8i8(
<vscale x 8 x i8>,
<vscale x 8 x i8>,
<vscale x 8 x i8>,
- i32);
+ iXLen);
-define <vscale x 8 x i8> @intrinsic_vadd_vv_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i32 %2) nounwind {
+define <vscale x 8 x i8> @intrinsic_vadd_vv_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vadd_vv_nxv8i8_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
@@ -156,7 +158,7 @@ entry:
<vscale x 8 x i8> undef,
<vscale x 8 x i8> %0,
<vscale x 8 x i8> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 8 x i8> %a
}
@@ -166,9 +168,9 @@ declare <vscale x 8 x i8> @llvm.riscv.vadd.mask.nxv8i8.nxv8i8(
<vscale x 8 x i8>,
<vscale x 8 x i8>,
<vscale x 8 x i1>,
- i32, i32);
+ iXLen, iXLen);
-define <vscale x 8 x i8> @intrinsic_vadd_mask_vv_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+define <vscale x 8 x i8> @intrinsic_vadd_mask_vv_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv8i8_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
@@ -180,7 +182,7 @@ entry:
<vscale x 8 x i8> %1,
<vscale x 8 x i8> %2,
<vscale x 8 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 8 x i8> %a
}
@@ -189,9 +191,9 @@ declare <vscale x 16 x i8> @llvm.riscv.vadd.nxv16i8.nxv16i8(
<vscale x 16 x i8>,
<vscale x 16 x i8>,
<vscale x 16 x i8>,
- i32);
+ iXLen);
-define <vscale x 16 x i8> @intrinsic_vadd_vv_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i32 %2) nounwind {
+define <vscale x 16 x i8> @intrinsic_vadd_vv_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vadd_vv_nxv16i8_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
@@ -202,7 +204,7 @@ entry:
<vscale x 16 x i8> undef,
<vscale x 16 x i8> %0,
<vscale x 16 x i8> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 16 x i8> %a
}
@@ -212,9 +214,9 @@ declare <vscale x 16 x i8> @llvm.riscv.vadd.mask.nxv16i8.nxv16i8(
<vscale x 16 x i8>,
<vscale x 16 x i8>,
<vscale x 16 x i1>,
- i32, i32);
+ iXLen, iXLen);
-define <vscale x 16 x i8> @intrinsic_vadd_mask_vv_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+define <vscale x 16 x i8> @intrinsic_vadd_mask_vv_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv16i8_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
@@ -226,7 +228,7 @@ entry:
<vscale x 16 x i8> %1,
<vscale x 16 x i8> %2,
<vscale x 16 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 16 x i8> %a
}
@@ -235,9 +237,9 @@ declare <vscale x 32 x i8> @llvm.riscv.vadd.nxv32i8.nxv32i8(
<vscale x 32 x i8>,
<vscale x 32 x i8>,
<vscale x 32 x i8>,
- i32);
+ iXLen);
-define <vscale x 32 x i8> @intrinsic_vadd_vv_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i32 %2) nounwind {
+define <vscale x 32 x i8> @intrinsic_vadd_vv_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vadd_vv_nxv32i8_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
@@ -248,7 +250,7 @@ entry:
<vscale x 32 x i8> undef,
<vscale x 32 x i8> %0,
<vscale x 32 x i8> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 32 x i8> %a
}
@@ -258,9 +260,9 @@ declare <vscale x 32 x i8> @llvm.riscv.vadd.mask.nxv32i8.nxv32i8(
<vscale x 32 x i8>,
<vscale x 32 x i8>,
<vscale x 32 x i1>,
- i32, i32);
+ iXLen, iXLen);
-define <vscale x 32 x i8> @intrinsic_vadd_mask_vv_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
+define <vscale x 32 x i8> @intrinsic_vadd_mask_vv_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv32i8_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
@@ -272,7 +274,7 @@ entry:
<vscale x 32 x i8> %1,
<vscale x 32 x i8> %2,
<vscale x 32 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 32 x i8> %a
}
@@ -281,9 +283,9 @@ declare <vscale x 64 x i8> @llvm.riscv.vadd.nxv64i8.nxv64i8(
<vscale x 64 x i8>,
<vscale x 64 x i8>,
<vscale x 64 x i8>,
- i32);
+ iXLen);
-define <vscale x 64 x i8> @intrinsic_vadd_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i32 %2) nounwind {
+define <vscale x 64 x i8> @intrinsic_vadd_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vadd_vv_nxv64i8_nxv64i8_nxv64i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, mu
@@ -294,7 +296,7 @@ entry:
<vscale x 64 x i8> undef,
<vscale x 64 x i8> %0,
<vscale x 64 x i8> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 64 x i8> %a
}
@@ -304,9 +306,9 @@ declare <vscale x 64 x i8> @llvm.riscv.vadd.mask.nxv64i8.nxv64i8(
<vscale x 64 x i8>,
<vscale x 64 x i8>,
<vscale x 64 x i1>,
- i32, i32);
+ iXLen, iXLen);
-define <vscale x 64 x i8> @intrinsic_vadd_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, i32 %4) nounwind {
+define <vscale x 64 x i8> @intrinsic_vadd_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv64i8_nxv64i8_nxv64i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vl8r.v v24, (a0)
@@ -319,7 +321,7 @@ entry:
<vscale x 64 x i8> %1,
<vscale x 64 x i8> %2,
<vscale x 64 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 64 x i8> %a
}
@@ -328,9 +330,9 @@ declare <vscale x 1 x i16> @llvm.riscv.vadd.nxv1i16.nxv1i16(
<vscale x 1 x i16>,
<vscale x 1 x i16>,
<vscale x 1 x i16>,
- i32);
+ iXLen);
-define <vscale x 1 x i16> @intrinsic_vadd_vv_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i32 %2) nounwind {
+define <vscale x 1 x i16> @intrinsic_vadd_vv_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vadd_vv_nxv1i16_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
@@ -341,7 +343,7 @@ entry:
<vscale x 1 x i16> undef,
<vscale x 1 x i16> %0,
<vscale x 1 x i16> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 1 x i16> %a
}
@@ -351,9 +353,9 @@ declare <vscale x 1 x i16> @llvm.riscv.vadd.mask.nxv1i16.nxv1i16(
<vscale x 1 x i16>,
<vscale x 1 x i16>,
<vscale x 1 x i1>,
- i32, i32);
+ iXLen, iXLen);
-define <vscale x 1 x i16> @intrinsic_vadd_mask_vv_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+define <vscale x 1 x i16> @intrinsic_vadd_mask_vv_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv1i16_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
@@ -365,7 +367,7 @@ entry:
<vscale x 1 x i16> %1,
<vscale x 1 x i16> %2,
<vscale x 1 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 1 x i16> %a
}
@@ -374,9 +376,9 @@ declare <vscale x 2 x i16> @llvm.riscv.vadd.nxv2i16.nxv2i16(
<vscale x 2 x i16>,
<vscale x 2 x i16>,
<vscale x 2 x i16>,
- i32);
+ iXLen);
-define <vscale x 2 x i16> @intrinsic_vadd_vv_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i32 %2) nounwind {
+define <vscale x 2 x i16> @intrinsic_vadd_vv_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vadd_vv_nxv2i16_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
@@ -387,7 +389,7 @@ entry:
<vscale x 2 x i16> undef,
<vscale x 2 x i16> %0,
<vscale x 2 x i16> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 2 x i16> %a
}
@@ -397,9 +399,9 @@ declare <vscale x 2 x i16> @llvm.riscv.vadd.mask.nxv2i16.nxv2i16(
<vscale x 2 x i16>,
<vscale x 2 x i16>,
<vscale x 2 x i1>,
- i32, i32);
+ iXLen, iXLen);
-define <vscale x 2 x i16> @intrinsic_vadd_mask_vv_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+define <vscale x 2 x i16> @intrinsic_vadd_mask_vv_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv2i16_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
@@ -411,7 +413,7 @@ entry:
<vscale x 2 x i16> %1,
<vscale x 2 x i16> %2,
<vscale x 2 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 2 x i16> %a
}
@@ -420,9 +422,9 @@ declare <vscale x 4 x i16> @llvm.riscv.vadd.nxv4i16.nxv4i16(
<vscale x 4 x i16>,
<vscale x 4 x i16>,
<vscale x 4 x i16>,
- i32);
+ iXLen);
-define <vscale x 4 x i16> @intrinsic_vadd_vv_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i32 %2) nounwind {
+define <vscale x 4 x i16> @intrinsic_vadd_vv_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vadd_vv_nxv4i16_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
@@ -433,7 +435,7 @@ entry:
<vscale x 4 x i16> undef,
<vscale x 4 x i16> %0,
<vscale x 4 x i16> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 4 x i16> %a
}
@@ -443,9 +445,9 @@ declare <vscale x 4 x i16> @llvm.riscv.vadd.mask.nxv4i16.nxv4i16(
<vscale x 4 x i16>,
<vscale x 4 x i16>,
<vscale x 4 x i1>,
- i32, i32);
+ iXLen, iXLen);
-define <vscale x 4 x i16> @intrinsic_vadd_mask_vv_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+define <vscale x 4 x i16> @intrinsic_vadd_mask_vv_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv4i16_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
@@ -457,7 +459,7 @@ entry:
<vscale x 4 x i16> %1,
<vscale x 4 x i16> %2,
<vscale x 4 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 4 x i16> %a
}
@@ -466,9 +468,9 @@ declare <vscale x 8 x i16> @llvm.riscv.vadd.nxv8i16.nxv8i16(
<vscale x 8 x i16>,
<vscale x 8 x i16>,
<vscale x 8 x i16>,
- i32);
+ iXLen);
-define <vscale x 8 x i16> @intrinsic_vadd_vv_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i32 %2) nounwind {
+define <vscale x 8 x i16> @intrinsic_vadd_vv_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vadd_vv_nxv8i16_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
@@ -479,7 +481,7 @@ entry:
<vscale x 8 x i16> undef,
<vscale x 8 x i16> %0,
<vscale x 8 x i16> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 8 x i16> %a
}
@@ -489,9 +491,9 @@ declare <vscale x 8 x i16> @llvm.riscv.vadd.mask.nxv8i16.nxv8i16(
<vscale x 8 x i16>,
<vscale x 8 x i16>,
<vscale x 8 x i1>,
- i32, i32);
+ iXLen, iXLen);
-define <vscale x 8 x i16> @intrinsic_vadd_mask_vv_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+define <vscale x 8 x i16> @intrinsic_vadd_mask_vv_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv8i16_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
@@ -503,7 +505,7 @@ entry:
<vscale x 8 x i16> %1,
<vscale x 8 x i16> %2,
<vscale x 8 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 8 x i16> %a
}
@@ -512,9 +514,9 @@ declare <vscale x 16 x i16> @llvm.riscv.vadd.nxv16i16.nxv16i16(
<vscale x 16 x i16>,
<vscale x 16 x i16>,
<vscale x 16 x i16>,
- i32);
+ iXLen);
-define <vscale x 16 x i16> @intrinsic_vadd_vv_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i32 %2) nounwind {
+define <vscale x 16 x i16> @intrinsic_vadd_vv_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vadd_vv_nxv16i16_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
@@ -525,7 +527,7 @@ entry:
<vscale x 16 x i16> undef,
<vscale x 16 x i16> %0,
<vscale x 16 x i16> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 16 x i16> %a
}
@@ -535,9 +537,9 @@ declare <vscale x 16 x i16> @llvm.riscv.vadd.mask.nxv16i16.nxv16i16(
<vscale x 16 x i16>,
<vscale x 16 x i16>,
<vscale x 16 x i1>,
- i32, i32);
+ iXLen, iXLen);
-define <vscale x 16 x i16> @intrinsic_vadd_mask_vv_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+define <vscale x 16 x i16> @intrinsic_vadd_mask_vv_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv16i16_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
@@ -549,7 +551,7 @@ entry:
<vscale x 16 x i16> %1,
<vscale x 16 x i16> %2,
<vscale x 16 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 16 x i16> %a
}
@@ -558,9 +560,9 @@ declare <vscale x 32 x i16> @llvm.riscv.vadd.nxv32i16.nxv32i16(
<vscale x 32 x i16>,
<vscale x 32 x i16>,
<vscale x 32 x i16>,
- i32);
+ iXLen);
-define <vscale x 32 x i16> @intrinsic_vadd_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, i32 %2) nounwind {
+define <vscale x 32 x i16> @intrinsic_vadd_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vadd_vv_nxv32i16_nxv32i16_nxv32i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, mu
@@ -571,7 +573,7 @@ entry:
<vscale x 32 x i16> undef,
<vscale x 32 x i16> %0,
<vscale x 32 x i16> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 32 x i16> %a
}
@@ -581,9 +583,9 @@ declare <vscale x 32 x i16> @llvm.riscv.vadd.mask.nxv32i16.nxv32i16(
<vscale x 32 x i16>,
<vscale x 32 x i16>,
<vscale x 32 x i1>,
- i32, i32);
+ iXLen, iXLen);
-define <vscale x 32 x i16> @intrinsic_vadd_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
+define <vscale x 32 x i16> @intrinsic_vadd_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv32i16_nxv32i16_nxv32i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vl8re16.v v24, (a0)
@@ -596,7 +598,7 @@ entry:
<vscale x 32 x i16> %1,
<vscale x 32 x i16> %2,
<vscale x 32 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 32 x i16> %a
}
@@ -605,9 +607,9 @@ declare <vscale x 1 x i32> @llvm.riscv.vadd.nxv1i32.nxv1i32(
<vscale x 1 x i32>,
<vscale x 1 x i32>,
<vscale x 1 x i32>,
- i32);
+ iXLen);
-define <vscale x 1 x i32> @intrinsic_vadd_vv_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2) nounwind {
+define <vscale x 1 x i32> @intrinsic_vadd_vv_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vadd_vv_nxv1i32_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
@@ -618,7 +620,7 @@ entry:
<vscale x 1 x i32> undef,
<vscale x 1 x i32> %0,
<vscale x 1 x i32> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 1 x i32> %a
}
@@ -628,9 +630,9 @@ declare <vscale x 1 x i32> @llvm.riscv.vadd.mask.nxv1i32.nxv1i32(
<vscale x 1 x i32>,
<vscale x 1 x i32>,
<vscale x 1 x i1>,
- i32, i32);
+ iXLen, iXLen);
-define <vscale x 1 x i32> @intrinsic_vadd_mask_vv_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+define <vscale x 1 x i32> @intrinsic_vadd_mask_vv_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv1i32_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
@@ -642,7 +644,7 @@ entry:
<vscale x 1 x i32> %1,
<vscale x 1 x i32> %2,
<vscale x 1 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 1 x i32> %a
}
@@ -651,9 +653,9 @@ declare <vscale x 2 x i32> @llvm.riscv.vadd.nxv2i32.nxv2i32(
<vscale x 2 x i32>,
<vscale x 2 x i32>,
<vscale x 2 x i32>,
- i32);
+ iXLen);
-define <vscale x 2 x i32> @intrinsic_vadd_vv_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2) nounwind {
+define <vscale x 2 x i32> @intrinsic_vadd_vv_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vadd_vv_nxv2i32_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
@@ -664,7 +666,7 @@ entry:
<vscale x 2 x i32> undef,
<vscale x 2 x i32> %0,
<vscale x 2 x i32> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 2 x i32> %a
}
@@ -674,9 +676,9 @@ declare <vscale x 2 x i32> @llvm.riscv.vadd.mask.nxv2i32.nxv2i32(
<vscale x 2 x i32>,
<vscale x 2 x i32>,
<vscale x 2 x i1>,
- i32, i32);
+ iXLen, iXLen);
-define <vscale x 2 x i32> @intrinsic_vadd_mask_vv_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+define <vscale x 2 x i32> @intrinsic_vadd_mask_vv_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv2i32_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
@@ -688,7 +690,7 @@ entry:
<vscale x 2 x i32> %1,
<vscale x 2 x i32> %2,
<vscale x 2 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 2 x i32> %a
}
@@ -697,9 +699,9 @@ declare <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(
<vscale x 4 x i32>,
<vscale x 4 x i32>,
<vscale x 4 x i32>,
- i32);
+ iXLen);
-define <vscale x 4 x i32> @intrinsic_vadd_vv_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2) nounwind {
+define <vscale x 4 x i32> @intrinsic_vadd_vv_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vadd_vv_nxv4i32_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
@@ -710,7 +712,7 @@ entry:
<vscale x 4 x i32> undef,
<vscale x 4 x i32> %0,
<vscale x 4 x i32> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 4 x i32> %a
}
@@ -720,9 +722,9 @@ declare <vscale x 4 x i32> @llvm.riscv.vadd.mask.nxv4i32.nxv4i32(
<vscale x 4 x i32>,
<vscale x 4 x i32>,
<vscale x 4 x i1>,
- i32, i32);
+ iXLen, iXLen);
-define <vscale x 4 x i32> @intrinsic_vadd_mask_vv_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+define <vscale x 4 x i32> @intrinsic_vadd_mask_vv_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv4i32_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
@@ -734,7 +736,7 @@ entry:
<vscale x 4 x i32> %1,
<vscale x 4 x i32> %2,
<vscale x 4 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 4 x i32> %a
}
@@ -743,9 +745,9 @@ declare <vscale x 8 x i32> @llvm.riscv.vadd.nxv8i32.nxv8i32(
<vscale x 8 x i32>,
<vscale x 8 x i32>,
<vscale x 8 x i32>,
- i32);
+ iXLen);
-define <vscale x 8 x i32> @intrinsic_vadd_vv_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2) nounwind {
+define <vscale x 8 x i32> @intrinsic_vadd_vv_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vadd_vv_nxv8i32_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
@@ -756,7 +758,7 @@ entry:
<vscale x 8 x i32> undef,
<vscale x 8 x i32> %0,
<vscale x 8 x i32> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 8 x i32> %a
}
@@ -766,9 +768,9 @@ declare <vscale x 8 x i32> @llvm.riscv.vadd.mask.nxv8i32.nxv8i32(
<vscale x 8 x i32>,
<vscale x 8 x i32>,
<vscale x 8 x i1>,
- i32, i32);
+ iXLen, iXLen);
-define <vscale x 8 x i32> @intrinsic_vadd_mask_vv_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+define <vscale x 8 x i32> @intrinsic_vadd_mask_vv_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv8i32_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
@@ -780,7 +782,7 @@ entry:
<vscale x 8 x i32> %1,
<vscale x 8 x i32> %2,
<vscale x 8 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 8 x i32> %a
}
@@ -789,9 +791,9 @@ declare <vscale x 16 x i32> @llvm.riscv.vadd.nxv16i32.nxv16i32(
<vscale x 16 x i32>,
<vscale x 16 x i32>,
<vscale x 16 x i32>,
- i32);
+ iXLen);
-define <vscale x 16 x i32> @intrinsic_vadd_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2) nounwind {
+define <vscale x 16 x i32> @intrinsic_vadd_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vadd_vv_nxv16i32_nxv16i32_nxv16i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu
@@ -802,7 +804,7 @@ entry:
<vscale x 16 x i32> undef,
<vscale x 16 x i32> %0,
<vscale x 16 x i32> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 16 x i32> %a
}
@@ -812,9 +814,9 @@ declare <vscale x 16 x i32> @llvm.riscv.vadd.mask.nxv16i32.nxv16i32(
<vscale x 16 x i32>,
<vscale x 16 x i32>,
<vscale x 16 x i1>,
- i32, i32);
+ iXLen, iXLen);
-define <vscale x 16 x i32> @intrinsic_vadd_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+define <vscale x 16 x i32> @intrinsic_vadd_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv16i32_nxv16i32_nxv16i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vl8re32.v v24, (a0)
@@ -827,7 +829,7 @@ entry:
<vscale x 16 x i32> %1,
<vscale x 16 x i32> %2,
<vscale x 16 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 16 x i32> %a
}
@@ -836,9 +838,9 @@ declare <vscale x 1 x i64> @llvm.riscv.vadd.nxv1i64.nxv1i64(
<vscale x 1 x i64>,
<vscale x 1 x i64>,
<vscale x 1 x i64>,
- i32);
+ iXLen);
-define <vscale x 1 x i64> @intrinsic_vadd_vv_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i32 %2) nounwind {
+define <vscale x 1 x i64> @intrinsic_vadd_vv_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vadd_vv_nxv1i64_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
@@ -849,7 +851,7 @@ entry:
<vscale x 1 x i64> undef,
<vscale x 1 x i64> %0,
<vscale x 1 x i64> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 1 x i64> %a
}
@@ -859,9 +861,9 @@ declare <vscale x 1 x i64> @llvm.riscv.vadd.mask.nxv1i64.nxv1i64(
<vscale x 1 x i64>,
<vscale x 1 x i64>,
<vscale x 1 x i1>,
- i32, i32);
+ iXLen, iXLen);
-define <vscale x 1 x i64> @intrinsic_vadd_mask_vv_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+define <vscale x 1 x i64> @intrinsic_vadd_mask_vv_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv1i64_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
@@ -873,7 +875,7 @@ entry:
<vscale x 1 x i64> %1,
<vscale x 1 x i64> %2,
<vscale x 1 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 1 x i64> %a
}
@@ -882,9 +884,9 @@ declare <vscale x 2 x i64> @llvm.riscv.vadd.nxv2i64.nxv2i64(
<vscale x 2 x i64>,
<vscale x 2 x i64>,
<vscale x 2 x i64>,
- i32);
+ iXLen);
-define <vscale x 2 x i64> @intrinsic_vadd_vv_nxv2i64_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i32 %2) nounwind {
+define <vscale x 2 x i64> @intrinsic_vadd_vv_nxv2i64_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vadd_vv_nxv2i64_nxv2i64_nxv2i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
@@ -895,7 +897,7 @@ entry:
<vscale x 2 x i64> undef,
<vscale x 2 x i64> %0,
<vscale x 2 x i64> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 2 x i64> %a
}
@@ -905,9 +907,9 @@ declare <vscale x 2 x i64> @llvm.riscv.vadd.mask.nxv2i64.nxv2i64(
<vscale x 2 x i64>,
<vscale x 2 x i64>,
<vscale x 2 x i1>,
- i32, i32);
+ iXLen, iXLen);
-define <vscale x 2 x i64> @intrinsic_vadd_mask_vv_nxv2i64_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+define <vscale x 2 x i64> @intrinsic_vadd_mask_vv_nxv2i64_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv2i64_nxv2i64_nxv2i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
@@ -919,7 +921,7 @@ entry:
<vscale x 2 x i64> %1,
<vscale x 2 x i64> %2,
<vscale x 2 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 2 x i64> %a
}
@@ -928,9 +930,9 @@ declare <vscale x 4 x i64> @llvm.riscv.vadd.nxv4i64.nxv4i64(
<vscale x 4 x i64>,
<vscale x 4 x i64>,
<vscale x 4 x i64>,
- i32);
+ iXLen);
-define <vscale x 4 x i64> @intrinsic_vadd_vv_nxv4i64_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i32 %2) nounwind {
+define <vscale x 4 x i64> @intrinsic_vadd_vv_nxv4i64_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vadd_vv_nxv4i64_nxv4i64_nxv4i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
@@ -941,7 +943,7 @@ entry:
<vscale x 4 x i64> undef,
<vscale x 4 x i64> %0,
<vscale x 4 x i64> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 4 x i64> %a
}
@@ -951,9 +953,9 @@ declare <vscale x 4 x i64> @llvm.riscv.vadd.mask.nxv4i64.nxv4i64(
<vscale x 4 x i64>,
<vscale x 4 x i64>,
<vscale x 4 x i1>,
- i32, i32);
+ iXLen, iXLen);
-define <vscale x 4 x i64> @intrinsic_vadd_mask_vv_nxv4i64_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+define <vscale x 4 x i64> @intrinsic_vadd_mask_vv_nxv4i64_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv4i64_nxv4i64_nxv4i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
@@ -965,7 +967,7 @@ entry:
<vscale x 4 x i64> %1,
<vscale x 4 x i64> %2,
<vscale x 4 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 4 x i64> %a
}
@@ -974,9 +976,9 @@ declare <vscale x 8 x i64> @llvm.riscv.vadd.nxv8i64.nxv8i64(
<vscale x 8 x i64>,
<vscale x 8 x i64>,
<vscale x 8 x i64>,
- i32);
+ iXLen);
-define <vscale x 8 x i64> @intrinsic_vadd_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i32 %2) nounwind {
+define <vscale x 8 x i64> @intrinsic_vadd_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vadd_vv_nxv8i64_nxv8i64_nxv8i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu
@@ -987,7 +989,7 @@ entry:
<vscale x 8 x i64> undef,
<vscale x 8 x i64> %0,
<vscale x 8 x i64> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 8 x i64> %a
}
@@ -997,9 +999,9 @@ declare <vscale x 8 x i64> @llvm.riscv.vadd.mask.nxv8i64.nxv8i64(
<vscale x 8 x i64>,
<vscale x 8 x i64>,
<vscale x 8 x i1>,
- i32, i32);
+ iXLen, iXLen);
-define <vscale x 8 x i64> @intrinsic_vadd_mask_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+define <vscale x 8 x i64> @intrinsic_vadd_mask_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv8i64_nxv8i64_nxv8i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vl8re64.v v24, (a0)
@@ -1012,7 +1014,7 @@ entry:
<vscale x 8 x i64> %1,
<vscale x 8 x i64> %2,
<vscale x 8 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 8 x i64> %a
}
@@ -1021,9 +1023,9 @@ declare <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.i8(
<vscale x 1 x i8>,
<vscale x 1 x i8>,
i8,
- i32);
+ iXLen);
-define <vscale x 1 x i8> @intrinsic_vadd_vx_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, i8 %1, i32 %2) nounwind {
+define <vscale x 1 x i8> @intrinsic_vadd_vx_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, i8 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vadd_vx_nxv1i8_nxv1i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
@@ -1034,7 +1036,7 @@ entry:
<vscale x 1 x i8> undef,
<vscale x 1 x i8> %0,
i8 %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 1 x i8> %a
}
@@ -1044,9 +1046,9 @@ declare <vscale x 1 x i8> @llvm.riscv.vadd.mask.nxv1i8.i8(
<vscale x 1 x i8>,
i8,
<vscale x 1 x i1>,
- i32, i32);
+ iXLen, iXLen);
-define <vscale x 1 x i8> @intrinsic_vadd_mask_vx_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+define <vscale x 1 x i8> @intrinsic_vadd_mask_vx_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv1i8_nxv1i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
@@ -1058,7 +1060,7 @@ entry:
<vscale x 1 x i8> %1,
i8 %2,
<vscale x 1 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 1 x i8> %a
}
@@ -1067,9 +1069,9 @@ declare <vscale x 2 x i8> @llvm.riscv.vadd.nxv2i8.i8(
<vscale x 2 x i8>,
<vscale x 2 x i8>,
i8,
- i32);
+ iXLen);
-define <vscale x 2 x i8> @intrinsic_vadd_vx_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, i8 %1, i32 %2) nounwind {
+define <vscale x 2 x i8> @intrinsic_vadd_vx_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, i8 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vadd_vx_nxv2i8_nxv2i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
@@ -1080,7 +1082,7 @@ entry:
<vscale x 2 x i8> undef,
<vscale x 2 x i8> %0,
i8 %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 2 x i8> %a
}
@@ -1090,9 +1092,9 @@ declare <vscale x 2 x i8> @llvm.riscv.vadd.mask.nxv2i8.i8(
<vscale x 2 x i8>,
i8,
<vscale x 2 x i1>,
- i32, i32);
+ iXLen, iXLen);
-define <vscale x 2 x i8> @intrinsic_vadd_mask_vx_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+define <vscale x 2 x i8> @intrinsic_vadd_mask_vx_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv2i8_nxv2i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
@@ -1104,7 +1106,7 @@ entry:
<vscale x 2 x i8> %1,
i8 %2,
<vscale x 2 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 2 x i8> %a
}
@@ -1113,9 +1115,9 @@ declare <vscale x 4 x i8> @llvm.riscv.vadd.nxv4i8.i8(
<vscale x 4 x i8>,
<vscale x 4 x i8>,
i8,
- i32);
+ iXLen);
-define <vscale x 4 x i8> @intrinsic_vadd_vx_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, i8 %1, i32 %2) nounwind {
+define <vscale x 4 x i8> @intrinsic_vadd_vx_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, i8 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vadd_vx_nxv4i8_nxv4i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
@@ -1126,7 +1128,7 @@ entry:
<vscale x 4 x i8> undef,
<vscale x 4 x i8> %0,
i8 %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 4 x i8> %a
}
@@ -1136,9 +1138,9 @@ declare <vscale x 4 x i8> @llvm.riscv.vadd.mask.nxv4i8.i8(
<vscale x 4 x i8>,
i8,
<vscale x 4 x i1>,
- i32, i32);
+ iXLen, iXLen);
-define <vscale x 4 x i8> @intrinsic_vadd_mask_vx_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+define <vscale x 4 x i8> @intrinsic_vadd_mask_vx_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv4i8_nxv4i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
@@ -1150,7 +1152,7 @@ entry:
<vscale x 4 x i8> %1,
i8 %2,
<vscale x 4 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 4 x i8> %a
}
@@ -1159,9 +1161,9 @@ declare <vscale x 8 x i8> @llvm.riscv.vadd.nxv8i8.i8(
<vscale x 8 x i8>,
<vscale x 8 x i8>,
i8,
- i32);
+ iXLen);
-define <vscale x 8 x i8> @intrinsic_vadd_vx_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, i8 %1, i32 %2) nounwind {
+define <vscale x 8 x i8> @intrinsic_vadd_vx_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, i8 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vadd_vx_nxv8i8_nxv8i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
@@ -1172,7 +1174,7 @@ entry:
<vscale x 8 x i8> undef,
<vscale x 8 x i8> %0,
i8 %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 8 x i8> %a
}
@@ -1182,9 +1184,9 @@ declare <vscale x 8 x i8> @llvm.riscv.vadd.mask.nxv8i8.i8(
<vscale x 8 x i8>,
i8,
<vscale x 8 x i1>,
- i32, i32);
+ iXLen, iXLen);
-define <vscale x 8 x i8> @intrinsic_vadd_mask_vx_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+define <vscale x 8 x i8> @intrinsic_vadd_mask_vx_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv8i8_nxv8i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
@@ -1196,7 +1198,7 @@ entry:
<vscale x 8 x i8> %1,
i8 %2,
<vscale x 8 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 8 x i8> %a
}
@@ -1205,9 +1207,9 @@ declare <vscale x 16 x i8> @llvm.riscv.vadd.nxv16i8.i8(
<vscale x 16 x i8>,
<vscale x 16 x i8>,
i8,
- i32);
+ iXLen);
-define <vscale x 16 x i8> @intrinsic_vadd_vx_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, i8 %1, i32 %2) nounwind {
+define <vscale x 16 x i8> @intrinsic_vadd_vx_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, i8 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vadd_vx_nxv16i8_nxv16i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
@@ -1218,7 +1220,7 @@ entry:
<vscale x 16 x i8> undef,
<vscale x 16 x i8> %0,
i8 %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 16 x i8> %a
}
@@ -1228,9 +1230,9 @@ declare <vscale x 16 x i8> @llvm.riscv.vadd.mask.nxv16i8.i8(
<vscale x 16 x i8>,
i8,
<vscale x 16 x i1>,
- i32, i32);
+ iXLen, iXLen);
-define <vscale x 16 x i8> @intrinsic_vadd_mask_vx_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+define <vscale x 16 x i8> @intrinsic_vadd_mask_vx_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv16i8_nxv16i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
@@ -1242,7 +1244,7 @@ entry:
<vscale x 16 x i8> %1,
i8 %2,
<vscale x 16 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 16 x i8> %a
}
@@ -1251,9 +1253,9 @@ declare <vscale x 32 x i8> @llvm.riscv.vadd.nxv32i8.i8(
<vscale x 32 x i8>,
<vscale x 32 x i8>,
i8,
- i32);
+ iXLen);
-define <vscale x 32 x i8> @intrinsic_vadd_vx_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, i8 %1, i32 %2) nounwind {
+define <vscale x 32 x i8> @intrinsic_vadd_vx_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, i8 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vadd_vx_nxv32i8_nxv32i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
@@ -1264,7 +1266,7 @@ entry:
<vscale x 32 x i8> undef,
<vscale x 32 x i8> %0,
i8 %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 32 x i8> %a
}
@@ -1274,9 +1276,9 @@ declare <vscale x 32 x i8> @llvm.riscv.vadd.mask.nxv32i8.i8(
<vscale x 32 x i8>,
i8,
<vscale x 32 x i1>,
- i32, i32);
+ iXLen, iXLen);
-define <vscale x 32 x i8> @intrinsic_vadd_mask_vx_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
+define <vscale x 32 x i8> @intrinsic_vadd_mask_vx_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv32i8_nxv32i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
@@ -1288,7 +1290,7 @@ entry:
<vscale x 32 x i8> %1,
i8 %2,
<vscale x 32 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 32 x i8> %a
}
@@ -1297,9 +1299,9 @@ declare <vscale x 64 x i8> @llvm.riscv.vadd.nxv64i8.i8(
<vscale x 64 x i8>,
<vscale x 64 x i8>,
i8,
- i32);
+ iXLen);
-define <vscale x 64 x i8> @intrinsic_vadd_vx_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, i8 %1, i32 %2) nounwind {
+define <vscale x 64 x i8> @intrinsic_vadd_vx_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, i8 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vadd_vx_nxv64i8_nxv64i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu
@@ -1310,7 +1312,7 @@ entry:
<vscale x 64 x i8> undef,
<vscale x 64 x i8> %0,
i8 %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 64 x i8> %a
}
@@ -1320,9 +1322,9 @@ declare <vscale x 64 x i8> @llvm.riscv.vadd.mask.nxv64i8.i8(
<vscale x 64 x i8>,
i8,
<vscale x 64 x i1>,
- i32, i32);
+ iXLen, iXLen);
-define <vscale x 64 x i8> @intrinsic_vadd_mask_vx_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i8 %2, <vscale x 64 x i1> %3, i32 %4) nounwind {
+define <vscale x 64 x i8> @intrinsic_vadd_mask_vx_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i8 %2, <vscale x 64 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv64i8_nxv64i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu
@@ -1334,7 +1336,7 @@ entry:
<vscale x 64 x i8> %1,
i8 %2,
<vscale x 64 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 64 x i8> %a
}
@@ -1343,9 +1345,9 @@ declare <vscale x 1 x i16> @llvm.riscv.vadd.nxv1i16.i16(
<vscale x 1 x i16>,
<vscale x 1 x i16>,
i16,
- i32);
+ iXLen);
-define <vscale x 1 x i16> @intrinsic_vadd_vx_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, i16 %1, i32 %2) nounwind {
+define <vscale x 1 x i16> @intrinsic_vadd_vx_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, i16 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vadd_vx_nxv1i16_nxv1i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
@@ -1356,7 +1358,7 @@ entry:
<vscale x 1 x i16> undef,
<vscale x 1 x i16> %0,
i16 %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 1 x i16> %a
}
@@ -1366,9 +1368,9 @@ declare <vscale x 1 x i16> @llvm.riscv.vadd.mask.nxv1i16.i16(
<vscale x 1 x i16>,
i16,
<vscale x 1 x i1>,
- i32, i32);
+ iXLen, iXLen);
-define <vscale x 1 x i16> @intrinsic_vadd_mask_vx_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+define <vscale x 1 x i16> @intrinsic_vadd_mask_vx_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv1i16_nxv1i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
@@ -1380,7 +1382,7 @@ entry:
<vscale x 1 x i16> %1,
i16 %2,
<vscale x 1 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 1 x i16> %a
}
@@ -1389,9 +1391,9 @@ declare <vscale x 2 x i16> @llvm.riscv.vadd.nxv2i16.i16(
<vscale x 2 x i16>,
<vscale x 2 x i16>,
i16,
- i32);
+ iXLen);
-define <vscale x 2 x i16> @intrinsic_vadd_vx_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, i16 %1, i32 %2) nounwind {
+define <vscale x 2 x i16> @intrinsic_vadd_vx_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, i16 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vadd_vx_nxv2i16_nxv2i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
@@ -1402,7 +1404,7 @@ entry:
<vscale x 2 x i16> undef,
<vscale x 2 x i16> %0,
i16 %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 2 x i16> %a
}
@@ -1412,9 +1414,9 @@ declare <vscale x 2 x i16> @llvm.riscv.vadd.mask.nxv2i16.i16(
<vscale x 2 x i16>,
i16,
<vscale x 2 x i1>,
- i32, i32);
+ iXLen, iXLen);
-define <vscale x 2 x i16> @intrinsic_vadd_mask_vx_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+define <vscale x 2 x i16> @intrinsic_vadd_mask_vx_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv2i16_nxv2i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
@@ -1426,7 +1428,7 @@ entry:
<vscale x 2 x i16> %1,
i16 %2,
<vscale x 2 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 2 x i16> %a
}
@@ -1435,9 +1437,9 @@ declare <vscale x 4 x i16> @llvm.riscv.vadd.nxv4i16.i16(
<vscale x 4 x i16>,
<vscale x 4 x i16>,
i16,
- i32);
+ iXLen);
-define <vscale x 4 x i16> @intrinsic_vadd_vx_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, i16 %1, i32 %2) nounwind {
+define <vscale x 4 x i16> @intrinsic_vadd_vx_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, i16 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vadd_vx_nxv4i16_nxv4i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
@@ -1448,7 +1450,7 @@ entry:
<vscale x 4 x i16> undef,
<vscale x 4 x i16> %0,
i16 %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 4 x i16> %a
}
@@ -1458,9 +1460,9 @@ declare <vscale x 4 x i16> @llvm.riscv.vadd.mask.nxv4i16.i16(
<vscale x 4 x i16>,
i16,
<vscale x 4 x i1>,
- i32, i32);
+ iXLen, iXLen);
-define <vscale x 4 x i16> @intrinsic_vadd_mask_vx_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+define <vscale x 4 x i16> @intrinsic_vadd_mask_vx_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv4i16_nxv4i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
@@ -1472,7 +1474,7 @@ entry:
<vscale x 4 x i16> %1,
i16 %2,
<vscale x 4 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 4 x i16> %a
}
@@ -1481,9 +1483,9 @@ declare <vscale x 8 x i16> @llvm.riscv.vadd.nxv8i16.i16(
<vscale x 8 x i16>,
<vscale x 8 x i16>,
i16,
- i32);
+ iXLen);
-define <vscale x 8 x i16> @intrinsic_vadd_vx_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, i16 %1, i32 %2) nounwind {
+define <vscale x 8 x i16> @intrinsic_vadd_vx_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, i16 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vadd_vx_nxv8i16_nxv8i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
@@ -1494,7 +1496,7 @@ entry:
<vscale x 8 x i16> undef,
<vscale x 8 x i16> %0,
i16 %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 8 x i16> %a
}
@@ -1504,9 +1506,9 @@ declare <vscale x 8 x i16> @llvm.riscv.vadd.mask.nxv8i16.i16(
<vscale x 8 x i16>,
i16,
<vscale x 8 x i1>,
- i32, i32);
+ iXLen, iXLen);
-define <vscale x 8 x i16> @intrinsic_vadd_mask_vx_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+define <vscale x 8 x i16> @intrinsic_vadd_mask_vx_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv8i16_nxv8i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
@@ -1518,7 +1520,7 @@ entry:
<vscale x 8 x i16> %1,
i16 %2,
<vscale x 8 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 8 x i16> %a
}
@@ -1527,9 +1529,9 @@ declare <vscale x 16 x i16> @llvm.riscv.vadd.nxv16i16.i16(
<vscale x 16 x i16>,
<vscale x 16 x i16>,
i16,
- i32);
+ iXLen);
-define <vscale x 16 x i16> @intrinsic_vadd_vx_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, i16 %1, i32 %2) nounwind {
+define <vscale x 16 x i16> @intrinsic_vadd_vx_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, i16 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vadd_vx_nxv16i16_nxv16i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
@@ -1540,7 +1542,7 @@ entry:
<vscale x 16 x i16> undef,
<vscale x 16 x i16> %0,
i16 %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 16 x i16> %a
}
@@ -1550,9 +1552,9 @@ declare <vscale x 16 x i16> @llvm.riscv.vadd.mask.nxv16i16.i16(
<vscale x 16 x i16>,
i16,
<vscale x 16 x i1>,
- i32, i32);
+ iXLen, iXLen);
-define <vscale x 16 x i16> @intrinsic_vadd_mask_vx_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+define <vscale x 16 x i16> @intrinsic_vadd_mask_vx_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv16i16_nxv16i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
@@ -1564,7 +1566,7 @@ entry:
<vscale x 16 x i16> %1,
i16 %2,
<vscale x 16 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 16 x i16> %a
}
@@ -1573,9 +1575,9 @@ declare <vscale x 32 x i16> @llvm.riscv.vadd.nxv32i16.i16(
<vscale x 32 x i16>,
<vscale x 32 x i16>,
i16,
- i32);
+ iXLen);
-define <vscale x 32 x i16> @intrinsic_vadd_vx_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, i16 %1, i32 %2) nounwind {
+define <vscale x 32 x i16> @intrinsic_vadd_vx_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, i16 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vadd_vx_nxv32i16_nxv32i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu
@@ -1586,7 +1588,7 @@ entry:
<vscale x 32 x i16> undef,
<vscale x 32 x i16> %0,
i16 %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 32 x i16> %a
}
@@ -1596,9 +1598,9 @@ declare <vscale x 32 x i16> @llvm.riscv.vadd.mask.nxv32i16.i16(
<vscale x 32 x i16>,
i16,
<vscale x 32 x i1>,
- i32, i32);
+ iXLen, iXLen);
-define <vscale x 32 x i16> @intrinsic_vadd_mask_vx_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, i16 %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
+define <vscale x 32 x i16> @intrinsic_vadd_mask_vx_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, i16 %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv32i16_nxv32i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu
@@ -1610,7 +1612,7 @@ entry:
<vscale x 32 x i16> %1,
i16 %2,
<vscale x 32 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 32 x i16> %a
}
@@ -1619,9 +1621,9 @@ declare <vscale x 1 x i32> @llvm.riscv.vadd.nxv1i32.i32(
<vscale x 1 x i32>,
<vscale x 1 x i32>,
i32,
- i32);
+ iXLen);
-define <vscale x 1 x i32> @intrinsic_vadd_vx_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, i32 %1, i32 %2) nounwind {
+define <vscale x 1 x i32> @intrinsic_vadd_vx_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, i32 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vadd_vx_nxv1i32_nxv1i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
@@ -1632,7 +1634,7 @@ entry:
<vscale x 1 x i32> undef,
<vscale x 1 x i32> %0,
i32 %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 1 x i32> %a
}
@@ -1642,9 +1644,9 @@ declare <vscale x 1 x i32> @llvm.riscv.vadd.mask.nxv1i32.i32(
<vscale x 1 x i32>,
i32,
<vscale x 1 x i1>,
- i32, i32);
+ iXLen, iXLen);
-define <vscale x 1 x i32> @intrinsic_vadd_mask_vx_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+define <vscale x 1 x i32> @intrinsic_vadd_mask_vx_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv1i32_nxv1i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
@@ -1656,7 +1658,7 @@ entry:
<vscale x 1 x i32> %1,
i32 %2,
<vscale x 1 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 1 x i32> %a
}
@@ -1665,9 +1667,9 @@ declare <vscale x 2 x i32> @llvm.riscv.vadd.nxv2i32.i32(
<vscale x 2 x i32>,
<vscale x 2 x i32>,
i32,
- i32);
+ iXLen);
-define <vscale x 2 x i32> @intrinsic_vadd_vx_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, i32 %1, i32 %2) nounwind {
+define <vscale x 2 x i32> @intrinsic_vadd_vx_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, i32 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vadd_vx_nxv2i32_nxv2i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
@@ -1678,7 +1680,7 @@ entry:
<vscale x 2 x i32> undef,
<vscale x 2 x i32> %0,
i32 %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 2 x i32> %a
}
@@ -1688,9 +1690,9 @@ declare <vscale x 2 x i32> @llvm.riscv.vadd.mask.nxv2i32.i32(
<vscale x 2 x i32>,
i32,
<vscale x 2 x i1>,
- i32, i32);
+ iXLen, iXLen);
-define <vscale x 2 x i32> @intrinsic_vadd_mask_vx_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+define <vscale x 2 x i32> @intrinsic_vadd_mask_vx_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv2i32_nxv2i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
@@ -1702,7 +1704,7 @@ entry:
<vscale x 2 x i32> %1,
i32 %2,
<vscale x 2 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 2 x i32> %a
}
@@ -1711,9 +1713,9 @@ declare <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.i32(
<vscale x 4 x i32>,
<vscale x 4 x i32>,
i32,
- i32);
+ iXLen);
-define <vscale x 4 x i32> @intrinsic_vadd_vx_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, i32 %1, i32 %2) nounwind {
+define <vscale x 4 x i32> @intrinsic_vadd_vx_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, i32 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vadd_vx_nxv4i32_nxv4i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
@@ -1724,7 +1726,7 @@ entry:
<vscale x 4 x i32> undef,
<vscale x 4 x i32> %0,
i32 %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 4 x i32> %a
}
@@ -1734,9 +1736,9 @@ declare <vscale x 4 x i32> @llvm.riscv.vadd.mask.nxv4i32.i32(
<vscale x 4 x i32>,
i32,
<vscale x 4 x i1>,
- i32, i32);
+ iXLen, iXLen);
-define <vscale x 4 x i32> @intrinsic_vadd_mask_vx_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+define <vscale x 4 x i32> @intrinsic_vadd_mask_vx_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv4i32_nxv4i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
@@ -1748,7 +1750,7 @@ entry:
<vscale x 4 x i32> %1,
i32 %2,
<vscale x 4 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 4 x i32> %a
}
@@ -1757,9 +1759,9 @@ declare <vscale x 8 x i32> @llvm.riscv.vadd.nxv8i32.i32(
<vscale x 8 x i32>,
<vscale x 8 x i32>,
i32,
- i32);
+ iXLen);
-define <vscale x 8 x i32> @intrinsic_vadd_vx_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, i32 %1, i32 %2) nounwind {
+define <vscale x 8 x i32> @intrinsic_vadd_vx_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, i32 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vadd_vx_nxv8i32_nxv8i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
@@ -1770,7 +1772,7 @@ entry:
<vscale x 8 x i32> undef,
<vscale x 8 x i32> %0,
i32 %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 8 x i32> %a
}
@@ -1780,9 +1782,9 @@ declare <vscale x 8 x i32> @llvm.riscv.vadd.mask.nxv8i32.i32(
<vscale x 8 x i32>,
i32,
<vscale x 8 x i1>,
- i32, i32);
+ iXLen, iXLen);
-define <vscale x 8 x i32> @intrinsic_vadd_mask_vx_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+define <vscale x 8 x i32> @intrinsic_vadd_mask_vx_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv8i32_nxv8i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
@@ -1794,7 +1796,7 @@ entry:
<vscale x 8 x i32> %1,
i32 %2,
<vscale x 8 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 8 x i32> %a
}
@@ -1803,9 +1805,9 @@ declare <vscale x 16 x i32> @llvm.riscv.vadd.nxv16i32.i32(
<vscale x 16 x i32>,
<vscale x 16 x i32>,
i32,
- i32);
+ iXLen);
-define <vscale x 16 x i32> @intrinsic_vadd_vx_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, i32 %1, i32 %2) nounwind {
+define <vscale x 16 x i32> @intrinsic_vadd_vx_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, i32 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vadd_vx_nxv16i32_nxv16i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu
@@ -1816,7 +1818,7 @@ entry:
<vscale x 16 x i32> undef,
<vscale x 16 x i32> %0,
i32 %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 16 x i32> %a
}
@@ -1826,9 +1828,9 @@ declare <vscale x 16 x i32> @llvm.riscv.vadd.mask.nxv16i32.i32(
<vscale x 16 x i32>,
i32,
<vscale x 16 x i1>,
- i32, i32);
+ iXLen, iXLen);
-define <vscale x 16 x i32> @intrinsic_vadd_mask_vx_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+define <vscale x 16 x i32> @intrinsic_vadd_mask_vx_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv16i32_nxv16i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu
@@ -1840,7 +1842,7 @@ entry:
<vscale x 16 x i32> %1,
i32 %2,
<vscale x 16 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 16 x i32> %a
}
@@ -1849,26 +1851,32 @@ declare <vscale x 1 x i64> @llvm.riscv.vadd.nxv1i64.i64(
<vscale x 1 x i64>,
<vscale x 1 x i64>,
i64,
- i32);
-
-define <vscale x 1 x i64> @intrinsic_vadd_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vadd_vx_nxv1i64_nxv1i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addi sp, sp, -16
-; CHECK-NEXT: sw a1, 12(sp)
-; CHECK-NEXT: sw a0, 8(sp)
-; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
-; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v9, (a0), zero
-; CHECK-NEXT: vadd.vv v8, v8, v9
-; CHECK-NEXT: addi sp, sp, 16
-; CHECK-NEXT: ret
+ iXLen);
+
+define <vscale x 1 x i64> @intrinsic_vadd_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, iXLen %2) nounwind {
+; RV32-LABEL: intrinsic_vadd_vx_nxv1i64_nxv1i64_i64:
+; RV32: # %bb.0: # %entry
+; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: sw a1, 12(sp)
+; RV32-NEXT: sw a0, 8(sp)
+; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
+; RV32-NEXT: addi a0, sp, 8
+; RV32-NEXT: vlse64.v v9, (a0), zero
+; RV32-NEXT: vadd.vv v8, v8, v9
+; RV32-NEXT: addi sp, sp, 16
+; RV32-NEXT: ret
+;
+; RV64-LABEL: intrinsic_vadd_vx_nxv1i64_nxv1i64_i64:
+; RV64: # %bb.0: # %entry
+; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, mu
+; RV64-NEXT: vadd.vx v8, v8, a0
+; RV64-NEXT: ret
entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vadd.nxv1i64.i64(
<vscale x 1 x i64> undef,
<vscale x 1 x i64> %0,
i64 %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 1 x i64> %a
}
@@ -1878,27 +1886,33 @@ declare <vscale x 1 x i64> @llvm.riscv.vadd.mask.nxv1i64.i64(
<vscale x 1 x i64>,
i64,
<vscale x 1 x i1>,
- i32, i32);
-
-define <vscale x 1 x i64> @intrinsic_vadd_mask_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv1i64_nxv1i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addi sp, sp, -16
-; CHECK-NEXT: sw a1, 12(sp)
-; CHECK-NEXT: sw a0, 8(sp)
-; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
-; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v10, (a0), zero
-; CHECK-NEXT: vadd.vv v8, v9, v10, v0.t
-; CHECK-NEXT: addi sp, sp, 16
-; CHECK-NEXT: ret
+ iXLen, iXLen);
+
+define <vscale x 1 x i64> @intrinsic_vadd_mask_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
+; RV32-LABEL: intrinsic_vadd_mask_vx_nxv1i64_nxv1i64_i64:
+; RV32: # %bb.0: # %entry
+; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: sw a1, 12(sp)
+; RV32-NEXT: sw a0, 8(sp)
+; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
+; RV32-NEXT: addi a0, sp, 8
+; RV32-NEXT: vlse64.v v10, (a0), zero
+; RV32-NEXT: vadd.vv v8, v9, v10, v0.t
+; RV32-NEXT: addi sp, sp, 16
+; RV32-NEXT: ret
+;
+; RV64-LABEL: intrinsic_vadd_mask_vx_nxv1i64_nxv1i64_i64:
+; RV64: # %bb.0: # %entry
+; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, mu
+; RV64-NEXT: vadd.vx v8, v9, a0, v0.t
+; RV64-NEXT: ret
entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vadd.mask.nxv1i64.i64(
<vscale x 1 x i64> %0,
<vscale x 1 x i64> %1,
i64 %2,
<vscale x 1 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 1 x i64> %a
}
@@ -1907,26 +1921,32 @@ declare <vscale x 2 x i64> @llvm.riscv.vadd.nxv2i64.i64(
<vscale x 2 x i64>,
<vscale x 2 x i64>,
i64,
- i32);
-
-define <vscale x 2 x i64> @intrinsic_vadd_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vadd_vx_nxv2i64_nxv2i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addi sp, sp, -16
-; CHECK-NEXT: sw a1, 12(sp)
-; CHECK-NEXT: sw a0, 8(sp)
-; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
-; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v10, (a0), zero
-; CHECK-NEXT: vadd.vv v8, v8, v10
-; CHECK-NEXT: addi sp, sp, 16
-; CHECK-NEXT: ret
+ iXLen);
+
+define <vscale x 2 x i64> @intrinsic_vadd_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, iXLen %2) nounwind {
+; RV32-LABEL: intrinsic_vadd_vx_nxv2i64_nxv2i64_i64:
+; RV32: # %bb.0: # %entry
+; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: sw a1, 12(sp)
+; RV32-NEXT: sw a0, 8(sp)
+; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
+; RV32-NEXT: addi a0, sp, 8
+; RV32-NEXT: vlse64.v v10, (a0), zero
+; RV32-NEXT: vadd.vv v8, v8, v10
+; RV32-NEXT: addi sp, sp, 16
+; RV32-NEXT: ret
+;
+; RV64-LABEL: intrinsic_vadd_vx_nxv2i64_nxv2i64_i64:
+; RV64: # %bb.0: # %entry
+; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, mu
+; RV64-NEXT: vadd.vx v8, v8, a0
+; RV64-NEXT: ret
entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vadd.nxv2i64.i64(
<vscale x 2 x i64> undef,
<vscale x 2 x i64> %0,
i64 %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 2 x i64> %a
}
@@ -1936,27 +1956,33 @@ declare <vscale x 2 x i64> @llvm.riscv.vadd.mask.nxv2i64.i64(
<vscale x 2 x i64>,
i64,
<vscale x 2 x i1>,
- i32, i32);
-
-define <vscale x 2 x i64> @intrinsic_vadd_mask_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv2i64_nxv2i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addi sp, sp, -16
-; CHECK-NEXT: sw a1, 12(sp)
-; CHECK-NEXT: sw a0, 8(sp)
-; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
-; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v12, (a0), zero
-; CHECK-NEXT: vadd.vv v8, v10, v12, v0.t
-; CHECK-NEXT: addi sp, sp, 16
-; CHECK-NEXT: ret
+ iXLen, iXLen);
+
+define <vscale x 2 x i64> @intrinsic_vadd_mask_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
+; RV32-LABEL: intrinsic_vadd_mask_vx_nxv2i64_nxv2i64_i64:
+; RV32: # %bb.0: # %entry
+; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: sw a1, 12(sp)
+; RV32-NEXT: sw a0, 8(sp)
+; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
+; RV32-NEXT: addi a0, sp, 8
+; RV32-NEXT: vlse64.v v12, (a0), zero
+; RV32-NEXT: vadd.vv v8, v10, v12, v0.t
+; RV32-NEXT: addi sp, sp, 16
+; RV32-NEXT: ret
+;
+; RV64-LABEL: intrinsic_vadd_mask_vx_nxv2i64_nxv2i64_i64:
+; RV64: # %bb.0: # %entry
+; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, mu
+; RV64-NEXT: vadd.vx v8, v10, a0, v0.t
+; RV64-NEXT: ret
entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vadd.mask.nxv2i64.i64(
<vscale x 2 x i64> %0,
<vscale x 2 x i64> %1,
i64 %2,
<vscale x 2 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 2 x i64> %a
}
@@ -1965,26 +1991,32 @@ declare <vscale x 4 x i64> @llvm.riscv.vadd.nxv4i64.i64(
<vscale x 4 x i64>,
<vscale x 4 x i64>,
i64,
- i32);
-
-define <vscale x 4 x i64> @intrinsic_vadd_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vadd_vx_nxv4i64_nxv4i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addi sp, sp, -16
-; CHECK-NEXT: sw a1, 12(sp)
-; CHECK-NEXT: sw a0, 8(sp)
-; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
-; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v12, (a0), zero
-; CHECK-NEXT: vadd.vv v8, v8, v12
-; CHECK-NEXT: addi sp, sp, 16
-; CHECK-NEXT: ret
+ iXLen);
+
+define <vscale x 4 x i64> @intrinsic_vadd_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, iXLen %2) nounwind {
+; RV32-LABEL: intrinsic_vadd_vx_nxv4i64_nxv4i64_i64:
+; RV32: # %bb.0: # %entry
+; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: sw a1, 12(sp)
+; RV32-NEXT: sw a0, 8(sp)
+; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
+; RV32-NEXT: addi a0, sp, 8
+; RV32-NEXT: vlse64.v v12, (a0), zero
+; RV32-NEXT: vadd.vv v8, v8, v12
+; RV32-NEXT: addi sp, sp, 16
+; RV32-NEXT: ret
+;
+; RV64-LABEL: intrinsic_vadd_vx_nxv4i64_nxv4i64_i64:
+; RV64: # %bb.0: # %entry
+; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu
+; RV64-NEXT: vadd.vx v8, v8, a0
+; RV64-NEXT: ret
entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vadd.nxv4i64.i64(
<vscale x 4 x i64> undef,
<vscale x 4 x i64> %0,
i64 %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 4 x i64> %a
}
@@ -1994,27 +2026,33 @@ declare <vscale x 4 x i64> @llvm.riscv.vadd.mask.nxv4i64.i64(
<vscale x 4 x i64>,
i64,
<vscale x 4 x i1>,
- i32, i32);
-
-define <vscale x 4 x i64> @intrinsic_vadd_mask_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv4i64_nxv4i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addi sp, sp, -16
-; CHECK-NEXT: sw a1, 12(sp)
-; CHECK-NEXT: sw a0, 8(sp)
-; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
-; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v16, (a0), zero
-; CHECK-NEXT: vadd.vv v8, v12, v16, v0.t
-; CHECK-NEXT: addi sp, sp, 16
-; CHECK-NEXT: ret
+ iXLen, iXLen);
+
+define <vscale x 4 x i64> @intrinsic_vadd_mask_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
+; RV32-LABEL: intrinsic_vadd_mask_vx_nxv4i64_nxv4i64_i64:
+; RV32: # %bb.0: # %entry
+; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: sw a1, 12(sp)
+; RV32-NEXT: sw a0, 8(sp)
+; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
+; RV32-NEXT: addi a0, sp, 8
+; RV32-NEXT: vlse64.v v16, (a0), zero
+; RV32-NEXT: vadd.vv v8, v12, v16, v0.t
+; RV32-NEXT: addi sp, sp, 16
+; RV32-NEXT: ret
+;
+; RV64-LABEL: intrinsic_vadd_mask_vx_nxv4i64_nxv4i64_i64:
+; RV64: # %bb.0: # %entry
+; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu
+; RV64-NEXT: vadd.vx v8, v12, a0, v0.t
+; RV64-NEXT: ret
entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vadd.mask.nxv4i64.i64(
<vscale x 4 x i64> %0,
<vscale x 4 x i64> %1,
i64 %2,
<vscale x 4 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 4 x i64> %a
}
@@ -2023,26 +2061,32 @@ declare <vscale x 8 x i64> @llvm.riscv.vadd.nxv8i64.i64(
<vscale x 8 x i64>,
<vscale x 8 x i64>,
i64,
- i32);
-
-define <vscale x 8 x i64> @intrinsic_vadd_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, i64 %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vadd_vx_nxv8i64_nxv8i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addi sp, sp, -16
-; CHECK-NEXT: sw a1, 12(sp)
-; CHECK-NEXT: sw a0, 8(sp)
-; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, mu
-; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v16, (a0), zero
-; CHECK-NEXT: vadd.vv v8, v8, v16
-; CHECK-NEXT: addi sp, sp, 16
-; CHECK-NEXT: ret
+ iXLen);
+
+define <vscale x 8 x i64> @intrinsic_vadd_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, i64 %1, iXLen %2) nounwind {
+; RV32-LABEL: intrinsic_vadd_vx_nxv8i64_nxv8i64_i64:
+; RV32: # %bb.0: # %entry
+; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: sw a1, 12(sp)
+; RV32-NEXT: sw a0, 8(sp)
+; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu
+; RV32-NEXT: addi a0, sp, 8
+; RV32-NEXT: vlse64.v v16, (a0), zero
+; RV32-NEXT: vadd.vv v8, v8, v16
+; RV32-NEXT: addi sp, sp, 16
+; RV32-NEXT: ret
+;
+; RV64-LABEL: intrinsic_vadd_vx_nxv8i64_nxv8i64_i64:
+; RV64: # %bb.0: # %entry
+; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, mu
+; RV64-NEXT: vadd.vx v8, v8, a0
+; RV64-NEXT: ret
entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vadd.nxv8i64.i64(
<vscale x 8 x i64> undef,
<vscale x 8 x i64> %0,
i64 %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 8 x i64> %a
}
@@ -2052,32 +2096,38 @@ declare <vscale x 8 x i64> @llvm.riscv.vadd.mask.nxv8i64.i64(
<vscale x 8 x i64>,
i64,
<vscale x 8 x i1>,
- i32, i32);
-
-define <vscale x 8 x i64> @intrinsic_vadd_mask_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv8i64_nxv8i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addi sp, sp, -16
-; CHECK-NEXT: sw a1, 12(sp)
-; CHECK-NEXT: sw a0, 8(sp)
-; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, mu
-; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v24, (a0), zero
-; CHECK-NEXT: vadd.vv v8, v16, v24, v0.t
-; CHECK-NEXT: addi sp, sp, 16
-; CHECK-NEXT: ret
+ iXLen, iXLen);
+
+define <vscale x 8 x i64> @intrinsic_vadd_mask_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
+; RV32-LABEL: intrinsic_vadd_mask_vx_nxv8i64_nxv8i64_i64:
+; RV32: # %bb.0: # %entry
+; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: sw a1, 12(sp)
+; RV32-NEXT: sw a0, 8(sp)
+; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu
+; RV32-NEXT: addi a0, sp, 8
+; RV32-NEXT: vlse64.v v24, (a0), zero
+; RV32-NEXT: vadd.vv v8, v16, v24, v0.t
+; RV32-NEXT: addi sp, sp, 16
+; RV32-NEXT: ret
+;
+; RV64-LABEL: intrinsic_vadd_mask_vx_nxv8i64_nxv8i64_i64:
+; RV64: # %bb.0: # %entry
+; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, mu
+; RV64-NEXT: vadd.vx v8, v16, a0, v0.t
+; RV64-NEXT: ret
entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vadd.mask.nxv8i64.i64(
<vscale x 8 x i64> %0,
<vscale x 8 x i64> %1,
i64 %2,
<vscale x 8 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 8 x i64> %a
}
-define <vscale x 1 x i8> @intrinsic_vadd_vi_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, i32 %1) nounwind {
+define <vscale x 1 x i8> @intrinsic_vadd_vi_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vadd_vi_nxv1i8_nxv1i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
@@ -2088,12 +2138,12 @@ entry:
<vscale x 1 x i8> undef,
<vscale x 1 x i8> %0,
i8 9,
- i32 %1)
+ iXLen %1)
ret <vscale x 1 x i8> %a
}
-define <vscale x 1 x i8> @intrinsic_vadd_mask_vi_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
+define <vscale x 1 x i8> @intrinsic_vadd_mask_vi_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv1i8_nxv1i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
@@ -2105,12 +2155,12 @@ entry:
<vscale x 1 x i8> %1,
i8 -9,
<vscale x 1 x i1> %2,
- i32 %3, i32 1)
+ iXLen %3, iXLen 1)
ret <vscale x 1 x i8> %a
}
-define <vscale x 2 x i8> @intrinsic_vadd_vi_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, i32 %1) nounwind {
+define <vscale x 2 x i8> @intrinsic_vadd_vi_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vadd_vi_nxv2i8_nxv2i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
@@ -2121,12 +2171,12 @@ entry:
<vscale x 2 x i8> undef,
<vscale x 2 x i8> %0,
i8 9,
- i32 %1)
+ iXLen %1)
ret <vscale x 2 x i8> %a
}
-define <vscale x 2 x i8> @intrinsic_vadd_mask_vi_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
+define <vscale x 2 x i8> @intrinsic_vadd_mask_vi_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv2i8_nxv2i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
@@ -2138,12 +2188,12 @@ entry:
<vscale x 2 x i8> %1,
i8 -9,
<vscale x 2 x i1> %2,
- i32 %3, i32 1)
+ iXLen %3, iXLen 1)
ret <vscale x 2 x i8> %a
}
-define <vscale x 4 x i8> @intrinsic_vadd_vi_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, i32 %1) nounwind {
+define <vscale x 4 x i8> @intrinsic_vadd_vi_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vadd_vi_nxv4i8_nxv4i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
@@ -2154,12 +2204,12 @@ entry:
<vscale x 4 x i8> undef,
<vscale x 4 x i8> %0,
i8 9,
- i32 %1)
+ iXLen %1)
ret <vscale x 4 x i8> %a
}
-define <vscale x 4 x i8> @intrinsic_vadd_mask_vi_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
+define <vscale x 4 x i8> @intrinsic_vadd_mask_vi_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv4i8_nxv4i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
@@ -2171,12 +2221,12 @@ entry:
<vscale x 4 x i8> %1,
i8 -9,
<vscale x 4 x i1> %2,
- i32 %3, i32 1)
+ iXLen %3, iXLen 1)
ret <vscale x 4 x i8> %a
}
-define <vscale x 8 x i8> @intrinsic_vadd_vi_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, i32 %1) nounwind {
+define <vscale x 8 x i8> @intrinsic_vadd_vi_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vadd_vi_nxv8i8_nxv8i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
@@ -2187,12 +2237,12 @@ entry:
<vscale x 8 x i8> undef,
<vscale x 8 x i8> %0,
i8 9,
- i32 %1)
+ iXLen %1)
ret <vscale x 8 x i8> %a
}
-define <vscale x 8 x i8> @intrinsic_vadd_mask_vi_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
+define <vscale x 8 x i8> @intrinsic_vadd_mask_vi_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv8i8_nxv8i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
@@ -2204,12 +2254,12 @@ entry:
<vscale x 8 x i8> %1,
i8 -9,
<vscale x 8 x i1> %2,
- i32 %3, i32 1)
+ iXLen %3, iXLen 1)
ret <vscale x 8 x i8> %a
}
-define <vscale x 16 x i8> @intrinsic_vadd_vi_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, i32 %1) nounwind {
+define <vscale x 16 x i8> @intrinsic_vadd_vi_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vadd_vi_nxv16i8_nxv16i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
@@ -2220,12 +2270,12 @@ entry:
<vscale x 16 x i8> undef,
<vscale x 16 x i8> %0,
i8 9,
- i32 %1)
+ iXLen %1)
ret <vscale x 16 x i8> %a
}
-define <vscale x 16 x i8> @intrinsic_vadd_mask_vi_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i1> %2, i32 %3) nounwind {
+define <vscale x 16 x i8> @intrinsic_vadd_mask_vi_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv16i8_nxv16i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
@@ -2237,12 +2287,12 @@ entry:
<vscale x 16 x i8> %1,
i8 -9,
<vscale x 16 x i1> %2,
- i32 %3, i32 1)
+ iXLen %3, iXLen 1)
ret <vscale x 16 x i8> %a
}
-define <vscale x 32 x i8> @intrinsic_vadd_vi_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, i32 %1) nounwind {
+define <vscale x 32 x i8> @intrinsic_vadd_vi_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vadd_vi_nxv32i8_nxv32i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
@@ -2253,12 +2303,12 @@ entry:
<vscale x 32 x i8> undef,
<vscale x 32 x i8> %0,
i8 9,
- i32 %1)
+ iXLen %1)
ret <vscale x 32 x i8> %a
}
-define <vscale x 32 x i8> @intrinsic_vadd_mask_vi_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i1> %2, i32 %3) nounwind {
+define <vscale x 32 x i8> @intrinsic_vadd_mask_vi_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv32i8_nxv32i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
@@ -2270,12 +2320,12 @@ entry:
<vscale x 32 x i8> %1,
i8 -9,
<vscale x 32 x i1> %2,
- i32 %3, i32 1)
+ iXLen %3, iXLen 1)
ret <vscale x 32 x i8> %a
}
-define <vscale x 64 x i8> @intrinsic_vadd_vi_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, i32 %1) nounwind {
+define <vscale x 64 x i8> @intrinsic_vadd_vi_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vadd_vi_nxv64i8_nxv64i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, mu
@@ -2286,12 +2336,12 @@ entry:
<vscale x 64 x i8> undef,
<vscale x 64 x i8> %0,
i8 -9,
- i32 %1)
+ iXLen %1)
ret <vscale x 64 x i8> %a
}
-define <vscale x 64 x i8> @intrinsic_vadd_mask_vi_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i1> %2, i32 %3) nounwind {
+define <vscale x 64 x i8> @intrinsic_vadd_mask_vi_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv64i8_nxv64i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, mu
@@ -2303,12 +2353,12 @@ entry:
<vscale x 64 x i8> %1,
i8 -9,
<vscale x 64 x i1> %2,
- i32 %3, i32 1)
+ iXLen %3, iXLen 1)
ret <vscale x 64 x i8> %a
}
-define <vscale x 1 x i16> @intrinsic_vadd_vi_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, i32 %1) nounwind {
+define <vscale x 1 x i16> @intrinsic_vadd_vi_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vadd_vi_nxv1i16_nxv1i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
@@ -2319,12 +2369,12 @@ entry:
<vscale x 1 x i16> undef,
<vscale x 1 x i16> %0,
i16 9,
- i32 %1)
+ iXLen %1)
ret <vscale x 1 x i16> %a
}
-define <vscale x 1 x i16> @intrinsic_vadd_mask_vi_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
+define <vscale x 1 x i16> @intrinsic_vadd_mask_vi_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv1i16_nxv1i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
@@ -2336,12 +2386,12 @@ entry:
<vscale x 1 x i16> %1,
i16 -9,
<vscale x 1 x i1> %2,
- i32 %3, i32 1)
+ iXLen %3, iXLen 1)
ret <vscale x 1 x i16> %a
}
-define <vscale x 2 x i16> @intrinsic_vadd_vi_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, i32 %1) nounwind {
+define <vscale x 2 x i16> @intrinsic_vadd_vi_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vadd_vi_nxv2i16_nxv2i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
@@ -2352,12 +2402,12 @@ entry:
<vscale x 2 x i16> undef,
<vscale x 2 x i16> %0,
i16 9,
- i32 %1)
+ iXLen %1)
ret <vscale x 2 x i16> %a
}
-define <vscale x 2 x i16> @intrinsic_vadd_mask_vi_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
+define <vscale x 2 x i16> @intrinsic_vadd_mask_vi_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv2i16_nxv2i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
@@ -2369,12 +2419,12 @@ entry:
<vscale x 2 x i16> %1,
i16 -9,
<vscale x 2 x i1> %2,
- i32 %3, i32 1)
+ iXLen %3, iXLen 1)
ret <vscale x 2 x i16> %a
}
-define <vscale x 4 x i16> @intrinsic_vadd_vi_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, i32 %1) nounwind {
+define <vscale x 4 x i16> @intrinsic_vadd_vi_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vadd_vi_nxv4i16_nxv4i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
@@ -2385,12 +2435,12 @@ entry:
<vscale x 4 x i16> undef,
<vscale x 4 x i16> %0,
i16 9,
- i32 %1)
+ iXLen %1)
ret <vscale x 4 x i16> %a
}
-define <vscale x 4 x i16> @intrinsic_vadd_mask_vi_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
+define <vscale x 4 x i16> @intrinsic_vadd_mask_vi_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv4i16_nxv4i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
@@ -2402,12 +2452,12 @@ entry:
<vscale x 4 x i16> %1,
i16 -9,
<vscale x 4 x i1> %2,
- i32 %3, i32 1)
+ iXLen %3, iXLen 1)
ret <vscale x 4 x i16> %a
}
-define <vscale x 8 x i16> @intrinsic_vadd_vi_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, i32 %1) nounwind {
+define <vscale x 8 x i16> @intrinsic_vadd_vi_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vadd_vi_nxv8i16_nxv8i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
@@ -2418,12 +2468,12 @@ entry:
<vscale x 8 x i16> undef,
<vscale x 8 x i16> %0,
i16 9,
- i32 %1)
+ iXLen %1)
ret <vscale x 8 x i16> %a
}
-define <vscale x 8 x i16> @intrinsic_vadd_mask_vi_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
+define <vscale x 8 x i16> @intrinsic_vadd_mask_vi_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv8i16_nxv8i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
@@ -2435,12 +2485,12 @@ entry:
<vscale x 8 x i16> %1,
i16 -9,
<vscale x 8 x i1> %2,
- i32 %3, i32 1)
+ iXLen %3, iXLen 1)
ret <vscale x 8 x i16> %a
}
-define <vscale x 16 x i16> @intrinsic_vadd_vi_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, i32 %1) nounwind {
+define <vscale x 16 x i16> @intrinsic_vadd_vi_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vadd_vi_nxv16i16_nxv16i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
@@ -2451,12 +2501,12 @@ entry:
<vscale x 16 x i16> undef,
<vscale x 16 x i16> %0,
i16 9,
- i32 %1)
+ iXLen %1)
ret <vscale x 16 x i16> %a
}
-define <vscale x 16 x i16> @intrinsic_vadd_mask_vi_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i1> %2, i32 %3) nounwind {
+define <vscale x 16 x i16> @intrinsic_vadd_mask_vi_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv16i16_nxv16i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
@@ -2468,12 +2518,12 @@ entry:
<vscale x 16 x i16> %1,
i16 -9,
<vscale x 16 x i1> %2,
- i32 %3, i32 1)
+ iXLen %3, iXLen 1)
ret <vscale x 16 x i16> %a
}
-define <vscale x 32 x i16> @intrinsic_vadd_vi_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, i32 %1) nounwind {
+define <vscale x 32 x i16> @intrinsic_vadd_vi_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vadd_vi_nxv32i16_nxv32i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, mu
@@ -2484,12 +2534,12 @@ entry:
<vscale x 32 x i16> undef,
<vscale x 32 x i16> %0,
i16 9,
- i32 %1)
+ iXLen %1)
ret <vscale x 32 x i16> %a
}
-define <vscale x 32 x i16> @intrinsic_vadd_mask_vi_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i1> %2, i32 %3) nounwind {
+define <vscale x 32 x i16> @intrinsic_vadd_mask_vi_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv32i16_nxv32i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, mu
@@ -2501,12 +2551,12 @@ entry:
<vscale x 32 x i16> %1,
i16 -9,
<vscale x 32 x i1> %2,
- i32 %3, i32 1)
+ iXLen %3, iXLen 1)
ret <vscale x 32 x i16> %a
}
-define <vscale x 1 x i32> @intrinsic_vadd_vi_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, i32 %1) nounwind {
+define <vscale x 1 x i32> @intrinsic_vadd_vi_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vadd_vi_nxv1i32_nxv1i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
@@ -2517,12 +2567,12 @@ entry:
<vscale x 1 x i32> undef,
<vscale x 1 x i32> %0,
i32 9,
- i32 %1)
+ iXLen %1)
ret <vscale x 1 x i32> %a
}
-define <vscale x 1 x i32> @intrinsic_vadd_mask_vi_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
+define <vscale x 1 x i32> @intrinsic_vadd_mask_vi_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv1i32_nxv1i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
@@ -2534,12 +2584,12 @@ entry:
<vscale x 1 x i32> %1,
i32 -9,
<vscale x 1 x i1> %2,
- i32 %3, i32 1)
+ iXLen %3, iXLen 1)
ret <vscale x 1 x i32> %a
}
-define <vscale x 2 x i32> @intrinsic_vadd_vi_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, i32 %1) nounwind {
+define <vscale x 2 x i32> @intrinsic_vadd_vi_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vadd_vi_nxv2i32_nxv2i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
@@ -2550,12 +2600,12 @@ entry:
<vscale x 2 x i32> undef,
<vscale x 2 x i32> %0,
i32 9,
- i32 %1)
+ iXLen %1)
ret <vscale x 2 x i32> %a
}
-define <vscale x 2 x i32> @intrinsic_vadd_mask_vi_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
+define <vscale x 2 x i32> @intrinsic_vadd_mask_vi_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv2i32_nxv2i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
@@ -2567,12 +2617,12 @@ entry:
<vscale x 2 x i32> %1,
i32 -9,
<vscale x 2 x i1> %2,
- i32 %3, i32 1)
+ iXLen %3, iXLen 1)
ret <vscale x 2 x i32> %a
}
-define <vscale x 4 x i32> @intrinsic_vadd_vi_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, i32 %1) nounwind {
+define <vscale x 4 x i32> @intrinsic_vadd_vi_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vadd_vi_nxv4i32_nxv4i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
@@ -2583,12 +2633,12 @@ entry:
<vscale x 4 x i32> undef,
<vscale x 4 x i32> %0,
i32 9,
- i32 %1)
+ iXLen %1)
ret <vscale x 4 x i32> %a
}
-define <vscale x 4 x i32> @intrinsic_vadd_mask_vi_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
+define <vscale x 4 x i32> @intrinsic_vadd_mask_vi_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv4i32_nxv4i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
@@ -2600,12 +2650,12 @@ entry:
<vscale x 4 x i32> %1,
i32 -9,
<vscale x 4 x i1> %2,
- i32 %3, i32 1)
+ iXLen %3, iXLen 1)
ret <vscale x 4 x i32> %a
}
-define <vscale x 8 x i32> @intrinsic_vadd_vi_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, i32 %1) nounwind {
+define <vscale x 8 x i32> @intrinsic_vadd_vi_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vadd_vi_nxv8i32_nxv8i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
@@ -2616,12 +2666,12 @@ entry:
<vscale x 8 x i32> undef,
<vscale x 8 x i32> %0,
i32 9,
- i32 %1)
+ iXLen %1)
ret <vscale x 8 x i32> %a
}
-define <vscale x 8 x i32> @intrinsic_vadd_mask_vi_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
+define <vscale x 8 x i32> @intrinsic_vadd_mask_vi_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv8i32_nxv8i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
@@ -2633,12 +2683,12 @@ entry:
<vscale x 8 x i32> %1,
i32 -9,
<vscale x 8 x i1> %2,
- i32 %3, i32 1)
+ iXLen %3, iXLen 1)
ret <vscale x 8 x i32> %a
}
-define <vscale x 16 x i32> @intrinsic_vadd_vi_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, i32 %1) nounwind {
+define <vscale x 16 x i32> @intrinsic_vadd_vi_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vadd_vi_nxv16i32_nxv16i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu
@@ -2649,12 +2699,12 @@ entry:
<vscale x 16 x i32> undef,
<vscale x 16 x i32> %0,
i32 9,
- i32 %1)
+ iXLen %1)
ret <vscale x 16 x i32> %a
}
-define <vscale x 16 x i32> @intrinsic_vadd_mask_vi_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i1> %2, i32 %3) nounwind {
+define <vscale x 16 x i32> @intrinsic_vadd_mask_vi_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv16i32_nxv16i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu
@@ -2666,12 +2716,12 @@ entry:
<vscale x 16 x i32> %1,
i32 -9,
<vscale x 16 x i1> %2,
- i32 %3, i32 1)
+ iXLen %3, iXLen 1)
ret <vscale x 16 x i32> %a
}
-define <vscale x 1 x i64> @intrinsic_vadd_vi_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, i32 %1) nounwind {
+define <vscale x 1 x i64> @intrinsic_vadd_vi_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vadd_vi_nxv1i64_nxv1i64_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
@@ -2682,12 +2732,12 @@ entry:
<vscale x 1 x i64> undef,
<vscale x 1 x i64> %0,
i64 9,
- i32 %1)
+ iXLen %1)
ret <vscale x 1 x i64> %a
}
-define <vscale x 1 x i64> @intrinsic_vadd_mask_vi_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
+define <vscale x 1 x i64> @intrinsic_vadd_mask_vi_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv1i64_nxv1i64_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
@@ -2699,12 +2749,12 @@ entry:
<vscale x 1 x i64> %1,
i64 9,
<vscale x 1 x i1> %2,
- i32 %3, i32 1)
+ iXLen %3, iXLen 1)
ret <vscale x 1 x i64> %a
}
-define <vscale x 2 x i64> @intrinsic_vadd_vi_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, i32 %1) nounwind {
+define <vscale x 2 x i64> @intrinsic_vadd_vi_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vadd_vi_nxv2i64_nxv2i64_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
@@ -2715,12 +2765,12 @@ entry:
<vscale x 2 x i64> undef,
<vscale x 2 x i64> %0,
i64 9,
- i32 %1)
+ iXLen %1)
ret <vscale x 2 x i64> %a
}
-define <vscale x 2 x i64> @intrinsic_vadd_mask_vi_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
+define <vscale x 2 x i64> @intrinsic_vadd_mask_vi_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv2i64_nxv2i64_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
@@ -2732,12 +2782,12 @@ entry:
<vscale x 2 x i64> %1,
i64 9,
<vscale x 2 x i1> %2,
- i32 %3, i32 1)
+ iXLen %3, iXLen 1)
ret <vscale x 2 x i64> %a
}
-define <vscale x 4 x i64> @intrinsic_vadd_vi_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, i32 %1) nounwind {
+define <vscale x 4 x i64> @intrinsic_vadd_vi_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vadd_vi_nxv4i64_nxv4i64_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
@@ -2748,12 +2798,12 @@ entry:
<vscale x 4 x i64> undef,
<vscale x 4 x i64> %0,
i64 9,
- i32 %1)
+ iXLen %1)
ret <vscale x 4 x i64> %a
}
-define <vscale x 4 x i64> @intrinsic_vadd_mask_vi_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
+define <vscale x 4 x i64> @intrinsic_vadd_mask_vi_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv4i64_nxv4i64_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
@@ -2765,12 +2815,12 @@ entry:
<vscale x 4 x i64> %1,
i64 9,
<vscale x 4 x i1> %2,
- i32 %3, i32 1)
+ iXLen %3, iXLen 1)
ret <vscale x 4 x i64> %a
}
-define <vscale x 8 x i64> @intrinsic_vadd_vi_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, i32 %1) nounwind {
+define <vscale x 8 x i64> @intrinsic_vadd_vi_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vadd_vi_nxv8i64_nxv8i64_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu
@@ -2781,12 +2831,12 @@ entry:
<vscale x 8 x i64> undef,
<vscale x 8 x i64> %0,
i64 9,
- i32 %1)
+ iXLen %1)
ret <vscale x 8 x i64> %a
}
-define <vscale x 8 x i64> @intrinsic_vadd_mask_vi_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
+define <vscale x 8 x i64> @intrinsic_vadd_mask_vi_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv8i64_nxv8i64_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu
@@ -2798,7 +2848,7 @@ entry:
<vscale x 8 x i64> %1,
i64 9,
<vscale x 8 x i1> %2,
- i32 %3, i32 1)
+ iXLen %3, iXLen 1)
ret <vscale x 8 x i64> %a
}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vasub-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vasub-rv64.ll
deleted file mode 100644
index 595c05baa7a0f..0000000000000
--- a/llvm/test/CodeGen/RISCV/rvv/vasub-rv64.ll
+++ /dev/null
@@ -1,2074 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs \
-; RUN: < %s | FileCheck %s
-declare <vscale x 1 x i8> @llvm.riscv.vasub.nxv1i8.nxv1i8(
- <vscale x 1 x i8>,
- <vscale x 1 x i8>,
- <vscale x 1 x i8>,
- i64);
-
-define <vscale x 1 x i8> @intrinsic_vasub_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vasub_vv_nxv1i8_nxv1i8_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
-; CHECK-NEXT: vasub.vv v8, v8, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i8> @llvm.riscv.vasub.nxv1i8.nxv1i8(
- <vscale x 1 x i8> undef,
- <vscale x 1 x i8> %0,
- <vscale x 1 x i8> %1,
- i64 %2)
-
- ret <vscale x 1 x i8> %a
-}
-
-declare <vscale x 1 x i8> @llvm.riscv.vasub.mask.nxv1i8.nxv1i8(
- <vscale x 1 x i8>,
- <vscale x 1 x i8>,
- <vscale x 1 x i8>,
- <vscale x 1 x i1>,
- i64,
- i64);
-
-define <vscale x 1 x i8> @intrinsic_vasub_mask_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv1i8_nxv1i8_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
-; CHECK-NEXT: vasub.vv v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i8> @llvm.riscv.vasub.mask.nxv1i8.nxv1i8(
- <vscale x 1 x i8> %0,
- <vscale x 1 x i8> %1,
- <vscale x 1 x i8> %2,
- <vscale x 1 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 1 x i8> %a
-}
-
-declare <vscale x 2 x i8> @llvm.riscv.vasub.nxv2i8.nxv2i8(
- <vscale x 2 x i8>,
- <vscale x 2 x i8>,
- <vscale x 2 x i8>,
- i64);
-
-define <vscale x 2 x i8> @intrinsic_vasub_vv_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vasub_vv_nxv2i8_nxv2i8_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
-; CHECK-NEXT: vasub.vv v8, v8, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i8> @llvm.riscv.vasub.nxv2i8.nxv2i8(
- <vscale x 2 x i8> undef,
- <vscale x 2 x i8> %0,
- <vscale x 2 x i8> %1,
- i64 %2)
-
- ret <vscale x 2 x i8> %a
-}
-
-declare <vscale x 2 x i8> @llvm.riscv.vasub.mask.nxv2i8.nxv2i8(
- <vscale x 2 x i8>,
- <vscale x 2 x i8>,
- <vscale x 2 x i8>,
- <vscale x 2 x i1>,
- i64,
- i64);
-
-define <vscale x 2 x i8> @intrinsic_vasub_mask_vv_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv2i8_nxv2i8_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
-; CHECK-NEXT: vasub.vv v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i8> @llvm.riscv.vasub.mask.nxv2i8.nxv2i8(
- <vscale x 2 x i8> %0,
- <vscale x 2 x i8> %1,
- <vscale x 2 x i8> %2,
- <vscale x 2 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 2 x i8> %a
-}
-
-declare <vscale x 4 x i8> @llvm.riscv.vasub.nxv4i8.nxv4i8(
- <vscale x 4 x i8>,
- <vscale x 4 x i8>,
- <vscale x 4 x i8>,
- i64);
-
-define <vscale x 4 x i8> @intrinsic_vasub_vv_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vasub_vv_nxv4i8_nxv4i8_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
-; CHECK-NEXT: vasub.vv v8, v8, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i8> @llvm.riscv.vasub.nxv4i8.nxv4i8(
- <vscale x 4 x i8> undef,
- <vscale x 4 x i8> %0,
- <vscale x 4 x i8> %1,
- i64 %2)
-
- ret <vscale x 4 x i8> %a
-}
-
-declare <vscale x 4 x i8> @llvm.riscv.vasub.mask.nxv4i8.nxv4i8(
- <vscale x 4 x i8>,
- <vscale x 4 x i8>,
- <vscale x 4 x i8>,
- <vscale x 4 x i1>,
- i64,
- i64);
-
-define <vscale x 4 x i8> @intrinsic_vasub_mask_vv_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv4i8_nxv4i8_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
-; CHECK-NEXT: vasub.vv v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i8> @llvm.riscv.vasub.mask.nxv4i8.nxv4i8(
- <vscale x 4 x i8> %0,
- <vscale x 4 x i8> %1,
- <vscale x 4 x i8> %2,
- <vscale x 4 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 4 x i8> %a
-}
-
-declare <vscale x 8 x i8> @llvm.riscv.vasub.nxv8i8.nxv8i8(
- <vscale x 8 x i8>,
- <vscale x 8 x i8>,
- <vscale x 8 x i8>,
- i64);
-
-define <vscale x 8 x i8> @intrinsic_vasub_vv_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vasub_vv_nxv8i8_nxv8i8_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
-; CHECK-NEXT: vasub.vv v8, v8, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i8> @llvm.riscv.vasub.nxv8i8.nxv8i8(
- <vscale x 8 x i8> undef,
- <vscale x 8 x i8> %0,
- <vscale x 8 x i8> %1,
- i64 %2)
-
- ret <vscale x 8 x i8> %a
-}
-
-declare <vscale x 8 x i8> @llvm.riscv.vasub.mask.nxv8i8.nxv8i8(
- <vscale x 8 x i8>,
- <vscale x 8 x i8>,
- <vscale x 8 x i8>,
- <vscale x 8 x i1>,
- i64,
- i64);
-
-define <vscale x 8 x i8> @intrinsic_vasub_mask_vv_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv8i8_nxv8i8_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
-; CHECK-NEXT: vasub.vv v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i8> @llvm.riscv.vasub.mask.nxv8i8.nxv8i8(
- <vscale x 8 x i8> %0,
- <vscale x 8 x i8> %1,
- <vscale x 8 x i8> %2,
- <vscale x 8 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 8 x i8> %a
-}
-
-declare <vscale x 16 x i8> @llvm.riscv.vasub.nxv16i8.nxv16i8(
- <vscale x 16 x i8>,
- <vscale x 16 x i8>,
- <vscale x 16 x i8>,
- i64);
-
-define <vscale x 16 x i8> @intrinsic_vasub_vv_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vasub_vv_nxv16i8_nxv16i8_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
-; CHECK-NEXT: vasub.vv v8, v8, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i8> @llvm.riscv.vasub.nxv16i8.nxv16i8(
- <vscale x 16 x i8> undef,
- <vscale x 16 x i8> %0,
- <vscale x 16 x i8> %1,
- i64 %2)
-
- ret <vscale x 16 x i8> %a
-}
-
-declare <vscale x 16 x i8> @llvm.riscv.vasub.mask.nxv16i8.nxv16i8(
- <vscale x 16 x i8>,
- <vscale x 16 x i8>,
- <vscale x 16 x i8>,
- <vscale x 16 x i1>,
- i64,
- i64);
-
-define <vscale x 16 x i8> @intrinsic_vasub_mask_vv_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv16i8_nxv16i8_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
-; CHECK-NEXT: vasub.vv v8, v10, v12, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i8> @llvm.riscv.vasub.mask.nxv16i8.nxv16i8(
- <vscale x 16 x i8> %0,
- <vscale x 16 x i8> %1,
- <vscale x 16 x i8> %2,
- <vscale x 16 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 16 x i8> %a
-}
-
-declare <vscale x 32 x i8> @llvm.riscv.vasub.nxv32i8.nxv32i8(
- <vscale x 32 x i8>,
- <vscale x 32 x i8>,
- <vscale x 32 x i8>,
- i64);
-
-define <vscale x 32 x i8> @intrinsic_vasub_vv_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vasub_vv_nxv32i8_nxv32i8_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
-; CHECK-NEXT: vasub.vv v8, v8, v12
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 32 x i8> @llvm.riscv.vasub.nxv32i8.nxv32i8(
- <vscale x 32 x i8> undef,
- <vscale x 32 x i8> %0,
- <vscale x 32 x i8> %1,
- i64 %2)
-
- ret <vscale x 32 x i8> %a
-}
-
-declare <vscale x 32 x i8> @llvm.riscv.vasub.mask.nxv32i8.nxv32i8(
- <vscale x 32 x i8>,
- <vscale x 32 x i8>,
- <vscale x 32 x i8>,
- <vscale x 32 x i1>,
- i64,
- i64);
-
-define <vscale x 32 x i8> @intrinsic_vasub_mask_vv_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv32i8_nxv32i8_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
-; CHECK-NEXT: vasub.vv v8, v12, v16, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 32 x i8> @llvm.riscv.vasub.mask.nxv32i8.nxv32i8(
- <vscale x 32 x i8> %0,
- <vscale x 32 x i8> %1,
- <vscale x 32 x i8> %2,
- <vscale x 32 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 32 x i8> %a
-}
-
-declare <vscale x 64 x i8> @llvm.riscv.vasub.nxv64i8.nxv64i8(
- <vscale x 64 x i8>,
- <vscale x 64 x i8>,
- <vscale x 64 x i8>,
- i64);
-
-define <vscale x 64 x i8> @intrinsic_vasub_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vasub_vv_nxv64i8_nxv64i8_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, mu
-; CHECK-NEXT: vasub.vv v8, v8, v16
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 64 x i8> @llvm.riscv.vasub.nxv64i8.nxv64i8(
- <vscale x 64 x i8> undef,
- <vscale x 64 x i8> %0,
- <vscale x 64 x i8> %1,
- i64 %2)
-
- ret <vscale x 64 x i8> %a
-}
-
-declare <vscale x 64 x i8> @llvm.riscv.vasub.mask.nxv64i8.nxv64i8(
- <vscale x 64 x i8>,
- <vscale x 64 x i8>,
- <vscale x 64 x i8>,
- <vscale x 64 x i1>,
- i64,
- i64);
-
-define <vscale x 64 x i8> @intrinsic_vasub_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv64i8_nxv64i8_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vl8r.v v24, (a0)
-; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu
-; CHECK-NEXT: vasub.vv v8, v16, v24, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 64 x i8> @llvm.riscv.vasub.mask.nxv64i8.nxv64i8(
- <vscale x 64 x i8> %0,
- <vscale x 64 x i8> %1,
- <vscale x 64 x i8> %2,
- <vscale x 64 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 64 x i8> %a
-}
-
-declare <vscale x 1 x i16> @llvm.riscv.vasub.nxv1i16.nxv1i16(
- <vscale x 1 x i16>,
- <vscale x 1 x i16>,
- <vscale x 1 x i16>,
- i64);
-
-define <vscale x 1 x i16> @intrinsic_vasub_vv_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vasub_vv_nxv1i16_nxv1i16_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vasub.vv v8, v8, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i16> @llvm.riscv.vasub.nxv1i16.nxv1i16(
- <vscale x 1 x i16> undef,
- <vscale x 1 x i16> %0,
- <vscale x 1 x i16> %1,
- i64 %2)
-
- ret <vscale x 1 x i16> %a
-}
-
-declare <vscale x 1 x i16> @llvm.riscv.vasub.mask.nxv1i16.nxv1i16(
- <vscale x 1 x i16>,
- <vscale x 1 x i16>,
- <vscale x 1 x i16>,
- <vscale x 1 x i1>,
- i64,
- i64);
-
-define <vscale x 1 x i16> @intrinsic_vasub_mask_vv_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv1i16_nxv1i16_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vasub.vv v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i16> @llvm.riscv.vasub.mask.nxv1i16.nxv1i16(
- <vscale x 1 x i16> %0,
- <vscale x 1 x i16> %1,
- <vscale x 1 x i16> %2,
- <vscale x 1 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 1 x i16> %a
-}
-
-declare <vscale x 2 x i16> @llvm.riscv.vasub.nxv2i16.nxv2i16(
- <vscale x 2 x i16>,
- <vscale x 2 x i16>,
- <vscale x 2 x i16>,
- i64);
-
-define <vscale x 2 x i16> @intrinsic_vasub_vv_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vasub_vv_nxv2i16_nxv2i16_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vasub.vv v8, v8, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i16> @llvm.riscv.vasub.nxv2i16.nxv2i16(
- <vscale x 2 x i16> undef,
- <vscale x 2 x i16> %0,
- <vscale x 2 x i16> %1,
- i64 %2)
-
- ret <vscale x 2 x i16> %a
-}
-
-declare <vscale x 2 x i16> @llvm.riscv.vasub.mask.nxv2i16.nxv2i16(
- <vscale x 2 x i16>,
- <vscale x 2 x i16>,
- <vscale x 2 x i16>,
- <vscale x 2 x i1>,
- i64,
- i64);
-
-define <vscale x 2 x i16> @intrinsic_vasub_mask_vv_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv2i16_nxv2i16_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vasub.vv v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i16> @llvm.riscv.vasub.mask.nxv2i16.nxv2i16(
- <vscale x 2 x i16> %0,
- <vscale x 2 x i16> %1,
- <vscale x 2 x i16> %2,
- <vscale x 2 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 2 x i16> %a
-}
-
-declare <vscale x 4 x i16> @llvm.riscv.vasub.nxv4i16.nxv4i16(
- <vscale x 4 x i16>,
- <vscale x 4 x i16>,
- <vscale x 4 x i16>,
- i64);
-
-define <vscale x 4 x i16> @intrinsic_vasub_vv_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vasub_vv_nxv4i16_nxv4i16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vasub.vv v8, v8, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i16> @llvm.riscv.vasub.nxv4i16.nxv4i16(
- <vscale x 4 x i16> undef,
- <vscale x 4 x i16> %0,
- <vscale x 4 x i16> %1,
- i64 %2)
-
- ret <vscale x 4 x i16> %a
-}
-
-declare <vscale x 4 x i16> @llvm.riscv.vasub.mask.nxv4i16.nxv4i16(
- <vscale x 4 x i16>,
- <vscale x 4 x i16>,
- <vscale x 4 x i16>,
- <vscale x 4 x i1>,
- i64,
- i64);
-
-define <vscale x 4 x i16> @intrinsic_vasub_mask_vv_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv4i16_nxv4i16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vasub.vv v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i16> @llvm.riscv.vasub.mask.nxv4i16.nxv4i16(
- <vscale x 4 x i16> %0,
- <vscale x 4 x i16> %1,
- <vscale x 4 x i16> %2,
- <vscale x 4 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 4 x i16> %a
-}
-
-declare <vscale x 8 x i16> @llvm.riscv.vasub.nxv8i16.nxv8i16(
- <vscale x 8 x i16>,
- <vscale x 8 x i16>,
- <vscale x 8 x i16>,
- i64);
-
-define <vscale x 8 x i16> @intrinsic_vasub_vv_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vasub_vv_nxv8i16_nxv8i16_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vasub.vv v8, v8, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i16> @llvm.riscv.vasub.nxv8i16.nxv8i16(
- <vscale x 8 x i16> undef,
- <vscale x 8 x i16> %0,
- <vscale x 8 x i16> %1,
- i64 %2)
-
- ret <vscale x 8 x i16> %a
-}
-
-declare <vscale x 8 x i16> @llvm.riscv.vasub.mask.nxv8i16.nxv8i16(
- <vscale x 8 x i16>,
- <vscale x 8 x i16>,
- <vscale x 8 x i16>,
- <vscale x 8 x i1>,
- i64,
- i64);
-
-define <vscale x 8 x i16> @intrinsic_vasub_mask_vv_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv8i16_nxv8i16_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vasub.vv v8, v10, v12, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i16> @llvm.riscv.vasub.mask.nxv8i16.nxv8i16(
- <vscale x 8 x i16> %0,
- <vscale x 8 x i16> %1,
- <vscale x 8 x i16> %2,
- <vscale x 8 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 8 x i16> %a
-}
-
-declare <vscale x 16 x i16> @llvm.riscv.vasub.nxv16i16.nxv16i16(
- <vscale x 16 x i16>,
- <vscale x 16 x i16>,
- <vscale x 16 x i16>,
- i64);
-
-define <vscale x 16 x i16> @intrinsic_vasub_vv_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vasub_vv_nxv16i16_nxv16i16_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
-; CHECK-NEXT: vasub.vv v8, v8, v12
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i16> @llvm.riscv.vasub.nxv16i16.nxv16i16(
- <vscale x 16 x i16> undef,
- <vscale x 16 x i16> %0,
- <vscale x 16 x i16> %1,
- i64 %2)
-
- ret <vscale x 16 x i16> %a
-}
-
-declare <vscale x 16 x i16> @llvm.riscv.vasub.mask.nxv16i16.nxv16i16(
- <vscale x 16 x i16>,
- <vscale x 16 x i16>,
- <vscale x 16 x i16>,
- <vscale x 16 x i1>,
- i64,
- i64);
-
-define <vscale x 16 x i16> @intrinsic_vasub_mask_vv_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv16i16_nxv16i16_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
-; CHECK-NEXT: vasub.vv v8, v12, v16, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i16> @llvm.riscv.vasub.mask.nxv16i16.nxv16i16(
- <vscale x 16 x i16> %0,
- <vscale x 16 x i16> %1,
- <vscale x 16 x i16> %2,
- <vscale x 16 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 16 x i16> %a
-}
-
-declare <vscale x 32 x i16> @llvm.riscv.vasub.nxv32i16.nxv32i16(
- <vscale x 32 x i16>,
- <vscale x 32 x i16>,
- <vscale x 32 x i16>,
- i64);
-
-define <vscale x 32 x i16> @intrinsic_vasub_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vasub_vv_nxv32i16_nxv32i16_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, mu
-; CHECK-NEXT: vasub.vv v8, v8, v16
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 32 x i16> @llvm.riscv.vasub.nxv32i16.nxv32i16(
- <vscale x 32 x i16> undef,
- <vscale x 32 x i16> %0,
- <vscale x 32 x i16> %1,
- i64 %2)
-
- ret <vscale x 32 x i16> %a
-}
-
-declare <vscale x 32 x i16> @llvm.riscv.vasub.mask.nxv32i16.nxv32i16(
- <vscale x 32 x i16>,
- <vscale x 32 x i16>,
- <vscale x 32 x i16>,
- <vscale x 32 x i1>,
- i64,
- i64);
-
-define <vscale x 32 x i16> @intrinsic_vasub_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv32i16_nxv32i16_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vl8re16.v v24, (a0)
-; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu
-; CHECK-NEXT: vasub.vv v8, v16, v24, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 32 x i16> @llvm.riscv.vasub.mask.nxv32i16.nxv32i16(
- <vscale x 32 x i16> %0,
- <vscale x 32 x i16> %1,
- <vscale x 32 x i16> %2,
- <vscale x 32 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 32 x i16> %a
-}
-
-declare <vscale x 1 x i32> @llvm.riscv.vasub.nxv1i32.nxv1i32(
- <vscale x 1 x i32>,
- <vscale x 1 x i32>,
- <vscale x 1 x i32>,
- i64);
-
-define <vscale x 1 x i32> @intrinsic_vasub_vv_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vasub_vv_nxv1i32_nxv1i32_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vasub.vv v8, v8, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i32> @llvm.riscv.vasub.nxv1i32.nxv1i32(
- <vscale x 1 x i32> undef,
- <vscale x 1 x i32> %0,
- <vscale x 1 x i32> %1,
- i64 %2)
-
- ret <vscale x 1 x i32> %a
-}
-
-declare <vscale x 1 x i32> @llvm.riscv.vasub.mask.nxv1i32.nxv1i32(
- <vscale x 1 x i32>,
- <vscale x 1 x i32>,
- <vscale x 1 x i32>,
- <vscale x 1 x i1>,
- i64,
- i64);
-
-define <vscale x 1 x i32> @intrinsic_vasub_mask_vv_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv1i32_nxv1i32_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vasub.vv v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i32> @llvm.riscv.vasub.mask.nxv1i32.nxv1i32(
- <vscale x 1 x i32> %0,
- <vscale x 1 x i32> %1,
- <vscale x 1 x i32> %2,
- <vscale x 1 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 1 x i32> %a
-}
-
-declare <vscale x 2 x i32> @llvm.riscv.vasub.nxv2i32.nxv2i32(
- <vscale x 2 x i32>,
- <vscale x 2 x i32>,
- <vscale x 2 x i32>,
- i64);
-
-define <vscale x 2 x i32> @intrinsic_vasub_vv_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vasub_vv_nxv2i32_nxv2i32_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vasub.vv v8, v8, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i32> @llvm.riscv.vasub.nxv2i32.nxv2i32(
- <vscale x 2 x i32> undef,
- <vscale x 2 x i32> %0,
- <vscale x 2 x i32> %1,
- i64 %2)
-
- ret <vscale x 2 x i32> %a
-}
-
-declare <vscale x 2 x i32> @llvm.riscv.vasub.mask.nxv2i32.nxv2i32(
- <vscale x 2 x i32>,
- <vscale x 2 x i32>,
- <vscale x 2 x i32>,
- <vscale x 2 x i1>,
- i64,
- i64);
-
-define <vscale x 2 x i32> @intrinsic_vasub_mask_vv_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv2i32_nxv2i32_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vasub.vv v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i32> @llvm.riscv.vasub.mask.nxv2i32.nxv2i32(
- <vscale x 2 x i32> %0,
- <vscale x 2 x i32> %1,
- <vscale x 2 x i32> %2,
- <vscale x 2 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 2 x i32> %a
-}
-
-declare <vscale x 4 x i32> @llvm.riscv.vasub.nxv4i32.nxv4i32(
- <vscale x 4 x i32>,
- <vscale x 4 x i32>,
- <vscale x 4 x i32>,
- i64);
-
-define <vscale x 4 x i32> @intrinsic_vasub_vv_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vasub_vv_nxv4i32_nxv4i32_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vasub.vv v8, v8, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i32> @llvm.riscv.vasub.nxv4i32.nxv4i32(
- <vscale x 4 x i32> undef,
- <vscale x 4 x i32> %0,
- <vscale x 4 x i32> %1,
- i64 %2)
-
- ret <vscale x 4 x i32> %a
-}
-
-declare <vscale x 4 x i32> @llvm.riscv.vasub.mask.nxv4i32.nxv4i32(
- <vscale x 4 x i32>,
- <vscale x 4 x i32>,
- <vscale x 4 x i32>,
- <vscale x 4 x i1>,
- i64,
- i64);
-
-define <vscale x 4 x i32> @intrinsic_vasub_mask_vv_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv4i32_nxv4i32_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vasub.vv v8, v10, v12, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i32> @llvm.riscv.vasub.mask.nxv4i32.nxv4i32(
- <vscale x 4 x i32> %0,
- <vscale x 4 x i32> %1,
- <vscale x 4 x i32> %2,
- <vscale x 4 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 4 x i32> %a
-}
-
-declare <vscale x 8 x i32> @llvm.riscv.vasub.nxv8i32.nxv8i32(
- <vscale x 8 x i32>,
- <vscale x 8 x i32>,
- <vscale x 8 x i32>,
- i64);
-
-define <vscale x 8 x i32> @intrinsic_vasub_vv_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vasub_vv_nxv8i32_nxv8i32_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
-; CHECK-NEXT: vasub.vv v8, v8, v12
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i32> @llvm.riscv.vasub.nxv8i32.nxv8i32(
- <vscale x 8 x i32> undef,
- <vscale x 8 x i32> %0,
- <vscale x 8 x i32> %1,
- i64 %2)
-
- ret <vscale x 8 x i32> %a
-}
-
-declare <vscale x 8 x i32> @llvm.riscv.vasub.mask.nxv8i32.nxv8i32(
- <vscale x 8 x i32>,
- <vscale x 8 x i32>,
- <vscale x 8 x i32>,
- <vscale x 8 x i1>,
- i64,
- i64);
-
-define <vscale x 8 x i32> @intrinsic_vasub_mask_vv_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv8i32_nxv8i32_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
-; CHECK-NEXT: vasub.vv v8, v12, v16, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i32> @llvm.riscv.vasub.mask.nxv8i32.nxv8i32(
- <vscale x 8 x i32> %0,
- <vscale x 8 x i32> %1,
- <vscale x 8 x i32> %2,
- <vscale x 8 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 8 x i32> %a
-}
-
-declare <vscale x 16 x i32> @llvm.riscv.vasub.nxv16i32.nxv16i32(
- <vscale x 16 x i32>,
- <vscale x 16 x i32>,
- <vscale x 16 x i32>,
- i64);
-
-define <vscale x 16 x i32> @intrinsic_vasub_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vasub_vv_nxv16i32_nxv16i32_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu
-; CHECK-NEXT: vasub.vv v8, v8, v16
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i32> @llvm.riscv.vasub.nxv16i32.nxv16i32(
- <vscale x 16 x i32> undef,
- <vscale x 16 x i32> %0,
- <vscale x 16 x i32> %1,
- i64 %2)
-
- ret <vscale x 16 x i32> %a
-}
-
-declare <vscale x 16 x i32> @llvm.riscv.vasub.mask.nxv16i32.nxv16i32(
- <vscale x 16 x i32>,
- <vscale x 16 x i32>,
- <vscale x 16 x i32>,
- <vscale x 16 x i1>,
- i64,
- i64);
-
-define <vscale x 16 x i32> @intrinsic_vasub_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv16i32_nxv16i32_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vl8re32.v v24, (a0)
-; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu
-; CHECK-NEXT: vasub.vv v8, v16, v24, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i32> @llvm.riscv.vasub.mask.nxv16i32.nxv16i32(
- <vscale x 16 x i32> %0,
- <vscale x 16 x i32> %1,
- <vscale x 16 x i32> %2,
- <vscale x 16 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 16 x i32> %a
-}
-
-declare <vscale x 1 x i64> @llvm.riscv.vasub.nxv1i64.nxv1i64(
- <vscale x 1 x i64>,
- <vscale x 1 x i64>,
- <vscale x 1 x i64>,
- i64);
-
-define <vscale x 1 x i64> @intrinsic_vasub_vv_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vasub_vv_nxv1i64_nxv1i64_nxv1i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
-; CHECK-NEXT: vasub.vv v8, v8, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i64> @llvm.riscv.vasub.nxv1i64.nxv1i64(
- <vscale x 1 x i64> undef,
- <vscale x 1 x i64> %0,
- <vscale x 1 x i64> %1,
- i64 %2)
-
- ret <vscale x 1 x i64> %a
-}
-
-declare <vscale x 1 x i64> @llvm.riscv.vasub.mask.nxv1i64.nxv1i64(
- <vscale x 1 x i64>,
- <vscale x 1 x i64>,
- <vscale x 1 x i64>,
- <vscale x 1 x i1>,
- i64,
- i64);
-
-define <vscale x 1 x i64> @intrinsic_vasub_mask_vv_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv1i64_nxv1i64_nxv1i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
-; CHECK-NEXT: vasub.vv v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i64> @llvm.riscv.vasub.mask.nxv1i64.nxv1i64(
- <vscale x 1 x i64> %0,
- <vscale x 1 x i64> %1,
- <vscale x 1 x i64> %2,
- <vscale x 1 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 1 x i64> %a
-}
-
-declare <vscale x 2 x i64> @llvm.riscv.vasub.nxv2i64.nxv2i64(
- <vscale x 2 x i64>,
- <vscale x 2 x i64>,
- <vscale x 2 x i64>,
- i64);
-
-define <vscale x 2 x i64> @intrinsic_vasub_vv_nxv2i64_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vasub_vv_nxv2i64_nxv2i64_nxv2i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
-; CHECK-NEXT: vasub.vv v8, v8, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i64> @llvm.riscv.vasub.nxv2i64.nxv2i64(
- <vscale x 2 x i64> undef,
- <vscale x 2 x i64> %0,
- <vscale x 2 x i64> %1,
- i64 %2)
-
- ret <vscale x 2 x i64> %a
-}
-
-declare <vscale x 2 x i64> @llvm.riscv.vasub.mask.nxv2i64.nxv2i64(
- <vscale x 2 x i64>,
- <vscale x 2 x i64>,
- <vscale x 2 x i64>,
- <vscale x 2 x i1>,
- i64,
- i64);
-
-define <vscale x 2 x i64> @intrinsic_vasub_mask_vv_nxv2i64_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv2i64_nxv2i64_nxv2i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
-; CHECK-NEXT: vasub.vv v8, v10, v12, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i64> @llvm.riscv.vasub.mask.nxv2i64.nxv2i64(
- <vscale x 2 x i64> %0,
- <vscale x 2 x i64> %1,
- <vscale x 2 x i64> %2,
- <vscale x 2 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 2 x i64> %a
-}
-
-declare <vscale x 4 x i64> @llvm.riscv.vasub.nxv4i64.nxv4i64(
- <vscale x 4 x i64>,
- <vscale x 4 x i64>,
- <vscale x 4 x i64>,
- i64);
-
-define <vscale x 4 x i64> @intrinsic_vasub_vv_nxv4i64_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vasub_vv_nxv4i64_nxv4i64_nxv4i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
-; CHECK-NEXT: vasub.vv v8, v8, v12
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i64> @llvm.riscv.vasub.nxv4i64.nxv4i64(
- <vscale x 4 x i64> undef,
- <vscale x 4 x i64> %0,
- <vscale x 4 x i64> %1,
- i64 %2)
-
- ret <vscale x 4 x i64> %a
-}
-
-declare <vscale x 4 x i64> @llvm.riscv.vasub.mask.nxv4i64.nxv4i64(
- <vscale x 4 x i64>,
- <vscale x 4 x i64>,
- <vscale x 4 x i64>,
- <vscale x 4 x i1>,
- i64,
- i64);
-
-define <vscale x 4 x i64> @intrinsic_vasub_mask_vv_nxv4i64_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv4i64_nxv4i64_nxv4i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
-; CHECK-NEXT: vasub.vv v8, v12, v16, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i64> @llvm.riscv.vasub.mask.nxv4i64.nxv4i64(
- <vscale x 4 x i64> %0,
- <vscale x 4 x i64> %1,
- <vscale x 4 x i64> %2,
- <vscale x 4 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 4 x i64> %a
-}
-
-declare <vscale x 8 x i64> @llvm.riscv.vasub.nxv8i64.nxv8i64(
- <vscale x 8 x i64>,
- <vscale x 8 x i64>,
- <vscale x 8 x i64>,
- i64);
-
-define <vscale x 8 x i64> @intrinsic_vasub_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vasub_vv_nxv8i64_nxv8i64_nxv8i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu
-; CHECK-NEXT: vasub.vv v8, v8, v16
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i64> @llvm.riscv.vasub.nxv8i64.nxv8i64(
- <vscale x 8 x i64> undef,
- <vscale x 8 x i64> %0,
- <vscale x 8 x i64> %1,
- i64 %2)
-
- ret <vscale x 8 x i64> %a
-}
-
-declare <vscale x 8 x i64> @llvm.riscv.vasub.mask.nxv8i64.nxv8i64(
- <vscale x 8 x i64>,
- <vscale x 8 x i64>,
- <vscale x 8 x i64>,
- <vscale x 8 x i1>,
- i64,
- i64);
-
-define <vscale x 8 x i64> @intrinsic_vasub_mask_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv8i64_nxv8i64_nxv8i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vl8re64.v v24, (a0)
-; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu
-; CHECK-NEXT: vasub.vv v8, v16, v24, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i64> @llvm.riscv.vasub.mask.nxv8i64.nxv8i64(
- <vscale x 8 x i64> %0,
- <vscale x 8 x i64> %1,
- <vscale x 8 x i64> %2,
- <vscale x 8 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 8 x i64> %a
-}
-
-declare <vscale x 1 x i8> @llvm.riscv.vasub.nxv1i8.i8(
- <vscale x 1 x i8>,
- <vscale x 1 x i8>,
- i8,
- i64);
-
-define <vscale x 1 x i8> @intrinsic_vasub_vx_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, i8 %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vasub_vx_nxv1i8_nxv1i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
-; CHECK-NEXT: vasub.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i8> @llvm.riscv.vasub.nxv1i8.i8(
- <vscale x 1 x i8> undef,
- <vscale x 1 x i8> %0,
- i8 %1,
- i64 %2)
-
- ret <vscale x 1 x i8> %a
-}
-
-declare <vscale x 1 x i8> @llvm.riscv.vasub.mask.nxv1i8.i8(
- <vscale x 1 x i8>,
- <vscale x 1 x i8>,
- i8,
- <vscale x 1 x i1>,
- i64,
- i64);
-
-define <vscale x 1 x i8> @intrinsic_vasub_mask_vx_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vasub_mask_vx_nxv1i8_nxv1i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
-; CHECK-NEXT: vasub.vx v8, v9, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i8> @llvm.riscv.vasub.mask.nxv1i8.i8(
- <vscale x 1 x i8> %0,
- <vscale x 1 x i8> %1,
- i8 %2,
- <vscale x 1 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 1 x i8> %a
-}
-
-declare <vscale x 2 x i8> @llvm.riscv.vasub.nxv2i8.i8(
- <vscale x 2 x i8>,
- <vscale x 2 x i8>,
- i8,
- i64);
-
-define <vscale x 2 x i8> @intrinsic_vasub_vx_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, i8 %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vasub_vx_nxv2i8_nxv2i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
-; CHECK-NEXT: vasub.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i8> @llvm.riscv.vasub.nxv2i8.i8(
- <vscale x 2 x i8> undef,
- <vscale x 2 x i8> %0,
- i8 %1,
- i64 %2)
-
- ret <vscale x 2 x i8> %a
-}
-
-declare <vscale x 2 x i8> @llvm.riscv.vasub.mask.nxv2i8.i8(
- <vscale x 2 x i8>,
- <vscale x 2 x i8>,
- i8,
- <vscale x 2 x i1>,
- i64,
- i64);
-
-define <vscale x 2 x i8> @intrinsic_vasub_mask_vx_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vasub_mask_vx_nxv2i8_nxv2i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
-; CHECK-NEXT: vasub.vx v8, v9, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i8> @llvm.riscv.vasub.mask.nxv2i8.i8(
- <vscale x 2 x i8> %0,
- <vscale x 2 x i8> %1,
- i8 %2,
- <vscale x 2 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 2 x i8> %a
-}
-
-declare <vscale x 4 x i8> @llvm.riscv.vasub.nxv4i8.i8(
- <vscale x 4 x i8>,
- <vscale x 4 x i8>,
- i8,
- i64);
-
-define <vscale x 4 x i8> @intrinsic_vasub_vx_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, i8 %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vasub_vx_nxv4i8_nxv4i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
-; CHECK-NEXT: vasub.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i8> @llvm.riscv.vasub.nxv4i8.i8(
- <vscale x 4 x i8> undef,
- <vscale x 4 x i8> %0,
- i8 %1,
- i64 %2)
-
- ret <vscale x 4 x i8> %a
-}
-
-declare <vscale x 4 x i8> @llvm.riscv.vasub.mask.nxv4i8.i8(
- <vscale x 4 x i8>,
- <vscale x 4 x i8>,
- i8,
- <vscale x 4 x i1>,
- i64,
- i64);
-
-define <vscale x 4 x i8> @intrinsic_vasub_mask_vx_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vasub_mask_vx_nxv4i8_nxv4i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
-; CHECK-NEXT: vasub.vx v8, v9, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i8> @llvm.riscv.vasub.mask.nxv4i8.i8(
- <vscale x 4 x i8> %0,
- <vscale x 4 x i8> %1,
- i8 %2,
- <vscale x 4 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 4 x i8> %a
-}
-
-declare <vscale x 8 x i8> @llvm.riscv.vasub.nxv8i8.i8(
- <vscale x 8 x i8>,
- <vscale x 8 x i8>,
- i8,
- i64);
-
-define <vscale x 8 x i8> @intrinsic_vasub_vx_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, i8 %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vasub_vx_nxv8i8_nxv8i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
-; CHECK-NEXT: vasub.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i8> @llvm.riscv.vasub.nxv8i8.i8(
- <vscale x 8 x i8> undef,
- <vscale x 8 x i8> %0,
- i8 %1,
- i64 %2)
-
- ret <vscale x 8 x i8> %a
-}
-
-declare <vscale x 8 x i8> @llvm.riscv.vasub.mask.nxv8i8.i8(
- <vscale x 8 x i8>,
- <vscale x 8 x i8>,
- i8,
- <vscale x 8 x i1>,
- i64,
- i64);
-
-define <vscale x 8 x i8> @intrinsic_vasub_mask_vx_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vasub_mask_vx_nxv8i8_nxv8i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
-; CHECK-NEXT: vasub.vx v8, v9, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i8> @llvm.riscv.vasub.mask.nxv8i8.i8(
- <vscale x 8 x i8> %0,
- <vscale x 8 x i8> %1,
- i8 %2,
- <vscale x 8 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 8 x i8> %a
-}
-
-declare <vscale x 16 x i8> @llvm.riscv.vasub.nxv16i8.i8(
- <vscale x 16 x i8>,
- <vscale x 16 x i8>,
- i8,
- i64);
-
-define <vscale x 16 x i8> @intrinsic_vasub_vx_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, i8 %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vasub_vx_nxv16i8_nxv16i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
-; CHECK-NEXT: vasub.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i8> @llvm.riscv.vasub.nxv16i8.i8(
- <vscale x 16 x i8> undef,
- <vscale x 16 x i8> %0,
- i8 %1,
- i64 %2)
-
- ret <vscale x 16 x i8> %a
-}
-
-declare <vscale x 16 x i8> @llvm.riscv.vasub.mask.nxv16i8.i8(
- <vscale x 16 x i8>,
- <vscale x 16 x i8>,
- i8,
- <vscale x 16 x i1>,
- i64,
- i64);
-
-define <vscale x 16 x i8> @intrinsic_vasub_mask_vx_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vasub_mask_vx_nxv16i8_nxv16i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
-; CHECK-NEXT: vasub.vx v8, v10, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i8> @llvm.riscv.vasub.mask.nxv16i8.i8(
- <vscale x 16 x i8> %0,
- <vscale x 16 x i8> %1,
- i8 %2,
- <vscale x 16 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 16 x i8> %a
-}
-
-declare <vscale x 32 x i8> @llvm.riscv.vasub.nxv32i8.i8(
- <vscale x 32 x i8>,
- <vscale x 32 x i8>,
- i8,
- i64);
-
-define <vscale x 32 x i8> @intrinsic_vasub_vx_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, i8 %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vasub_vx_nxv32i8_nxv32i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
-; CHECK-NEXT: vasub.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 32 x i8> @llvm.riscv.vasub.nxv32i8.i8(
- <vscale x 32 x i8> undef,
- <vscale x 32 x i8> %0,
- i8 %1,
- i64 %2)
-
- ret <vscale x 32 x i8> %a
-}
-
-declare <vscale x 32 x i8> @llvm.riscv.vasub.mask.nxv32i8.i8(
- <vscale x 32 x i8>,
- <vscale x 32 x i8>,
- i8,
- <vscale x 32 x i1>,
- i64,
- i64);
-
-define <vscale x 32 x i8> @intrinsic_vasub_mask_vx_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vasub_mask_vx_nxv32i8_nxv32i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
-; CHECK-NEXT: vasub.vx v8, v12, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 32 x i8> @llvm.riscv.vasub.mask.nxv32i8.i8(
- <vscale x 32 x i8> %0,
- <vscale x 32 x i8> %1,
- i8 %2,
- <vscale x 32 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 32 x i8> %a
-}
-
-declare <vscale x 64 x i8> @llvm.riscv.vasub.nxv64i8.i8(
- <vscale x 64 x i8>,
- <vscale x 64 x i8>,
- i8,
- i64);
-
-define <vscale x 64 x i8> @intrinsic_vasub_vx_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, i8 %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vasub_vx_nxv64i8_nxv64i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu
-; CHECK-NEXT: vasub.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 64 x i8> @llvm.riscv.vasub.nxv64i8.i8(
- <vscale x 64 x i8> undef,
- <vscale x 64 x i8> %0,
- i8 %1,
- i64 %2)
-
- ret <vscale x 64 x i8> %a
-}
-
-declare <vscale x 64 x i8> @llvm.riscv.vasub.mask.nxv64i8.i8(
- <vscale x 64 x i8>,
- <vscale x 64 x i8>,
- i8,
- <vscale x 64 x i1>,
- i64,
- i64);
-
-define <vscale x 64 x i8> @intrinsic_vasub_mask_vx_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i8 %2, <vscale x 64 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vasub_mask_vx_nxv64i8_nxv64i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu
-; CHECK-NEXT: vasub.vx v8, v16, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 64 x i8> @llvm.riscv.vasub.mask.nxv64i8.i8(
- <vscale x 64 x i8> %0,
- <vscale x 64 x i8> %1,
- i8 %2,
- <vscale x 64 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 64 x i8> %a
-}
-
-declare <vscale x 1 x i16> @llvm.riscv.vasub.nxv1i16.i16(
- <vscale x 1 x i16>,
- <vscale x 1 x i16>,
- i16,
- i64);
-
-define <vscale x 1 x i16> @intrinsic_vasub_vx_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, i16 %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vasub_vx_nxv1i16_nxv1i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
-; CHECK-NEXT: vasub.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i16> @llvm.riscv.vasub.nxv1i16.i16(
- <vscale x 1 x i16> undef,
- <vscale x 1 x i16> %0,
- i16 %1,
- i64 %2)
-
- ret <vscale x 1 x i16> %a
-}
-
-declare <vscale x 1 x i16> @llvm.riscv.vasub.mask.nxv1i16.i16(
- <vscale x 1 x i16>,
- <vscale x 1 x i16>,
- i16,
- <vscale x 1 x i1>,
- i64,
- i64);
-
-define <vscale x 1 x i16> @intrinsic_vasub_mask_vx_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vasub_mask_vx_nxv1i16_nxv1i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
-; CHECK-NEXT: vasub.vx v8, v9, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i16> @llvm.riscv.vasub.mask.nxv1i16.i16(
- <vscale x 1 x i16> %0,
- <vscale x 1 x i16> %1,
- i16 %2,
- <vscale x 1 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 1 x i16> %a
-}
-
-declare <vscale x 2 x i16> @llvm.riscv.vasub.nxv2i16.i16(
- <vscale x 2 x i16>,
- <vscale x 2 x i16>,
- i16,
- i64);
-
-define <vscale x 2 x i16> @intrinsic_vasub_vx_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, i16 %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vasub_vx_nxv2i16_nxv2i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
-; CHECK-NEXT: vasub.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i16> @llvm.riscv.vasub.nxv2i16.i16(
- <vscale x 2 x i16> undef,
- <vscale x 2 x i16> %0,
- i16 %1,
- i64 %2)
-
- ret <vscale x 2 x i16> %a
-}
-
-declare <vscale x 2 x i16> @llvm.riscv.vasub.mask.nxv2i16.i16(
- <vscale x 2 x i16>,
- <vscale x 2 x i16>,
- i16,
- <vscale x 2 x i1>,
- i64,
- i64);
-
-define <vscale x 2 x i16> @intrinsic_vasub_mask_vx_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vasub_mask_vx_nxv2i16_nxv2i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
-; CHECK-NEXT: vasub.vx v8, v9, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i16> @llvm.riscv.vasub.mask.nxv2i16.i16(
- <vscale x 2 x i16> %0,
- <vscale x 2 x i16> %1,
- i16 %2,
- <vscale x 2 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 2 x i16> %a
-}
-
-declare <vscale x 4 x i16> @llvm.riscv.vasub.nxv4i16.i16(
- <vscale x 4 x i16>,
- <vscale x 4 x i16>,
- i16,
- i64);
-
-define <vscale x 4 x i16> @intrinsic_vasub_vx_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, i16 %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vasub_vx_nxv4i16_nxv4i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
-; CHECK-NEXT: vasub.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i16> @llvm.riscv.vasub.nxv4i16.i16(
- <vscale x 4 x i16> undef,
- <vscale x 4 x i16> %0,
- i16 %1,
- i64 %2)
-
- ret <vscale x 4 x i16> %a
-}
-
-declare <vscale x 4 x i16> @llvm.riscv.vasub.mask.nxv4i16.i16(
- <vscale x 4 x i16>,
- <vscale x 4 x i16>,
- i16,
- <vscale x 4 x i1>,
- i64,
- i64);
-
-define <vscale x 4 x i16> @intrinsic_vasub_mask_vx_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vasub_mask_vx_nxv4i16_nxv4i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
-; CHECK-NEXT: vasub.vx v8, v9, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i16> @llvm.riscv.vasub.mask.nxv4i16.i16(
- <vscale x 4 x i16> %0,
- <vscale x 4 x i16> %1,
- i16 %2,
- <vscale x 4 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 4 x i16> %a
-}
-
-declare <vscale x 8 x i16> @llvm.riscv.vasub.nxv8i16.i16(
- <vscale x 8 x i16>,
- <vscale x 8 x i16>,
- i16,
- i64);
-
-define <vscale x 8 x i16> @intrinsic_vasub_vx_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, i16 %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vasub_vx_nxv8i16_nxv8i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
-; CHECK-NEXT: vasub.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i16> @llvm.riscv.vasub.nxv8i16.i16(
- <vscale x 8 x i16> undef,
- <vscale x 8 x i16> %0,
- i16 %1,
- i64 %2)
-
- ret <vscale x 8 x i16> %a
-}
-
-declare <vscale x 8 x i16> @llvm.riscv.vasub.mask.nxv8i16.i16(
- <vscale x 8 x i16>,
- <vscale x 8 x i16>,
- i16,
- <vscale x 8 x i1>,
- i64,
- i64);
-
-define <vscale x 8 x i16> @intrinsic_vasub_mask_vx_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vasub_mask_vx_nxv8i16_nxv8i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
-; CHECK-NEXT: vasub.vx v8, v10, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i16> @llvm.riscv.vasub.mask.nxv8i16.i16(
- <vscale x 8 x i16> %0,
- <vscale x 8 x i16> %1,
- i16 %2,
- <vscale x 8 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 8 x i16> %a
-}
-
-declare <vscale x 16 x i16> @llvm.riscv.vasub.nxv16i16.i16(
- <vscale x 16 x i16>,
- <vscale x 16 x i16>,
- i16,
- i64);
-
-define <vscale x 16 x i16> @intrinsic_vasub_vx_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, i16 %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vasub_vx_nxv16i16_nxv16i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
-; CHECK-NEXT: vasub.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i16> @llvm.riscv.vasub.nxv16i16.i16(
- <vscale x 16 x i16> undef,
- <vscale x 16 x i16> %0,
- i16 %1,
- i64 %2)
-
- ret <vscale x 16 x i16> %a
-}
-
-declare <vscale x 16 x i16> @llvm.riscv.vasub.mask.nxv16i16.i16(
- <vscale x 16 x i16>,
- <vscale x 16 x i16>,
- i16,
- <vscale x 16 x i1>,
- i64,
- i64);
-
-define <vscale x 16 x i16> @intrinsic_vasub_mask_vx_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vasub_mask_vx_nxv16i16_nxv16i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
-; CHECK-NEXT: vasub.vx v8, v12, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i16> @llvm.riscv.vasub.mask.nxv16i16.i16(
- <vscale x 16 x i16> %0,
- <vscale x 16 x i16> %1,
- i16 %2,
- <vscale x 16 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 16 x i16> %a
-}
-
-declare <vscale x 32 x i16> @llvm.riscv.vasub.nxv32i16.i16(
- <vscale x 32 x i16>,
- <vscale x 32 x i16>,
- i16,
- i64);
-
-define <vscale x 32 x i16> @intrinsic_vasub_vx_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, i16 %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vasub_vx_nxv32i16_nxv32i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu
-; CHECK-NEXT: vasub.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 32 x i16> @llvm.riscv.vasub.nxv32i16.i16(
- <vscale x 32 x i16> undef,
- <vscale x 32 x i16> %0,
- i16 %1,
- i64 %2)
-
- ret <vscale x 32 x i16> %a
-}
-
-declare <vscale x 32 x i16> @llvm.riscv.vasub.mask.nxv32i16.i16(
- <vscale x 32 x i16>,
- <vscale x 32 x i16>,
- i16,
- <vscale x 32 x i1>,
- i64,
- i64);
-
-define <vscale x 32 x i16> @intrinsic_vasub_mask_vx_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, i16 %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vasub_mask_vx_nxv32i16_nxv32i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu
-; CHECK-NEXT: vasub.vx v8, v16, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 32 x i16> @llvm.riscv.vasub.mask.nxv32i16.i16(
- <vscale x 32 x i16> %0,
- <vscale x 32 x i16> %1,
- i16 %2,
- <vscale x 32 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 32 x i16> %a
-}
-
-declare <vscale x 1 x i32> @llvm.riscv.vasub.nxv1i32.i32(
- <vscale x 1 x i32>,
- <vscale x 1 x i32>,
- i32,
- i64);
-
-define <vscale x 1 x i32> @intrinsic_vasub_vx_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, i32 %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vasub_vx_nxv1i32_nxv1i32_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
-; CHECK-NEXT: vasub.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i32> @llvm.riscv.vasub.nxv1i32.i32(
- <vscale x 1 x i32> undef,
- <vscale x 1 x i32> %0,
- i32 %1,
- i64 %2)
-
- ret <vscale x 1 x i32> %a
-}
-
-declare <vscale x 1 x i32> @llvm.riscv.vasub.mask.nxv1i32.i32(
- <vscale x 1 x i32>,
- <vscale x 1 x i32>,
- i32,
- <vscale x 1 x i1>,
- i64,
- i64);
-
-define <vscale x 1 x i32> @intrinsic_vasub_mask_vx_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vasub_mask_vx_nxv1i32_nxv1i32_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
-; CHECK-NEXT: vasub.vx v8, v9, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i32> @llvm.riscv.vasub.mask.nxv1i32.i32(
- <vscale x 1 x i32> %0,
- <vscale x 1 x i32> %1,
- i32 %2,
- <vscale x 1 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 1 x i32> %a
-}
-
-declare <vscale x 2 x i32> @llvm.riscv.vasub.nxv2i32.i32(
- <vscale x 2 x i32>,
- <vscale x 2 x i32>,
- i32,
- i64);
-
-define <vscale x 2 x i32> @intrinsic_vasub_vx_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, i32 %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vasub_vx_nxv2i32_nxv2i32_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
-; CHECK-NEXT: vasub.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i32> @llvm.riscv.vasub.nxv2i32.i32(
- <vscale x 2 x i32> undef,
- <vscale x 2 x i32> %0,
- i32 %1,
- i64 %2)
-
- ret <vscale x 2 x i32> %a
-}
-
-declare <vscale x 2 x i32> @llvm.riscv.vasub.mask.nxv2i32.i32(
- <vscale x 2 x i32>,
- <vscale x 2 x i32>,
- i32,
- <vscale x 2 x i1>,
- i64,
- i64);
-
-define <vscale x 2 x i32> @intrinsic_vasub_mask_vx_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vasub_mask_vx_nxv2i32_nxv2i32_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
-; CHECK-NEXT: vasub.vx v8, v9, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i32> @llvm.riscv.vasub.mask.nxv2i32.i32(
- <vscale x 2 x i32> %0,
- <vscale x 2 x i32> %1,
- i32 %2,
- <vscale x 2 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 2 x i32> %a
-}
-
-declare <vscale x 4 x i32> @llvm.riscv.vasub.nxv4i32.i32(
- <vscale x 4 x i32>,
- <vscale x 4 x i32>,
- i32,
- i64);
-
-define <vscale x 4 x i32> @intrinsic_vasub_vx_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, i32 %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vasub_vx_nxv4i32_nxv4i32_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; CHECK-NEXT: vasub.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i32> @llvm.riscv.vasub.nxv4i32.i32(
- <vscale x 4 x i32> undef,
- <vscale x 4 x i32> %0,
- i32 %1,
- i64 %2)
-
- ret <vscale x 4 x i32> %a
-}
-
-declare <vscale x 4 x i32> @llvm.riscv.vasub.mask.nxv4i32.i32(
- <vscale x 4 x i32>,
- <vscale x 4 x i32>,
- i32,
- <vscale x 4 x i1>,
- i64,
- i64);
-
-define <vscale x 4 x i32> @intrinsic_vasub_mask_vx_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vasub_mask_vx_nxv4i32_nxv4i32_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; CHECK-NEXT: vasub.vx v8, v10, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i32> @llvm.riscv.vasub.mask.nxv4i32.i32(
- <vscale x 4 x i32> %0,
- <vscale x 4 x i32> %1,
- i32 %2,
- <vscale x 4 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 4 x i32> %a
-}
-
-declare <vscale x 8 x i32> @llvm.riscv.vasub.nxv8i32.i32(
- <vscale x 8 x i32>,
- <vscale x 8 x i32>,
- i32,
- i64);
-
-define <vscale x 8 x i32> @intrinsic_vasub_vx_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, i32 %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vasub_vx_nxv8i32_nxv8i32_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
-; CHECK-NEXT: vasub.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i32> @llvm.riscv.vasub.nxv8i32.i32(
- <vscale x 8 x i32> undef,
- <vscale x 8 x i32> %0,
- i32 %1,
- i64 %2)
-
- ret <vscale x 8 x i32> %a
-}
-
-declare <vscale x 8 x i32> @llvm.riscv.vasub.mask.nxv8i32.i32(
- <vscale x 8 x i32>,
- <vscale x 8 x i32>,
- i32,
- <vscale x 8 x i1>,
- i64,
- i64);
-
-define <vscale x 8 x i32> @intrinsic_vasub_mask_vx_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vasub_mask_vx_nxv8i32_nxv8i32_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
-; CHECK-NEXT: vasub.vx v8, v12, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i32> @llvm.riscv.vasub.mask.nxv8i32.i32(
- <vscale x 8 x i32> %0,
- <vscale x 8 x i32> %1,
- i32 %2,
- <vscale x 8 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 8 x i32> %a
-}
-
-declare <vscale x 16 x i32> @llvm.riscv.vasub.nxv16i32.i32(
- <vscale x 16 x i32>,
- <vscale x 16 x i32>,
- i32,
- i64);
-
-define <vscale x 16 x i32> @intrinsic_vasub_vx_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, i32 %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vasub_vx_nxv16i32_nxv16i32_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu
-; CHECK-NEXT: vasub.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i32> @llvm.riscv.vasub.nxv16i32.i32(
- <vscale x 16 x i32> undef,
- <vscale x 16 x i32> %0,
- i32 %1,
- i64 %2)
-
- ret <vscale x 16 x i32> %a
-}
-
-declare <vscale x 16 x i32> @llvm.riscv.vasub.mask.nxv16i32.i32(
- <vscale x 16 x i32>,
- <vscale x 16 x i32>,
- i32,
- <vscale x 16 x i1>,
- i64,
- i64);
-
-define <vscale x 16 x i32> @intrinsic_vasub_mask_vx_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vasub_mask_vx_nxv16i32_nxv16i32_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu
-; CHECK-NEXT: vasub.vx v8, v16, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i32> @llvm.riscv.vasub.mask.nxv16i32.i32(
- <vscale x 16 x i32> %0,
- <vscale x 16 x i32> %1,
- i32 %2,
- <vscale x 16 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 16 x i32> %a
-}
-
-declare <vscale x 1 x i64> @llvm.riscv.vasub.nxv1i64.i64(
- <vscale x 1 x i64>,
- <vscale x 1 x i64>,
- i64,
- i64);
-
-define <vscale x 1 x i64> @intrinsic_vasub_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vasub_vx_nxv1i64_nxv1i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
-; CHECK-NEXT: vasub.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i64> @llvm.riscv.vasub.nxv1i64.i64(
- <vscale x 1 x i64> undef,
- <vscale x 1 x i64> %0,
- i64 %1,
- i64 %2)
-
- ret <vscale x 1 x i64> %a
-}
-
-declare <vscale x 1 x i64> @llvm.riscv.vasub.mask.nxv1i64.i64(
- <vscale x 1 x i64>,
- <vscale x 1 x i64>,
- i64,
- <vscale x 1 x i1>,
- i64,
- i64);
-
-define <vscale x 1 x i64> @intrinsic_vasub_mask_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vasub_mask_vx_nxv1i64_nxv1i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
-; CHECK-NEXT: vasub.vx v8, v9, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i64> @llvm.riscv.vasub.mask.nxv1i64.i64(
- <vscale x 1 x i64> %0,
- <vscale x 1 x i64> %1,
- i64 %2,
- <vscale x 1 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 1 x i64> %a
-}
-
-declare <vscale x 2 x i64> @llvm.riscv.vasub.nxv2i64.i64(
- <vscale x 2 x i64>,
- <vscale x 2 x i64>,
- i64,
- i64);
-
-define <vscale x 2 x i64> @intrinsic_vasub_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vasub_vx_nxv2i64_nxv2i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
-; CHECK-NEXT: vasub.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i64> @llvm.riscv.vasub.nxv2i64.i64(
- <vscale x 2 x i64> undef,
- <vscale x 2 x i64> %0,
- i64 %1,
- i64 %2)
-
- ret <vscale x 2 x i64> %a
-}
-
-declare <vscale x 2 x i64> @llvm.riscv.vasub.mask.nxv2i64.i64(
- <vscale x 2 x i64>,
- <vscale x 2 x i64>,
- i64,
- <vscale x 2 x i1>,
- i64,
- i64);
-
-define <vscale x 2 x i64> @intrinsic_vasub_mask_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vasub_mask_vx_nxv2i64_nxv2i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
-; CHECK-NEXT: vasub.vx v8, v10, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i64> @llvm.riscv.vasub.mask.nxv2i64.i64(
- <vscale x 2 x i64> %0,
- <vscale x 2 x i64> %1,
- i64 %2,
- <vscale x 2 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 2 x i64> %a
-}
-
-declare <vscale x 4 x i64> @llvm.riscv.vasub.nxv4i64.i64(
- <vscale x 4 x i64>,
- <vscale x 4 x i64>,
- i64,
- i64);
-
-define <vscale x 4 x i64> @intrinsic_vasub_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vasub_vx_nxv4i64_nxv4i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
-; CHECK-NEXT: vasub.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i64> @llvm.riscv.vasub.nxv4i64.i64(
- <vscale x 4 x i64> undef,
- <vscale x 4 x i64> %0,
- i64 %1,
- i64 %2)
-
- ret <vscale x 4 x i64> %a
-}
-
-declare <vscale x 4 x i64> @llvm.riscv.vasub.mask.nxv4i64.i64(
- <vscale x 4 x i64>,
- <vscale x 4 x i64>,
- i64,
- <vscale x 4 x i1>,
- i64,
- i64);
-
-define <vscale x 4 x i64> @intrinsic_vasub_mask_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vasub_mask_vx_nxv4i64_nxv4i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
-; CHECK-NEXT: vasub.vx v8, v12, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i64> @llvm.riscv.vasub.mask.nxv4i64.i64(
- <vscale x 4 x i64> %0,
- <vscale x 4 x i64> %1,
- i64 %2,
- <vscale x 4 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 4 x i64> %a
-}
-
-declare <vscale x 8 x i64> @llvm.riscv.vasub.nxv8i64.i64(
- <vscale x 8 x i64>,
- <vscale x 8 x i64>,
- i64,
- i64);
-
-define <vscale x 8 x i64> @intrinsic_vasub_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, i64 %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vasub_vx_nxv8i64_nxv8i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu
-; CHECK-NEXT: vasub.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i64> @llvm.riscv.vasub.nxv8i64.i64(
- <vscale x 8 x i64> undef,
- <vscale x 8 x i64> %0,
- i64 %1,
- i64 %2)
-
- ret <vscale x 8 x i64> %a
-}
-
-declare <vscale x 8 x i64> @llvm.riscv.vasub.mask.nxv8i64.i64(
- <vscale x 8 x i64>,
- <vscale x 8 x i64>,
- i64,
- <vscale x 8 x i1>,
- i64,
- i64);
-
-define <vscale x 8 x i64> @intrinsic_vasub_mask_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vasub_mask_vx_nxv8i64_nxv8i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu
-; CHECK-NEXT: vasub.vx v8, v16, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i64> @llvm.riscv.vasub.mask.nxv8i64.i64(
- <vscale x 8 x i64> %0,
- <vscale x 8 x i64> %1,
- i64 %2,
- <vscale x 8 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 8 x i64> %a
-}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vasub-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vasub.ll
similarity index 80%
rename from llvm/test/CodeGen/RISCV/rvv/vasub-rv32.ll
rename to llvm/test/CodeGen/RISCV/rvv/vasub.ll
index fb1f8927d85b4..36a3780384e3a 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vasub-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vasub.ll
@@ -1,13 +1,15 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs \
-; RUN: < %s | FileCheck %s
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v \
+; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,RV32
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v \
+; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,RV64
declare <vscale x 1 x i8> @llvm.riscv.vasub.nxv1i8.nxv1i8(
<vscale x 1 x i8>,
<vscale x 1 x i8>,
<vscale x 1 x i8>,
- i32);
+ iXLen);
-define <vscale x 1 x i8> @intrinsic_vasub_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i32 %2) nounwind {
+define <vscale x 1 x i8> @intrinsic_vasub_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vasub_vv_nxv1i8_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
@@ -18,7 +20,7 @@ entry:
<vscale x 1 x i8> undef,
<vscale x 1 x i8> %0,
<vscale x 1 x i8> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 1 x i8> %a
}
@@ -28,10 +30,9 @@ declare <vscale x 1 x i8> @llvm.riscv.vasub.mask.nxv1i8.nxv1i8(
<vscale x 1 x i8>,
<vscale x 1 x i8>,
<vscale x 1 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 1 x i8> @intrinsic_vasub_mask_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+define <vscale x 1 x i8> @intrinsic_vasub_mask_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv1i8_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
@@ -43,7 +44,7 @@ entry:
<vscale x 1 x i8> %1,
<vscale x 1 x i8> %2,
<vscale x 1 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 1 x i8> %a
}
@@ -52,9 +53,9 @@ declare <vscale x 2 x i8> @llvm.riscv.vasub.nxv2i8.nxv2i8(
<vscale x 2 x i8>,
<vscale x 2 x i8>,
<vscale x 2 x i8>,
- i32);
+ iXLen);
-define <vscale x 2 x i8> @intrinsic_vasub_vv_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i32 %2) nounwind {
+define <vscale x 2 x i8> @intrinsic_vasub_vv_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vasub_vv_nxv2i8_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
@@ -65,7 +66,7 @@ entry:
<vscale x 2 x i8> undef,
<vscale x 2 x i8> %0,
<vscale x 2 x i8> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 2 x i8> %a
}
@@ -75,10 +76,9 @@ declare <vscale x 2 x i8> @llvm.riscv.vasub.mask.nxv2i8.nxv2i8(
<vscale x 2 x i8>,
<vscale x 2 x i8>,
<vscale x 2 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 2 x i8> @intrinsic_vasub_mask_vv_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+define <vscale x 2 x i8> @intrinsic_vasub_mask_vv_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv2i8_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
@@ -90,7 +90,7 @@ entry:
<vscale x 2 x i8> %1,
<vscale x 2 x i8> %2,
<vscale x 2 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 2 x i8> %a
}
@@ -99,9 +99,9 @@ declare <vscale x 4 x i8> @llvm.riscv.vasub.nxv4i8.nxv4i8(
<vscale x 4 x i8>,
<vscale x 4 x i8>,
<vscale x 4 x i8>,
- i32);
+ iXLen);
-define <vscale x 4 x i8> @intrinsic_vasub_vv_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i32 %2) nounwind {
+define <vscale x 4 x i8> @intrinsic_vasub_vv_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vasub_vv_nxv4i8_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
@@ -112,7 +112,7 @@ entry:
<vscale x 4 x i8> undef,
<vscale x 4 x i8> %0,
<vscale x 4 x i8> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 4 x i8> %a
}
@@ -122,10 +122,9 @@ declare <vscale x 4 x i8> @llvm.riscv.vasub.mask.nxv4i8.nxv4i8(
<vscale x 4 x i8>,
<vscale x 4 x i8>,
<vscale x 4 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 4 x i8> @intrinsic_vasub_mask_vv_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+define <vscale x 4 x i8> @intrinsic_vasub_mask_vv_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv4i8_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
@@ -137,7 +136,7 @@ entry:
<vscale x 4 x i8> %1,
<vscale x 4 x i8> %2,
<vscale x 4 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 4 x i8> %a
}
@@ -146,9 +145,9 @@ declare <vscale x 8 x i8> @llvm.riscv.vasub.nxv8i8.nxv8i8(
<vscale x 8 x i8>,
<vscale x 8 x i8>,
<vscale x 8 x i8>,
- i32);
+ iXLen);
-define <vscale x 8 x i8> @intrinsic_vasub_vv_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i32 %2) nounwind {
+define <vscale x 8 x i8> @intrinsic_vasub_vv_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vasub_vv_nxv8i8_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
@@ -159,7 +158,7 @@ entry:
<vscale x 8 x i8> undef,
<vscale x 8 x i8> %0,
<vscale x 8 x i8> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 8 x i8> %a
}
@@ -169,10 +168,9 @@ declare <vscale x 8 x i8> @llvm.riscv.vasub.mask.nxv8i8.nxv8i8(
<vscale x 8 x i8>,
<vscale x 8 x i8>,
<vscale x 8 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 8 x i8> @intrinsic_vasub_mask_vv_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+define <vscale x 8 x i8> @intrinsic_vasub_mask_vv_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv8i8_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
@@ -184,7 +182,7 @@ entry:
<vscale x 8 x i8> %1,
<vscale x 8 x i8> %2,
<vscale x 8 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 8 x i8> %a
}
@@ -193,9 +191,9 @@ declare <vscale x 16 x i8> @llvm.riscv.vasub.nxv16i8.nxv16i8(
<vscale x 16 x i8>,
<vscale x 16 x i8>,
<vscale x 16 x i8>,
- i32);
+ iXLen);
-define <vscale x 16 x i8> @intrinsic_vasub_vv_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i32 %2) nounwind {
+define <vscale x 16 x i8> @intrinsic_vasub_vv_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vasub_vv_nxv16i8_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
@@ -206,7 +204,7 @@ entry:
<vscale x 16 x i8> undef,
<vscale x 16 x i8> %0,
<vscale x 16 x i8> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 16 x i8> %a
}
@@ -216,10 +214,9 @@ declare <vscale x 16 x i8> @llvm.riscv.vasub.mask.nxv16i8.nxv16i8(
<vscale x 16 x i8>,
<vscale x 16 x i8>,
<vscale x 16 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 16 x i8> @intrinsic_vasub_mask_vv_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+define <vscale x 16 x i8> @intrinsic_vasub_mask_vv_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv16i8_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
@@ -231,7 +228,7 @@ entry:
<vscale x 16 x i8> %1,
<vscale x 16 x i8> %2,
<vscale x 16 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 16 x i8> %a
}
@@ -240,9 +237,9 @@ declare <vscale x 32 x i8> @llvm.riscv.vasub.nxv32i8.nxv32i8(
<vscale x 32 x i8>,
<vscale x 32 x i8>,
<vscale x 32 x i8>,
- i32);
+ iXLen);
-define <vscale x 32 x i8> @intrinsic_vasub_vv_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i32 %2) nounwind {
+define <vscale x 32 x i8> @intrinsic_vasub_vv_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vasub_vv_nxv32i8_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
@@ -253,7 +250,7 @@ entry:
<vscale x 32 x i8> undef,
<vscale x 32 x i8> %0,
<vscale x 32 x i8> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 32 x i8> %a
}
@@ -263,10 +260,9 @@ declare <vscale x 32 x i8> @llvm.riscv.vasub.mask.nxv32i8.nxv32i8(
<vscale x 32 x i8>,
<vscale x 32 x i8>,
<vscale x 32 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 32 x i8> @intrinsic_vasub_mask_vv_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
+define <vscale x 32 x i8> @intrinsic_vasub_mask_vv_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv32i8_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
@@ -278,7 +274,7 @@ entry:
<vscale x 32 x i8> %1,
<vscale x 32 x i8> %2,
<vscale x 32 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 32 x i8> %a
}
@@ -287,9 +283,9 @@ declare <vscale x 64 x i8> @llvm.riscv.vasub.nxv64i8.nxv64i8(
<vscale x 64 x i8>,
<vscale x 64 x i8>,
<vscale x 64 x i8>,
- i32);
+ iXLen);
-define <vscale x 64 x i8> @intrinsic_vasub_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i32 %2) nounwind {
+define <vscale x 64 x i8> @intrinsic_vasub_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vasub_vv_nxv64i8_nxv64i8_nxv64i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, mu
@@ -300,7 +296,7 @@ entry:
<vscale x 64 x i8> undef,
<vscale x 64 x i8> %0,
<vscale x 64 x i8> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 64 x i8> %a
}
@@ -310,10 +306,9 @@ declare <vscale x 64 x i8> @llvm.riscv.vasub.mask.nxv64i8.nxv64i8(
<vscale x 64 x i8>,
<vscale x 64 x i8>,
<vscale x 64 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 64 x i8> @intrinsic_vasub_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, i32 %4) nounwind {
+define <vscale x 64 x i8> @intrinsic_vasub_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv64i8_nxv64i8_nxv64i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vl8r.v v24, (a0)
@@ -326,7 +321,7 @@ entry:
<vscale x 64 x i8> %1,
<vscale x 64 x i8> %2,
<vscale x 64 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 64 x i8> %a
}
@@ -335,9 +330,9 @@ declare <vscale x 1 x i16> @llvm.riscv.vasub.nxv1i16.nxv1i16(
<vscale x 1 x i16>,
<vscale x 1 x i16>,
<vscale x 1 x i16>,
- i32);
+ iXLen);
-define <vscale x 1 x i16> @intrinsic_vasub_vv_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i32 %2) nounwind {
+define <vscale x 1 x i16> @intrinsic_vasub_vv_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vasub_vv_nxv1i16_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
@@ -348,7 +343,7 @@ entry:
<vscale x 1 x i16> undef,
<vscale x 1 x i16> %0,
<vscale x 1 x i16> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 1 x i16> %a
}
@@ -358,10 +353,9 @@ declare <vscale x 1 x i16> @llvm.riscv.vasub.mask.nxv1i16.nxv1i16(
<vscale x 1 x i16>,
<vscale x 1 x i16>,
<vscale x 1 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 1 x i16> @intrinsic_vasub_mask_vv_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+define <vscale x 1 x i16> @intrinsic_vasub_mask_vv_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv1i16_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
@@ -373,7 +367,7 @@ entry:
<vscale x 1 x i16> %1,
<vscale x 1 x i16> %2,
<vscale x 1 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 1 x i16> %a
}
@@ -382,9 +376,9 @@ declare <vscale x 2 x i16> @llvm.riscv.vasub.nxv2i16.nxv2i16(
<vscale x 2 x i16>,
<vscale x 2 x i16>,
<vscale x 2 x i16>,
- i32);
+ iXLen);
-define <vscale x 2 x i16> @intrinsic_vasub_vv_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i32 %2) nounwind {
+define <vscale x 2 x i16> @intrinsic_vasub_vv_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vasub_vv_nxv2i16_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
@@ -395,7 +389,7 @@ entry:
<vscale x 2 x i16> undef,
<vscale x 2 x i16> %0,
<vscale x 2 x i16> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 2 x i16> %a
}
@@ -405,10 +399,9 @@ declare <vscale x 2 x i16> @llvm.riscv.vasub.mask.nxv2i16.nxv2i16(
<vscale x 2 x i16>,
<vscale x 2 x i16>,
<vscale x 2 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 2 x i16> @intrinsic_vasub_mask_vv_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+define <vscale x 2 x i16> @intrinsic_vasub_mask_vv_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv2i16_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
@@ -420,7 +413,7 @@ entry:
<vscale x 2 x i16> %1,
<vscale x 2 x i16> %2,
<vscale x 2 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 2 x i16> %a
}
@@ -429,9 +422,9 @@ declare <vscale x 4 x i16> @llvm.riscv.vasub.nxv4i16.nxv4i16(
<vscale x 4 x i16>,
<vscale x 4 x i16>,
<vscale x 4 x i16>,
- i32);
+ iXLen);
-define <vscale x 4 x i16> @intrinsic_vasub_vv_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i32 %2) nounwind {
+define <vscale x 4 x i16> @intrinsic_vasub_vv_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vasub_vv_nxv4i16_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
@@ -442,7 +435,7 @@ entry:
<vscale x 4 x i16> undef,
<vscale x 4 x i16> %0,
<vscale x 4 x i16> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 4 x i16> %a
}
@@ -452,10 +445,9 @@ declare <vscale x 4 x i16> @llvm.riscv.vasub.mask.nxv4i16.nxv4i16(
<vscale x 4 x i16>,
<vscale x 4 x i16>,
<vscale x 4 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 4 x i16> @intrinsic_vasub_mask_vv_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+define <vscale x 4 x i16> @intrinsic_vasub_mask_vv_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv4i16_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
@@ -467,7 +459,7 @@ entry:
<vscale x 4 x i16> %1,
<vscale x 4 x i16> %2,
<vscale x 4 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 4 x i16> %a
}
@@ -476,9 +468,9 @@ declare <vscale x 8 x i16> @llvm.riscv.vasub.nxv8i16.nxv8i16(
<vscale x 8 x i16>,
<vscale x 8 x i16>,
<vscale x 8 x i16>,
- i32);
+ iXLen);
-define <vscale x 8 x i16> @intrinsic_vasub_vv_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i32 %2) nounwind {
+define <vscale x 8 x i16> @intrinsic_vasub_vv_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vasub_vv_nxv8i16_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
@@ -489,7 +481,7 @@ entry:
<vscale x 8 x i16> undef,
<vscale x 8 x i16> %0,
<vscale x 8 x i16> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 8 x i16> %a
}
@@ -499,10 +491,9 @@ declare <vscale x 8 x i16> @llvm.riscv.vasub.mask.nxv8i16.nxv8i16(
<vscale x 8 x i16>,
<vscale x 8 x i16>,
<vscale x 8 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 8 x i16> @intrinsic_vasub_mask_vv_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+define <vscale x 8 x i16> @intrinsic_vasub_mask_vv_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv8i16_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
@@ -514,7 +505,7 @@ entry:
<vscale x 8 x i16> %1,
<vscale x 8 x i16> %2,
<vscale x 8 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 8 x i16> %a
}
@@ -523,9 +514,9 @@ declare <vscale x 16 x i16> @llvm.riscv.vasub.nxv16i16.nxv16i16(
<vscale x 16 x i16>,
<vscale x 16 x i16>,
<vscale x 16 x i16>,
- i32);
+ iXLen);
-define <vscale x 16 x i16> @intrinsic_vasub_vv_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i32 %2) nounwind {
+define <vscale x 16 x i16> @intrinsic_vasub_vv_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vasub_vv_nxv16i16_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
@@ -536,7 +527,7 @@ entry:
<vscale x 16 x i16> undef,
<vscale x 16 x i16> %0,
<vscale x 16 x i16> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 16 x i16> %a
}
@@ -546,10 +537,9 @@ declare <vscale x 16 x i16> @llvm.riscv.vasub.mask.nxv16i16.nxv16i16(
<vscale x 16 x i16>,
<vscale x 16 x i16>,
<vscale x 16 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 16 x i16> @intrinsic_vasub_mask_vv_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+define <vscale x 16 x i16> @intrinsic_vasub_mask_vv_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv16i16_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
@@ -561,7 +551,7 @@ entry:
<vscale x 16 x i16> %1,
<vscale x 16 x i16> %2,
<vscale x 16 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 16 x i16> %a
}
@@ -570,9 +560,9 @@ declare <vscale x 32 x i16> @llvm.riscv.vasub.nxv32i16.nxv32i16(
<vscale x 32 x i16>,
<vscale x 32 x i16>,
<vscale x 32 x i16>,
- i32);
+ iXLen);
-define <vscale x 32 x i16> @intrinsic_vasub_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, i32 %2) nounwind {
+define <vscale x 32 x i16> @intrinsic_vasub_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vasub_vv_nxv32i16_nxv32i16_nxv32i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, mu
@@ -583,7 +573,7 @@ entry:
<vscale x 32 x i16> undef,
<vscale x 32 x i16> %0,
<vscale x 32 x i16> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 32 x i16> %a
}
@@ -593,10 +583,9 @@ declare <vscale x 32 x i16> @llvm.riscv.vasub.mask.nxv32i16.nxv32i16(
<vscale x 32 x i16>,
<vscale x 32 x i16>,
<vscale x 32 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 32 x i16> @intrinsic_vasub_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
+define <vscale x 32 x i16> @intrinsic_vasub_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv32i16_nxv32i16_nxv32i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vl8re16.v v24, (a0)
@@ -609,7 +598,7 @@ entry:
<vscale x 32 x i16> %1,
<vscale x 32 x i16> %2,
<vscale x 32 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 32 x i16> %a
}
@@ -618,9 +607,9 @@ declare <vscale x 1 x i32> @llvm.riscv.vasub.nxv1i32.nxv1i32(
<vscale x 1 x i32>,
<vscale x 1 x i32>,
<vscale x 1 x i32>,
- i32);
+ iXLen);
-define <vscale x 1 x i32> @intrinsic_vasub_vv_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2) nounwind {
+define <vscale x 1 x i32> @intrinsic_vasub_vv_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vasub_vv_nxv1i32_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
@@ -631,7 +620,7 @@ entry:
<vscale x 1 x i32> undef,
<vscale x 1 x i32> %0,
<vscale x 1 x i32> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 1 x i32> %a
}
@@ -641,10 +630,9 @@ declare <vscale x 1 x i32> @llvm.riscv.vasub.mask.nxv1i32.nxv1i32(
<vscale x 1 x i32>,
<vscale x 1 x i32>,
<vscale x 1 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 1 x i32> @intrinsic_vasub_mask_vv_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+define <vscale x 1 x i32> @intrinsic_vasub_mask_vv_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv1i32_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
@@ -656,7 +644,7 @@ entry:
<vscale x 1 x i32> %1,
<vscale x 1 x i32> %2,
<vscale x 1 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 1 x i32> %a
}
@@ -665,9 +653,9 @@ declare <vscale x 2 x i32> @llvm.riscv.vasub.nxv2i32.nxv2i32(
<vscale x 2 x i32>,
<vscale x 2 x i32>,
<vscale x 2 x i32>,
- i32);
+ iXLen);
-define <vscale x 2 x i32> @intrinsic_vasub_vv_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2) nounwind {
+define <vscale x 2 x i32> @intrinsic_vasub_vv_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vasub_vv_nxv2i32_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
@@ -678,7 +666,7 @@ entry:
<vscale x 2 x i32> undef,
<vscale x 2 x i32> %0,
<vscale x 2 x i32> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 2 x i32> %a
}
@@ -688,10 +676,9 @@ declare <vscale x 2 x i32> @llvm.riscv.vasub.mask.nxv2i32.nxv2i32(
<vscale x 2 x i32>,
<vscale x 2 x i32>,
<vscale x 2 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 2 x i32> @intrinsic_vasub_mask_vv_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+define <vscale x 2 x i32> @intrinsic_vasub_mask_vv_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv2i32_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
@@ -703,7 +690,7 @@ entry:
<vscale x 2 x i32> %1,
<vscale x 2 x i32> %2,
<vscale x 2 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 2 x i32> %a
}
@@ -712,9 +699,9 @@ declare <vscale x 4 x i32> @llvm.riscv.vasub.nxv4i32.nxv4i32(
<vscale x 4 x i32>,
<vscale x 4 x i32>,
<vscale x 4 x i32>,
- i32);
+ iXLen);
-define <vscale x 4 x i32> @intrinsic_vasub_vv_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2) nounwind {
+define <vscale x 4 x i32> @intrinsic_vasub_vv_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vasub_vv_nxv4i32_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
@@ -725,7 +712,7 @@ entry:
<vscale x 4 x i32> undef,
<vscale x 4 x i32> %0,
<vscale x 4 x i32> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 4 x i32> %a
}
@@ -735,10 +722,9 @@ declare <vscale x 4 x i32> @llvm.riscv.vasub.mask.nxv4i32.nxv4i32(
<vscale x 4 x i32>,
<vscale x 4 x i32>,
<vscale x 4 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 4 x i32> @intrinsic_vasub_mask_vv_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+define <vscale x 4 x i32> @intrinsic_vasub_mask_vv_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv4i32_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
@@ -750,7 +736,7 @@ entry:
<vscale x 4 x i32> %1,
<vscale x 4 x i32> %2,
<vscale x 4 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 4 x i32> %a
}
@@ -759,9 +745,9 @@ declare <vscale x 8 x i32> @llvm.riscv.vasub.nxv8i32.nxv8i32(
<vscale x 8 x i32>,
<vscale x 8 x i32>,
<vscale x 8 x i32>,
- i32);
+ iXLen);
-define <vscale x 8 x i32> @intrinsic_vasub_vv_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2) nounwind {
+define <vscale x 8 x i32> @intrinsic_vasub_vv_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vasub_vv_nxv8i32_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
@@ -772,7 +758,7 @@ entry:
<vscale x 8 x i32> undef,
<vscale x 8 x i32> %0,
<vscale x 8 x i32> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 8 x i32> %a
}
@@ -782,10 +768,9 @@ declare <vscale x 8 x i32> @llvm.riscv.vasub.mask.nxv8i32.nxv8i32(
<vscale x 8 x i32>,
<vscale x 8 x i32>,
<vscale x 8 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 8 x i32> @intrinsic_vasub_mask_vv_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+define <vscale x 8 x i32> @intrinsic_vasub_mask_vv_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv8i32_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
@@ -797,7 +782,7 @@ entry:
<vscale x 8 x i32> %1,
<vscale x 8 x i32> %2,
<vscale x 8 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 8 x i32> %a
}
@@ -806,9 +791,9 @@ declare <vscale x 16 x i32> @llvm.riscv.vasub.nxv16i32.nxv16i32(
<vscale x 16 x i32>,
<vscale x 16 x i32>,
<vscale x 16 x i32>,
- i32);
+ iXLen);
-define <vscale x 16 x i32> @intrinsic_vasub_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2) nounwind {
+define <vscale x 16 x i32> @intrinsic_vasub_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vasub_vv_nxv16i32_nxv16i32_nxv16i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu
@@ -819,7 +804,7 @@ entry:
<vscale x 16 x i32> undef,
<vscale x 16 x i32> %0,
<vscale x 16 x i32> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 16 x i32> %a
}
@@ -829,10 +814,9 @@ declare <vscale x 16 x i32> @llvm.riscv.vasub.mask.nxv16i32.nxv16i32(
<vscale x 16 x i32>,
<vscale x 16 x i32>,
<vscale x 16 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 16 x i32> @intrinsic_vasub_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+define <vscale x 16 x i32> @intrinsic_vasub_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv16i32_nxv16i32_nxv16i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vl8re32.v v24, (a0)
@@ -845,7 +829,7 @@ entry:
<vscale x 16 x i32> %1,
<vscale x 16 x i32> %2,
<vscale x 16 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 16 x i32> %a
}
@@ -854,9 +838,9 @@ declare <vscale x 1 x i64> @llvm.riscv.vasub.nxv1i64.nxv1i64(
<vscale x 1 x i64>,
<vscale x 1 x i64>,
<vscale x 1 x i64>,
- i32);
+ iXLen);
-define <vscale x 1 x i64> @intrinsic_vasub_vv_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i32 %2) nounwind {
+define <vscale x 1 x i64> @intrinsic_vasub_vv_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vasub_vv_nxv1i64_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
@@ -867,7 +851,7 @@ entry:
<vscale x 1 x i64> undef,
<vscale x 1 x i64> %0,
<vscale x 1 x i64> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 1 x i64> %a
}
@@ -877,10 +861,9 @@ declare <vscale x 1 x i64> @llvm.riscv.vasub.mask.nxv1i64.nxv1i64(
<vscale x 1 x i64>,
<vscale x 1 x i64>,
<vscale x 1 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 1 x i64> @intrinsic_vasub_mask_vv_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+define <vscale x 1 x i64> @intrinsic_vasub_mask_vv_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv1i64_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
@@ -892,7 +875,7 @@ entry:
<vscale x 1 x i64> %1,
<vscale x 1 x i64> %2,
<vscale x 1 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 1 x i64> %a
}
@@ -901,9 +884,9 @@ declare <vscale x 2 x i64> @llvm.riscv.vasub.nxv2i64.nxv2i64(
<vscale x 2 x i64>,
<vscale x 2 x i64>,
<vscale x 2 x i64>,
- i32);
+ iXLen);
-define <vscale x 2 x i64> @intrinsic_vasub_vv_nxv2i64_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i32 %2) nounwind {
+define <vscale x 2 x i64> @intrinsic_vasub_vv_nxv2i64_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vasub_vv_nxv2i64_nxv2i64_nxv2i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
@@ -914,7 +897,7 @@ entry:
<vscale x 2 x i64> undef,
<vscale x 2 x i64> %0,
<vscale x 2 x i64> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 2 x i64> %a
}
@@ -924,10 +907,9 @@ declare <vscale x 2 x i64> @llvm.riscv.vasub.mask.nxv2i64.nxv2i64(
<vscale x 2 x i64>,
<vscale x 2 x i64>,
<vscale x 2 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 2 x i64> @intrinsic_vasub_mask_vv_nxv2i64_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+define <vscale x 2 x i64> @intrinsic_vasub_mask_vv_nxv2i64_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv2i64_nxv2i64_nxv2i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
@@ -939,7 +921,7 @@ entry:
<vscale x 2 x i64> %1,
<vscale x 2 x i64> %2,
<vscale x 2 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 2 x i64> %a
}
@@ -948,9 +930,9 @@ declare <vscale x 4 x i64> @llvm.riscv.vasub.nxv4i64.nxv4i64(
<vscale x 4 x i64>,
<vscale x 4 x i64>,
<vscale x 4 x i64>,
- i32);
+ iXLen);
-define <vscale x 4 x i64> @intrinsic_vasub_vv_nxv4i64_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i32 %2) nounwind {
+define <vscale x 4 x i64> @intrinsic_vasub_vv_nxv4i64_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vasub_vv_nxv4i64_nxv4i64_nxv4i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
@@ -961,7 +943,7 @@ entry:
<vscale x 4 x i64> undef,
<vscale x 4 x i64> %0,
<vscale x 4 x i64> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 4 x i64> %a
}
@@ -971,10 +953,9 @@ declare <vscale x 4 x i64> @llvm.riscv.vasub.mask.nxv4i64.nxv4i64(
<vscale x 4 x i64>,
<vscale x 4 x i64>,
<vscale x 4 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 4 x i64> @intrinsic_vasub_mask_vv_nxv4i64_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+define <vscale x 4 x i64> @intrinsic_vasub_mask_vv_nxv4i64_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv4i64_nxv4i64_nxv4i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
@@ -986,7 +967,7 @@ entry:
<vscale x 4 x i64> %1,
<vscale x 4 x i64> %2,
<vscale x 4 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 4 x i64> %a
}
@@ -995,9 +976,9 @@ declare <vscale x 8 x i64> @llvm.riscv.vasub.nxv8i64.nxv8i64(
<vscale x 8 x i64>,
<vscale x 8 x i64>,
<vscale x 8 x i64>,
- i32);
+ iXLen);
-define <vscale x 8 x i64> @intrinsic_vasub_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i32 %2) nounwind {
+define <vscale x 8 x i64> @intrinsic_vasub_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vasub_vv_nxv8i64_nxv8i64_nxv8i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu
@@ -1008,7 +989,7 @@ entry:
<vscale x 8 x i64> undef,
<vscale x 8 x i64> %0,
<vscale x 8 x i64> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 8 x i64> %a
}
@@ -1018,10 +999,9 @@ declare <vscale x 8 x i64> @llvm.riscv.vasub.mask.nxv8i64.nxv8i64(
<vscale x 8 x i64>,
<vscale x 8 x i64>,
<vscale x 8 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 8 x i64> @intrinsic_vasub_mask_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+define <vscale x 8 x i64> @intrinsic_vasub_mask_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv8i64_nxv8i64_nxv8i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vl8re64.v v24, (a0)
@@ -1034,7 +1014,7 @@ entry:
<vscale x 8 x i64> %1,
<vscale x 8 x i64> %2,
<vscale x 8 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 8 x i64> %a
}
@@ -1043,9 +1023,9 @@ declare <vscale x 1 x i8> @llvm.riscv.vasub.nxv1i8.i8(
<vscale x 1 x i8>,
<vscale x 1 x i8>,
i8,
- i32);
+ iXLen);
-define <vscale x 1 x i8> @intrinsic_vasub_vx_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, i8 %1, i32 %2) nounwind {
+define <vscale x 1 x i8> @intrinsic_vasub_vx_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, i8 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vasub_vx_nxv1i8_nxv1i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
@@ -1056,7 +1036,7 @@ entry:
<vscale x 1 x i8> undef,
<vscale x 1 x i8> %0,
i8 %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 1 x i8> %a
}
@@ -1066,10 +1046,9 @@ declare <vscale x 1 x i8> @llvm.riscv.vasub.mask.nxv1i8.i8(
<vscale x 1 x i8>,
i8,
<vscale x 1 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 1 x i8> @intrinsic_vasub_mask_vx_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+define <vscale x 1 x i8> @intrinsic_vasub_mask_vx_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vasub_mask_vx_nxv1i8_nxv1i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
@@ -1081,7 +1060,7 @@ entry:
<vscale x 1 x i8> %1,
i8 %2,
<vscale x 1 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 1 x i8> %a
}
@@ -1090,9 +1069,9 @@ declare <vscale x 2 x i8> @llvm.riscv.vasub.nxv2i8.i8(
<vscale x 2 x i8>,
<vscale x 2 x i8>,
i8,
- i32);
+ iXLen);
-define <vscale x 2 x i8> @intrinsic_vasub_vx_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, i8 %1, i32 %2) nounwind {
+define <vscale x 2 x i8> @intrinsic_vasub_vx_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, i8 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vasub_vx_nxv2i8_nxv2i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
@@ -1103,7 +1082,7 @@ entry:
<vscale x 2 x i8> undef,
<vscale x 2 x i8> %0,
i8 %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 2 x i8> %a
}
@@ -1113,10 +1092,9 @@ declare <vscale x 2 x i8> @llvm.riscv.vasub.mask.nxv2i8.i8(
<vscale x 2 x i8>,
i8,
<vscale x 2 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 2 x i8> @intrinsic_vasub_mask_vx_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+define <vscale x 2 x i8> @intrinsic_vasub_mask_vx_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vasub_mask_vx_nxv2i8_nxv2i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
@@ -1128,7 +1106,7 @@ entry:
<vscale x 2 x i8> %1,
i8 %2,
<vscale x 2 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 2 x i8> %a
}
@@ -1137,9 +1115,9 @@ declare <vscale x 4 x i8> @llvm.riscv.vasub.nxv4i8.i8(
<vscale x 4 x i8>,
<vscale x 4 x i8>,
i8,
- i32);
+ iXLen);
-define <vscale x 4 x i8> @intrinsic_vasub_vx_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, i8 %1, i32 %2) nounwind {
+define <vscale x 4 x i8> @intrinsic_vasub_vx_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, i8 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vasub_vx_nxv4i8_nxv4i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
@@ -1150,7 +1128,7 @@ entry:
<vscale x 4 x i8> undef,
<vscale x 4 x i8> %0,
i8 %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 4 x i8> %a
}
@@ -1160,10 +1138,9 @@ declare <vscale x 4 x i8> @llvm.riscv.vasub.mask.nxv4i8.i8(
<vscale x 4 x i8>,
i8,
<vscale x 4 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 4 x i8> @intrinsic_vasub_mask_vx_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+define <vscale x 4 x i8> @intrinsic_vasub_mask_vx_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vasub_mask_vx_nxv4i8_nxv4i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
@@ -1175,7 +1152,7 @@ entry:
<vscale x 4 x i8> %1,
i8 %2,
<vscale x 4 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 4 x i8> %a
}
@@ -1184,9 +1161,9 @@ declare <vscale x 8 x i8> @llvm.riscv.vasub.nxv8i8.i8(
<vscale x 8 x i8>,
<vscale x 8 x i8>,
i8,
- i32);
+ iXLen);
-define <vscale x 8 x i8> @intrinsic_vasub_vx_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, i8 %1, i32 %2) nounwind {
+define <vscale x 8 x i8> @intrinsic_vasub_vx_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, i8 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vasub_vx_nxv8i8_nxv8i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
@@ -1197,7 +1174,7 @@ entry:
<vscale x 8 x i8> undef,
<vscale x 8 x i8> %0,
i8 %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 8 x i8> %a
}
@@ -1207,10 +1184,9 @@ declare <vscale x 8 x i8> @llvm.riscv.vasub.mask.nxv8i8.i8(
<vscale x 8 x i8>,
i8,
<vscale x 8 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 8 x i8> @intrinsic_vasub_mask_vx_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+define <vscale x 8 x i8> @intrinsic_vasub_mask_vx_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vasub_mask_vx_nxv8i8_nxv8i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
@@ -1222,7 +1198,7 @@ entry:
<vscale x 8 x i8> %1,
i8 %2,
<vscale x 8 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 8 x i8> %a
}
@@ -1231,9 +1207,9 @@ declare <vscale x 16 x i8> @llvm.riscv.vasub.nxv16i8.i8(
<vscale x 16 x i8>,
<vscale x 16 x i8>,
i8,
- i32);
+ iXLen);
-define <vscale x 16 x i8> @intrinsic_vasub_vx_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, i8 %1, i32 %2) nounwind {
+define <vscale x 16 x i8> @intrinsic_vasub_vx_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, i8 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vasub_vx_nxv16i8_nxv16i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
@@ -1244,7 +1220,7 @@ entry:
<vscale x 16 x i8> undef,
<vscale x 16 x i8> %0,
i8 %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 16 x i8> %a
}
@@ -1254,10 +1230,9 @@ declare <vscale x 16 x i8> @llvm.riscv.vasub.mask.nxv16i8.i8(
<vscale x 16 x i8>,
i8,
<vscale x 16 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 16 x i8> @intrinsic_vasub_mask_vx_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+define <vscale x 16 x i8> @intrinsic_vasub_mask_vx_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vasub_mask_vx_nxv16i8_nxv16i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
@@ -1269,7 +1244,7 @@ entry:
<vscale x 16 x i8> %1,
i8 %2,
<vscale x 16 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 16 x i8> %a
}
@@ -1278,9 +1253,9 @@ declare <vscale x 32 x i8> @llvm.riscv.vasub.nxv32i8.i8(
<vscale x 32 x i8>,
<vscale x 32 x i8>,
i8,
- i32);
+ iXLen);
-define <vscale x 32 x i8> @intrinsic_vasub_vx_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, i8 %1, i32 %2) nounwind {
+define <vscale x 32 x i8> @intrinsic_vasub_vx_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, i8 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vasub_vx_nxv32i8_nxv32i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
@@ -1291,7 +1266,7 @@ entry:
<vscale x 32 x i8> undef,
<vscale x 32 x i8> %0,
i8 %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 32 x i8> %a
}
@@ -1301,10 +1276,9 @@ declare <vscale x 32 x i8> @llvm.riscv.vasub.mask.nxv32i8.i8(
<vscale x 32 x i8>,
i8,
<vscale x 32 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 32 x i8> @intrinsic_vasub_mask_vx_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
+define <vscale x 32 x i8> @intrinsic_vasub_mask_vx_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vasub_mask_vx_nxv32i8_nxv32i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
@@ -1316,7 +1290,7 @@ entry:
<vscale x 32 x i8> %1,
i8 %2,
<vscale x 32 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 32 x i8> %a
}
@@ -1325,9 +1299,9 @@ declare <vscale x 64 x i8> @llvm.riscv.vasub.nxv64i8.i8(
<vscale x 64 x i8>,
<vscale x 64 x i8>,
i8,
- i32);
+ iXLen);
-define <vscale x 64 x i8> @intrinsic_vasub_vx_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, i8 %1, i32 %2) nounwind {
+define <vscale x 64 x i8> @intrinsic_vasub_vx_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, i8 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vasub_vx_nxv64i8_nxv64i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu
@@ -1338,7 +1312,7 @@ entry:
<vscale x 64 x i8> undef,
<vscale x 64 x i8> %0,
i8 %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 64 x i8> %a
}
@@ -1348,10 +1322,9 @@ declare <vscale x 64 x i8> @llvm.riscv.vasub.mask.nxv64i8.i8(
<vscale x 64 x i8>,
i8,
<vscale x 64 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 64 x i8> @intrinsic_vasub_mask_vx_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i8 %2, <vscale x 64 x i1> %3, i32 %4) nounwind {
+define <vscale x 64 x i8> @intrinsic_vasub_mask_vx_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i8 %2, <vscale x 64 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vasub_mask_vx_nxv64i8_nxv64i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu
@@ -1363,7 +1336,7 @@ entry:
<vscale x 64 x i8> %1,
i8 %2,
<vscale x 64 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 64 x i8> %a
}
@@ -1372,9 +1345,9 @@ declare <vscale x 1 x i16> @llvm.riscv.vasub.nxv1i16.i16(
<vscale x 1 x i16>,
<vscale x 1 x i16>,
i16,
- i32);
+ iXLen);
-define <vscale x 1 x i16> @intrinsic_vasub_vx_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, i16 %1, i32 %2) nounwind {
+define <vscale x 1 x i16> @intrinsic_vasub_vx_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, i16 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vasub_vx_nxv1i16_nxv1i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
@@ -1385,7 +1358,7 @@ entry:
<vscale x 1 x i16> undef,
<vscale x 1 x i16> %0,
i16 %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 1 x i16> %a
}
@@ -1395,10 +1368,9 @@ declare <vscale x 1 x i16> @llvm.riscv.vasub.mask.nxv1i16.i16(
<vscale x 1 x i16>,
i16,
<vscale x 1 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 1 x i16> @intrinsic_vasub_mask_vx_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+define <vscale x 1 x i16> @intrinsic_vasub_mask_vx_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vasub_mask_vx_nxv1i16_nxv1i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
@@ -1410,7 +1382,7 @@ entry:
<vscale x 1 x i16> %1,
i16 %2,
<vscale x 1 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 1 x i16> %a
}
@@ -1419,9 +1391,9 @@ declare <vscale x 2 x i16> @llvm.riscv.vasub.nxv2i16.i16(
<vscale x 2 x i16>,
<vscale x 2 x i16>,
i16,
- i32);
+ iXLen);
-define <vscale x 2 x i16> @intrinsic_vasub_vx_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, i16 %1, i32 %2) nounwind {
+define <vscale x 2 x i16> @intrinsic_vasub_vx_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, i16 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vasub_vx_nxv2i16_nxv2i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
@@ -1432,7 +1404,7 @@ entry:
<vscale x 2 x i16> undef,
<vscale x 2 x i16> %0,
i16 %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 2 x i16> %a
}
@@ -1442,10 +1414,9 @@ declare <vscale x 2 x i16> @llvm.riscv.vasub.mask.nxv2i16.i16(
<vscale x 2 x i16>,
i16,
<vscale x 2 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 2 x i16> @intrinsic_vasub_mask_vx_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+define <vscale x 2 x i16> @intrinsic_vasub_mask_vx_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vasub_mask_vx_nxv2i16_nxv2i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
@@ -1457,7 +1428,7 @@ entry:
<vscale x 2 x i16> %1,
i16 %2,
<vscale x 2 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 2 x i16> %a
}
@@ -1466,9 +1437,9 @@ declare <vscale x 4 x i16> @llvm.riscv.vasub.nxv4i16.i16(
<vscale x 4 x i16>,
<vscale x 4 x i16>,
i16,
- i32);
+ iXLen);
-define <vscale x 4 x i16> @intrinsic_vasub_vx_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, i16 %1, i32 %2) nounwind {
+define <vscale x 4 x i16> @intrinsic_vasub_vx_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, i16 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vasub_vx_nxv4i16_nxv4i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
@@ -1479,7 +1450,7 @@ entry:
<vscale x 4 x i16> undef,
<vscale x 4 x i16> %0,
i16 %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 4 x i16> %a
}
@@ -1489,10 +1460,9 @@ declare <vscale x 4 x i16> @llvm.riscv.vasub.mask.nxv4i16.i16(
<vscale x 4 x i16>,
i16,
<vscale x 4 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 4 x i16> @intrinsic_vasub_mask_vx_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+define <vscale x 4 x i16> @intrinsic_vasub_mask_vx_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vasub_mask_vx_nxv4i16_nxv4i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
@@ -1504,7 +1474,7 @@ entry:
<vscale x 4 x i16> %1,
i16 %2,
<vscale x 4 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 4 x i16> %a
}
@@ -1513,9 +1483,9 @@ declare <vscale x 8 x i16> @llvm.riscv.vasub.nxv8i16.i16(
<vscale x 8 x i16>,
<vscale x 8 x i16>,
i16,
- i32);
+ iXLen);
-define <vscale x 8 x i16> @intrinsic_vasub_vx_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, i16 %1, i32 %2) nounwind {
+define <vscale x 8 x i16> @intrinsic_vasub_vx_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, i16 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vasub_vx_nxv8i16_nxv8i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
@@ -1526,7 +1496,7 @@ entry:
<vscale x 8 x i16> undef,
<vscale x 8 x i16> %0,
i16 %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 8 x i16> %a
}
@@ -1536,10 +1506,9 @@ declare <vscale x 8 x i16> @llvm.riscv.vasub.mask.nxv8i16.i16(
<vscale x 8 x i16>,
i16,
<vscale x 8 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 8 x i16> @intrinsic_vasub_mask_vx_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+define <vscale x 8 x i16> @intrinsic_vasub_mask_vx_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vasub_mask_vx_nxv8i16_nxv8i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
@@ -1551,7 +1520,7 @@ entry:
<vscale x 8 x i16> %1,
i16 %2,
<vscale x 8 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 8 x i16> %a
}
@@ -1560,9 +1529,9 @@ declare <vscale x 16 x i16> @llvm.riscv.vasub.nxv16i16.i16(
<vscale x 16 x i16>,
<vscale x 16 x i16>,
i16,
- i32);
+ iXLen);
-define <vscale x 16 x i16> @intrinsic_vasub_vx_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, i16 %1, i32 %2) nounwind {
+define <vscale x 16 x i16> @intrinsic_vasub_vx_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, i16 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vasub_vx_nxv16i16_nxv16i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
@@ -1573,7 +1542,7 @@ entry:
<vscale x 16 x i16> undef,
<vscale x 16 x i16> %0,
i16 %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 16 x i16> %a
}
@@ -1583,10 +1552,9 @@ declare <vscale x 16 x i16> @llvm.riscv.vasub.mask.nxv16i16.i16(
<vscale x 16 x i16>,
i16,
<vscale x 16 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 16 x i16> @intrinsic_vasub_mask_vx_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+define <vscale x 16 x i16> @intrinsic_vasub_mask_vx_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vasub_mask_vx_nxv16i16_nxv16i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
@@ -1598,7 +1566,7 @@ entry:
<vscale x 16 x i16> %1,
i16 %2,
<vscale x 16 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 16 x i16> %a
}
@@ -1607,9 +1575,9 @@ declare <vscale x 32 x i16> @llvm.riscv.vasub.nxv32i16.i16(
<vscale x 32 x i16>,
<vscale x 32 x i16>,
i16,
- i32);
+ iXLen);
-define <vscale x 32 x i16> @intrinsic_vasub_vx_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, i16 %1, i32 %2) nounwind {
+define <vscale x 32 x i16> @intrinsic_vasub_vx_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, i16 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vasub_vx_nxv32i16_nxv32i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu
@@ -1620,7 +1588,7 @@ entry:
<vscale x 32 x i16> undef,
<vscale x 32 x i16> %0,
i16 %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 32 x i16> %a
}
@@ -1630,10 +1598,9 @@ declare <vscale x 32 x i16> @llvm.riscv.vasub.mask.nxv32i16.i16(
<vscale x 32 x i16>,
i16,
<vscale x 32 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 32 x i16> @intrinsic_vasub_mask_vx_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, i16 %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
+define <vscale x 32 x i16> @intrinsic_vasub_mask_vx_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, i16 %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vasub_mask_vx_nxv32i16_nxv32i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu
@@ -1645,7 +1612,7 @@ entry:
<vscale x 32 x i16> %1,
i16 %2,
<vscale x 32 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 32 x i16> %a
}
@@ -1654,9 +1621,9 @@ declare <vscale x 1 x i32> @llvm.riscv.vasub.nxv1i32.i32(
<vscale x 1 x i32>,
<vscale x 1 x i32>,
i32,
- i32);
+ iXLen);
-define <vscale x 1 x i32> @intrinsic_vasub_vx_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, i32 %1, i32 %2) nounwind {
+define <vscale x 1 x i32> @intrinsic_vasub_vx_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, i32 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vasub_vx_nxv1i32_nxv1i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
@@ -1667,7 +1634,7 @@ entry:
<vscale x 1 x i32> undef,
<vscale x 1 x i32> %0,
i32 %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 1 x i32> %a
}
@@ -1677,10 +1644,9 @@ declare <vscale x 1 x i32> @llvm.riscv.vasub.mask.nxv1i32.i32(
<vscale x 1 x i32>,
i32,
<vscale x 1 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 1 x i32> @intrinsic_vasub_mask_vx_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+define <vscale x 1 x i32> @intrinsic_vasub_mask_vx_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vasub_mask_vx_nxv1i32_nxv1i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
@@ -1692,7 +1658,7 @@ entry:
<vscale x 1 x i32> %1,
i32 %2,
<vscale x 1 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 1 x i32> %a
}
@@ -1701,9 +1667,9 @@ declare <vscale x 2 x i32> @llvm.riscv.vasub.nxv2i32.i32(
<vscale x 2 x i32>,
<vscale x 2 x i32>,
i32,
- i32);
+ iXLen);
-define <vscale x 2 x i32> @intrinsic_vasub_vx_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, i32 %1, i32 %2) nounwind {
+define <vscale x 2 x i32> @intrinsic_vasub_vx_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, i32 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vasub_vx_nxv2i32_nxv2i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
@@ -1714,7 +1680,7 @@ entry:
<vscale x 2 x i32> undef,
<vscale x 2 x i32> %0,
i32 %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 2 x i32> %a
}
@@ -1724,10 +1690,9 @@ declare <vscale x 2 x i32> @llvm.riscv.vasub.mask.nxv2i32.i32(
<vscale x 2 x i32>,
i32,
<vscale x 2 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 2 x i32> @intrinsic_vasub_mask_vx_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+define <vscale x 2 x i32> @intrinsic_vasub_mask_vx_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vasub_mask_vx_nxv2i32_nxv2i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
@@ -1739,7 +1704,7 @@ entry:
<vscale x 2 x i32> %1,
i32 %2,
<vscale x 2 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 2 x i32> %a
}
@@ -1748,9 +1713,9 @@ declare <vscale x 4 x i32> @llvm.riscv.vasub.nxv4i32.i32(
<vscale x 4 x i32>,
<vscale x 4 x i32>,
i32,
- i32);
+ iXLen);
-define <vscale x 4 x i32> @intrinsic_vasub_vx_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, i32 %1, i32 %2) nounwind {
+define <vscale x 4 x i32> @intrinsic_vasub_vx_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, i32 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vasub_vx_nxv4i32_nxv4i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
@@ -1761,7 +1726,7 @@ entry:
<vscale x 4 x i32> undef,
<vscale x 4 x i32> %0,
i32 %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 4 x i32> %a
}
@@ -1771,10 +1736,9 @@ declare <vscale x 4 x i32> @llvm.riscv.vasub.mask.nxv4i32.i32(
<vscale x 4 x i32>,
i32,
<vscale x 4 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 4 x i32> @intrinsic_vasub_mask_vx_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+define <vscale x 4 x i32> @intrinsic_vasub_mask_vx_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vasub_mask_vx_nxv4i32_nxv4i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
@@ -1786,7 +1750,7 @@ entry:
<vscale x 4 x i32> %1,
i32 %2,
<vscale x 4 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 4 x i32> %a
}
@@ -1795,9 +1759,9 @@ declare <vscale x 8 x i32> @llvm.riscv.vasub.nxv8i32.i32(
<vscale x 8 x i32>,
<vscale x 8 x i32>,
i32,
- i32);
+ iXLen);
-define <vscale x 8 x i32> @intrinsic_vasub_vx_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, i32 %1, i32 %2) nounwind {
+define <vscale x 8 x i32> @intrinsic_vasub_vx_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, i32 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vasub_vx_nxv8i32_nxv8i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
@@ -1808,7 +1772,7 @@ entry:
<vscale x 8 x i32> undef,
<vscale x 8 x i32> %0,
i32 %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 8 x i32> %a
}
@@ -1818,10 +1782,9 @@ declare <vscale x 8 x i32> @llvm.riscv.vasub.mask.nxv8i32.i32(
<vscale x 8 x i32>,
i32,
<vscale x 8 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 8 x i32> @intrinsic_vasub_mask_vx_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+define <vscale x 8 x i32> @intrinsic_vasub_mask_vx_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vasub_mask_vx_nxv8i32_nxv8i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
@@ -1833,7 +1796,7 @@ entry:
<vscale x 8 x i32> %1,
i32 %2,
<vscale x 8 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 8 x i32> %a
}
@@ -1842,9 +1805,9 @@ declare <vscale x 16 x i32> @llvm.riscv.vasub.nxv16i32.i32(
<vscale x 16 x i32>,
<vscale x 16 x i32>,
i32,
- i32);
+ iXLen);
-define <vscale x 16 x i32> @intrinsic_vasub_vx_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, i32 %1, i32 %2) nounwind {
+define <vscale x 16 x i32> @intrinsic_vasub_vx_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, i32 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vasub_vx_nxv16i32_nxv16i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu
@@ -1855,7 +1818,7 @@ entry:
<vscale x 16 x i32> undef,
<vscale x 16 x i32> %0,
i32 %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 16 x i32> %a
}
@@ -1865,10 +1828,9 @@ declare <vscale x 16 x i32> @llvm.riscv.vasub.mask.nxv16i32.i32(
<vscale x 16 x i32>,
i32,
<vscale x 16 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 16 x i32> @intrinsic_vasub_mask_vx_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+define <vscale x 16 x i32> @intrinsic_vasub_mask_vx_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vasub_mask_vx_nxv16i32_nxv16i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu
@@ -1880,7 +1842,7 @@ entry:
<vscale x 16 x i32> %1,
i32 %2,
<vscale x 16 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 16 x i32> %a
}
@@ -1889,26 +1851,32 @@ declare <vscale x 1 x i64> @llvm.riscv.vasub.nxv1i64.i64(
<vscale x 1 x i64>,
<vscale x 1 x i64>,
i64,
- i32);
-
-define <vscale x 1 x i64> @intrinsic_vasub_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vasub_vx_nxv1i64_nxv1i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addi sp, sp, -16
-; CHECK-NEXT: sw a1, 12(sp)
-; CHECK-NEXT: sw a0, 8(sp)
-; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
-; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v9, (a0), zero
-; CHECK-NEXT: vasub.vv v8, v8, v9
-; CHECK-NEXT: addi sp, sp, 16
-; CHECK-NEXT: ret
+ iXLen);
+
+define <vscale x 1 x i64> @intrinsic_vasub_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, iXLen %2) nounwind {
+; RV32-LABEL: intrinsic_vasub_vx_nxv1i64_nxv1i64_i64:
+; RV32: # %bb.0: # %entry
+; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: sw a1, 12(sp)
+; RV32-NEXT: sw a0, 8(sp)
+; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
+; RV32-NEXT: addi a0, sp, 8
+; RV32-NEXT: vlse64.v v9, (a0), zero
+; RV32-NEXT: vasub.vv v8, v8, v9
+; RV32-NEXT: addi sp, sp, 16
+; RV32-NEXT: ret
+;
+; RV64-LABEL: intrinsic_vasub_vx_nxv1i64_nxv1i64_i64:
+; RV64: # %bb.0: # %entry
+; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, mu
+; RV64-NEXT: vasub.vx v8, v8, a0
+; RV64-NEXT: ret
entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vasub.nxv1i64.i64(
<vscale x 1 x i64> undef,
<vscale x 1 x i64> %0,
i64 %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 1 x i64> %a
}
@@ -1918,28 +1886,33 @@ declare <vscale x 1 x i64> @llvm.riscv.vasub.mask.nxv1i64.i64(
<vscale x 1 x i64>,
i64,
<vscale x 1 x i1>,
- i32,
- i32);
-
-define <vscale x 1 x i64> @intrinsic_vasub_mask_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vasub_mask_vx_nxv1i64_nxv1i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addi sp, sp, -16
-; CHECK-NEXT: sw a1, 12(sp)
-; CHECK-NEXT: sw a0, 8(sp)
-; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
-; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v10, (a0), zero
-; CHECK-NEXT: vasub.vv v8, v9, v10, v0.t
-; CHECK-NEXT: addi sp, sp, 16
-; CHECK-NEXT: ret
+ iXLen, iXLen);
+
+define <vscale x 1 x i64> @intrinsic_vasub_mask_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
+; RV32-LABEL: intrinsic_vasub_mask_vx_nxv1i64_nxv1i64_i64:
+; RV32: # %bb.0: # %entry
+; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: sw a1, 12(sp)
+; RV32-NEXT: sw a0, 8(sp)
+; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
+; RV32-NEXT: addi a0, sp, 8
+; RV32-NEXT: vlse64.v v10, (a0), zero
+; RV32-NEXT: vasub.vv v8, v9, v10, v0.t
+; RV32-NEXT: addi sp, sp, 16
+; RV32-NEXT: ret
+;
+; RV64-LABEL: intrinsic_vasub_mask_vx_nxv1i64_nxv1i64_i64:
+; RV64: # %bb.0: # %entry
+; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, mu
+; RV64-NEXT: vasub.vx v8, v9, a0, v0.t
+; RV64-NEXT: ret
entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vasub.mask.nxv1i64.i64(
<vscale x 1 x i64> %0,
<vscale x 1 x i64> %1,
i64 %2,
<vscale x 1 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 1 x i64> %a
}
@@ -1948,26 +1921,32 @@ declare <vscale x 2 x i64> @llvm.riscv.vasub.nxv2i64.i64(
<vscale x 2 x i64>,
<vscale x 2 x i64>,
i64,
- i32);
-
-define <vscale x 2 x i64> @intrinsic_vasub_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vasub_vx_nxv2i64_nxv2i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addi sp, sp, -16
-; CHECK-NEXT: sw a1, 12(sp)
-; CHECK-NEXT: sw a0, 8(sp)
-; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
-; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v10, (a0), zero
-; CHECK-NEXT: vasub.vv v8, v8, v10
-; CHECK-NEXT: addi sp, sp, 16
-; CHECK-NEXT: ret
+ iXLen);
+
+define <vscale x 2 x i64> @intrinsic_vasub_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, iXLen %2) nounwind {
+; RV32-LABEL: intrinsic_vasub_vx_nxv2i64_nxv2i64_i64:
+; RV32: # %bb.0: # %entry
+; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: sw a1, 12(sp)
+; RV32-NEXT: sw a0, 8(sp)
+; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
+; RV32-NEXT: addi a0, sp, 8
+; RV32-NEXT: vlse64.v v10, (a0), zero
+; RV32-NEXT: vasub.vv v8, v8, v10
+; RV32-NEXT: addi sp, sp, 16
+; RV32-NEXT: ret
+;
+; RV64-LABEL: intrinsic_vasub_vx_nxv2i64_nxv2i64_i64:
+; RV64: # %bb.0: # %entry
+; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, mu
+; RV64-NEXT: vasub.vx v8, v8, a0
+; RV64-NEXT: ret
entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vasub.nxv2i64.i64(
<vscale x 2 x i64> undef,
<vscale x 2 x i64> %0,
i64 %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 2 x i64> %a
}
@@ -1977,28 +1956,33 @@ declare <vscale x 2 x i64> @llvm.riscv.vasub.mask.nxv2i64.i64(
<vscale x 2 x i64>,
i64,
<vscale x 2 x i1>,
- i32,
- i32);
-
-define <vscale x 2 x i64> @intrinsic_vasub_mask_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vasub_mask_vx_nxv2i64_nxv2i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addi sp, sp, -16
-; CHECK-NEXT: sw a1, 12(sp)
-; CHECK-NEXT: sw a0, 8(sp)
-; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
-; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v12, (a0), zero
-; CHECK-NEXT: vasub.vv v8, v10, v12, v0.t
-; CHECK-NEXT: addi sp, sp, 16
-; CHECK-NEXT: ret
+ iXLen, iXLen);
+
+define <vscale x 2 x i64> @intrinsic_vasub_mask_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
+; RV32-LABEL: intrinsic_vasub_mask_vx_nxv2i64_nxv2i64_i64:
+; RV32: # %bb.0: # %entry
+; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: sw a1, 12(sp)
+; RV32-NEXT: sw a0, 8(sp)
+; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
+; RV32-NEXT: addi a0, sp, 8
+; RV32-NEXT: vlse64.v v12, (a0), zero
+; RV32-NEXT: vasub.vv v8, v10, v12, v0.t
+; RV32-NEXT: addi sp, sp, 16
+; RV32-NEXT: ret
+;
+; RV64-LABEL: intrinsic_vasub_mask_vx_nxv2i64_nxv2i64_i64:
+; RV64: # %bb.0: # %entry
+; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, mu
+; RV64-NEXT: vasub.vx v8, v10, a0, v0.t
+; RV64-NEXT: ret
entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vasub.mask.nxv2i64.i64(
<vscale x 2 x i64> %0,
<vscale x 2 x i64> %1,
i64 %2,
<vscale x 2 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 2 x i64> %a
}
@@ -2007,26 +1991,32 @@ declare <vscale x 4 x i64> @llvm.riscv.vasub.nxv4i64.i64(
<vscale x 4 x i64>,
<vscale x 4 x i64>,
i64,
- i32);
-
-define <vscale x 4 x i64> @intrinsic_vasub_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vasub_vx_nxv4i64_nxv4i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addi sp, sp, -16
-; CHECK-NEXT: sw a1, 12(sp)
-; CHECK-NEXT: sw a0, 8(sp)
-; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
-; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v12, (a0), zero
-; CHECK-NEXT: vasub.vv v8, v8, v12
-; CHECK-NEXT: addi sp, sp, 16
-; CHECK-NEXT: ret
+ iXLen);
+
+define <vscale x 4 x i64> @intrinsic_vasub_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, iXLen %2) nounwind {
+; RV32-LABEL: intrinsic_vasub_vx_nxv4i64_nxv4i64_i64:
+; RV32: # %bb.0: # %entry
+; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: sw a1, 12(sp)
+; RV32-NEXT: sw a0, 8(sp)
+; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
+; RV32-NEXT: addi a0, sp, 8
+; RV32-NEXT: vlse64.v v12, (a0), zero
+; RV32-NEXT: vasub.vv v8, v8, v12
+; RV32-NEXT: addi sp, sp, 16
+; RV32-NEXT: ret
+;
+; RV64-LABEL: intrinsic_vasub_vx_nxv4i64_nxv4i64_i64:
+; RV64: # %bb.0: # %entry
+; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu
+; RV64-NEXT: vasub.vx v8, v8, a0
+; RV64-NEXT: ret
entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vasub.nxv4i64.i64(
<vscale x 4 x i64> undef,
<vscale x 4 x i64> %0,
i64 %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 4 x i64> %a
}
@@ -2036,28 +2026,33 @@ declare <vscale x 4 x i64> @llvm.riscv.vasub.mask.nxv4i64.i64(
<vscale x 4 x i64>,
i64,
<vscale x 4 x i1>,
- i32,
- i32);
-
-define <vscale x 4 x i64> @intrinsic_vasub_mask_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vasub_mask_vx_nxv4i64_nxv4i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addi sp, sp, -16
-; CHECK-NEXT: sw a1, 12(sp)
-; CHECK-NEXT: sw a0, 8(sp)
-; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
-; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v16, (a0), zero
-; CHECK-NEXT: vasub.vv v8, v12, v16, v0.t
-; CHECK-NEXT: addi sp, sp, 16
-; CHECK-NEXT: ret
+ iXLen, iXLen);
+
+define <vscale x 4 x i64> @intrinsic_vasub_mask_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
+; RV32-LABEL: intrinsic_vasub_mask_vx_nxv4i64_nxv4i64_i64:
+; RV32: # %bb.0: # %entry
+; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: sw a1, 12(sp)
+; RV32-NEXT: sw a0, 8(sp)
+; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
+; RV32-NEXT: addi a0, sp, 8
+; RV32-NEXT: vlse64.v v16, (a0), zero
+; RV32-NEXT: vasub.vv v8, v12, v16, v0.t
+; RV32-NEXT: addi sp, sp, 16
+; RV32-NEXT: ret
+;
+; RV64-LABEL: intrinsic_vasub_mask_vx_nxv4i64_nxv4i64_i64:
+; RV64: # %bb.0: # %entry
+; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu
+; RV64-NEXT: vasub.vx v8, v12, a0, v0.t
+; RV64-NEXT: ret
entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vasub.mask.nxv4i64.i64(
<vscale x 4 x i64> %0,
<vscale x 4 x i64> %1,
i64 %2,
<vscale x 4 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 4 x i64> %a
}
@@ -2066,26 +2061,32 @@ declare <vscale x 8 x i64> @llvm.riscv.vasub.nxv8i64.i64(
<vscale x 8 x i64>,
<vscale x 8 x i64>,
i64,
- i32);
-
-define <vscale x 8 x i64> @intrinsic_vasub_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, i64 %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vasub_vx_nxv8i64_nxv8i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addi sp, sp, -16
-; CHECK-NEXT: sw a1, 12(sp)
-; CHECK-NEXT: sw a0, 8(sp)
-; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, mu
-; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v16, (a0), zero
-; CHECK-NEXT: vasub.vv v8, v8, v16
-; CHECK-NEXT: addi sp, sp, 16
-; CHECK-NEXT: ret
+ iXLen);
+
+define <vscale x 8 x i64> @intrinsic_vasub_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, i64 %1, iXLen %2) nounwind {
+; RV32-LABEL: intrinsic_vasub_vx_nxv8i64_nxv8i64_i64:
+; RV32: # %bb.0: # %entry
+; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: sw a1, 12(sp)
+; RV32-NEXT: sw a0, 8(sp)
+; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu
+; RV32-NEXT: addi a0, sp, 8
+; RV32-NEXT: vlse64.v v16, (a0), zero
+; RV32-NEXT: vasub.vv v8, v8, v16
+; RV32-NEXT: addi sp, sp, 16
+; RV32-NEXT: ret
+;
+; RV64-LABEL: intrinsic_vasub_vx_nxv8i64_nxv8i64_i64:
+; RV64: # %bb.0: # %entry
+; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, mu
+; RV64-NEXT: vasub.vx v8, v8, a0
+; RV64-NEXT: ret
entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vasub.nxv8i64.i64(
<vscale x 8 x i64> undef,
<vscale x 8 x i64> %0,
i64 %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 8 x i64> %a
}
@@ -2095,28 +2096,33 @@ declare <vscale x 8 x i64> @llvm.riscv.vasub.mask.nxv8i64.i64(
<vscale x 8 x i64>,
i64,
<vscale x 8 x i1>,
- i32,
- i32);
-
-define <vscale x 8 x i64> @intrinsic_vasub_mask_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vasub_mask_vx_nxv8i64_nxv8i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addi sp, sp, -16
-; CHECK-NEXT: sw a1, 12(sp)
-; CHECK-NEXT: sw a0, 8(sp)
-; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, mu
-; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v24, (a0), zero
-; CHECK-NEXT: vasub.vv v8, v16, v24, v0.t
-; CHECK-NEXT: addi sp, sp, 16
-; CHECK-NEXT: ret
+ iXLen, iXLen);
+
+define <vscale x 8 x i64> @intrinsic_vasub_mask_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
+; RV32-LABEL: intrinsic_vasub_mask_vx_nxv8i64_nxv8i64_i64:
+; RV32: # %bb.0: # %entry
+; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: sw a1, 12(sp)
+; RV32-NEXT: sw a0, 8(sp)
+; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu
+; RV32-NEXT: addi a0, sp, 8
+; RV32-NEXT: vlse64.v v24, (a0), zero
+; RV32-NEXT: vasub.vv v8, v16, v24, v0.t
+; RV32-NEXT: addi sp, sp, 16
+; RV32-NEXT: ret
+;
+; RV64-LABEL: intrinsic_vasub_mask_vx_nxv8i64_nxv8i64_i64:
+; RV64: # %bb.0: # %entry
+; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, mu
+; RV64-NEXT: vasub.vx v8, v16, a0, v0.t
+; RV64-NEXT: ret
entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vasub.mask.nxv8i64.i64(
<vscale x 8 x i64> %0,
<vscale x 8 x i64> %1,
i64 %2,
<vscale x 8 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 8 x i64> %a
}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vasubu-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vasubu-rv32.ll
deleted file mode 100644
index 1845da27c7b49..0000000000000
--- a/llvm/test/CodeGen/RISCV/rvv/vasubu-rv32.ll
+++ /dev/null
@@ -1,2122 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs \
-; RUN: < %s | FileCheck %s
-declare <vscale x 1 x i8> @llvm.riscv.vasubu.nxv1i8.nxv1i8(
- <vscale x 1 x i8>,
- <vscale x 1 x i8>,
- <vscale x 1 x i8>,
- i32);
-
-define <vscale x 1 x i8> @intrinsic_vasubu_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vasubu_vv_nxv1i8_nxv1i8_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
-; CHECK-NEXT: vasubu.vv v8, v8, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i8> @llvm.riscv.vasubu.nxv1i8.nxv1i8(
- <vscale x 1 x i8> undef,
- <vscale x 1 x i8> %0,
- <vscale x 1 x i8> %1,
- i32 %2)
-
- ret <vscale x 1 x i8> %a
-}
-
-declare <vscale x 1 x i8> @llvm.riscv.vasubu.mask.nxv1i8.nxv1i8(
- <vscale x 1 x i8>,
- <vscale x 1 x i8>,
- <vscale x 1 x i8>,
- <vscale x 1 x i1>,
- i32,
- i32);
-
-define <vscale x 1 x i8> @intrinsic_vasubu_mask_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv1i8_nxv1i8_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
-; CHECK-NEXT: vasubu.vv v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i8> @llvm.riscv.vasubu.mask.nxv1i8.nxv1i8(
- <vscale x 1 x i8> %0,
- <vscale x 1 x i8> %1,
- <vscale x 1 x i8> %2,
- <vscale x 1 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 1 x i8> %a
-}
-
-declare <vscale x 2 x i8> @llvm.riscv.vasubu.nxv2i8.nxv2i8(
- <vscale x 2 x i8>,
- <vscale x 2 x i8>,
- <vscale x 2 x i8>,
- i32);
-
-define <vscale x 2 x i8> @intrinsic_vasubu_vv_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vasubu_vv_nxv2i8_nxv2i8_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
-; CHECK-NEXT: vasubu.vv v8, v8, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i8> @llvm.riscv.vasubu.nxv2i8.nxv2i8(
- <vscale x 2 x i8> undef,
- <vscale x 2 x i8> %0,
- <vscale x 2 x i8> %1,
- i32 %2)
-
- ret <vscale x 2 x i8> %a
-}
-
-declare <vscale x 2 x i8> @llvm.riscv.vasubu.mask.nxv2i8.nxv2i8(
- <vscale x 2 x i8>,
- <vscale x 2 x i8>,
- <vscale x 2 x i8>,
- <vscale x 2 x i1>,
- i32,
- i32);
-
-define <vscale x 2 x i8> @intrinsic_vasubu_mask_vv_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv2i8_nxv2i8_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
-; CHECK-NEXT: vasubu.vv v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i8> @llvm.riscv.vasubu.mask.nxv2i8.nxv2i8(
- <vscale x 2 x i8> %0,
- <vscale x 2 x i8> %1,
- <vscale x 2 x i8> %2,
- <vscale x 2 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 2 x i8> %a
-}
-
-declare <vscale x 4 x i8> @llvm.riscv.vasubu.nxv4i8.nxv4i8(
- <vscale x 4 x i8>,
- <vscale x 4 x i8>,
- <vscale x 4 x i8>,
- i32);
-
-define <vscale x 4 x i8> @intrinsic_vasubu_vv_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vasubu_vv_nxv4i8_nxv4i8_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
-; CHECK-NEXT: vasubu.vv v8, v8, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i8> @llvm.riscv.vasubu.nxv4i8.nxv4i8(
- <vscale x 4 x i8> undef,
- <vscale x 4 x i8> %0,
- <vscale x 4 x i8> %1,
- i32 %2)
-
- ret <vscale x 4 x i8> %a
-}
-
-declare <vscale x 4 x i8> @llvm.riscv.vasubu.mask.nxv4i8.nxv4i8(
- <vscale x 4 x i8>,
- <vscale x 4 x i8>,
- <vscale x 4 x i8>,
- <vscale x 4 x i1>,
- i32,
- i32);
-
-define <vscale x 4 x i8> @intrinsic_vasubu_mask_vv_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv4i8_nxv4i8_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
-; CHECK-NEXT: vasubu.vv v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i8> @llvm.riscv.vasubu.mask.nxv4i8.nxv4i8(
- <vscale x 4 x i8> %0,
- <vscale x 4 x i8> %1,
- <vscale x 4 x i8> %2,
- <vscale x 4 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 4 x i8> %a
-}
-
-declare <vscale x 8 x i8> @llvm.riscv.vasubu.nxv8i8.nxv8i8(
- <vscale x 8 x i8>,
- <vscale x 8 x i8>,
- <vscale x 8 x i8>,
- i32);
-
-define <vscale x 8 x i8> @intrinsic_vasubu_vv_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vasubu_vv_nxv8i8_nxv8i8_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
-; CHECK-NEXT: vasubu.vv v8, v8, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i8> @llvm.riscv.vasubu.nxv8i8.nxv8i8(
- <vscale x 8 x i8> undef,
- <vscale x 8 x i8> %0,
- <vscale x 8 x i8> %1,
- i32 %2)
-
- ret <vscale x 8 x i8> %a
-}
-
-declare <vscale x 8 x i8> @llvm.riscv.vasubu.mask.nxv8i8.nxv8i8(
- <vscale x 8 x i8>,
- <vscale x 8 x i8>,
- <vscale x 8 x i8>,
- <vscale x 8 x i1>,
- i32,
- i32);
-
-define <vscale x 8 x i8> @intrinsic_vasubu_mask_vv_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv8i8_nxv8i8_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
-; CHECK-NEXT: vasubu.vv v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i8> @llvm.riscv.vasubu.mask.nxv8i8.nxv8i8(
- <vscale x 8 x i8> %0,
- <vscale x 8 x i8> %1,
- <vscale x 8 x i8> %2,
- <vscale x 8 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 8 x i8> %a
-}
-
-declare <vscale x 16 x i8> @llvm.riscv.vasubu.nxv16i8.nxv16i8(
- <vscale x 16 x i8>,
- <vscale x 16 x i8>,
- <vscale x 16 x i8>,
- i32);
-
-define <vscale x 16 x i8> @intrinsic_vasubu_vv_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vasubu_vv_nxv16i8_nxv16i8_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
-; CHECK-NEXT: vasubu.vv v8, v8, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i8> @llvm.riscv.vasubu.nxv16i8.nxv16i8(
- <vscale x 16 x i8> undef,
- <vscale x 16 x i8> %0,
- <vscale x 16 x i8> %1,
- i32 %2)
-
- ret <vscale x 16 x i8> %a
-}
-
-declare <vscale x 16 x i8> @llvm.riscv.vasubu.mask.nxv16i8.nxv16i8(
- <vscale x 16 x i8>,
- <vscale x 16 x i8>,
- <vscale x 16 x i8>,
- <vscale x 16 x i1>,
- i32,
- i32);
-
-define <vscale x 16 x i8> @intrinsic_vasubu_mask_vv_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv16i8_nxv16i8_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
-; CHECK-NEXT: vasubu.vv v8, v10, v12, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i8> @llvm.riscv.vasubu.mask.nxv16i8.nxv16i8(
- <vscale x 16 x i8> %0,
- <vscale x 16 x i8> %1,
- <vscale x 16 x i8> %2,
- <vscale x 16 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 16 x i8> %a
-}
-
-declare <vscale x 32 x i8> @llvm.riscv.vasubu.nxv32i8.nxv32i8(
- <vscale x 32 x i8>,
- <vscale x 32 x i8>,
- <vscale x 32 x i8>,
- i32);
-
-define <vscale x 32 x i8> @intrinsic_vasubu_vv_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vasubu_vv_nxv32i8_nxv32i8_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
-; CHECK-NEXT: vasubu.vv v8, v8, v12
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 32 x i8> @llvm.riscv.vasubu.nxv32i8.nxv32i8(
- <vscale x 32 x i8> undef,
- <vscale x 32 x i8> %0,
- <vscale x 32 x i8> %1,
- i32 %2)
-
- ret <vscale x 32 x i8> %a
-}
-
-declare <vscale x 32 x i8> @llvm.riscv.vasubu.mask.nxv32i8.nxv32i8(
- <vscale x 32 x i8>,
- <vscale x 32 x i8>,
- <vscale x 32 x i8>,
- <vscale x 32 x i1>,
- i32,
- i32);
-
-define <vscale x 32 x i8> @intrinsic_vasubu_mask_vv_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv32i8_nxv32i8_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
-; CHECK-NEXT: vasubu.vv v8, v12, v16, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 32 x i8> @llvm.riscv.vasubu.mask.nxv32i8.nxv32i8(
- <vscale x 32 x i8> %0,
- <vscale x 32 x i8> %1,
- <vscale x 32 x i8> %2,
- <vscale x 32 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 32 x i8> %a
-}
-
-declare <vscale x 64 x i8> @llvm.riscv.vasubu.nxv64i8.nxv64i8(
- <vscale x 64 x i8>,
- <vscale x 64 x i8>,
- <vscale x 64 x i8>,
- i32);
-
-define <vscale x 64 x i8> @intrinsic_vasubu_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vasubu_vv_nxv64i8_nxv64i8_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, mu
-; CHECK-NEXT: vasubu.vv v8, v8, v16
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 64 x i8> @llvm.riscv.vasubu.nxv64i8.nxv64i8(
- <vscale x 64 x i8> undef,
- <vscale x 64 x i8> %0,
- <vscale x 64 x i8> %1,
- i32 %2)
-
- ret <vscale x 64 x i8> %a
-}
-
-declare <vscale x 64 x i8> @llvm.riscv.vasubu.mask.nxv64i8.nxv64i8(
- <vscale x 64 x i8>,
- <vscale x 64 x i8>,
- <vscale x 64 x i8>,
- <vscale x 64 x i1>,
- i32,
- i32);
-
-define <vscale x 64 x i8> @intrinsic_vasubu_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv64i8_nxv64i8_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vl8r.v v24, (a0)
-; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu
-; CHECK-NEXT: vasubu.vv v8, v16, v24, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 64 x i8> @llvm.riscv.vasubu.mask.nxv64i8.nxv64i8(
- <vscale x 64 x i8> %0,
- <vscale x 64 x i8> %1,
- <vscale x 64 x i8> %2,
- <vscale x 64 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 64 x i8> %a
-}
-
-declare <vscale x 1 x i16> @llvm.riscv.vasubu.nxv1i16.nxv1i16(
- <vscale x 1 x i16>,
- <vscale x 1 x i16>,
- <vscale x 1 x i16>,
- i32);
-
-define <vscale x 1 x i16> @intrinsic_vasubu_vv_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vasubu_vv_nxv1i16_nxv1i16_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vasubu.vv v8, v8, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i16> @llvm.riscv.vasubu.nxv1i16.nxv1i16(
- <vscale x 1 x i16> undef,
- <vscale x 1 x i16> %0,
- <vscale x 1 x i16> %1,
- i32 %2)
-
- ret <vscale x 1 x i16> %a
-}
-
-declare <vscale x 1 x i16> @llvm.riscv.vasubu.mask.nxv1i16.nxv1i16(
- <vscale x 1 x i16>,
- <vscale x 1 x i16>,
- <vscale x 1 x i16>,
- <vscale x 1 x i1>,
- i32,
- i32);
-
-define <vscale x 1 x i16> @intrinsic_vasubu_mask_vv_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv1i16_nxv1i16_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vasubu.vv v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i16> @llvm.riscv.vasubu.mask.nxv1i16.nxv1i16(
- <vscale x 1 x i16> %0,
- <vscale x 1 x i16> %1,
- <vscale x 1 x i16> %2,
- <vscale x 1 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 1 x i16> %a
-}
-
-declare <vscale x 2 x i16> @llvm.riscv.vasubu.nxv2i16.nxv2i16(
- <vscale x 2 x i16>,
- <vscale x 2 x i16>,
- <vscale x 2 x i16>,
- i32);
-
-define <vscale x 2 x i16> @intrinsic_vasubu_vv_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vasubu_vv_nxv2i16_nxv2i16_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vasubu.vv v8, v8, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i16> @llvm.riscv.vasubu.nxv2i16.nxv2i16(
- <vscale x 2 x i16> undef,
- <vscale x 2 x i16> %0,
- <vscale x 2 x i16> %1,
- i32 %2)
-
- ret <vscale x 2 x i16> %a
-}
-
-declare <vscale x 2 x i16> @llvm.riscv.vasubu.mask.nxv2i16.nxv2i16(
- <vscale x 2 x i16>,
- <vscale x 2 x i16>,
- <vscale x 2 x i16>,
- <vscale x 2 x i1>,
- i32,
- i32);
-
-define <vscale x 2 x i16> @intrinsic_vasubu_mask_vv_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv2i16_nxv2i16_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vasubu.vv v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i16> @llvm.riscv.vasubu.mask.nxv2i16.nxv2i16(
- <vscale x 2 x i16> %0,
- <vscale x 2 x i16> %1,
- <vscale x 2 x i16> %2,
- <vscale x 2 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 2 x i16> %a
-}
-
-declare <vscale x 4 x i16> @llvm.riscv.vasubu.nxv4i16.nxv4i16(
- <vscale x 4 x i16>,
- <vscale x 4 x i16>,
- <vscale x 4 x i16>,
- i32);
-
-define <vscale x 4 x i16> @intrinsic_vasubu_vv_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vasubu_vv_nxv4i16_nxv4i16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vasubu.vv v8, v8, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i16> @llvm.riscv.vasubu.nxv4i16.nxv4i16(
- <vscale x 4 x i16> undef,
- <vscale x 4 x i16> %0,
- <vscale x 4 x i16> %1,
- i32 %2)
-
- ret <vscale x 4 x i16> %a
-}
-
-declare <vscale x 4 x i16> @llvm.riscv.vasubu.mask.nxv4i16.nxv4i16(
- <vscale x 4 x i16>,
- <vscale x 4 x i16>,
- <vscale x 4 x i16>,
- <vscale x 4 x i1>,
- i32,
- i32);
-
-define <vscale x 4 x i16> @intrinsic_vasubu_mask_vv_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv4i16_nxv4i16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vasubu.vv v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i16> @llvm.riscv.vasubu.mask.nxv4i16.nxv4i16(
- <vscale x 4 x i16> %0,
- <vscale x 4 x i16> %1,
- <vscale x 4 x i16> %2,
- <vscale x 4 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 4 x i16> %a
-}
-
-declare <vscale x 8 x i16> @llvm.riscv.vasubu.nxv8i16.nxv8i16(
- <vscale x 8 x i16>,
- <vscale x 8 x i16>,
- <vscale x 8 x i16>,
- i32);
-
-define <vscale x 8 x i16> @intrinsic_vasubu_vv_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vasubu_vv_nxv8i16_nxv8i16_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vasubu.vv v8, v8, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i16> @llvm.riscv.vasubu.nxv8i16.nxv8i16(
- <vscale x 8 x i16> undef,
- <vscale x 8 x i16> %0,
- <vscale x 8 x i16> %1,
- i32 %2)
-
- ret <vscale x 8 x i16> %a
-}
-
-declare <vscale x 8 x i16> @llvm.riscv.vasubu.mask.nxv8i16.nxv8i16(
- <vscale x 8 x i16>,
- <vscale x 8 x i16>,
- <vscale x 8 x i16>,
- <vscale x 8 x i1>,
- i32,
- i32);
-
-define <vscale x 8 x i16> @intrinsic_vasubu_mask_vv_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv8i16_nxv8i16_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vasubu.vv v8, v10, v12, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i16> @llvm.riscv.vasubu.mask.nxv8i16.nxv8i16(
- <vscale x 8 x i16> %0,
- <vscale x 8 x i16> %1,
- <vscale x 8 x i16> %2,
- <vscale x 8 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 8 x i16> %a
-}
-
-declare <vscale x 16 x i16> @llvm.riscv.vasubu.nxv16i16.nxv16i16(
- <vscale x 16 x i16>,
- <vscale x 16 x i16>,
- <vscale x 16 x i16>,
- i32);
-
-define <vscale x 16 x i16> @intrinsic_vasubu_vv_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vasubu_vv_nxv16i16_nxv16i16_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
-; CHECK-NEXT: vasubu.vv v8, v8, v12
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i16> @llvm.riscv.vasubu.nxv16i16.nxv16i16(
- <vscale x 16 x i16> undef,
- <vscale x 16 x i16> %0,
- <vscale x 16 x i16> %1,
- i32 %2)
-
- ret <vscale x 16 x i16> %a
-}
-
-declare <vscale x 16 x i16> @llvm.riscv.vasubu.mask.nxv16i16.nxv16i16(
- <vscale x 16 x i16>,
- <vscale x 16 x i16>,
- <vscale x 16 x i16>,
- <vscale x 16 x i1>,
- i32,
- i32);
-
-define <vscale x 16 x i16> @intrinsic_vasubu_mask_vv_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv16i16_nxv16i16_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
-; CHECK-NEXT: vasubu.vv v8, v12, v16, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i16> @llvm.riscv.vasubu.mask.nxv16i16.nxv16i16(
- <vscale x 16 x i16> %0,
- <vscale x 16 x i16> %1,
- <vscale x 16 x i16> %2,
- <vscale x 16 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 16 x i16> %a
-}
-
-declare <vscale x 32 x i16> @llvm.riscv.vasubu.nxv32i16.nxv32i16(
- <vscale x 32 x i16>,
- <vscale x 32 x i16>,
- <vscale x 32 x i16>,
- i32);
-
-define <vscale x 32 x i16> @intrinsic_vasubu_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vasubu_vv_nxv32i16_nxv32i16_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, mu
-; CHECK-NEXT: vasubu.vv v8, v8, v16
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 32 x i16> @llvm.riscv.vasubu.nxv32i16.nxv32i16(
- <vscale x 32 x i16> undef,
- <vscale x 32 x i16> %0,
- <vscale x 32 x i16> %1,
- i32 %2)
-
- ret <vscale x 32 x i16> %a
-}
-
-declare <vscale x 32 x i16> @llvm.riscv.vasubu.mask.nxv32i16.nxv32i16(
- <vscale x 32 x i16>,
- <vscale x 32 x i16>,
- <vscale x 32 x i16>,
- <vscale x 32 x i1>,
- i32,
- i32);
-
-define <vscale x 32 x i16> @intrinsic_vasubu_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv32i16_nxv32i16_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vl8re16.v v24, (a0)
-; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu
-; CHECK-NEXT: vasubu.vv v8, v16, v24, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 32 x i16> @llvm.riscv.vasubu.mask.nxv32i16.nxv32i16(
- <vscale x 32 x i16> %0,
- <vscale x 32 x i16> %1,
- <vscale x 32 x i16> %2,
- <vscale x 32 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 32 x i16> %a
-}
-
-declare <vscale x 1 x i32> @llvm.riscv.vasubu.nxv1i32.nxv1i32(
- <vscale x 1 x i32>,
- <vscale x 1 x i32>,
- <vscale x 1 x i32>,
- i32);
-
-define <vscale x 1 x i32> @intrinsic_vasubu_vv_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vasubu_vv_nxv1i32_nxv1i32_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vasubu.vv v8, v8, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i32> @llvm.riscv.vasubu.nxv1i32.nxv1i32(
- <vscale x 1 x i32> undef,
- <vscale x 1 x i32> %0,
- <vscale x 1 x i32> %1,
- i32 %2)
-
- ret <vscale x 1 x i32> %a
-}
-
-declare <vscale x 1 x i32> @llvm.riscv.vasubu.mask.nxv1i32.nxv1i32(
- <vscale x 1 x i32>,
- <vscale x 1 x i32>,
- <vscale x 1 x i32>,
- <vscale x 1 x i1>,
- i32,
- i32);
-
-define <vscale x 1 x i32> @intrinsic_vasubu_mask_vv_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv1i32_nxv1i32_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vasubu.vv v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i32> @llvm.riscv.vasubu.mask.nxv1i32.nxv1i32(
- <vscale x 1 x i32> %0,
- <vscale x 1 x i32> %1,
- <vscale x 1 x i32> %2,
- <vscale x 1 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 1 x i32> %a
-}
-
-declare <vscale x 2 x i32> @llvm.riscv.vasubu.nxv2i32.nxv2i32(
- <vscale x 2 x i32>,
- <vscale x 2 x i32>,
- <vscale x 2 x i32>,
- i32);
-
-define <vscale x 2 x i32> @intrinsic_vasubu_vv_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vasubu_vv_nxv2i32_nxv2i32_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vasubu.vv v8, v8, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i32> @llvm.riscv.vasubu.nxv2i32.nxv2i32(
- <vscale x 2 x i32> undef,
- <vscale x 2 x i32> %0,
- <vscale x 2 x i32> %1,
- i32 %2)
-
- ret <vscale x 2 x i32> %a
-}
-
-declare <vscale x 2 x i32> @llvm.riscv.vasubu.mask.nxv2i32.nxv2i32(
- <vscale x 2 x i32>,
- <vscale x 2 x i32>,
- <vscale x 2 x i32>,
- <vscale x 2 x i1>,
- i32,
- i32);
-
-define <vscale x 2 x i32> @intrinsic_vasubu_mask_vv_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv2i32_nxv2i32_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vasubu.vv v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i32> @llvm.riscv.vasubu.mask.nxv2i32.nxv2i32(
- <vscale x 2 x i32> %0,
- <vscale x 2 x i32> %1,
- <vscale x 2 x i32> %2,
- <vscale x 2 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 2 x i32> %a
-}
-
-declare <vscale x 4 x i32> @llvm.riscv.vasubu.nxv4i32.nxv4i32(
- <vscale x 4 x i32>,
- <vscale x 4 x i32>,
- <vscale x 4 x i32>,
- i32);
-
-define <vscale x 4 x i32> @intrinsic_vasubu_vv_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vasubu_vv_nxv4i32_nxv4i32_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vasubu.vv v8, v8, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i32> @llvm.riscv.vasubu.nxv4i32.nxv4i32(
- <vscale x 4 x i32> undef,
- <vscale x 4 x i32> %0,
- <vscale x 4 x i32> %1,
- i32 %2)
-
- ret <vscale x 4 x i32> %a
-}
-
-declare <vscale x 4 x i32> @llvm.riscv.vasubu.mask.nxv4i32.nxv4i32(
- <vscale x 4 x i32>,
- <vscale x 4 x i32>,
- <vscale x 4 x i32>,
- <vscale x 4 x i1>,
- i32,
- i32);
-
-define <vscale x 4 x i32> @intrinsic_vasubu_mask_vv_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv4i32_nxv4i32_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vasubu.vv v8, v10, v12, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i32> @llvm.riscv.vasubu.mask.nxv4i32.nxv4i32(
- <vscale x 4 x i32> %0,
- <vscale x 4 x i32> %1,
- <vscale x 4 x i32> %2,
- <vscale x 4 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 4 x i32> %a
-}
-
-declare <vscale x 8 x i32> @llvm.riscv.vasubu.nxv8i32.nxv8i32(
- <vscale x 8 x i32>,
- <vscale x 8 x i32>,
- <vscale x 8 x i32>,
- i32);
-
-define <vscale x 8 x i32> @intrinsic_vasubu_vv_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vasubu_vv_nxv8i32_nxv8i32_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
-; CHECK-NEXT: vasubu.vv v8, v8, v12
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i32> @llvm.riscv.vasubu.nxv8i32.nxv8i32(
- <vscale x 8 x i32> undef,
- <vscale x 8 x i32> %0,
- <vscale x 8 x i32> %1,
- i32 %2)
-
- ret <vscale x 8 x i32> %a
-}
-
-declare <vscale x 8 x i32> @llvm.riscv.vasubu.mask.nxv8i32.nxv8i32(
- <vscale x 8 x i32>,
- <vscale x 8 x i32>,
- <vscale x 8 x i32>,
- <vscale x 8 x i1>,
- i32,
- i32);
-
-define <vscale x 8 x i32> @intrinsic_vasubu_mask_vv_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv8i32_nxv8i32_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
-; CHECK-NEXT: vasubu.vv v8, v12, v16, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i32> @llvm.riscv.vasubu.mask.nxv8i32.nxv8i32(
- <vscale x 8 x i32> %0,
- <vscale x 8 x i32> %1,
- <vscale x 8 x i32> %2,
- <vscale x 8 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 8 x i32> %a
-}
-
-declare <vscale x 16 x i32> @llvm.riscv.vasubu.nxv16i32.nxv16i32(
- <vscale x 16 x i32>,
- <vscale x 16 x i32>,
- <vscale x 16 x i32>,
- i32);
-
-define <vscale x 16 x i32> @intrinsic_vasubu_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vasubu_vv_nxv16i32_nxv16i32_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu
-; CHECK-NEXT: vasubu.vv v8, v8, v16
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i32> @llvm.riscv.vasubu.nxv16i32.nxv16i32(
- <vscale x 16 x i32> undef,
- <vscale x 16 x i32> %0,
- <vscale x 16 x i32> %1,
- i32 %2)
-
- ret <vscale x 16 x i32> %a
-}
-
-declare <vscale x 16 x i32> @llvm.riscv.vasubu.mask.nxv16i32.nxv16i32(
- <vscale x 16 x i32>,
- <vscale x 16 x i32>,
- <vscale x 16 x i32>,
- <vscale x 16 x i1>,
- i32,
- i32);
-
-define <vscale x 16 x i32> @intrinsic_vasubu_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv16i32_nxv16i32_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vl8re32.v v24, (a0)
-; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu
-; CHECK-NEXT: vasubu.vv v8, v16, v24, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i32> @llvm.riscv.vasubu.mask.nxv16i32.nxv16i32(
- <vscale x 16 x i32> %0,
- <vscale x 16 x i32> %1,
- <vscale x 16 x i32> %2,
- <vscale x 16 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 16 x i32> %a
-}
-
-declare <vscale x 1 x i64> @llvm.riscv.vasubu.nxv1i64.nxv1i64(
- <vscale x 1 x i64>,
- <vscale x 1 x i64>,
- <vscale x 1 x i64>,
- i32);
-
-define <vscale x 1 x i64> @intrinsic_vasubu_vv_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vasubu_vv_nxv1i64_nxv1i64_nxv1i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
-; CHECK-NEXT: vasubu.vv v8, v8, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i64> @llvm.riscv.vasubu.nxv1i64.nxv1i64(
- <vscale x 1 x i64> undef,
- <vscale x 1 x i64> %0,
- <vscale x 1 x i64> %1,
- i32 %2)
-
- ret <vscale x 1 x i64> %a
-}
-
-declare <vscale x 1 x i64> @llvm.riscv.vasubu.mask.nxv1i64.nxv1i64(
- <vscale x 1 x i64>,
- <vscale x 1 x i64>,
- <vscale x 1 x i64>,
- <vscale x 1 x i1>,
- i32,
- i32);
-
-define <vscale x 1 x i64> @intrinsic_vasubu_mask_vv_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv1i64_nxv1i64_nxv1i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
-; CHECK-NEXT: vasubu.vv v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i64> @llvm.riscv.vasubu.mask.nxv1i64.nxv1i64(
- <vscale x 1 x i64> %0,
- <vscale x 1 x i64> %1,
- <vscale x 1 x i64> %2,
- <vscale x 1 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 1 x i64> %a
-}
-
-declare <vscale x 2 x i64> @llvm.riscv.vasubu.nxv2i64.nxv2i64(
- <vscale x 2 x i64>,
- <vscale x 2 x i64>,
- <vscale x 2 x i64>,
- i32);
-
-define <vscale x 2 x i64> @intrinsic_vasubu_vv_nxv2i64_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vasubu_vv_nxv2i64_nxv2i64_nxv2i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
-; CHECK-NEXT: vasubu.vv v8, v8, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i64> @llvm.riscv.vasubu.nxv2i64.nxv2i64(
- <vscale x 2 x i64> undef,
- <vscale x 2 x i64> %0,
- <vscale x 2 x i64> %1,
- i32 %2)
-
- ret <vscale x 2 x i64> %a
-}
-
-declare <vscale x 2 x i64> @llvm.riscv.vasubu.mask.nxv2i64.nxv2i64(
- <vscale x 2 x i64>,
- <vscale x 2 x i64>,
- <vscale x 2 x i64>,
- <vscale x 2 x i1>,
- i32,
- i32);
-
-define <vscale x 2 x i64> @intrinsic_vasubu_mask_vv_nxv2i64_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv2i64_nxv2i64_nxv2i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
-; CHECK-NEXT: vasubu.vv v8, v10, v12, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i64> @llvm.riscv.vasubu.mask.nxv2i64.nxv2i64(
- <vscale x 2 x i64> %0,
- <vscale x 2 x i64> %1,
- <vscale x 2 x i64> %2,
- <vscale x 2 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 2 x i64> %a
-}
-
-declare <vscale x 4 x i64> @llvm.riscv.vasubu.nxv4i64.nxv4i64(
- <vscale x 4 x i64>,
- <vscale x 4 x i64>,
- <vscale x 4 x i64>,
- i32);
-
-define <vscale x 4 x i64> @intrinsic_vasubu_vv_nxv4i64_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vasubu_vv_nxv4i64_nxv4i64_nxv4i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
-; CHECK-NEXT: vasubu.vv v8, v8, v12
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i64> @llvm.riscv.vasubu.nxv4i64.nxv4i64(
- <vscale x 4 x i64> undef,
- <vscale x 4 x i64> %0,
- <vscale x 4 x i64> %1,
- i32 %2)
-
- ret <vscale x 4 x i64> %a
-}
-
-declare <vscale x 4 x i64> @llvm.riscv.vasubu.mask.nxv4i64.nxv4i64(
- <vscale x 4 x i64>,
- <vscale x 4 x i64>,
- <vscale x 4 x i64>,
- <vscale x 4 x i1>,
- i32,
- i32);
-
-define <vscale x 4 x i64> @intrinsic_vasubu_mask_vv_nxv4i64_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv4i64_nxv4i64_nxv4i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
-; CHECK-NEXT: vasubu.vv v8, v12, v16, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i64> @llvm.riscv.vasubu.mask.nxv4i64.nxv4i64(
- <vscale x 4 x i64> %0,
- <vscale x 4 x i64> %1,
- <vscale x 4 x i64> %2,
- <vscale x 4 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 4 x i64> %a
-}
-
-declare <vscale x 8 x i64> @llvm.riscv.vasubu.nxv8i64.nxv8i64(
- <vscale x 8 x i64>,
- <vscale x 8 x i64>,
- <vscale x 8 x i64>,
- i32);
-
-define <vscale x 8 x i64> @intrinsic_vasubu_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vasubu_vv_nxv8i64_nxv8i64_nxv8i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu
-; CHECK-NEXT: vasubu.vv v8, v8, v16
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i64> @llvm.riscv.vasubu.nxv8i64.nxv8i64(
- <vscale x 8 x i64> undef,
- <vscale x 8 x i64> %0,
- <vscale x 8 x i64> %1,
- i32 %2)
-
- ret <vscale x 8 x i64> %a
-}
-
-declare <vscale x 8 x i64> @llvm.riscv.vasubu.mask.nxv8i64.nxv8i64(
- <vscale x 8 x i64>,
- <vscale x 8 x i64>,
- <vscale x 8 x i64>,
- <vscale x 8 x i1>,
- i32,
- i32);
-
-define <vscale x 8 x i64> @intrinsic_vasubu_mask_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv8i64_nxv8i64_nxv8i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vl8re64.v v24, (a0)
-; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu
-; CHECK-NEXT: vasubu.vv v8, v16, v24, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i64> @llvm.riscv.vasubu.mask.nxv8i64.nxv8i64(
- <vscale x 8 x i64> %0,
- <vscale x 8 x i64> %1,
- <vscale x 8 x i64> %2,
- <vscale x 8 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 8 x i64> %a
-}
-
-declare <vscale x 1 x i8> @llvm.riscv.vasubu.nxv1i8.i8(
- <vscale x 1 x i8>,
- <vscale x 1 x i8>,
- i8,
- i32);
-
-define <vscale x 1 x i8> @intrinsic_vasubu_vx_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, i8 %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vasubu_vx_nxv1i8_nxv1i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
-; CHECK-NEXT: vasubu.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i8> @llvm.riscv.vasubu.nxv1i8.i8(
- <vscale x 1 x i8> undef,
- <vscale x 1 x i8> %0,
- i8 %1,
- i32 %2)
-
- ret <vscale x 1 x i8> %a
-}
-
-declare <vscale x 1 x i8> @llvm.riscv.vasubu.mask.nxv1i8.i8(
- <vscale x 1 x i8>,
- <vscale x 1 x i8>,
- i8,
- <vscale x 1 x i1>,
- i32,
- i32);
-
-define <vscale x 1 x i8> @intrinsic_vasubu_mask_vx_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv1i8_nxv1i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
-; CHECK-NEXT: vasubu.vx v8, v9, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i8> @llvm.riscv.vasubu.mask.nxv1i8.i8(
- <vscale x 1 x i8> %0,
- <vscale x 1 x i8> %1,
- i8 %2,
- <vscale x 1 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 1 x i8> %a
-}
-
-declare <vscale x 2 x i8> @llvm.riscv.vasubu.nxv2i8.i8(
- <vscale x 2 x i8>,
- <vscale x 2 x i8>,
- i8,
- i32);
-
-define <vscale x 2 x i8> @intrinsic_vasubu_vx_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, i8 %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vasubu_vx_nxv2i8_nxv2i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
-; CHECK-NEXT: vasubu.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i8> @llvm.riscv.vasubu.nxv2i8.i8(
- <vscale x 2 x i8> undef,
- <vscale x 2 x i8> %0,
- i8 %1,
- i32 %2)
-
- ret <vscale x 2 x i8> %a
-}
-
-declare <vscale x 2 x i8> @llvm.riscv.vasubu.mask.nxv2i8.i8(
- <vscale x 2 x i8>,
- <vscale x 2 x i8>,
- i8,
- <vscale x 2 x i1>,
- i32,
- i32);
-
-define <vscale x 2 x i8> @intrinsic_vasubu_mask_vx_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv2i8_nxv2i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
-; CHECK-NEXT: vasubu.vx v8, v9, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i8> @llvm.riscv.vasubu.mask.nxv2i8.i8(
- <vscale x 2 x i8> %0,
- <vscale x 2 x i8> %1,
- i8 %2,
- <vscale x 2 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 2 x i8> %a
-}
-
-declare <vscale x 4 x i8> @llvm.riscv.vasubu.nxv4i8.i8(
- <vscale x 4 x i8>,
- <vscale x 4 x i8>,
- i8,
- i32);
-
-define <vscale x 4 x i8> @intrinsic_vasubu_vx_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, i8 %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vasubu_vx_nxv4i8_nxv4i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
-; CHECK-NEXT: vasubu.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i8> @llvm.riscv.vasubu.nxv4i8.i8(
- <vscale x 4 x i8> undef,
- <vscale x 4 x i8> %0,
- i8 %1,
- i32 %2)
-
- ret <vscale x 4 x i8> %a
-}
-
-declare <vscale x 4 x i8> @llvm.riscv.vasubu.mask.nxv4i8.i8(
- <vscale x 4 x i8>,
- <vscale x 4 x i8>,
- i8,
- <vscale x 4 x i1>,
- i32,
- i32);
-
-define <vscale x 4 x i8> @intrinsic_vasubu_mask_vx_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv4i8_nxv4i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
-; CHECK-NEXT: vasubu.vx v8, v9, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i8> @llvm.riscv.vasubu.mask.nxv4i8.i8(
- <vscale x 4 x i8> %0,
- <vscale x 4 x i8> %1,
- i8 %2,
- <vscale x 4 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 4 x i8> %a
-}
-
-declare <vscale x 8 x i8> @llvm.riscv.vasubu.nxv8i8.i8(
- <vscale x 8 x i8>,
- <vscale x 8 x i8>,
- i8,
- i32);
-
-define <vscale x 8 x i8> @intrinsic_vasubu_vx_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, i8 %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vasubu_vx_nxv8i8_nxv8i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
-; CHECK-NEXT: vasubu.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i8> @llvm.riscv.vasubu.nxv8i8.i8(
- <vscale x 8 x i8> undef,
- <vscale x 8 x i8> %0,
- i8 %1,
- i32 %2)
-
- ret <vscale x 8 x i8> %a
-}
-
-declare <vscale x 8 x i8> @llvm.riscv.vasubu.mask.nxv8i8.i8(
- <vscale x 8 x i8>,
- <vscale x 8 x i8>,
- i8,
- <vscale x 8 x i1>,
- i32,
- i32);
-
-define <vscale x 8 x i8> @intrinsic_vasubu_mask_vx_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv8i8_nxv8i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
-; CHECK-NEXT: vasubu.vx v8, v9, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i8> @llvm.riscv.vasubu.mask.nxv8i8.i8(
- <vscale x 8 x i8> %0,
- <vscale x 8 x i8> %1,
- i8 %2,
- <vscale x 8 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 8 x i8> %a
-}
-
-declare <vscale x 16 x i8> @llvm.riscv.vasubu.nxv16i8.i8(
- <vscale x 16 x i8>,
- <vscale x 16 x i8>,
- i8,
- i32);
-
-define <vscale x 16 x i8> @intrinsic_vasubu_vx_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, i8 %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vasubu_vx_nxv16i8_nxv16i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
-; CHECK-NEXT: vasubu.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i8> @llvm.riscv.vasubu.nxv16i8.i8(
- <vscale x 16 x i8> undef,
- <vscale x 16 x i8> %0,
- i8 %1,
- i32 %2)
-
- ret <vscale x 16 x i8> %a
-}
-
-declare <vscale x 16 x i8> @llvm.riscv.vasubu.mask.nxv16i8.i8(
- <vscale x 16 x i8>,
- <vscale x 16 x i8>,
- i8,
- <vscale x 16 x i1>,
- i32,
- i32);
-
-define <vscale x 16 x i8> @intrinsic_vasubu_mask_vx_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv16i8_nxv16i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
-; CHECK-NEXT: vasubu.vx v8, v10, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i8> @llvm.riscv.vasubu.mask.nxv16i8.i8(
- <vscale x 16 x i8> %0,
- <vscale x 16 x i8> %1,
- i8 %2,
- <vscale x 16 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 16 x i8> %a
-}
-
-declare <vscale x 32 x i8> @llvm.riscv.vasubu.nxv32i8.i8(
- <vscale x 32 x i8>,
- <vscale x 32 x i8>,
- i8,
- i32);
-
-define <vscale x 32 x i8> @intrinsic_vasubu_vx_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, i8 %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vasubu_vx_nxv32i8_nxv32i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
-; CHECK-NEXT: vasubu.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 32 x i8> @llvm.riscv.vasubu.nxv32i8.i8(
- <vscale x 32 x i8> undef,
- <vscale x 32 x i8> %0,
- i8 %1,
- i32 %2)
-
- ret <vscale x 32 x i8> %a
-}
-
-declare <vscale x 32 x i8> @llvm.riscv.vasubu.mask.nxv32i8.i8(
- <vscale x 32 x i8>,
- <vscale x 32 x i8>,
- i8,
- <vscale x 32 x i1>,
- i32,
- i32);
-
-define <vscale x 32 x i8> @intrinsic_vasubu_mask_vx_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv32i8_nxv32i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
-; CHECK-NEXT: vasubu.vx v8, v12, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 32 x i8> @llvm.riscv.vasubu.mask.nxv32i8.i8(
- <vscale x 32 x i8> %0,
- <vscale x 32 x i8> %1,
- i8 %2,
- <vscale x 32 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 32 x i8> %a
-}
-
-declare <vscale x 64 x i8> @llvm.riscv.vasubu.nxv64i8.i8(
- <vscale x 64 x i8>,
- <vscale x 64 x i8>,
- i8,
- i32);
-
-define <vscale x 64 x i8> @intrinsic_vasubu_vx_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, i8 %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vasubu_vx_nxv64i8_nxv64i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu
-; CHECK-NEXT: vasubu.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 64 x i8> @llvm.riscv.vasubu.nxv64i8.i8(
- <vscale x 64 x i8> undef,
- <vscale x 64 x i8> %0,
- i8 %1,
- i32 %2)
-
- ret <vscale x 64 x i8> %a
-}
-
-declare <vscale x 64 x i8> @llvm.riscv.vasubu.mask.nxv64i8.i8(
- <vscale x 64 x i8>,
- <vscale x 64 x i8>,
- i8,
- <vscale x 64 x i1>,
- i32,
- i32);
-
-define <vscale x 64 x i8> @intrinsic_vasubu_mask_vx_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i8 %2, <vscale x 64 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv64i8_nxv64i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu
-; CHECK-NEXT: vasubu.vx v8, v16, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 64 x i8> @llvm.riscv.vasubu.mask.nxv64i8.i8(
- <vscale x 64 x i8> %0,
- <vscale x 64 x i8> %1,
- i8 %2,
- <vscale x 64 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 64 x i8> %a
-}
-
-declare <vscale x 1 x i16> @llvm.riscv.vasubu.nxv1i16.i16(
- <vscale x 1 x i16>,
- <vscale x 1 x i16>,
- i16,
- i32);
-
-define <vscale x 1 x i16> @intrinsic_vasubu_vx_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, i16 %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vasubu_vx_nxv1i16_nxv1i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
-; CHECK-NEXT: vasubu.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i16> @llvm.riscv.vasubu.nxv1i16.i16(
- <vscale x 1 x i16> undef,
- <vscale x 1 x i16> %0,
- i16 %1,
- i32 %2)
-
- ret <vscale x 1 x i16> %a
-}
-
-declare <vscale x 1 x i16> @llvm.riscv.vasubu.mask.nxv1i16.i16(
- <vscale x 1 x i16>,
- <vscale x 1 x i16>,
- i16,
- <vscale x 1 x i1>,
- i32,
- i32);
-
-define <vscale x 1 x i16> @intrinsic_vasubu_mask_vx_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv1i16_nxv1i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
-; CHECK-NEXT: vasubu.vx v8, v9, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i16> @llvm.riscv.vasubu.mask.nxv1i16.i16(
- <vscale x 1 x i16> %0,
- <vscale x 1 x i16> %1,
- i16 %2,
- <vscale x 1 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 1 x i16> %a
-}
-
-declare <vscale x 2 x i16> @llvm.riscv.vasubu.nxv2i16.i16(
- <vscale x 2 x i16>,
- <vscale x 2 x i16>,
- i16,
- i32);
-
-define <vscale x 2 x i16> @intrinsic_vasubu_vx_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, i16 %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vasubu_vx_nxv2i16_nxv2i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
-; CHECK-NEXT: vasubu.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i16> @llvm.riscv.vasubu.nxv2i16.i16(
- <vscale x 2 x i16> undef,
- <vscale x 2 x i16> %0,
- i16 %1,
- i32 %2)
-
- ret <vscale x 2 x i16> %a
-}
-
-declare <vscale x 2 x i16> @llvm.riscv.vasubu.mask.nxv2i16.i16(
- <vscale x 2 x i16>,
- <vscale x 2 x i16>,
- i16,
- <vscale x 2 x i1>,
- i32,
- i32);
-
-define <vscale x 2 x i16> @intrinsic_vasubu_mask_vx_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv2i16_nxv2i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
-; CHECK-NEXT: vasubu.vx v8, v9, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i16> @llvm.riscv.vasubu.mask.nxv2i16.i16(
- <vscale x 2 x i16> %0,
- <vscale x 2 x i16> %1,
- i16 %2,
- <vscale x 2 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 2 x i16> %a
-}
-
-declare <vscale x 4 x i16> @llvm.riscv.vasubu.nxv4i16.i16(
- <vscale x 4 x i16>,
- <vscale x 4 x i16>,
- i16,
- i32);
-
-define <vscale x 4 x i16> @intrinsic_vasubu_vx_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, i16 %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vasubu_vx_nxv4i16_nxv4i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
-; CHECK-NEXT: vasubu.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i16> @llvm.riscv.vasubu.nxv4i16.i16(
- <vscale x 4 x i16> undef,
- <vscale x 4 x i16> %0,
- i16 %1,
- i32 %2)
-
- ret <vscale x 4 x i16> %a
-}
-
-declare <vscale x 4 x i16> @llvm.riscv.vasubu.mask.nxv4i16.i16(
- <vscale x 4 x i16>,
- <vscale x 4 x i16>,
- i16,
- <vscale x 4 x i1>,
- i32,
- i32);
-
-define <vscale x 4 x i16> @intrinsic_vasubu_mask_vx_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv4i16_nxv4i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
-; CHECK-NEXT: vasubu.vx v8, v9, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i16> @llvm.riscv.vasubu.mask.nxv4i16.i16(
- <vscale x 4 x i16> %0,
- <vscale x 4 x i16> %1,
- i16 %2,
- <vscale x 4 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 4 x i16> %a
-}
-
-declare <vscale x 8 x i16> @llvm.riscv.vasubu.nxv8i16.i16(
- <vscale x 8 x i16>,
- <vscale x 8 x i16>,
- i16,
- i32);
-
-define <vscale x 8 x i16> @intrinsic_vasubu_vx_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, i16 %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vasubu_vx_nxv8i16_nxv8i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
-; CHECK-NEXT: vasubu.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i16> @llvm.riscv.vasubu.nxv8i16.i16(
- <vscale x 8 x i16> undef,
- <vscale x 8 x i16> %0,
- i16 %1,
- i32 %2)
-
- ret <vscale x 8 x i16> %a
-}
-
-declare <vscale x 8 x i16> @llvm.riscv.vasubu.mask.nxv8i16.i16(
- <vscale x 8 x i16>,
- <vscale x 8 x i16>,
- i16,
- <vscale x 8 x i1>,
- i32,
- i32);
-
-define <vscale x 8 x i16> @intrinsic_vasubu_mask_vx_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv8i16_nxv8i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
-; CHECK-NEXT: vasubu.vx v8, v10, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i16> @llvm.riscv.vasubu.mask.nxv8i16.i16(
- <vscale x 8 x i16> %0,
- <vscale x 8 x i16> %1,
- i16 %2,
- <vscale x 8 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 8 x i16> %a
-}
-
-declare <vscale x 16 x i16> @llvm.riscv.vasubu.nxv16i16.i16(
- <vscale x 16 x i16>,
- <vscale x 16 x i16>,
- i16,
- i32);
-
-define <vscale x 16 x i16> @intrinsic_vasubu_vx_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, i16 %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vasubu_vx_nxv16i16_nxv16i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
-; CHECK-NEXT: vasubu.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i16> @llvm.riscv.vasubu.nxv16i16.i16(
- <vscale x 16 x i16> undef,
- <vscale x 16 x i16> %0,
- i16 %1,
- i32 %2)
-
- ret <vscale x 16 x i16> %a
-}
-
-declare <vscale x 16 x i16> @llvm.riscv.vasubu.mask.nxv16i16.i16(
- <vscale x 16 x i16>,
- <vscale x 16 x i16>,
- i16,
- <vscale x 16 x i1>,
- i32,
- i32);
-
-define <vscale x 16 x i16> @intrinsic_vasubu_mask_vx_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv16i16_nxv16i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
-; CHECK-NEXT: vasubu.vx v8, v12, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i16> @llvm.riscv.vasubu.mask.nxv16i16.i16(
- <vscale x 16 x i16> %0,
- <vscale x 16 x i16> %1,
- i16 %2,
- <vscale x 16 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 16 x i16> %a
-}
-
-declare <vscale x 32 x i16> @llvm.riscv.vasubu.nxv32i16.i16(
- <vscale x 32 x i16>,
- <vscale x 32 x i16>,
- i16,
- i32);
-
-define <vscale x 32 x i16> @intrinsic_vasubu_vx_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, i16 %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vasubu_vx_nxv32i16_nxv32i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu
-; CHECK-NEXT: vasubu.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 32 x i16> @llvm.riscv.vasubu.nxv32i16.i16(
- <vscale x 32 x i16> undef,
- <vscale x 32 x i16> %0,
- i16 %1,
- i32 %2)
-
- ret <vscale x 32 x i16> %a
-}
-
-declare <vscale x 32 x i16> @llvm.riscv.vasubu.mask.nxv32i16.i16(
- <vscale x 32 x i16>,
- <vscale x 32 x i16>,
- i16,
- <vscale x 32 x i1>,
- i32,
- i32);
-
-define <vscale x 32 x i16> @intrinsic_vasubu_mask_vx_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, i16 %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv32i16_nxv32i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu
-; CHECK-NEXT: vasubu.vx v8, v16, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 32 x i16> @llvm.riscv.vasubu.mask.nxv32i16.i16(
- <vscale x 32 x i16> %0,
- <vscale x 32 x i16> %1,
- i16 %2,
- <vscale x 32 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 32 x i16> %a
-}
-
-declare <vscale x 1 x i32> @llvm.riscv.vasubu.nxv1i32.i32(
- <vscale x 1 x i32>,
- <vscale x 1 x i32>,
- i32,
- i32);
-
-define <vscale x 1 x i32> @intrinsic_vasubu_vx_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, i32 %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vasubu_vx_nxv1i32_nxv1i32_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
-; CHECK-NEXT: vasubu.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i32> @llvm.riscv.vasubu.nxv1i32.i32(
- <vscale x 1 x i32> undef,
- <vscale x 1 x i32> %0,
- i32 %1,
- i32 %2)
-
- ret <vscale x 1 x i32> %a
-}
-
-declare <vscale x 1 x i32> @llvm.riscv.vasubu.mask.nxv1i32.i32(
- <vscale x 1 x i32>,
- <vscale x 1 x i32>,
- i32,
- <vscale x 1 x i1>,
- i32,
- i32);
-
-define <vscale x 1 x i32> @intrinsic_vasubu_mask_vx_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv1i32_nxv1i32_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
-; CHECK-NEXT: vasubu.vx v8, v9, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i32> @llvm.riscv.vasubu.mask.nxv1i32.i32(
- <vscale x 1 x i32> %0,
- <vscale x 1 x i32> %1,
- i32 %2,
- <vscale x 1 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 1 x i32> %a
-}
-
-declare <vscale x 2 x i32> @llvm.riscv.vasubu.nxv2i32.i32(
- <vscale x 2 x i32>,
- <vscale x 2 x i32>,
- i32,
- i32);
-
-define <vscale x 2 x i32> @intrinsic_vasubu_vx_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, i32 %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vasubu_vx_nxv2i32_nxv2i32_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
-; CHECK-NEXT: vasubu.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i32> @llvm.riscv.vasubu.nxv2i32.i32(
- <vscale x 2 x i32> undef,
- <vscale x 2 x i32> %0,
- i32 %1,
- i32 %2)
-
- ret <vscale x 2 x i32> %a
-}
-
-declare <vscale x 2 x i32> @llvm.riscv.vasubu.mask.nxv2i32.i32(
- <vscale x 2 x i32>,
- <vscale x 2 x i32>,
- i32,
- <vscale x 2 x i1>,
- i32,
- i32);
-
-define <vscale x 2 x i32> @intrinsic_vasubu_mask_vx_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv2i32_nxv2i32_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
-; CHECK-NEXT: vasubu.vx v8, v9, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i32> @llvm.riscv.vasubu.mask.nxv2i32.i32(
- <vscale x 2 x i32> %0,
- <vscale x 2 x i32> %1,
- i32 %2,
- <vscale x 2 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 2 x i32> %a
-}
-
-declare <vscale x 4 x i32> @llvm.riscv.vasubu.nxv4i32.i32(
- <vscale x 4 x i32>,
- <vscale x 4 x i32>,
- i32,
- i32);
-
-define <vscale x 4 x i32> @intrinsic_vasubu_vx_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, i32 %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vasubu_vx_nxv4i32_nxv4i32_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; CHECK-NEXT: vasubu.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i32> @llvm.riscv.vasubu.nxv4i32.i32(
- <vscale x 4 x i32> undef,
- <vscale x 4 x i32> %0,
- i32 %1,
- i32 %2)
-
- ret <vscale x 4 x i32> %a
-}
-
-declare <vscale x 4 x i32> @llvm.riscv.vasubu.mask.nxv4i32.i32(
- <vscale x 4 x i32>,
- <vscale x 4 x i32>,
- i32,
- <vscale x 4 x i1>,
- i32,
- i32);
-
-define <vscale x 4 x i32> @intrinsic_vasubu_mask_vx_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv4i32_nxv4i32_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; CHECK-NEXT: vasubu.vx v8, v10, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i32> @llvm.riscv.vasubu.mask.nxv4i32.i32(
- <vscale x 4 x i32> %0,
- <vscale x 4 x i32> %1,
- i32 %2,
- <vscale x 4 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 4 x i32> %a
-}
-
-declare <vscale x 8 x i32> @llvm.riscv.vasubu.nxv8i32.i32(
- <vscale x 8 x i32>,
- <vscale x 8 x i32>,
- i32,
- i32);
-
-define <vscale x 8 x i32> @intrinsic_vasubu_vx_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, i32 %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vasubu_vx_nxv8i32_nxv8i32_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
-; CHECK-NEXT: vasubu.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i32> @llvm.riscv.vasubu.nxv8i32.i32(
- <vscale x 8 x i32> undef,
- <vscale x 8 x i32> %0,
- i32 %1,
- i32 %2)
-
- ret <vscale x 8 x i32> %a
-}
-
-declare <vscale x 8 x i32> @llvm.riscv.vasubu.mask.nxv8i32.i32(
- <vscale x 8 x i32>,
- <vscale x 8 x i32>,
- i32,
- <vscale x 8 x i1>,
- i32,
- i32);
-
-define <vscale x 8 x i32> @intrinsic_vasubu_mask_vx_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv8i32_nxv8i32_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
-; CHECK-NEXT: vasubu.vx v8, v12, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i32> @llvm.riscv.vasubu.mask.nxv8i32.i32(
- <vscale x 8 x i32> %0,
- <vscale x 8 x i32> %1,
- i32 %2,
- <vscale x 8 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 8 x i32> %a
-}
-
-declare <vscale x 16 x i32> @llvm.riscv.vasubu.nxv16i32.i32(
- <vscale x 16 x i32>,
- <vscale x 16 x i32>,
- i32,
- i32);
-
-define <vscale x 16 x i32> @intrinsic_vasubu_vx_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, i32 %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vasubu_vx_nxv16i32_nxv16i32_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu
-; CHECK-NEXT: vasubu.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i32> @llvm.riscv.vasubu.nxv16i32.i32(
- <vscale x 16 x i32> undef,
- <vscale x 16 x i32> %0,
- i32 %1,
- i32 %2)
-
- ret <vscale x 16 x i32> %a
-}
-
-declare <vscale x 16 x i32> @llvm.riscv.vasubu.mask.nxv16i32.i32(
- <vscale x 16 x i32>,
- <vscale x 16 x i32>,
- i32,
- <vscale x 16 x i1>,
- i32,
- i32);
-
-define <vscale x 16 x i32> @intrinsic_vasubu_mask_vx_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv16i32_nxv16i32_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu
-; CHECK-NEXT: vasubu.vx v8, v16, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i32> @llvm.riscv.vasubu.mask.nxv16i32.i32(
- <vscale x 16 x i32> %0,
- <vscale x 16 x i32> %1,
- i32 %2,
- <vscale x 16 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 16 x i32> %a
-}
-
-declare <vscale x 1 x i64> @llvm.riscv.vasubu.nxv1i64.i64(
- <vscale x 1 x i64>,
- <vscale x 1 x i64>,
- i64,
- i32);
-
-define <vscale x 1 x i64> @intrinsic_vasubu_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vasubu_vx_nxv1i64_nxv1i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addi sp, sp, -16
-; CHECK-NEXT: sw a1, 12(sp)
-; CHECK-NEXT: sw a0, 8(sp)
-; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
-; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v9, (a0), zero
-; CHECK-NEXT: vasubu.vv v8, v8, v9
-; CHECK-NEXT: addi sp, sp, 16
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i64> @llvm.riscv.vasubu.nxv1i64.i64(
- <vscale x 1 x i64> undef,
- <vscale x 1 x i64> %0,
- i64 %1,
- i32 %2)
-
- ret <vscale x 1 x i64> %a
-}
-
-declare <vscale x 1 x i64> @llvm.riscv.vasubu.mask.nxv1i64.i64(
- <vscale x 1 x i64>,
- <vscale x 1 x i64>,
- i64,
- <vscale x 1 x i1>,
- i32,
- i32);
-
-define <vscale x 1 x i64> @intrinsic_vasubu_mask_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv1i64_nxv1i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addi sp, sp, -16
-; CHECK-NEXT: sw a1, 12(sp)
-; CHECK-NEXT: sw a0, 8(sp)
-; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
-; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v10, (a0), zero
-; CHECK-NEXT: vasubu.vv v8, v9, v10, v0.t
-; CHECK-NEXT: addi sp, sp, 16
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i64> @llvm.riscv.vasubu.mask.nxv1i64.i64(
- <vscale x 1 x i64> %0,
- <vscale x 1 x i64> %1,
- i64 %2,
- <vscale x 1 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 1 x i64> %a
-}
-
-declare <vscale x 2 x i64> @llvm.riscv.vasubu.nxv2i64.i64(
- <vscale x 2 x i64>,
- <vscale x 2 x i64>,
- i64,
- i32);
-
-define <vscale x 2 x i64> @intrinsic_vasubu_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vasubu_vx_nxv2i64_nxv2i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addi sp, sp, -16
-; CHECK-NEXT: sw a1, 12(sp)
-; CHECK-NEXT: sw a0, 8(sp)
-; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
-; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v10, (a0), zero
-; CHECK-NEXT: vasubu.vv v8, v8, v10
-; CHECK-NEXT: addi sp, sp, 16
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i64> @llvm.riscv.vasubu.nxv2i64.i64(
- <vscale x 2 x i64> undef,
- <vscale x 2 x i64> %0,
- i64 %1,
- i32 %2)
-
- ret <vscale x 2 x i64> %a
-}
-
-declare <vscale x 2 x i64> @llvm.riscv.vasubu.mask.nxv2i64.i64(
- <vscale x 2 x i64>,
- <vscale x 2 x i64>,
- i64,
- <vscale x 2 x i1>,
- i32,
- i32);
-
-define <vscale x 2 x i64> @intrinsic_vasubu_mask_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv2i64_nxv2i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addi sp, sp, -16
-; CHECK-NEXT: sw a1, 12(sp)
-; CHECK-NEXT: sw a0, 8(sp)
-; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
-; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v12, (a0), zero
-; CHECK-NEXT: vasubu.vv v8, v10, v12, v0.t
-; CHECK-NEXT: addi sp, sp, 16
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i64> @llvm.riscv.vasubu.mask.nxv2i64.i64(
- <vscale x 2 x i64> %0,
- <vscale x 2 x i64> %1,
- i64 %2,
- <vscale x 2 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 2 x i64> %a
-}
-
-declare <vscale x 4 x i64> @llvm.riscv.vasubu.nxv4i64.i64(
- <vscale x 4 x i64>,
- <vscale x 4 x i64>,
- i64,
- i32);
-
-define <vscale x 4 x i64> @intrinsic_vasubu_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vasubu_vx_nxv4i64_nxv4i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addi sp, sp, -16
-; CHECK-NEXT: sw a1, 12(sp)
-; CHECK-NEXT: sw a0, 8(sp)
-; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
-; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v12, (a0), zero
-; CHECK-NEXT: vasubu.vv v8, v8, v12
-; CHECK-NEXT: addi sp, sp, 16
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i64> @llvm.riscv.vasubu.nxv4i64.i64(
- <vscale x 4 x i64> undef,
- <vscale x 4 x i64> %0,
- i64 %1,
- i32 %2)
-
- ret <vscale x 4 x i64> %a
-}
-
-declare <vscale x 4 x i64> @llvm.riscv.vasubu.mask.nxv4i64.i64(
- <vscale x 4 x i64>,
- <vscale x 4 x i64>,
- i64,
- <vscale x 4 x i1>,
- i32,
- i32);
-
-define <vscale x 4 x i64> @intrinsic_vasubu_mask_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv4i64_nxv4i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addi sp, sp, -16
-; CHECK-NEXT: sw a1, 12(sp)
-; CHECK-NEXT: sw a0, 8(sp)
-; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
-; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v16, (a0), zero
-; CHECK-NEXT: vasubu.vv v8, v12, v16, v0.t
-; CHECK-NEXT: addi sp, sp, 16
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i64> @llvm.riscv.vasubu.mask.nxv4i64.i64(
- <vscale x 4 x i64> %0,
- <vscale x 4 x i64> %1,
- i64 %2,
- <vscale x 4 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 4 x i64> %a
-}
-
-declare <vscale x 8 x i64> @llvm.riscv.vasubu.nxv8i64.i64(
- <vscale x 8 x i64>,
- <vscale x 8 x i64>,
- i64,
- i32);
-
-define <vscale x 8 x i64> @intrinsic_vasubu_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, i64 %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vasubu_vx_nxv8i64_nxv8i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addi sp, sp, -16
-; CHECK-NEXT: sw a1, 12(sp)
-; CHECK-NEXT: sw a0, 8(sp)
-; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, mu
-; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v16, (a0), zero
-; CHECK-NEXT: vasubu.vv v8, v8, v16
-; CHECK-NEXT: addi sp, sp, 16
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i64> @llvm.riscv.vasubu.nxv8i64.i64(
- <vscale x 8 x i64> undef,
- <vscale x 8 x i64> %0,
- i64 %1,
- i32 %2)
-
- ret <vscale x 8 x i64> %a
-}
-
-declare <vscale x 8 x i64> @llvm.riscv.vasubu.mask.nxv8i64.i64(
- <vscale x 8 x i64>,
- <vscale x 8 x i64>,
- i64,
- <vscale x 8 x i1>,
- i32,
- i32);
-
-define <vscale x 8 x i64> @intrinsic_vasubu_mask_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv8i64_nxv8i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addi sp, sp, -16
-; CHECK-NEXT: sw a1, 12(sp)
-; CHECK-NEXT: sw a0, 8(sp)
-; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, mu
-; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v24, (a0), zero
-; CHECK-NEXT: vasubu.vv v8, v16, v24, v0.t
-; CHECK-NEXT: addi sp, sp, 16
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i64> @llvm.riscv.vasubu.mask.nxv8i64.i64(
- <vscale x 8 x i64> %0,
- <vscale x 8 x i64> %1,
- i64 %2,
- <vscale x 8 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 8 x i64> %a
-}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vasubu-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vasubu.ll
similarity index 80%
rename from llvm/test/CodeGen/RISCV/rvv/vasubu-rv64.ll
rename to llvm/test/CodeGen/RISCV/rvv/vasubu.ll
index 7b9824e5592a8..c3cab46c148e6 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vasubu-rv64.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vasubu.ll
@@ -1,13 +1,15 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs \
-; RUN: < %s | FileCheck %s
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v \
+; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,RV32
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v \
+; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,RV64
declare <vscale x 1 x i8> @llvm.riscv.vasubu.nxv1i8.nxv1i8(
<vscale x 1 x i8>,
<vscale x 1 x i8>,
<vscale x 1 x i8>,
- i64);
+ iXLen);
-define <vscale x 1 x i8> @intrinsic_vasubu_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2) nounwind {
+define <vscale x 1 x i8> @intrinsic_vasubu_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vasubu_vv_nxv1i8_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
@@ -18,7 +20,7 @@ entry:
<vscale x 1 x i8> undef,
<vscale x 1 x i8> %0,
<vscale x 1 x i8> %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 1 x i8> %a
}
@@ -28,10 +30,9 @@ declare <vscale x 1 x i8> @llvm.riscv.vasubu.mask.nxv1i8.nxv1i8(
<vscale x 1 x i8>,
<vscale x 1 x i8>,
<vscale x 1 x i1>,
- i64,
- i64);
+ iXLen, iXLen);
-define <vscale x 1 x i8> @intrinsic_vasubu_mask_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+define <vscale x 1 x i8> @intrinsic_vasubu_mask_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv1i8_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
@@ -43,7 +44,7 @@ entry:
<vscale x 1 x i8> %1,
<vscale x 1 x i8> %2,
<vscale x 1 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 1 x i8> %a
}
@@ -52,9 +53,9 @@ declare <vscale x 2 x i8> @llvm.riscv.vasubu.nxv2i8.nxv2i8(
<vscale x 2 x i8>,
<vscale x 2 x i8>,
<vscale x 2 x i8>,
- i64);
+ iXLen);
-define <vscale x 2 x i8> @intrinsic_vasubu_vv_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2) nounwind {
+define <vscale x 2 x i8> @intrinsic_vasubu_vv_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vasubu_vv_nxv2i8_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
@@ -65,7 +66,7 @@ entry:
<vscale x 2 x i8> undef,
<vscale x 2 x i8> %0,
<vscale x 2 x i8> %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 2 x i8> %a
}
@@ -75,10 +76,9 @@ declare <vscale x 2 x i8> @llvm.riscv.vasubu.mask.nxv2i8.nxv2i8(
<vscale x 2 x i8>,
<vscale x 2 x i8>,
<vscale x 2 x i1>,
- i64,
- i64);
+ iXLen, iXLen);
-define <vscale x 2 x i8> @intrinsic_vasubu_mask_vv_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+define <vscale x 2 x i8> @intrinsic_vasubu_mask_vv_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv2i8_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
@@ -90,7 +90,7 @@ entry:
<vscale x 2 x i8> %1,
<vscale x 2 x i8> %2,
<vscale x 2 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 2 x i8> %a
}
@@ -99,9 +99,9 @@ declare <vscale x 4 x i8> @llvm.riscv.vasubu.nxv4i8.nxv4i8(
<vscale x 4 x i8>,
<vscale x 4 x i8>,
<vscale x 4 x i8>,
- i64);
+ iXLen);
-define <vscale x 4 x i8> @intrinsic_vasubu_vv_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2) nounwind {
+define <vscale x 4 x i8> @intrinsic_vasubu_vv_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vasubu_vv_nxv4i8_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
@@ -112,7 +112,7 @@ entry:
<vscale x 4 x i8> undef,
<vscale x 4 x i8> %0,
<vscale x 4 x i8> %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 4 x i8> %a
}
@@ -122,10 +122,9 @@ declare <vscale x 4 x i8> @llvm.riscv.vasubu.mask.nxv4i8.nxv4i8(
<vscale x 4 x i8>,
<vscale x 4 x i8>,
<vscale x 4 x i1>,
- i64,
- i64);
+ iXLen, iXLen);
-define <vscale x 4 x i8> @intrinsic_vasubu_mask_vv_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+define <vscale x 4 x i8> @intrinsic_vasubu_mask_vv_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv4i8_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
@@ -137,7 +136,7 @@ entry:
<vscale x 4 x i8> %1,
<vscale x 4 x i8> %2,
<vscale x 4 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 4 x i8> %a
}
@@ -146,9 +145,9 @@ declare <vscale x 8 x i8> @llvm.riscv.vasubu.nxv8i8.nxv8i8(
<vscale x 8 x i8>,
<vscale x 8 x i8>,
<vscale x 8 x i8>,
- i64);
+ iXLen);
-define <vscale x 8 x i8> @intrinsic_vasubu_vv_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2) nounwind {
+define <vscale x 8 x i8> @intrinsic_vasubu_vv_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vasubu_vv_nxv8i8_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
@@ -159,7 +158,7 @@ entry:
<vscale x 8 x i8> undef,
<vscale x 8 x i8> %0,
<vscale x 8 x i8> %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 8 x i8> %a
}
@@ -169,10 +168,9 @@ declare <vscale x 8 x i8> @llvm.riscv.vasubu.mask.nxv8i8.nxv8i8(
<vscale x 8 x i8>,
<vscale x 8 x i8>,
<vscale x 8 x i1>,
- i64,
- i64);
+ iXLen, iXLen);
-define <vscale x 8 x i8> @intrinsic_vasubu_mask_vv_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+define <vscale x 8 x i8> @intrinsic_vasubu_mask_vv_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv8i8_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
@@ -184,7 +182,7 @@ entry:
<vscale x 8 x i8> %1,
<vscale x 8 x i8> %2,
<vscale x 8 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 8 x i8> %a
}
@@ -193,9 +191,9 @@ declare <vscale x 16 x i8> @llvm.riscv.vasubu.nxv16i8.nxv16i8(
<vscale x 16 x i8>,
<vscale x 16 x i8>,
<vscale x 16 x i8>,
- i64);
+ iXLen);
-define <vscale x 16 x i8> @intrinsic_vasubu_vv_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2) nounwind {
+define <vscale x 16 x i8> @intrinsic_vasubu_vv_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vasubu_vv_nxv16i8_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
@@ -206,7 +204,7 @@ entry:
<vscale x 16 x i8> undef,
<vscale x 16 x i8> %0,
<vscale x 16 x i8> %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 16 x i8> %a
}
@@ -216,10 +214,9 @@ declare <vscale x 16 x i8> @llvm.riscv.vasubu.mask.nxv16i8.nxv16i8(
<vscale x 16 x i8>,
<vscale x 16 x i8>,
<vscale x 16 x i1>,
- i64,
- i64);
+ iXLen, iXLen);
-define <vscale x 16 x i8> @intrinsic_vasubu_mask_vv_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+define <vscale x 16 x i8> @intrinsic_vasubu_mask_vv_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv16i8_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
@@ -231,7 +228,7 @@ entry:
<vscale x 16 x i8> %1,
<vscale x 16 x i8> %2,
<vscale x 16 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 16 x i8> %a
}
@@ -240,9 +237,9 @@ declare <vscale x 32 x i8> @llvm.riscv.vasubu.nxv32i8.nxv32i8(
<vscale x 32 x i8>,
<vscale x 32 x i8>,
<vscale x 32 x i8>,
- i64);
+ iXLen);
-define <vscale x 32 x i8> @intrinsic_vasubu_vv_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i64 %2) nounwind {
+define <vscale x 32 x i8> @intrinsic_vasubu_vv_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vasubu_vv_nxv32i8_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
@@ -253,7 +250,7 @@ entry:
<vscale x 32 x i8> undef,
<vscale x 32 x i8> %0,
<vscale x 32 x i8> %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 32 x i8> %a
}
@@ -263,10 +260,9 @@ declare <vscale x 32 x i8> @llvm.riscv.vasubu.mask.nxv32i8.nxv32i8(
<vscale x 32 x i8>,
<vscale x 32 x i8>,
<vscale x 32 x i1>,
- i64,
- i64);
+ iXLen, iXLen);
-define <vscale x 32 x i8> @intrinsic_vasubu_mask_vv_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
+define <vscale x 32 x i8> @intrinsic_vasubu_mask_vv_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv32i8_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
@@ -278,7 +274,7 @@ entry:
<vscale x 32 x i8> %1,
<vscale x 32 x i8> %2,
<vscale x 32 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 32 x i8> %a
}
@@ -287,9 +283,9 @@ declare <vscale x 64 x i8> @llvm.riscv.vasubu.nxv64i8.nxv64i8(
<vscale x 64 x i8>,
<vscale x 64 x i8>,
<vscale x 64 x i8>,
- i64);
+ iXLen);
-define <vscale x 64 x i8> @intrinsic_vasubu_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i64 %2) nounwind {
+define <vscale x 64 x i8> @intrinsic_vasubu_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vasubu_vv_nxv64i8_nxv64i8_nxv64i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, mu
@@ -300,7 +296,7 @@ entry:
<vscale x 64 x i8> undef,
<vscale x 64 x i8> %0,
<vscale x 64 x i8> %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 64 x i8> %a
}
@@ -310,10 +306,9 @@ declare <vscale x 64 x i8> @llvm.riscv.vasubu.mask.nxv64i8.nxv64i8(
<vscale x 64 x i8>,
<vscale x 64 x i8>,
<vscale x 64 x i1>,
- i64,
- i64);
+ iXLen, iXLen);
-define <vscale x 64 x i8> @intrinsic_vasubu_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, i64 %4) nounwind {
+define <vscale x 64 x i8> @intrinsic_vasubu_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv64i8_nxv64i8_nxv64i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vl8r.v v24, (a0)
@@ -326,7 +321,7 @@ entry:
<vscale x 64 x i8> %1,
<vscale x 64 x i8> %2,
<vscale x 64 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 64 x i8> %a
}
@@ -335,9 +330,9 @@ declare <vscale x 1 x i16> @llvm.riscv.vasubu.nxv1i16.nxv1i16(
<vscale x 1 x i16>,
<vscale x 1 x i16>,
<vscale x 1 x i16>,
- i64);
+ iXLen);
-define <vscale x 1 x i16> @intrinsic_vasubu_vv_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i64 %2) nounwind {
+define <vscale x 1 x i16> @intrinsic_vasubu_vv_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vasubu_vv_nxv1i16_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
@@ -348,7 +343,7 @@ entry:
<vscale x 1 x i16> undef,
<vscale x 1 x i16> %0,
<vscale x 1 x i16> %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 1 x i16> %a
}
@@ -358,10 +353,9 @@ declare <vscale x 1 x i16> @llvm.riscv.vasubu.mask.nxv1i16.nxv1i16(
<vscale x 1 x i16>,
<vscale x 1 x i16>,
<vscale x 1 x i1>,
- i64,
- i64);
+ iXLen, iXLen);
-define <vscale x 1 x i16> @intrinsic_vasubu_mask_vv_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+define <vscale x 1 x i16> @intrinsic_vasubu_mask_vv_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv1i16_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
@@ -373,7 +367,7 @@ entry:
<vscale x 1 x i16> %1,
<vscale x 1 x i16> %2,
<vscale x 1 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 1 x i16> %a
}
@@ -382,9 +376,9 @@ declare <vscale x 2 x i16> @llvm.riscv.vasubu.nxv2i16.nxv2i16(
<vscale x 2 x i16>,
<vscale x 2 x i16>,
<vscale x 2 x i16>,
- i64);
+ iXLen);
-define <vscale x 2 x i16> @intrinsic_vasubu_vv_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i64 %2) nounwind {
+define <vscale x 2 x i16> @intrinsic_vasubu_vv_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vasubu_vv_nxv2i16_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
@@ -395,7 +389,7 @@ entry:
<vscale x 2 x i16> undef,
<vscale x 2 x i16> %0,
<vscale x 2 x i16> %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 2 x i16> %a
}
@@ -405,10 +399,9 @@ declare <vscale x 2 x i16> @llvm.riscv.vasubu.mask.nxv2i16.nxv2i16(
<vscale x 2 x i16>,
<vscale x 2 x i16>,
<vscale x 2 x i1>,
- i64,
- i64);
+ iXLen, iXLen);
-define <vscale x 2 x i16> @intrinsic_vasubu_mask_vv_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+define <vscale x 2 x i16> @intrinsic_vasubu_mask_vv_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv2i16_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
@@ -420,7 +413,7 @@ entry:
<vscale x 2 x i16> %1,
<vscale x 2 x i16> %2,
<vscale x 2 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 2 x i16> %a
}
@@ -429,9 +422,9 @@ declare <vscale x 4 x i16> @llvm.riscv.vasubu.nxv4i16.nxv4i16(
<vscale x 4 x i16>,
<vscale x 4 x i16>,
<vscale x 4 x i16>,
- i64);
+ iXLen);
-define <vscale x 4 x i16> @intrinsic_vasubu_vv_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i64 %2) nounwind {
+define <vscale x 4 x i16> @intrinsic_vasubu_vv_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vasubu_vv_nxv4i16_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
@@ -442,7 +435,7 @@ entry:
<vscale x 4 x i16> undef,
<vscale x 4 x i16> %0,
<vscale x 4 x i16> %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 4 x i16> %a
}
@@ -452,10 +445,9 @@ declare <vscale x 4 x i16> @llvm.riscv.vasubu.mask.nxv4i16.nxv4i16(
<vscale x 4 x i16>,
<vscale x 4 x i16>,
<vscale x 4 x i1>,
- i64,
- i64);
+ iXLen, iXLen);
-define <vscale x 4 x i16> @intrinsic_vasubu_mask_vv_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+define <vscale x 4 x i16> @intrinsic_vasubu_mask_vv_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv4i16_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
@@ -467,7 +459,7 @@ entry:
<vscale x 4 x i16> %1,
<vscale x 4 x i16> %2,
<vscale x 4 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 4 x i16> %a
}
@@ -476,9 +468,9 @@ declare <vscale x 8 x i16> @llvm.riscv.vasubu.nxv8i16.nxv8i16(
<vscale x 8 x i16>,
<vscale x 8 x i16>,
<vscale x 8 x i16>,
- i64);
+ iXLen);
-define <vscale x 8 x i16> @intrinsic_vasubu_vv_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i64 %2) nounwind {
+define <vscale x 8 x i16> @intrinsic_vasubu_vv_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vasubu_vv_nxv8i16_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
@@ -489,7 +481,7 @@ entry:
<vscale x 8 x i16> undef,
<vscale x 8 x i16> %0,
<vscale x 8 x i16> %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 8 x i16> %a
}
@@ -499,10 +491,9 @@ declare <vscale x 8 x i16> @llvm.riscv.vasubu.mask.nxv8i16.nxv8i16(
<vscale x 8 x i16>,
<vscale x 8 x i16>,
<vscale x 8 x i1>,
- i64,
- i64);
+ iXLen, iXLen);
-define <vscale x 8 x i16> @intrinsic_vasubu_mask_vv_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+define <vscale x 8 x i16> @intrinsic_vasubu_mask_vv_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv8i16_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
@@ -514,7 +505,7 @@ entry:
<vscale x 8 x i16> %1,
<vscale x 8 x i16> %2,
<vscale x 8 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 8 x i16> %a
}
@@ -523,9 +514,9 @@ declare <vscale x 16 x i16> @llvm.riscv.vasubu.nxv16i16.nxv16i16(
<vscale x 16 x i16>,
<vscale x 16 x i16>,
<vscale x 16 x i16>,
- i64);
+ iXLen);
-define <vscale x 16 x i16> @intrinsic_vasubu_vv_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i64 %2) nounwind {
+define <vscale x 16 x i16> @intrinsic_vasubu_vv_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vasubu_vv_nxv16i16_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
@@ -536,7 +527,7 @@ entry:
<vscale x 16 x i16> undef,
<vscale x 16 x i16> %0,
<vscale x 16 x i16> %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 16 x i16> %a
}
@@ -546,10 +537,9 @@ declare <vscale x 16 x i16> @llvm.riscv.vasubu.mask.nxv16i16.nxv16i16(
<vscale x 16 x i16>,
<vscale x 16 x i16>,
<vscale x 16 x i1>,
- i64,
- i64);
+ iXLen, iXLen);
-define <vscale x 16 x i16> @intrinsic_vasubu_mask_vv_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+define <vscale x 16 x i16> @intrinsic_vasubu_mask_vv_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv16i16_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
@@ -561,7 +551,7 @@ entry:
<vscale x 16 x i16> %1,
<vscale x 16 x i16> %2,
<vscale x 16 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 16 x i16> %a
}
@@ -570,9 +560,9 @@ declare <vscale x 32 x i16> @llvm.riscv.vasubu.nxv32i16.nxv32i16(
<vscale x 32 x i16>,
<vscale x 32 x i16>,
<vscale x 32 x i16>,
- i64);
+ iXLen);
-define <vscale x 32 x i16> @intrinsic_vasubu_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, i64 %2) nounwind {
+define <vscale x 32 x i16> @intrinsic_vasubu_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vasubu_vv_nxv32i16_nxv32i16_nxv32i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, mu
@@ -583,7 +573,7 @@ entry:
<vscale x 32 x i16> undef,
<vscale x 32 x i16> %0,
<vscale x 32 x i16> %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 32 x i16> %a
}
@@ -593,10 +583,9 @@ declare <vscale x 32 x i16> @llvm.riscv.vasubu.mask.nxv32i16.nxv32i16(
<vscale x 32 x i16>,
<vscale x 32 x i16>,
<vscale x 32 x i1>,
- i64,
- i64);
+ iXLen, iXLen);
-define <vscale x 32 x i16> @intrinsic_vasubu_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
+define <vscale x 32 x i16> @intrinsic_vasubu_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv32i16_nxv32i16_nxv32i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vl8re16.v v24, (a0)
@@ -609,7 +598,7 @@ entry:
<vscale x 32 x i16> %1,
<vscale x 32 x i16> %2,
<vscale x 32 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 32 x i16> %a
}
@@ -618,9 +607,9 @@ declare <vscale x 1 x i32> @llvm.riscv.vasubu.nxv1i32.nxv1i32(
<vscale x 1 x i32>,
<vscale x 1 x i32>,
<vscale x 1 x i32>,
- i64);
+ iXLen);
-define <vscale x 1 x i32> @intrinsic_vasubu_vv_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2) nounwind {
+define <vscale x 1 x i32> @intrinsic_vasubu_vv_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vasubu_vv_nxv1i32_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
@@ -631,7 +620,7 @@ entry:
<vscale x 1 x i32> undef,
<vscale x 1 x i32> %0,
<vscale x 1 x i32> %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 1 x i32> %a
}
@@ -641,10 +630,9 @@ declare <vscale x 1 x i32> @llvm.riscv.vasubu.mask.nxv1i32.nxv1i32(
<vscale x 1 x i32>,
<vscale x 1 x i32>,
<vscale x 1 x i1>,
- i64,
- i64);
+ iXLen, iXLen);
-define <vscale x 1 x i32> @intrinsic_vasubu_mask_vv_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+define <vscale x 1 x i32> @intrinsic_vasubu_mask_vv_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv1i32_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
@@ -656,7 +644,7 @@ entry:
<vscale x 1 x i32> %1,
<vscale x 1 x i32> %2,
<vscale x 1 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 1 x i32> %a
}
@@ -665,9 +653,9 @@ declare <vscale x 2 x i32> @llvm.riscv.vasubu.nxv2i32.nxv2i32(
<vscale x 2 x i32>,
<vscale x 2 x i32>,
<vscale x 2 x i32>,
- i64);
+ iXLen);
-define <vscale x 2 x i32> @intrinsic_vasubu_vv_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2) nounwind {
+define <vscale x 2 x i32> @intrinsic_vasubu_vv_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vasubu_vv_nxv2i32_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
@@ -678,7 +666,7 @@ entry:
<vscale x 2 x i32> undef,
<vscale x 2 x i32> %0,
<vscale x 2 x i32> %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 2 x i32> %a
}
@@ -688,10 +676,9 @@ declare <vscale x 2 x i32> @llvm.riscv.vasubu.mask.nxv2i32.nxv2i32(
<vscale x 2 x i32>,
<vscale x 2 x i32>,
<vscale x 2 x i1>,
- i64,
- i64);
+ iXLen, iXLen);
-define <vscale x 2 x i32> @intrinsic_vasubu_mask_vv_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+define <vscale x 2 x i32> @intrinsic_vasubu_mask_vv_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv2i32_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
@@ -703,7 +690,7 @@ entry:
<vscale x 2 x i32> %1,
<vscale x 2 x i32> %2,
<vscale x 2 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 2 x i32> %a
}
@@ -712,9 +699,9 @@ declare <vscale x 4 x i32> @llvm.riscv.vasubu.nxv4i32.nxv4i32(
<vscale x 4 x i32>,
<vscale x 4 x i32>,
<vscale x 4 x i32>,
- i64);
+ iXLen);
-define <vscale x 4 x i32> @intrinsic_vasubu_vv_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i64 %2) nounwind {
+define <vscale x 4 x i32> @intrinsic_vasubu_vv_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vasubu_vv_nxv4i32_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
@@ -725,7 +712,7 @@ entry:
<vscale x 4 x i32> undef,
<vscale x 4 x i32> %0,
<vscale x 4 x i32> %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 4 x i32> %a
}
@@ -735,10 +722,9 @@ declare <vscale x 4 x i32> @llvm.riscv.vasubu.mask.nxv4i32.nxv4i32(
<vscale x 4 x i32>,
<vscale x 4 x i32>,
<vscale x 4 x i1>,
- i64,
- i64);
+ iXLen, iXLen);
-define <vscale x 4 x i32> @intrinsic_vasubu_mask_vv_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+define <vscale x 4 x i32> @intrinsic_vasubu_mask_vv_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv4i32_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
@@ -750,7 +736,7 @@ entry:
<vscale x 4 x i32> %1,
<vscale x 4 x i32> %2,
<vscale x 4 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 4 x i32> %a
}
@@ -759,9 +745,9 @@ declare <vscale x 8 x i32> @llvm.riscv.vasubu.nxv8i32.nxv8i32(
<vscale x 8 x i32>,
<vscale x 8 x i32>,
<vscale x 8 x i32>,
- i64);
+ iXLen);
-define <vscale x 8 x i32> @intrinsic_vasubu_vv_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i64 %2) nounwind {
+define <vscale x 8 x i32> @intrinsic_vasubu_vv_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vasubu_vv_nxv8i32_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
@@ -772,7 +758,7 @@ entry:
<vscale x 8 x i32> undef,
<vscale x 8 x i32> %0,
<vscale x 8 x i32> %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 8 x i32> %a
}
@@ -782,10 +768,9 @@ declare <vscale x 8 x i32> @llvm.riscv.vasubu.mask.nxv8i32.nxv8i32(
<vscale x 8 x i32>,
<vscale x 8 x i32>,
<vscale x 8 x i1>,
- i64,
- i64);
+ iXLen, iXLen);
-define <vscale x 8 x i32> @intrinsic_vasubu_mask_vv_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+define <vscale x 8 x i32> @intrinsic_vasubu_mask_vv_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv8i32_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
@@ -797,7 +782,7 @@ entry:
<vscale x 8 x i32> %1,
<vscale x 8 x i32> %2,
<vscale x 8 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 8 x i32> %a
}
@@ -806,9 +791,9 @@ declare <vscale x 16 x i32> @llvm.riscv.vasubu.nxv16i32.nxv16i32(
<vscale x 16 x i32>,
<vscale x 16 x i32>,
<vscale x 16 x i32>,
- i64);
+ iXLen);
-define <vscale x 16 x i32> @intrinsic_vasubu_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i64 %2) nounwind {
+define <vscale x 16 x i32> @intrinsic_vasubu_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vasubu_vv_nxv16i32_nxv16i32_nxv16i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu
@@ -819,7 +804,7 @@ entry:
<vscale x 16 x i32> undef,
<vscale x 16 x i32> %0,
<vscale x 16 x i32> %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 16 x i32> %a
}
@@ -829,10 +814,9 @@ declare <vscale x 16 x i32> @llvm.riscv.vasubu.mask.nxv16i32.nxv16i32(
<vscale x 16 x i32>,
<vscale x 16 x i32>,
<vscale x 16 x i1>,
- i64,
- i64);
+ iXLen, iXLen);
-define <vscale x 16 x i32> @intrinsic_vasubu_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+define <vscale x 16 x i32> @intrinsic_vasubu_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv16i32_nxv16i32_nxv16i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vl8re32.v v24, (a0)
@@ -845,7 +829,7 @@ entry:
<vscale x 16 x i32> %1,
<vscale x 16 x i32> %2,
<vscale x 16 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 16 x i32> %a
}
@@ -854,9 +838,9 @@ declare <vscale x 1 x i64> @llvm.riscv.vasubu.nxv1i64.nxv1i64(
<vscale x 1 x i64>,
<vscale x 1 x i64>,
<vscale x 1 x i64>,
- i64);
+ iXLen);
-define <vscale x 1 x i64> @intrinsic_vasubu_vv_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2) nounwind {
+define <vscale x 1 x i64> @intrinsic_vasubu_vv_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vasubu_vv_nxv1i64_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
@@ -867,7 +851,7 @@ entry:
<vscale x 1 x i64> undef,
<vscale x 1 x i64> %0,
<vscale x 1 x i64> %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 1 x i64> %a
}
@@ -877,10 +861,9 @@ declare <vscale x 1 x i64> @llvm.riscv.vasubu.mask.nxv1i64.nxv1i64(
<vscale x 1 x i64>,
<vscale x 1 x i64>,
<vscale x 1 x i1>,
- i64,
- i64);
+ iXLen, iXLen);
-define <vscale x 1 x i64> @intrinsic_vasubu_mask_vv_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+define <vscale x 1 x i64> @intrinsic_vasubu_mask_vv_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv1i64_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
@@ -892,7 +875,7 @@ entry:
<vscale x 1 x i64> %1,
<vscale x 1 x i64> %2,
<vscale x 1 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 1 x i64> %a
}
@@ -901,9 +884,9 @@ declare <vscale x 2 x i64> @llvm.riscv.vasubu.nxv2i64.nxv2i64(
<vscale x 2 x i64>,
<vscale x 2 x i64>,
<vscale x 2 x i64>,
- i64);
+ iXLen);
-define <vscale x 2 x i64> @intrinsic_vasubu_vv_nxv2i64_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2) nounwind {
+define <vscale x 2 x i64> @intrinsic_vasubu_vv_nxv2i64_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vasubu_vv_nxv2i64_nxv2i64_nxv2i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
@@ -914,7 +897,7 @@ entry:
<vscale x 2 x i64> undef,
<vscale x 2 x i64> %0,
<vscale x 2 x i64> %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 2 x i64> %a
}
@@ -924,10 +907,9 @@ declare <vscale x 2 x i64> @llvm.riscv.vasubu.mask.nxv2i64.nxv2i64(
<vscale x 2 x i64>,
<vscale x 2 x i64>,
<vscale x 2 x i1>,
- i64,
- i64);
+ iXLen, iXLen);
-define <vscale x 2 x i64> @intrinsic_vasubu_mask_vv_nxv2i64_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+define <vscale x 2 x i64> @intrinsic_vasubu_mask_vv_nxv2i64_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv2i64_nxv2i64_nxv2i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
@@ -939,7 +921,7 @@ entry:
<vscale x 2 x i64> %1,
<vscale x 2 x i64> %2,
<vscale x 2 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 2 x i64> %a
}
@@ -948,9 +930,9 @@ declare <vscale x 4 x i64> @llvm.riscv.vasubu.nxv4i64.nxv4i64(
<vscale x 4 x i64>,
<vscale x 4 x i64>,
<vscale x 4 x i64>,
- i64);
+ iXLen);
-define <vscale x 4 x i64> @intrinsic_vasubu_vv_nxv4i64_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2) nounwind {
+define <vscale x 4 x i64> @intrinsic_vasubu_vv_nxv4i64_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vasubu_vv_nxv4i64_nxv4i64_nxv4i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
@@ -961,7 +943,7 @@ entry:
<vscale x 4 x i64> undef,
<vscale x 4 x i64> %0,
<vscale x 4 x i64> %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 4 x i64> %a
}
@@ -971,10 +953,9 @@ declare <vscale x 4 x i64> @llvm.riscv.vasubu.mask.nxv4i64.nxv4i64(
<vscale x 4 x i64>,
<vscale x 4 x i64>,
<vscale x 4 x i1>,
- i64,
- i64);
+ iXLen, iXLen);
-define <vscale x 4 x i64> @intrinsic_vasubu_mask_vv_nxv4i64_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+define <vscale x 4 x i64> @intrinsic_vasubu_mask_vv_nxv4i64_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv4i64_nxv4i64_nxv4i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
@@ -986,7 +967,7 @@ entry:
<vscale x 4 x i64> %1,
<vscale x 4 x i64> %2,
<vscale x 4 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 4 x i64> %a
}
@@ -995,9 +976,9 @@ declare <vscale x 8 x i64> @llvm.riscv.vasubu.nxv8i64.nxv8i64(
<vscale x 8 x i64>,
<vscale x 8 x i64>,
<vscale x 8 x i64>,
- i64);
+ iXLen);
-define <vscale x 8 x i64> @intrinsic_vasubu_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2) nounwind {
+define <vscale x 8 x i64> @intrinsic_vasubu_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vasubu_vv_nxv8i64_nxv8i64_nxv8i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu
@@ -1008,7 +989,7 @@ entry:
<vscale x 8 x i64> undef,
<vscale x 8 x i64> %0,
<vscale x 8 x i64> %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 8 x i64> %a
}
@@ -1018,10 +999,9 @@ declare <vscale x 8 x i64> @llvm.riscv.vasubu.mask.nxv8i64.nxv8i64(
<vscale x 8 x i64>,
<vscale x 8 x i64>,
<vscale x 8 x i1>,
- i64,
- i64);
+ iXLen, iXLen);
-define <vscale x 8 x i64> @intrinsic_vasubu_mask_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+define <vscale x 8 x i64> @intrinsic_vasubu_mask_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv8i64_nxv8i64_nxv8i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vl8re64.v v24, (a0)
@@ -1034,7 +1014,7 @@ entry:
<vscale x 8 x i64> %1,
<vscale x 8 x i64> %2,
<vscale x 8 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 8 x i64> %a
}
@@ -1043,9 +1023,9 @@ declare <vscale x 1 x i8> @llvm.riscv.vasubu.nxv1i8.i8(
<vscale x 1 x i8>,
<vscale x 1 x i8>,
i8,
- i64);
+ iXLen);
-define <vscale x 1 x i8> @intrinsic_vasubu_vx_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, i8 %1, i64 %2) nounwind {
+define <vscale x 1 x i8> @intrinsic_vasubu_vx_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, i8 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vasubu_vx_nxv1i8_nxv1i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
@@ -1056,7 +1036,7 @@ entry:
<vscale x 1 x i8> undef,
<vscale x 1 x i8> %0,
i8 %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 1 x i8> %a
}
@@ -1066,10 +1046,9 @@ declare <vscale x 1 x i8> @llvm.riscv.vasubu.mask.nxv1i8.i8(
<vscale x 1 x i8>,
i8,
<vscale x 1 x i1>,
- i64,
- i64);
+ iXLen, iXLen);
-define <vscale x 1 x i8> @intrinsic_vasubu_mask_vx_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+define <vscale x 1 x i8> @intrinsic_vasubu_mask_vx_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv1i8_nxv1i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
@@ -1081,7 +1060,7 @@ entry:
<vscale x 1 x i8> %1,
i8 %2,
<vscale x 1 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 1 x i8> %a
}
@@ -1090,9 +1069,9 @@ declare <vscale x 2 x i8> @llvm.riscv.vasubu.nxv2i8.i8(
<vscale x 2 x i8>,
<vscale x 2 x i8>,
i8,
- i64);
+ iXLen);
-define <vscale x 2 x i8> @intrinsic_vasubu_vx_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, i8 %1, i64 %2) nounwind {
+define <vscale x 2 x i8> @intrinsic_vasubu_vx_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, i8 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vasubu_vx_nxv2i8_nxv2i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
@@ -1103,7 +1082,7 @@ entry:
<vscale x 2 x i8> undef,
<vscale x 2 x i8> %0,
i8 %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 2 x i8> %a
}
@@ -1113,10 +1092,9 @@ declare <vscale x 2 x i8> @llvm.riscv.vasubu.mask.nxv2i8.i8(
<vscale x 2 x i8>,
i8,
<vscale x 2 x i1>,
- i64,
- i64);
+ iXLen, iXLen);
-define <vscale x 2 x i8> @intrinsic_vasubu_mask_vx_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+define <vscale x 2 x i8> @intrinsic_vasubu_mask_vx_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv2i8_nxv2i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
@@ -1128,7 +1106,7 @@ entry:
<vscale x 2 x i8> %1,
i8 %2,
<vscale x 2 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 2 x i8> %a
}
@@ -1137,9 +1115,9 @@ declare <vscale x 4 x i8> @llvm.riscv.vasubu.nxv4i8.i8(
<vscale x 4 x i8>,
<vscale x 4 x i8>,
i8,
- i64);
+ iXLen);
-define <vscale x 4 x i8> @intrinsic_vasubu_vx_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, i8 %1, i64 %2) nounwind {
+define <vscale x 4 x i8> @intrinsic_vasubu_vx_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, i8 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vasubu_vx_nxv4i8_nxv4i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
@@ -1150,7 +1128,7 @@ entry:
<vscale x 4 x i8> undef,
<vscale x 4 x i8> %0,
i8 %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 4 x i8> %a
}
@@ -1160,10 +1138,9 @@ declare <vscale x 4 x i8> @llvm.riscv.vasubu.mask.nxv4i8.i8(
<vscale x 4 x i8>,
i8,
<vscale x 4 x i1>,
- i64,
- i64);
+ iXLen, iXLen);
-define <vscale x 4 x i8> @intrinsic_vasubu_mask_vx_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+define <vscale x 4 x i8> @intrinsic_vasubu_mask_vx_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv4i8_nxv4i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
@@ -1175,7 +1152,7 @@ entry:
<vscale x 4 x i8> %1,
i8 %2,
<vscale x 4 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 4 x i8> %a
}
@@ -1184,9 +1161,9 @@ declare <vscale x 8 x i8> @llvm.riscv.vasubu.nxv8i8.i8(
<vscale x 8 x i8>,
<vscale x 8 x i8>,
i8,
- i64);
+ iXLen);
-define <vscale x 8 x i8> @intrinsic_vasubu_vx_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, i8 %1, i64 %2) nounwind {
+define <vscale x 8 x i8> @intrinsic_vasubu_vx_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, i8 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vasubu_vx_nxv8i8_nxv8i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
@@ -1197,7 +1174,7 @@ entry:
<vscale x 8 x i8> undef,
<vscale x 8 x i8> %0,
i8 %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 8 x i8> %a
}
@@ -1207,10 +1184,9 @@ declare <vscale x 8 x i8> @llvm.riscv.vasubu.mask.nxv8i8.i8(
<vscale x 8 x i8>,
i8,
<vscale x 8 x i1>,
- i64,
- i64);
+ iXLen, iXLen);
-define <vscale x 8 x i8> @intrinsic_vasubu_mask_vx_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+define <vscale x 8 x i8> @intrinsic_vasubu_mask_vx_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv8i8_nxv8i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
@@ -1222,7 +1198,7 @@ entry:
<vscale x 8 x i8> %1,
i8 %2,
<vscale x 8 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 8 x i8> %a
}
@@ -1231,9 +1207,9 @@ declare <vscale x 16 x i8> @llvm.riscv.vasubu.nxv16i8.i8(
<vscale x 16 x i8>,
<vscale x 16 x i8>,
i8,
- i64);
+ iXLen);
-define <vscale x 16 x i8> @intrinsic_vasubu_vx_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, i8 %1, i64 %2) nounwind {
+define <vscale x 16 x i8> @intrinsic_vasubu_vx_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, i8 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vasubu_vx_nxv16i8_nxv16i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
@@ -1244,7 +1220,7 @@ entry:
<vscale x 16 x i8> undef,
<vscale x 16 x i8> %0,
i8 %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 16 x i8> %a
}
@@ -1254,10 +1230,9 @@ declare <vscale x 16 x i8> @llvm.riscv.vasubu.mask.nxv16i8.i8(
<vscale x 16 x i8>,
i8,
<vscale x 16 x i1>,
- i64,
- i64);
+ iXLen, iXLen);
-define <vscale x 16 x i8> @intrinsic_vasubu_mask_vx_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+define <vscale x 16 x i8> @intrinsic_vasubu_mask_vx_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv16i8_nxv16i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
@@ -1269,7 +1244,7 @@ entry:
<vscale x 16 x i8> %1,
i8 %2,
<vscale x 16 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 16 x i8> %a
}
@@ -1278,9 +1253,9 @@ declare <vscale x 32 x i8> @llvm.riscv.vasubu.nxv32i8.i8(
<vscale x 32 x i8>,
<vscale x 32 x i8>,
i8,
- i64);
+ iXLen);
-define <vscale x 32 x i8> @intrinsic_vasubu_vx_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, i8 %1, i64 %2) nounwind {
+define <vscale x 32 x i8> @intrinsic_vasubu_vx_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, i8 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vasubu_vx_nxv32i8_nxv32i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
@@ -1291,7 +1266,7 @@ entry:
<vscale x 32 x i8> undef,
<vscale x 32 x i8> %0,
i8 %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 32 x i8> %a
}
@@ -1301,10 +1276,9 @@ declare <vscale x 32 x i8> @llvm.riscv.vasubu.mask.nxv32i8.i8(
<vscale x 32 x i8>,
i8,
<vscale x 32 x i1>,
- i64,
- i64);
+ iXLen, iXLen);
-define <vscale x 32 x i8> @intrinsic_vasubu_mask_vx_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
+define <vscale x 32 x i8> @intrinsic_vasubu_mask_vx_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv32i8_nxv32i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
@@ -1316,7 +1290,7 @@ entry:
<vscale x 32 x i8> %1,
i8 %2,
<vscale x 32 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 32 x i8> %a
}
@@ -1325,9 +1299,9 @@ declare <vscale x 64 x i8> @llvm.riscv.vasubu.nxv64i8.i8(
<vscale x 64 x i8>,
<vscale x 64 x i8>,
i8,
- i64);
+ iXLen);
-define <vscale x 64 x i8> @intrinsic_vasubu_vx_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, i8 %1, i64 %2) nounwind {
+define <vscale x 64 x i8> @intrinsic_vasubu_vx_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, i8 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vasubu_vx_nxv64i8_nxv64i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu
@@ -1338,7 +1312,7 @@ entry:
<vscale x 64 x i8> undef,
<vscale x 64 x i8> %0,
i8 %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 64 x i8> %a
}
@@ -1348,10 +1322,9 @@ declare <vscale x 64 x i8> @llvm.riscv.vasubu.mask.nxv64i8.i8(
<vscale x 64 x i8>,
i8,
<vscale x 64 x i1>,
- i64,
- i64);
+ iXLen, iXLen);
-define <vscale x 64 x i8> @intrinsic_vasubu_mask_vx_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i8 %2, <vscale x 64 x i1> %3, i64 %4) nounwind {
+define <vscale x 64 x i8> @intrinsic_vasubu_mask_vx_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i8 %2, <vscale x 64 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv64i8_nxv64i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu
@@ -1363,7 +1336,7 @@ entry:
<vscale x 64 x i8> %1,
i8 %2,
<vscale x 64 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 64 x i8> %a
}
@@ -1372,9 +1345,9 @@ declare <vscale x 1 x i16> @llvm.riscv.vasubu.nxv1i16.i16(
<vscale x 1 x i16>,
<vscale x 1 x i16>,
i16,
- i64);
+ iXLen);
-define <vscale x 1 x i16> @intrinsic_vasubu_vx_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, i16 %1, i64 %2) nounwind {
+define <vscale x 1 x i16> @intrinsic_vasubu_vx_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, i16 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vasubu_vx_nxv1i16_nxv1i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
@@ -1385,7 +1358,7 @@ entry:
<vscale x 1 x i16> undef,
<vscale x 1 x i16> %0,
i16 %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 1 x i16> %a
}
@@ -1395,10 +1368,9 @@ declare <vscale x 1 x i16> @llvm.riscv.vasubu.mask.nxv1i16.i16(
<vscale x 1 x i16>,
i16,
<vscale x 1 x i1>,
- i64,
- i64);
+ iXLen, iXLen);
-define <vscale x 1 x i16> @intrinsic_vasubu_mask_vx_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+define <vscale x 1 x i16> @intrinsic_vasubu_mask_vx_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv1i16_nxv1i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
@@ -1410,7 +1382,7 @@ entry:
<vscale x 1 x i16> %1,
i16 %2,
<vscale x 1 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 1 x i16> %a
}
@@ -1419,9 +1391,9 @@ declare <vscale x 2 x i16> @llvm.riscv.vasubu.nxv2i16.i16(
<vscale x 2 x i16>,
<vscale x 2 x i16>,
i16,
- i64);
+ iXLen);
-define <vscale x 2 x i16> @intrinsic_vasubu_vx_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, i16 %1, i64 %2) nounwind {
+define <vscale x 2 x i16> @intrinsic_vasubu_vx_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, i16 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vasubu_vx_nxv2i16_nxv2i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
@@ -1432,7 +1404,7 @@ entry:
<vscale x 2 x i16> undef,
<vscale x 2 x i16> %0,
i16 %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 2 x i16> %a
}
@@ -1442,10 +1414,9 @@ declare <vscale x 2 x i16> @llvm.riscv.vasubu.mask.nxv2i16.i16(
<vscale x 2 x i16>,
i16,
<vscale x 2 x i1>,
- i64,
- i64);
+ iXLen, iXLen);
-define <vscale x 2 x i16> @intrinsic_vasubu_mask_vx_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+define <vscale x 2 x i16> @intrinsic_vasubu_mask_vx_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv2i16_nxv2i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
@@ -1457,7 +1428,7 @@ entry:
<vscale x 2 x i16> %1,
i16 %2,
<vscale x 2 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 2 x i16> %a
}
@@ -1466,9 +1437,9 @@ declare <vscale x 4 x i16> @llvm.riscv.vasubu.nxv4i16.i16(
<vscale x 4 x i16>,
<vscale x 4 x i16>,
i16,
- i64);
+ iXLen);
-define <vscale x 4 x i16> @intrinsic_vasubu_vx_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, i16 %1, i64 %2) nounwind {
+define <vscale x 4 x i16> @intrinsic_vasubu_vx_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, i16 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vasubu_vx_nxv4i16_nxv4i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
@@ -1479,7 +1450,7 @@ entry:
<vscale x 4 x i16> undef,
<vscale x 4 x i16> %0,
i16 %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 4 x i16> %a
}
@@ -1489,10 +1460,9 @@ declare <vscale x 4 x i16> @llvm.riscv.vasubu.mask.nxv4i16.i16(
<vscale x 4 x i16>,
i16,
<vscale x 4 x i1>,
- i64,
- i64);
+ iXLen, iXLen);
-define <vscale x 4 x i16> @intrinsic_vasubu_mask_vx_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+define <vscale x 4 x i16> @intrinsic_vasubu_mask_vx_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv4i16_nxv4i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
@@ -1504,7 +1474,7 @@ entry:
<vscale x 4 x i16> %1,
i16 %2,
<vscale x 4 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 4 x i16> %a
}
@@ -1513,9 +1483,9 @@ declare <vscale x 8 x i16> @llvm.riscv.vasubu.nxv8i16.i16(
<vscale x 8 x i16>,
<vscale x 8 x i16>,
i16,
- i64);
+ iXLen);
-define <vscale x 8 x i16> @intrinsic_vasubu_vx_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, i16 %1, i64 %2) nounwind {
+define <vscale x 8 x i16> @intrinsic_vasubu_vx_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, i16 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vasubu_vx_nxv8i16_nxv8i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
@@ -1526,7 +1496,7 @@ entry:
<vscale x 8 x i16> undef,
<vscale x 8 x i16> %0,
i16 %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 8 x i16> %a
}
@@ -1536,10 +1506,9 @@ declare <vscale x 8 x i16> @llvm.riscv.vasubu.mask.nxv8i16.i16(
<vscale x 8 x i16>,
i16,
<vscale x 8 x i1>,
- i64,
- i64);
+ iXLen, iXLen);
-define <vscale x 8 x i16> @intrinsic_vasubu_mask_vx_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+define <vscale x 8 x i16> @intrinsic_vasubu_mask_vx_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv8i16_nxv8i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
@@ -1551,7 +1520,7 @@ entry:
<vscale x 8 x i16> %1,
i16 %2,
<vscale x 8 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 8 x i16> %a
}
@@ -1560,9 +1529,9 @@ declare <vscale x 16 x i16> @llvm.riscv.vasubu.nxv16i16.i16(
<vscale x 16 x i16>,
<vscale x 16 x i16>,
i16,
- i64);
+ iXLen);
-define <vscale x 16 x i16> @intrinsic_vasubu_vx_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, i16 %1, i64 %2) nounwind {
+define <vscale x 16 x i16> @intrinsic_vasubu_vx_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, i16 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vasubu_vx_nxv16i16_nxv16i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
@@ -1573,7 +1542,7 @@ entry:
<vscale x 16 x i16> undef,
<vscale x 16 x i16> %0,
i16 %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 16 x i16> %a
}
@@ -1583,10 +1552,9 @@ declare <vscale x 16 x i16> @llvm.riscv.vasubu.mask.nxv16i16.i16(
<vscale x 16 x i16>,
i16,
<vscale x 16 x i1>,
- i64,
- i64);
+ iXLen, iXLen);
-define <vscale x 16 x i16> @intrinsic_vasubu_mask_vx_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+define <vscale x 16 x i16> @intrinsic_vasubu_mask_vx_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv16i16_nxv16i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
@@ -1598,7 +1566,7 @@ entry:
<vscale x 16 x i16> %1,
i16 %2,
<vscale x 16 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 16 x i16> %a
}
@@ -1607,9 +1575,9 @@ declare <vscale x 32 x i16> @llvm.riscv.vasubu.nxv32i16.i16(
<vscale x 32 x i16>,
<vscale x 32 x i16>,
i16,
- i64);
+ iXLen);
-define <vscale x 32 x i16> @intrinsic_vasubu_vx_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, i16 %1, i64 %2) nounwind {
+define <vscale x 32 x i16> @intrinsic_vasubu_vx_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, i16 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vasubu_vx_nxv32i16_nxv32i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu
@@ -1620,7 +1588,7 @@ entry:
<vscale x 32 x i16> undef,
<vscale x 32 x i16> %0,
i16 %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 32 x i16> %a
}
@@ -1630,10 +1598,9 @@ declare <vscale x 32 x i16> @llvm.riscv.vasubu.mask.nxv32i16.i16(
<vscale x 32 x i16>,
i16,
<vscale x 32 x i1>,
- i64,
- i64);
+ iXLen, iXLen);
-define <vscale x 32 x i16> @intrinsic_vasubu_mask_vx_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, i16 %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
+define <vscale x 32 x i16> @intrinsic_vasubu_mask_vx_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, i16 %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv32i16_nxv32i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu
@@ -1645,7 +1612,7 @@ entry:
<vscale x 32 x i16> %1,
i16 %2,
<vscale x 32 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 32 x i16> %a
}
@@ -1654,9 +1621,9 @@ declare <vscale x 1 x i32> @llvm.riscv.vasubu.nxv1i32.i32(
<vscale x 1 x i32>,
<vscale x 1 x i32>,
i32,
- i64);
+ iXLen);
-define <vscale x 1 x i32> @intrinsic_vasubu_vx_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, i32 %1, i64 %2) nounwind {
+define <vscale x 1 x i32> @intrinsic_vasubu_vx_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, i32 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vasubu_vx_nxv1i32_nxv1i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
@@ -1667,7 +1634,7 @@ entry:
<vscale x 1 x i32> undef,
<vscale x 1 x i32> %0,
i32 %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 1 x i32> %a
}
@@ -1677,10 +1644,9 @@ declare <vscale x 1 x i32> @llvm.riscv.vasubu.mask.nxv1i32.i32(
<vscale x 1 x i32>,
i32,
<vscale x 1 x i1>,
- i64,
- i64);
+ iXLen, iXLen);
-define <vscale x 1 x i32> @intrinsic_vasubu_mask_vx_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+define <vscale x 1 x i32> @intrinsic_vasubu_mask_vx_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv1i32_nxv1i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
@@ -1692,7 +1658,7 @@ entry:
<vscale x 1 x i32> %1,
i32 %2,
<vscale x 1 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 1 x i32> %a
}
@@ -1701,9 +1667,9 @@ declare <vscale x 2 x i32> @llvm.riscv.vasubu.nxv2i32.i32(
<vscale x 2 x i32>,
<vscale x 2 x i32>,
i32,
- i64);
+ iXLen);
-define <vscale x 2 x i32> @intrinsic_vasubu_vx_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, i32 %1, i64 %2) nounwind {
+define <vscale x 2 x i32> @intrinsic_vasubu_vx_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, i32 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vasubu_vx_nxv2i32_nxv2i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
@@ -1714,7 +1680,7 @@ entry:
<vscale x 2 x i32> undef,
<vscale x 2 x i32> %0,
i32 %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 2 x i32> %a
}
@@ -1724,10 +1690,9 @@ declare <vscale x 2 x i32> @llvm.riscv.vasubu.mask.nxv2i32.i32(
<vscale x 2 x i32>,
i32,
<vscale x 2 x i1>,
- i64,
- i64);
+ iXLen, iXLen);
-define <vscale x 2 x i32> @intrinsic_vasubu_mask_vx_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+define <vscale x 2 x i32> @intrinsic_vasubu_mask_vx_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv2i32_nxv2i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
@@ -1739,7 +1704,7 @@ entry:
<vscale x 2 x i32> %1,
i32 %2,
<vscale x 2 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 2 x i32> %a
}
@@ -1748,9 +1713,9 @@ declare <vscale x 4 x i32> @llvm.riscv.vasubu.nxv4i32.i32(
<vscale x 4 x i32>,
<vscale x 4 x i32>,
i32,
- i64);
+ iXLen);
-define <vscale x 4 x i32> @intrinsic_vasubu_vx_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, i32 %1, i64 %2) nounwind {
+define <vscale x 4 x i32> @intrinsic_vasubu_vx_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, i32 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vasubu_vx_nxv4i32_nxv4i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
@@ -1761,7 +1726,7 @@ entry:
<vscale x 4 x i32> undef,
<vscale x 4 x i32> %0,
i32 %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 4 x i32> %a
}
@@ -1771,10 +1736,9 @@ declare <vscale x 4 x i32> @llvm.riscv.vasubu.mask.nxv4i32.i32(
<vscale x 4 x i32>,
i32,
<vscale x 4 x i1>,
- i64,
- i64);
+ iXLen, iXLen);
-define <vscale x 4 x i32> @intrinsic_vasubu_mask_vx_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+define <vscale x 4 x i32> @intrinsic_vasubu_mask_vx_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv4i32_nxv4i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
@@ -1786,7 +1750,7 @@ entry:
<vscale x 4 x i32> %1,
i32 %2,
<vscale x 4 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 4 x i32> %a
}
@@ -1795,9 +1759,9 @@ declare <vscale x 8 x i32> @llvm.riscv.vasubu.nxv8i32.i32(
<vscale x 8 x i32>,
<vscale x 8 x i32>,
i32,
- i64);
+ iXLen);
-define <vscale x 8 x i32> @intrinsic_vasubu_vx_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, i32 %1, i64 %2) nounwind {
+define <vscale x 8 x i32> @intrinsic_vasubu_vx_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, i32 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vasubu_vx_nxv8i32_nxv8i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
@@ -1808,7 +1772,7 @@ entry:
<vscale x 8 x i32> undef,
<vscale x 8 x i32> %0,
i32 %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 8 x i32> %a
}
@@ -1818,10 +1782,9 @@ declare <vscale x 8 x i32> @llvm.riscv.vasubu.mask.nxv8i32.i32(
<vscale x 8 x i32>,
i32,
<vscale x 8 x i1>,
- i64,
- i64);
+ iXLen, iXLen);
-define <vscale x 8 x i32> @intrinsic_vasubu_mask_vx_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+define <vscale x 8 x i32> @intrinsic_vasubu_mask_vx_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv8i32_nxv8i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
@@ -1833,7 +1796,7 @@ entry:
<vscale x 8 x i32> %1,
i32 %2,
<vscale x 8 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 8 x i32> %a
}
@@ -1842,9 +1805,9 @@ declare <vscale x 16 x i32> @llvm.riscv.vasubu.nxv16i32.i32(
<vscale x 16 x i32>,
<vscale x 16 x i32>,
i32,
- i64);
+ iXLen);
-define <vscale x 16 x i32> @intrinsic_vasubu_vx_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, i32 %1, i64 %2) nounwind {
+define <vscale x 16 x i32> @intrinsic_vasubu_vx_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, i32 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vasubu_vx_nxv16i32_nxv16i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu
@@ -1855,7 +1818,7 @@ entry:
<vscale x 16 x i32> undef,
<vscale x 16 x i32> %0,
i32 %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 16 x i32> %a
}
@@ -1865,10 +1828,9 @@ declare <vscale x 16 x i32> @llvm.riscv.vasubu.mask.nxv16i32.i32(
<vscale x 16 x i32>,
i32,
<vscale x 16 x i1>,
- i64,
- i64);
+ iXLen, iXLen);
-define <vscale x 16 x i32> @intrinsic_vasubu_mask_vx_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+define <vscale x 16 x i32> @intrinsic_vasubu_mask_vx_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv16i32_nxv16i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu
@@ -1880,7 +1842,7 @@ entry:
<vscale x 16 x i32> %1,
i32 %2,
<vscale x 16 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 16 x i32> %a
}
@@ -1889,20 +1851,32 @@ declare <vscale x 1 x i64> @llvm.riscv.vasubu.nxv1i64.i64(
<vscale x 1 x i64>,
<vscale x 1 x i64>,
i64,
- i64);
-
-define <vscale x 1 x i64> @intrinsic_vasubu_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vasubu_vx_nxv1i64_nxv1i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
-; CHECK-NEXT: vasubu.vx v8, v8, a0
-; CHECK-NEXT: ret
+ iXLen);
+
+define <vscale x 1 x i64> @intrinsic_vasubu_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, iXLen %2) nounwind {
+; RV32-LABEL: intrinsic_vasubu_vx_nxv1i64_nxv1i64_i64:
+; RV32: # %bb.0: # %entry
+; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: sw a1, 12(sp)
+; RV32-NEXT: sw a0, 8(sp)
+; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
+; RV32-NEXT: addi a0, sp, 8
+; RV32-NEXT: vlse64.v v9, (a0), zero
+; RV32-NEXT: vasubu.vv v8, v8, v9
+; RV32-NEXT: addi sp, sp, 16
+; RV32-NEXT: ret
+;
+; RV64-LABEL: intrinsic_vasubu_vx_nxv1i64_nxv1i64_i64:
+; RV64: # %bb.0: # %entry
+; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, mu
+; RV64-NEXT: vasubu.vx v8, v8, a0
+; RV64-NEXT: ret
entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vasubu.nxv1i64.i64(
<vscale x 1 x i64> undef,
<vscale x 1 x i64> %0,
i64 %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 1 x i64> %a
}
@@ -1912,22 +1886,33 @@ declare <vscale x 1 x i64> @llvm.riscv.vasubu.mask.nxv1i64.i64(
<vscale x 1 x i64>,
i64,
<vscale x 1 x i1>,
- i64,
- i64);
-
-define <vscale x 1 x i64> @intrinsic_vasubu_mask_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv1i64_nxv1i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
-; CHECK-NEXT: vasubu.vx v8, v9, a0, v0.t
-; CHECK-NEXT: ret
+ iXLen, iXLen);
+
+define <vscale x 1 x i64> @intrinsic_vasubu_mask_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
+; RV32-LABEL: intrinsic_vasubu_mask_vx_nxv1i64_nxv1i64_i64:
+; RV32: # %bb.0: # %entry
+; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: sw a1, 12(sp)
+; RV32-NEXT: sw a0, 8(sp)
+; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
+; RV32-NEXT: addi a0, sp, 8
+; RV32-NEXT: vlse64.v v10, (a0), zero
+; RV32-NEXT: vasubu.vv v8, v9, v10, v0.t
+; RV32-NEXT: addi sp, sp, 16
+; RV32-NEXT: ret
+;
+; RV64-LABEL: intrinsic_vasubu_mask_vx_nxv1i64_nxv1i64_i64:
+; RV64: # %bb.0: # %entry
+; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, mu
+; RV64-NEXT: vasubu.vx v8, v9, a0, v0.t
+; RV64-NEXT: ret
entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vasubu.mask.nxv1i64.i64(
<vscale x 1 x i64> %0,
<vscale x 1 x i64> %1,
i64 %2,
<vscale x 1 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 1 x i64> %a
}
@@ -1936,20 +1921,32 @@ declare <vscale x 2 x i64> @llvm.riscv.vasubu.nxv2i64.i64(
<vscale x 2 x i64>,
<vscale x 2 x i64>,
i64,
- i64);
-
-define <vscale x 2 x i64> @intrinsic_vasubu_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vasubu_vx_nxv2i64_nxv2i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
-; CHECK-NEXT: vasubu.vx v8, v8, a0
-; CHECK-NEXT: ret
+ iXLen);
+
+define <vscale x 2 x i64> @intrinsic_vasubu_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, iXLen %2) nounwind {
+; RV32-LABEL: intrinsic_vasubu_vx_nxv2i64_nxv2i64_i64:
+; RV32: # %bb.0: # %entry
+; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: sw a1, 12(sp)
+; RV32-NEXT: sw a0, 8(sp)
+; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
+; RV32-NEXT: addi a0, sp, 8
+; RV32-NEXT: vlse64.v v10, (a0), zero
+; RV32-NEXT: vasubu.vv v8, v8, v10
+; RV32-NEXT: addi sp, sp, 16
+; RV32-NEXT: ret
+;
+; RV64-LABEL: intrinsic_vasubu_vx_nxv2i64_nxv2i64_i64:
+; RV64: # %bb.0: # %entry
+; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, mu
+; RV64-NEXT: vasubu.vx v8, v8, a0
+; RV64-NEXT: ret
entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vasubu.nxv2i64.i64(
<vscale x 2 x i64> undef,
<vscale x 2 x i64> %0,
i64 %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 2 x i64> %a
}
@@ -1959,22 +1956,33 @@ declare <vscale x 2 x i64> @llvm.riscv.vasubu.mask.nxv2i64.i64(
<vscale x 2 x i64>,
i64,
<vscale x 2 x i1>,
- i64,
- i64);
-
-define <vscale x 2 x i64> @intrinsic_vasubu_mask_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv2i64_nxv2i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
-; CHECK-NEXT: vasubu.vx v8, v10, a0, v0.t
-; CHECK-NEXT: ret
+ iXLen, iXLen);
+
+define <vscale x 2 x i64> @intrinsic_vasubu_mask_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
+; RV32-LABEL: intrinsic_vasubu_mask_vx_nxv2i64_nxv2i64_i64:
+; RV32: # %bb.0: # %entry
+; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: sw a1, 12(sp)
+; RV32-NEXT: sw a0, 8(sp)
+; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
+; RV32-NEXT: addi a0, sp, 8
+; RV32-NEXT: vlse64.v v12, (a0), zero
+; RV32-NEXT: vasubu.vv v8, v10, v12, v0.t
+; RV32-NEXT: addi sp, sp, 16
+; RV32-NEXT: ret
+;
+; RV64-LABEL: intrinsic_vasubu_mask_vx_nxv2i64_nxv2i64_i64:
+; RV64: # %bb.0: # %entry
+; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, mu
+; RV64-NEXT: vasubu.vx v8, v10, a0, v0.t
+; RV64-NEXT: ret
entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vasubu.mask.nxv2i64.i64(
<vscale x 2 x i64> %0,
<vscale x 2 x i64> %1,
i64 %2,
<vscale x 2 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 2 x i64> %a
}
@@ -1983,20 +1991,32 @@ declare <vscale x 4 x i64> @llvm.riscv.vasubu.nxv4i64.i64(
<vscale x 4 x i64>,
<vscale x 4 x i64>,
i64,
- i64);
-
-define <vscale x 4 x i64> @intrinsic_vasubu_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vasubu_vx_nxv4i64_nxv4i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
-; CHECK-NEXT: vasubu.vx v8, v8, a0
-; CHECK-NEXT: ret
+ iXLen);
+
+define <vscale x 4 x i64> @intrinsic_vasubu_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, iXLen %2) nounwind {
+; RV32-LABEL: intrinsic_vasubu_vx_nxv4i64_nxv4i64_i64:
+; RV32: # %bb.0: # %entry
+; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: sw a1, 12(sp)
+; RV32-NEXT: sw a0, 8(sp)
+; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
+; RV32-NEXT: addi a0, sp, 8
+; RV32-NEXT: vlse64.v v12, (a0), zero
+; RV32-NEXT: vasubu.vv v8, v8, v12
+; RV32-NEXT: addi sp, sp, 16
+; RV32-NEXT: ret
+;
+; RV64-LABEL: intrinsic_vasubu_vx_nxv4i64_nxv4i64_i64:
+; RV64: # %bb.0: # %entry
+; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu
+; RV64-NEXT: vasubu.vx v8, v8, a0
+; RV64-NEXT: ret
entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vasubu.nxv4i64.i64(
<vscale x 4 x i64> undef,
<vscale x 4 x i64> %0,
i64 %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 4 x i64> %a
}
@@ -2006,22 +2026,33 @@ declare <vscale x 4 x i64> @llvm.riscv.vasubu.mask.nxv4i64.i64(
<vscale x 4 x i64>,
i64,
<vscale x 4 x i1>,
- i64,
- i64);
-
-define <vscale x 4 x i64> @intrinsic_vasubu_mask_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv4i64_nxv4i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
-; CHECK-NEXT: vasubu.vx v8, v12, a0, v0.t
-; CHECK-NEXT: ret
+ iXLen, iXLen);
+
+define <vscale x 4 x i64> @intrinsic_vasubu_mask_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
+; RV32-LABEL: intrinsic_vasubu_mask_vx_nxv4i64_nxv4i64_i64:
+; RV32: # %bb.0: # %entry
+; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: sw a1, 12(sp)
+; RV32-NEXT: sw a0, 8(sp)
+; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
+; RV32-NEXT: addi a0, sp, 8
+; RV32-NEXT: vlse64.v v16, (a0), zero
+; RV32-NEXT: vasubu.vv v8, v12, v16, v0.t
+; RV32-NEXT: addi sp, sp, 16
+; RV32-NEXT: ret
+;
+; RV64-LABEL: intrinsic_vasubu_mask_vx_nxv4i64_nxv4i64_i64:
+; RV64: # %bb.0: # %entry
+; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu
+; RV64-NEXT: vasubu.vx v8, v12, a0, v0.t
+; RV64-NEXT: ret
entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vasubu.mask.nxv4i64.i64(
<vscale x 4 x i64> %0,
<vscale x 4 x i64> %1,
i64 %2,
<vscale x 4 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 4 x i64> %a
}
@@ -2030,20 +2061,32 @@ declare <vscale x 8 x i64> @llvm.riscv.vasubu.nxv8i64.i64(
<vscale x 8 x i64>,
<vscale x 8 x i64>,
i64,
- i64);
-
-define <vscale x 8 x i64> @intrinsic_vasubu_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, i64 %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vasubu_vx_nxv8i64_nxv8i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu
-; CHECK-NEXT: vasubu.vx v8, v8, a0
-; CHECK-NEXT: ret
+ iXLen);
+
+define <vscale x 8 x i64> @intrinsic_vasubu_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, i64 %1, iXLen %2) nounwind {
+; RV32-LABEL: intrinsic_vasubu_vx_nxv8i64_nxv8i64_i64:
+; RV32: # %bb.0: # %entry
+; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: sw a1, 12(sp)
+; RV32-NEXT: sw a0, 8(sp)
+; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu
+; RV32-NEXT: addi a0, sp, 8
+; RV32-NEXT: vlse64.v v16, (a0), zero
+; RV32-NEXT: vasubu.vv v8, v8, v16
+; RV32-NEXT: addi sp, sp, 16
+; RV32-NEXT: ret
+;
+; RV64-LABEL: intrinsic_vasubu_vx_nxv8i64_nxv8i64_i64:
+; RV64: # %bb.0: # %entry
+; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, mu
+; RV64-NEXT: vasubu.vx v8, v8, a0
+; RV64-NEXT: ret
entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vasubu.nxv8i64.i64(
<vscale x 8 x i64> undef,
<vscale x 8 x i64> %0,
i64 %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 8 x i64> %a
}
@@ -2053,22 +2096,33 @@ declare <vscale x 8 x i64> @llvm.riscv.vasubu.mask.nxv8i64.i64(
<vscale x 8 x i64>,
i64,
<vscale x 8 x i1>,
- i64,
- i64);
-
-define <vscale x 8 x i64> @intrinsic_vasubu_mask_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv8i64_nxv8i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu
-; CHECK-NEXT: vasubu.vx v8, v16, a0, v0.t
-; CHECK-NEXT: ret
+ iXLen, iXLen);
+
+define <vscale x 8 x i64> @intrinsic_vasubu_mask_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
+; RV32-LABEL: intrinsic_vasubu_mask_vx_nxv8i64_nxv8i64_i64:
+; RV32: # %bb.0: # %entry
+; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: sw a1, 12(sp)
+; RV32-NEXT: sw a0, 8(sp)
+; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu
+; RV32-NEXT: addi a0, sp, 8
+; RV32-NEXT: vlse64.v v24, (a0), zero
+; RV32-NEXT: vasubu.vv v8, v16, v24, v0.t
+; RV32-NEXT: addi sp, sp, 16
+; RV32-NEXT: ret
+;
+; RV64-LABEL: intrinsic_vasubu_mask_vx_nxv8i64_nxv8i64_i64:
+; RV64: # %bb.0: # %entry
+; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, mu
+; RV64-NEXT: vasubu.vx v8, v16, a0, v0.t
+; RV64-NEXT: ret
entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vasubu.mask.nxv8i64.i64(
<vscale x 8 x i64> %0,
<vscale x 8 x i64> %1,
i64 %2,
<vscale x 8 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 8 x i64> %a
}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmerge-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmerge-rv32.ll
deleted file mode 100644
index 11e92e65dbc9f..0000000000000
--- a/llvm/test/CodeGen/RISCV/rvv/vmerge-rv32.ll
+++ /dev/null
@@ -1,1816 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -mattr=+v,+d,+zfh -verify-machineinstrs \
-; RUN: < %s | FileCheck %s
-declare <vscale x 1 x i8> @llvm.riscv.vmerge.nxv1i8.nxv1i8(
- <vscale x 1 x i8>,
- <vscale x 1 x i8>,
- <vscale x 1 x i8>,
- <vscale x 1 x i1>,
- i32);
-
-define <vscale x 1 x i8> @intrinsic_vmerge_vvm_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
-; CHECK-LABEL: intrinsic_vmerge_vvm_nxv1i8_nxv1i8_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
-; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i8> @llvm.riscv.vmerge.nxv1i8.nxv1i8(
- <vscale x 1 x i8> undef,
- <vscale x 1 x i8> %0,
- <vscale x 1 x i8> %1,
- <vscale x 1 x i1> %2,
- i32 %3)
-
- ret <vscale x 1 x i8> %a
-}
-
-declare <vscale x 2 x i8> @llvm.riscv.vmerge.nxv2i8.nxv2i8(
- <vscale x 2 x i8>,
- <vscale x 2 x i8>,
- <vscale x 2 x i8>,
- <vscale x 2 x i1>,
- i32);
-
-define <vscale x 2 x i8> @intrinsic_vmerge_vvm_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
-; CHECK-LABEL: intrinsic_vmerge_vvm_nxv2i8_nxv2i8_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
-; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i8> @llvm.riscv.vmerge.nxv2i8.nxv2i8(
- <vscale x 2 x i8> undef,
- <vscale x 2 x i8> %0,
- <vscale x 2 x i8> %1,
- <vscale x 2 x i1> %2,
- i32 %3)
-
- ret <vscale x 2 x i8> %a
-}
-
-declare <vscale x 4 x i8> @llvm.riscv.vmerge.nxv4i8.nxv4i8(
- <vscale x 4 x i8>,
- <vscale x 4 x i8>,
- <vscale x 4 x i8>,
- <vscale x 4 x i1>,
- i32);
-
-define <vscale x 4 x i8> @intrinsic_vmerge_vvm_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
-; CHECK-LABEL: intrinsic_vmerge_vvm_nxv4i8_nxv4i8_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
-; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i8> @llvm.riscv.vmerge.nxv4i8.nxv4i8(
- <vscale x 4 x i8> undef,
- <vscale x 4 x i8> %0,
- <vscale x 4 x i8> %1,
- <vscale x 4 x i1> %2,
- i32 %3)
-
- ret <vscale x 4 x i8> %a
-}
-
-declare <vscale x 8 x i8> @llvm.riscv.vmerge.nxv8i8.nxv8i8(
- <vscale x 8 x i8>,
- <vscale x 8 x i8>,
- <vscale x 8 x i8>,
- <vscale x 8 x i1>,
- i32);
-
-define <vscale x 8 x i8> @intrinsic_vmerge_vvm_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
-; CHECK-LABEL: intrinsic_vmerge_vvm_nxv8i8_nxv8i8_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
-; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i8> @llvm.riscv.vmerge.nxv8i8.nxv8i8(
- <vscale x 8 x i8> undef,
- <vscale x 8 x i8> %0,
- <vscale x 8 x i8> %1,
- <vscale x 8 x i1> %2,
- i32 %3)
-
- ret <vscale x 8 x i8> %a
-}
-
-declare <vscale x 16 x i8> @llvm.riscv.vmerge.nxv16i8.nxv16i8(
- <vscale x 16 x i8>,
- <vscale x 16 x i8>,
- <vscale x 16 x i8>,
- <vscale x 16 x i1>,
- i32);
-
-define <vscale x 16 x i8> @intrinsic_vmerge_vvm_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i1> %2, i32 %3) nounwind {
-; CHECK-LABEL: intrinsic_vmerge_vvm_nxv16i8_nxv16i8_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
-; CHECK-NEXT: vmerge.vvm v8, v8, v10, v0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i8> @llvm.riscv.vmerge.nxv16i8.nxv16i8(
- <vscale x 16 x i8> undef,
- <vscale x 16 x i8> %0,
- <vscale x 16 x i8> %1,
- <vscale x 16 x i1> %2,
- i32 %3)
-
- ret <vscale x 16 x i8> %a
-}
-
-declare <vscale x 32 x i8> @llvm.riscv.vmerge.nxv32i8.nxv32i8(
- <vscale x 32 x i8>,
- <vscale x 32 x i8>,
- <vscale x 32 x i8>,
- <vscale x 32 x i1>,
- i32);
-
-define <vscale x 32 x i8> @intrinsic_vmerge_vvm_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i1> %2, i32 %3) nounwind {
-; CHECK-LABEL: intrinsic_vmerge_vvm_nxv32i8_nxv32i8_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
-; CHECK-NEXT: vmerge.vvm v8, v8, v12, v0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 32 x i8> @llvm.riscv.vmerge.nxv32i8.nxv32i8(
- <vscale x 32 x i8> undef,
- <vscale x 32 x i8> %0,
- <vscale x 32 x i8> %1,
- <vscale x 32 x i1> %2,
- i32 %3)
-
- ret <vscale x 32 x i8> %a
-}
-
-declare <vscale x 64 x i8> @llvm.riscv.vmerge.nxv64i8.nxv64i8(
- <vscale x 64 x i8>,
- <vscale x 64 x i8>,
- <vscale x 64 x i8>,
- <vscale x 64 x i1>,
- i32);
-
-define <vscale x 64 x i8> @intrinsic_vmerge_vvm_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i1> %2, i32 %3) nounwind {
-; CHECK-LABEL: intrinsic_vmerge_vvm_nxv64i8_nxv64i8_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, mu
-; CHECK-NEXT: vmerge.vvm v8, v8, v16, v0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 64 x i8> @llvm.riscv.vmerge.nxv64i8.nxv64i8(
- <vscale x 64 x i8> undef,
- <vscale x 64 x i8> %0,
- <vscale x 64 x i8> %1,
- <vscale x 64 x i1> %2,
- i32 %3)
-
- ret <vscale x 64 x i8> %a
-}
-
-declare <vscale x 1 x i16> @llvm.riscv.vmerge.nxv1i16.nxv1i16(
- <vscale x 1 x i16>,
- <vscale x 1 x i16>,
- <vscale x 1 x i16>,
- <vscale x 1 x i1>,
- i32);
-
-define <vscale x 1 x i16> @intrinsic_vmerge_vvm_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
-; CHECK-LABEL: intrinsic_vmerge_vvm_nxv1i16_nxv1i16_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i16> @llvm.riscv.vmerge.nxv1i16.nxv1i16(
- <vscale x 1 x i16> undef,
- <vscale x 1 x i16> %0,
- <vscale x 1 x i16> %1,
- <vscale x 1 x i1> %2,
- i32 %3)
-
- ret <vscale x 1 x i16> %a
-}
-
-declare <vscale x 2 x i16> @llvm.riscv.vmerge.nxv2i16.nxv2i16(
- <vscale x 2 x i16>,
- <vscale x 2 x i16>,
- <vscale x 2 x i16>,
- <vscale x 2 x i1>,
- i32);
-
-define <vscale x 2 x i16> @intrinsic_vmerge_vvm_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
-; CHECK-LABEL: intrinsic_vmerge_vvm_nxv2i16_nxv2i16_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i16> @llvm.riscv.vmerge.nxv2i16.nxv2i16(
- <vscale x 2 x i16> undef,
- <vscale x 2 x i16> %0,
- <vscale x 2 x i16> %1,
- <vscale x 2 x i1> %2,
- i32 %3)
-
- ret <vscale x 2 x i16> %a
-}
-
-declare <vscale x 4 x i16> @llvm.riscv.vmerge.nxv4i16.nxv4i16(
- <vscale x 4 x i16>,
- <vscale x 4 x i16>,
- <vscale x 4 x i16>,
- <vscale x 4 x i1>,
- i32);
-
-define <vscale x 4 x i16> @intrinsic_vmerge_vvm_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
-; CHECK-LABEL: intrinsic_vmerge_vvm_nxv4i16_nxv4i16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i16> @llvm.riscv.vmerge.nxv4i16.nxv4i16(
- <vscale x 4 x i16> undef,
- <vscale x 4 x i16> %0,
- <vscale x 4 x i16> %1,
- <vscale x 4 x i1> %2,
- i32 %3)
-
- ret <vscale x 4 x i16> %a
-}
-
-declare <vscale x 8 x i16> @llvm.riscv.vmerge.nxv8i16.nxv8i16(
- <vscale x 8 x i16>,
- <vscale x 8 x i16>,
- <vscale x 8 x i16>,
- <vscale x 8 x i1>,
- i32);
-
-define <vscale x 8 x i16> @intrinsic_vmerge_vvm_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
-; CHECK-LABEL: intrinsic_vmerge_vvm_nxv8i16_nxv8i16_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vmerge.vvm v8, v8, v10, v0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i16> @llvm.riscv.vmerge.nxv8i16.nxv8i16(
- <vscale x 8 x i16> undef,
- <vscale x 8 x i16> %0,
- <vscale x 8 x i16> %1,
- <vscale x 8 x i1> %2,
- i32 %3)
-
- ret <vscale x 8 x i16> %a
-}
-
-declare <vscale x 16 x i16> @llvm.riscv.vmerge.nxv16i16.nxv16i16(
- <vscale x 16 x i16>,
- <vscale x 16 x i16>,
- <vscale x 16 x i16>,
- <vscale x 16 x i1>,
- i32);
-
-define <vscale x 16 x i16> @intrinsic_vmerge_vvm_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i1> %2, i32 %3) nounwind {
-; CHECK-LABEL: intrinsic_vmerge_vvm_nxv16i16_nxv16i16_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
-; CHECK-NEXT: vmerge.vvm v8, v8, v12, v0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i16> @llvm.riscv.vmerge.nxv16i16.nxv16i16(
- <vscale x 16 x i16> undef,
- <vscale x 16 x i16> %0,
- <vscale x 16 x i16> %1,
- <vscale x 16 x i1> %2,
- i32 %3)
-
- ret <vscale x 16 x i16> %a
-}
-
-declare <vscale x 32 x i16> @llvm.riscv.vmerge.nxv32i16.nxv32i16(
- <vscale x 32 x i16>,
- <vscale x 32 x i16>,
- <vscale x 32 x i16>,
- <vscale x 32 x i1>,
- i32);
-
-define <vscale x 32 x i16> @intrinsic_vmerge_vvm_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i1> %2, i32 %3) nounwind {
-; CHECK-LABEL: intrinsic_vmerge_vvm_nxv32i16_nxv32i16_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, mu
-; CHECK-NEXT: vmerge.vvm v8, v8, v16, v0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 32 x i16> @llvm.riscv.vmerge.nxv32i16.nxv32i16(
- <vscale x 32 x i16> undef,
- <vscale x 32 x i16> %0,
- <vscale x 32 x i16> %1,
- <vscale x 32 x i1> %2,
- i32 %3)
-
- ret <vscale x 32 x i16> %a
-}
-
-declare <vscale x 1 x i32> @llvm.riscv.vmerge.nxv1i32.nxv1i32(
- <vscale x 1 x i32>,
- <vscale x 1 x i32>,
- <vscale x 1 x i32>,
- <vscale x 1 x i1>,
- i32);
-
-define <vscale x 1 x i32> @intrinsic_vmerge_vvm_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
-; CHECK-LABEL: intrinsic_vmerge_vvm_nxv1i32_nxv1i32_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i32> @llvm.riscv.vmerge.nxv1i32.nxv1i32(
- <vscale x 1 x i32> undef,
- <vscale x 1 x i32> %0,
- <vscale x 1 x i32> %1,
- <vscale x 1 x i1> %2,
- i32 %3)
-
- ret <vscale x 1 x i32> %a
-}
-
-declare <vscale x 2 x i32> @llvm.riscv.vmerge.nxv2i32.nxv2i32(
- <vscale x 2 x i32>,
- <vscale x 2 x i32>,
- <vscale x 2 x i32>,
- <vscale x 2 x i1>,
- i32);
-
-define <vscale x 2 x i32> @intrinsic_vmerge_vvm_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
-; CHECK-LABEL: intrinsic_vmerge_vvm_nxv2i32_nxv2i32_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i32> @llvm.riscv.vmerge.nxv2i32.nxv2i32(
- <vscale x 2 x i32> undef,
- <vscale x 2 x i32> %0,
- <vscale x 2 x i32> %1,
- <vscale x 2 x i1> %2,
- i32 %3)
-
- ret <vscale x 2 x i32> %a
-}
-
-declare <vscale x 4 x i32> @llvm.riscv.vmerge.nxv4i32.nxv4i32(
- <vscale x 4 x i32>,
- <vscale x 4 x i32>,
- <vscale x 4 x i32>,
- <vscale x 4 x i1>,
- i32);
-
-define <vscale x 4 x i32> @intrinsic_vmerge_vvm_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
-; CHECK-LABEL: intrinsic_vmerge_vvm_nxv4i32_nxv4i32_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vmerge.vvm v8, v8, v10, v0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i32> @llvm.riscv.vmerge.nxv4i32.nxv4i32(
- <vscale x 4 x i32> undef,
- <vscale x 4 x i32> %0,
- <vscale x 4 x i32> %1,
- <vscale x 4 x i1> %2,
- i32 %3)
-
- ret <vscale x 4 x i32> %a
-}
-
-declare <vscale x 8 x i32> @llvm.riscv.vmerge.nxv8i32.nxv8i32(
- <vscale x 8 x i32>,
- <vscale x 8 x i32>,
- <vscale x 8 x i32>,
- <vscale x 8 x i1>,
- i32);
-
-define <vscale x 8 x i32> @intrinsic_vmerge_vvm_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
-; CHECK-LABEL: intrinsic_vmerge_vvm_nxv8i32_nxv8i32_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
-; CHECK-NEXT: vmerge.vvm v8, v8, v12, v0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i32> @llvm.riscv.vmerge.nxv8i32.nxv8i32(
- <vscale x 8 x i32> undef,
- <vscale x 8 x i32> %0,
- <vscale x 8 x i32> %1,
- <vscale x 8 x i1> %2,
- i32 %3)
-
- ret <vscale x 8 x i32> %a
-}
-
-declare <vscale x 16 x i32> @llvm.riscv.vmerge.nxv16i32.nxv16i32(
- <vscale x 16 x i32>,
- <vscale x 16 x i32>,
- <vscale x 16 x i32>,
- <vscale x 16 x i1>,
- i32);
-
-define <vscale x 16 x i32> @intrinsic_vmerge_vvm_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i1> %2, i32 %3) nounwind {
-; CHECK-LABEL: intrinsic_vmerge_vvm_nxv16i32_nxv16i32_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu
-; CHECK-NEXT: vmerge.vvm v8, v8, v16, v0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i32> @llvm.riscv.vmerge.nxv16i32.nxv16i32(
- <vscale x 16 x i32> undef,
- <vscale x 16 x i32> %0,
- <vscale x 16 x i32> %1,
- <vscale x 16 x i1> %2,
- i32 %3)
-
- ret <vscale x 16 x i32> %a
-}
-
-declare <vscale x 1 x i64> @llvm.riscv.vmerge.nxv1i64.nxv1i64(
- <vscale x 1 x i64>,
- <vscale x 1 x i64>,
- <vscale x 1 x i64>,
- <vscale x 1 x i1>,
- i32);
-
-define <vscale x 1 x i64> @intrinsic_vmerge_vvm_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
-; CHECK-LABEL: intrinsic_vmerge_vvm_nxv1i64_nxv1i64_nxv1i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
-; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i64> @llvm.riscv.vmerge.nxv1i64.nxv1i64(
- <vscale x 1 x i64> undef,
- <vscale x 1 x i64> %0,
- <vscale x 1 x i64> %1,
- <vscale x 1 x i1> %2,
- i32 %3)
-
- ret <vscale x 1 x i64> %a
-}
-
-declare <vscale x 2 x i64> @llvm.riscv.vmerge.nxv2i64.nxv2i64(
- <vscale x 2 x i64>,
- <vscale x 2 x i64>,
- <vscale x 2 x i64>,
- <vscale x 2 x i1>,
- i32);
-
-define <vscale x 2 x i64> @intrinsic_vmerge_vvm_nxv2i64_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
-; CHECK-LABEL: intrinsic_vmerge_vvm_nxv2i64_nxv2i64_nxv2i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
-; CHECK-NEXT: vmerge.vvm v8, v8, v10, v0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i64> @llvm.riscv.vmerge.nxv2i64.nxv2i64(
- <vscale x 2 x i64> undef,
- <vscale x 2 x i64> %0,
- <vscale x 2 x i64> %1,
- <vscale x 2 x i1> %2,
- i32 %3)
-
- ret <vscale x 2 x i64> %a
-}
-
-declare <vscale x 4 x i64> @llvm.riscv.vmerge.nxv4i64.nxv4i64(
- <vscale x 4 x i64>,
- <vscale x 4 x i64>,
- <vscale x 4 x i64>,
- <vscale x 4 x i1>,
- i32);
-
-define <vscale x 4 x i64> @intrinsic_vmerge_vvm_nxv4i64_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
-; CHECK-LABEL: intrinsic_vmerge_vvm_nxv4i64_nxv4i64_nxv4i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
-; CHECK-NEXT: vmerge.vvm v8, v8, v12, v0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i64> @llvm.riscv.vmerge.nxv4i64.nxv4i64(
- <vscale x 4 x i64> undef,
- <vscale x 4 x i64> %0,
- <vscale x 4 x i64> %1,
- <vscale x 4 x i1> %2,
- i32 %3)
-
- ret <vscale x 4 x i64> %a
-}
-
-declare <vscale x 8 x i64> @llvm.riscv.vmerge.nxv8i64.nxv8i64(
- <vscale x 8 x i64>,
- <vscale x 8 x i64>,
- <vscale x 8 x i64>,
- <vscale x 8 x i1>,
- i32);
-
-define <vscale x 8 x i64> @intrinsic_vmerge_vvm_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
-; CHECK-LABEL: intrinsic_vmerge_vvm_nxv8i64_nxv8i64_nxv8i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu
-; CHECK-NEXT: vmerge.vvm v8, v8, v16, v0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i64> @llvm.riscv.vmerge.nxv8i64.nxv8i64(
- <vscale x 8 x i64> undef,
- <vscale x 8 x i64> %0,
- <vscale x 8 x i64> %1,
- <vscale x 8 x i1> %2,
- i32 %3)
-
- ret <vscale x 8 x i64> %a
-}
-
-declare <vscale x 1 x i8> @llvm.riscv.vmerge.nxv1i8.i8(
- <vscale x 1 x i8>,
- <vscale x 1 x i8>,
- i8,
- <vscale x 1 x i1>,
- i32);
-
-define <vscale x 1 x i8> @intrinsic_vmerge_vxm_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
-; CHECK-LABEL: intrinsic_vmerge_vxm_nxv1i8_nxv1i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
-; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i8> @llvm.riscv.vmerge.nxv1i8.i8(
- <vscale x 1 x i8> undef,
- <vscale x 1 x i8> %0,
- i8 %1,
- <vscale x 1 x i1> %2,
- i32 %3)
-
- ret <vscale x 1 x i8> %a
-}
-
-declare <vscale x 2 x i8> @llvm.riscv.vmerge.nxv2i8.i8(
- <vscale x 2 x i8>,
- <vscale x 2 x i8>,
- i8,
- <vscale x 2 x i1>,
- i32);
-
-define <vscale x 2 x i8> @intrinsic_vmerge_vxm_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, i8 %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
-; CHECK-LABEL: intrinsic_vmerge_vxm_nxv2i8_nxv2i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
-; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i8> @llvm.riscv.vmerge.nxv2i8.i8(
- <vscale x 2 x i8> undef,
- <vscale x 2 x i8> %0,
- i8 %1,
- <vscale x 2 x i1> %2,
- i32 %3)
-
- ret <vscale x 2 x i8> %a
-}
-
-declare <vscale x 4 x i8> @llvm.riscv.vmerge.nxv4i8.i8(
- <vscale x 4 x i8>,
- <vscale x 4 x i8>,
- i8,
- <vscale x 4 x i1>,
- i32);
-
-define <vscale x 4 x i8> @intrinsic_vmerge_vxm_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, i8 %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
-; CHECK-LABEL: intrinsic_vmerge_vxm_nxv4i8_nxv4i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
-; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i8> @llvm.riscv.vmerge.nxv4i8.i8(
- <vscale x 4 x i8> undef,
- <vscale x 4 x i8> %0,
- i8 %1,
- <vscale x 4 x i1> %2,
- i32 %3)
-
- ret <vscale x 4 x i8> %a
-}
-
-declare <vscale x 8 x i8> @llvm.riscv.vmerge.nxv8i8.i8(
- <vscale x 8 x i8>,
- <vscale x 8 x i8>,
- i8,
- <vscale x 8 x i1>,
- i32);
-
-define <vscale x 8 x i8> @intrinsic_vmerge_vxm_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, i8 %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
-; CHECK-LABEL: intrinsic_vmerge_vxm_nxv8i8_nxv8i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
-; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i8> @llvm.riscv.vmerge.nxv8i8.i8(
- <vscale x 8 x i8> undef,
- <vscale x 8 x i8> %0,
- i8 %1,
- <vscale x 8 x i1> %2,
- i32 %3)
-
- ret <vscale x 8 x i8> %a
-}
-
-declare <vscale x 16 x i8> @llvm.riscv.vmerge.nxv16i8.i8(
- <vscale x 16 x i8>,
- <vscale x 16 x i8>,
- i8,
- <vscale x 16 x i1>,
- i32);
-
-define <vscale x 16 x i8> @intrinsic_vmerge_vxm_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, i8 %1, <vscale x 16 x i1> %2, i32 %3) nounwind {
-; CHECK-LABEL: intrinsic_vmerge_vxm_nxv16i8_nxv16i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
-; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i8> @llvm.riscv.vmerge.nxv16i8.i8(
- <vscale x 16 x i8> undef,
- <vscale x 16 x i8> %0,
- i8 %1,
- <vscale x 16 x i1> %2,
- i32 %3)
-
- ret <vscale x 16 x i8> %a
-}
-
-declare <vscale x 32 x i8> @llvm.riscv.vmerge.nxv32i8.i8(
- <vscale x 32 x i8>,
- <vscale x 32 x i8>,
- i8,
- <vscale x 32 x i1>,
- i32);
-
-define <vscale x 32 x i8> @intrinsic_vmerge_vxm_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, i8 %1, <vscale x 32 x i1> %2, i32 %3) nounwind {
-; CHECK-LABEL: intrinsic_vmerge_vxm_nxv32i8_nxv32i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
-; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 32 x i8> @llvm.riscv.vmerge.nxv32i8.i8(
- <vscale x 32 x i8> undef,
- <vscale x 32 x i8> %0,
- i8 %1,
- <vscale x 32 x i1> %2,
- i32 %3)
-
- ret <vscale x 32 x i8> %a
-}
-
-declare <vscale x 64 x i8> @llvm.riscv.vmerge.nxv64i8.i8(
- <vscale x 64 x i8>,
- <vscale x 64 x i8>,
- i8,
- <vscale x 64 x i1>,
- i32);
-
-define <vscale x 64 x i8> @intrinsic_vmerge_vxm_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, i8 %1, <vscale x 64 x i1> %2, i32 %3) nounwind {
-; CHECK-LABEL: intrinsic_vmerge_vxm_nxv64i8_nxv64i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu
-; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 64 x i8> @llvm.riscv.vmerge.nxv64i8.i8(
- <vscale x 64 x i8> undef,
- <vscale x 64 x i8> %0,
- i8 %1,
- <vscale x 64 x i1> %2,
- i32 %3)
-
- ret <vscale x 64 x i8> %a
-}
-
-declare <vscale x 1 x i16> @llvm.riscv.vmerge.nxv1i16.i16(
- <vscale x 1 x i16>,
- <vscale x 1 x i16>,
- i16,
- <vscale x 1 x i1>,
- i32);
-
-define <vscale x 1 x i16> @intrinsic_vmerge_vxm_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, i16 %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
-; CHECK-LABEL: intrinsic_vmerge_vxm_nxv1i16_nxv1i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
-; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i16> @llvm.riscv.vmerge.nxv1i16.i16(
- <vscale x 1 x i16> undef,
- <vscale x 1 x i16> %0,
- i16 %1,
- <vscale x 1 x i1> %2,
- i32 %3)
-
- ret <vscale x 1 x i16> %a
-}
-
-declare <vscale x 2 x i16> @llvm.riscv.vmerge.nxv2i16.i16(
- <vscale x 2 x i16>,
- <vscale x 2 x i16>,
- i16,
- <vscale x 2 x i1>,
- i32);
-
-define <vscale x 2 x i16> @intrinsic_vmerge_vxm_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, i16 %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
-; CHECK-LABEL: intrinsic_vmerge_vxm_nxv2i16_nxv2i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
-; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i16> @llvm.riscv.vmerge.nxv2i16.i16(
- <vscale x 2 x i16> undef,
- <vscale x 2 x i16> %0,
- i16 %1,
- <vscale x 2 x i1> %2,
- i32 %3)
-
- ret <vscale x 2 x i16> %a
-}
-
-declare <vscale x 4 x i16> @llvm.riscv.vmerge.nxv4i16.i16(
- <vscale x 4 x i16>,
- <vscale x 4 x i16>,
- i16,
- <vscale x 4 x i1>,
- i32);
-
-define <vscale x 4 x i16> @intrinsic_vmerge_vxm_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, i16 %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
-; CHECK-LABEL: intrinsic_vmerge_vxm_nxv4i16_nxv4i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
-; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i16> @llvm.riscv.vmerge.nxv4i16.i16(
- <vscale x 4 x i16> undef,
- <vscale x 4 x i16> %0,
- i16 %1,
- <vscale x 4 x i1> %2,
- i32 %3)
-
- ret <vscale x 4 x i16> %a
-}
-
-declare <vscale x 8 x i16> @llvm.riscv.vmerge.nxv8i16.i16(
- <vscale x 8 x i16>,
- <vscale x 8 x i16>,
- i16,
- <vscale x 8 x i1>,
- i32);
-
-define <vscale x 8 x i16> @intrinsic_vmerge_vxm_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, i16 %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
-; CHECK-LABEL: intrinsic_vmerge_vxm_nxv8i16_nxv8i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
-; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i16> @llvm.riscv.vmerge.nxv8i16.i16(
- <vscale x 8 x i16> undef,
- <vscale x 8 x i16> %0,
- i16 %1,
- <vscale x 8 x i1> %2,
- i32 %3)
-
- ret <vscale x 8 x i16> %a
-}
-
-declare <vscale x 16 x i16> @llvm.riscv.vmerge.nxv16i16.i16(
- <vscale x 16 x i16>,
- <vscale x 16 x i16>,
- i16,
- <vscale x 16 x i1>,
- i32);
-
-define <vscale x 16 x i16> @intrinsic_vmerge_vxm_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, i16 %1, <vscale x 16 x i1> %2, i32 %3) nounwind {
-; CHECK-LABEL: intrinsic_vmerge_vxm_nxv16i16_nxv16i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
-; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i16> @llvm.riscv.vmerge.nxv16i16.i16(
- <vscale x 16 x i16> undef,
- <vscale x 16 x i16> %0,
- i16 %1,
- <vscale x 16 x i1> %2,
- i32 %3)
-
- ret <vscale x 16 x i16> %a
-}
-
-declare <vscale x 32 x i16> @llvm.riscv.vmerge.nxv32i16.i16(
- <vscale x 32 x i16>,
- <vscale x 32 x i16>,
- i16,
- <vscale x 32 x i1>,
- i32);
-
-define <vscale x 32 x i16> @intrinsic_vmerge_vxm_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, i16 %1, <vscale x 32 x i1> %2, i32 %3) nounwind {
-; CHECK-LABEL: intrinsic_vmerge_vxm_nxv32i16_nxv32i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu
-; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 32 x i16> @llvm.riscv.vmerge.nxv32i16.i16(
- <vscale x 32 x i16> undef,
- <vscale x 32 x i16> %0,
- i16 %1,
- <vscale x 32 x i1> %2,
- i32 %3)
-
- ret <vscale x 32 x i16> %a
-}
-
-declare <vscale x 1 x i32> @llvm.riscv.vmerge.nxv1i32.i32(
- <vscale x 1 x i32>,
- <vscale x 1 x i32>,
- i32,
- <vscale x 1 x i1>,
- i32);
-
-define <vscale x 1 x i32> @intrinsic_vmerge_vxm_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, i32 %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
-; CHECK-LABEL: intrinsic_vmerge_vxm_nxv1i32_nxv1i32_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
-; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i32> @llvm.riscv.vmerge.nxv1i32.i32(
- <vscale x 1 x i32> undef,
- <vscale x 1 x i32> %0,
- i32 %1,
- <vscale x 1 x i1> %2,
- i32 %3)
-
- ret <vscale x 1 x i32> %a
-}
-
-declare <vscale x 2 x i32> @llvm.riscv.vmerge.nxv2i32.i32(
- <vscale x 2 x i32>,
- <vscale x 2 x i32>,
- i32,
- <vscale x 2 x i1>,
- i32);
-
-define <vscale x 2 x i32> @intrinsic_vmerge_vxm_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, i32 %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
-; CHECK-LABEL: intrinsic_vmerge_vxm_nxv2i32_nxv2i32_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
-; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i32> @llvm.riscv.vmerge.nxv2i32.i32(
- <vscale x 2 x i32> undef,
- <vscale x 2 x i32> %0,
- i32 %1,
- <vscale x 2 x i1> %2,
- i32 %3)
-
- ret <vscale x 2 x i32> %a
-}
-
-declare <vscale x 4 x i32> @llvm.riscv.vmerge.nxv4i32.i32(
- <vscale x 4 x i32>,
- <vscale x 4 x i32>,
- i32,
- <vscale x 4 x i1>,
- i32);
-
-define <vscale x 4 x i32> @intrinsic_vmerge_vxm_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, i32 %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
-; CHECK-LABEL: intrinsic_vmerge_vxm_nxv4i32_nxv4i32_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i32> @llvm.riscv.vmerge.nxv4i32.i32(
- <vscale x 4 x i32> undef,
- <vscale x 4 x i32> %0,
- i32 %1,
- <vscale x 4 x i1> %2,
- i32 %3)
-
- ret <vscale x 4 x i32> %a
-}
-
-declare <vscale x 8 x i32> @llvm.riscv.vmerge.nxv8i32.i32(
- <vscale x 8 x i32>,
- <vscale x 8 x i32>,
- i32,
- <vscale x 8 x i1>,
- i32);
-
-define <vscale x 8 x i32> @intrinsic_vmerge_vxm_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, i32 %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
-; CHECK-LABEL: intrinsic_vmerge_vxm_nxv8i32_nxv8i32_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
-; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i32> @llvm.riscv.vmerge.nxv8i32.i32(
- <vscale x 8 x i32> undef,
- <vscale x 8 x i32> %0,
- i32 %1,
- <vscale x 8 x i1> %2,
- i32 %3)
-
- ret <vscale x 8 x i32> %a
-}
-
-declare <vscale x 16 x i32> @llvm.riscv.vmerge.nxv16i32.i32(
- <vscale x 16 x i32>,
- <vscale x 16 x i32>,
- i32,
- <vscale x 16 x i1>,
- i32);
-
-define <vscale x 16 x i32> @intrinsic_vmerge_vxm_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, i32 %1, <vscale x 16 x i1> %2, i32 %3) nounwind {
-; CHECK-LABEL: intrinsic_vmerge_vxm_nxv16i32_nxv16i32_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu
-; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i32> @llvm.riscv.vmerge.nxv16i32.i32(
- <vscale x 16 x i32> undef,
- <vscale x 16 x i32> %0,
- i32 %1,
- <vscale x 16 x i1> %2,
- i32 %3)
-
- ret <vscale x 16 x i32> %a
-}
-
-declare <vscale x 1 x i64> @llvm.riscv.vmerge.nxv1i64.i64(
- <vscale x 1 x i64>,
- <vscale x 1 x i64>,
- i64,
- <vscale x 1 x i1>,
- i32);
-
-define <vscale x 1 x i64> @intrinsic_vmerge_vxm_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
-; CHECK-LABEL: intrinsic_vmerge_vxm_nxv1i64_nxv1i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addi sp, sp, -16
-; CHECK-NEXT: sw a1, 12(sp)
-; CHECK-NEXT: sw a0, 8(sp)
-; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
-; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v9, (a0), zero
-; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0
-; CHECK-NEXT: addi sp, sp, 16
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i64> @llvm.riscv.vmerge.nxv1i64.i64(
- <vscale x 1 x i64> undef,
- <vscale x 1 x i64> %0,
- i64 %1,
- <vscale x 1 x i1> %2,
- i32 %3)
-
- ret <vscale x 1 x i64> %a
-}
-
-declare <vscale x 2 x i64> @llvm.riscv.vmerge.nxv2i64.i64(
- <vscale x 2 x i64>,
- <vscale x 2 x i64>,
- i64,
- <vscale x 2 x i1>,
- i32);
-
-define <vscale x 2 x i64> @intrinsic_vmerge_vxm_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
-; CHECK-LABEL: intrinsic_vmerge_vxm_nxv2i64_nxv2i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addi sp, sp, -16
-; CHECK-NEXT: sw a1, 12(sp)
-; CHECK-NEXT: sw a0, 8(sp)
-; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
-; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v10, (a0), zero
-; CHECK-NEXT: vmerge.vvm v8, v8, v10, v0
-; CHECK-NEXT: addi sp, sp, 16
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i64> @llvm.riscv.vmerge.nxv2i64.i64(
- <vscale x 2 x i64> undef,
- <vscale x 2 x i64> %0,
- i64 %1,
- <vscale x 2 x i1> %2,
- i32 %3)
-
- ret <vscale x 2 x i64> %a
-}
-
-declare <vscale x 4 x i64> @llvm.riscv.vmerge.nxv4i64.i64(
- <vscale x 4 x i64>,
- <vscale x 4 x i64>,
- i64,
- <vscale x 4 x i1>,
- i32);
-
-define <vscale x 4 x i64> @intrinsic_vmerge_vxm_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
-; CHECK-LABEL: intrinsic_vmerge_vxm_nxv4i64_nxv4i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addi sp, sp, -16
-; CHECK-NEXT: sw a1, 12(sp)
-; CHECK-NEXT: sw a0, 8(sp)
-; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
-; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v12, (a0), zero
-; CHECK-NEXT: vmerge.vvm v8, v8, v12, v0
-; CHECK-NEXT: addi sp, sp, 16
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i64> @llvm.riscv.vmerge.nxv4i64.i64(
- <vscale x 4 x i64> undef,
- <vscale x 4 x i64> %0,
- i64 %1,
- <vscale x 4 x i1> %2,
- i32 %3)
-
- ret <vscale x 4 x i64> %a
-}
-
-declare <vscale x 8 x i64> @llvm.riscv.vmerge.nxv8i64.i64(
- <vscale x 8 x i64>,
- <vscale x 8 x i64>,
- i64,
- <vscale x 8 x i1>,
- i32);
-
-define <vscale x 8 x i64> @intrinsic_vmerge_vxm_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, i64 %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
-; CHECK-LABEL: intrinsic_vmerge_vxm_nxv8i64_nxv8i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addi sp, sp, -16
-; CHECK-NEXT: sw a1, 12(sp)
-; CHECK-NEXT: sw a0, 8(sp)
-; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, mu
-; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v16, (a0), zero
-; CHECK-NEXT: vmerge.vvm v8, v8, v16, v0
-; CHECK-NEXT: addi sp, sp, 16
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i64> @llvm.riscv.vmerge.nxv8i64.i64(
- <vscale x 8 x i64> undef,
- <vscale x 8 x i64> %0,
- i64 %1,
- <vscale x 8 x i1> %2,
- i32 %3)
-
- ret <vscale x 8 x i64> %a
-}
-
-define <vscale x 1 x i8> @intrinsic_vmerge_vim_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, <vscale x 1 x i1> %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmerge_vim_nxv1i8_nxv1i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
-; CHECK-NEXT: vmerge.vim v8, v8, 9, v0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i8> @llvm.riscv.vmerge.nxv1i8.i8(
- <vscale x 1 x i8> undef,
- <vscale x 1 x i8> %0,
- i8 9,
- <vscale x 1 x i1> %1,
- i32 %2)
-
- ret <vscale x 1 x i8> %a
-}
-
-define <vscale x 2 x i8> @intrinsic_vmerge_vim_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, <vscale x 2 x i1> %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmerge_vim_nxv2i8_nxv2i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
-; CHECK-NEXT: vmerge.vim v8, v8, 9, v0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i8> @llvm.riscv.vmerge.nxv2i8.i8(
- <vscale x 2 x i8> undef,
- <vscale x 2 x i8> %0,
- i8 9,
- <vscale x 2 x i1> %1,
- i32 %2)
-
- ret <vscale x 2 x i8> %a
-}
-
-define <vscale x 4 x i8> @intrinsic_vmerge_vim_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, <vscale x 4 x i1> %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmerge_vim_nxv4i8_nxv4i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
-; CHECK-NEXT: vmerge.vim v8, v8, 9, v0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i8> @llvm.riscv.vmerge.nxv4i8.i8(
- <vscale x 4 x i8> undef,
- <vscale x 4 x i8> %0,
- i8 9,
- <vscale x 4 x i1> %1,
- i32 %2)
-
- ret <vscale x 4 x i8> %a
-}
-
-define <vscale x 8 x i8> @intrinsic_vmerge_vim_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, <vscale x 8 x i1> %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmerge_vim_nxv8i8_nxv8i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
-; CHECK-NEXT: vmerge.vim v8, v8, 9, v0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i8> @llvm.riscv.vmerge.nxv8i8.i8(
- <vscale x 8 x i8> undef,
- <vscale x 8 x i8> %0,
- i8 9,
- <vscale x 8 x i1> %1,
- i32 %2)
-
- ret <vscale x 8 x i8> %a
-}
-
-define <vscale x 16 x i8> @intrinsic_vmerge_vim_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, <vscale x 16 x i1> %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmerge_vim_nxv16i8_nxv16i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
-; CHECK-NEXT: vmerge.vim v8, v8, 9, v0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i8> @llvm.riscv.vmerge.nxv16i8.i8(
- <vscale x 16 x i8> undef,
- <vscale x 16 x i8> %0,
- i8 9,
- <vscale x 16 x i1> %1,
- i32 %2)
-
- ret <vscale x 16 x i8> %a
-}
-
-define <vscale x 32 x i8> @intrinsic_vmerge_vim_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, <vscale x 32 x i1> %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmerge_vim_nxv32i8_nxv32i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
-; CHECK-NEXT: vmerge.vim v8, v8, 9, v0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 32 x i8> @llvm.riscv.vmerge.nxv32i8.i8(
- <vscale x 32 x i8> undef,
- <vscale x 32 x i8> %0,
- i8 9,
- <vscale x 32 x i1> %1,
- i32 %2)
-
- ret <vscale x 32 x i8> %a
-}
-
-define <vscale x 64 x i8> @intrinsic_vmerge_vim_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, <vscale x 64 x i1> %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmerge_vim_nxv64i8_nxv64i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, mu
-; CHECK-NEXT: vmerge.vim v8, v8, 9, v0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 64 x i8> @llvm.riscv.vmerge.nxv64i8.i8(
- <vscale x 64 x i8> undef,
- <vscale x 64 x i8> %0,
- i8 9,
- <vscale x 64 x i1> %1,
- i32 %2)
-
- ret <vscale x 64 x i8> %a
-}
-
-define <vscale x 1 x i16> @intrinsic_vmerge_vim_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, <vscale x 1 x i1> %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmerge_vim_nxv1i16_nxv1i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vmerge.vim v8, v8, 9, v0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i16> @llvm.riscv.vmerge.nxv1i16.i16(
- <vscale x 1 x i16> undef,
- <vscale x 1 x i16> %0,
- i16 9,
- <vscale x 1 x i1> %1,
- i32 %2)
-
- ret <vscale x 1 x i16> %a
-}
-
-define <vscale x 2 x i16> @intrinsic_vmerge_vim_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, <vscale x 2 x i1> %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmerge_vim_nxv2i16_nxv2i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vmerge.vim v8, v8, 9, v0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i16> @llvm.riscv.vmerge.nxv2i16.i16(
- <vscale x 2 x i16> undef,
- <vscale x 2 x i16> %0,
- i16 9,
- <vscale x 2 x i1> %1,
- i32 %2)
-
- ret <vscale x 2 x i16> %a
-}
-
-define <vscale x 4 x i16> @intrinsic_vmerge_vim_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, <vscale x 4 x i1> %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmerge_vim_nxv4i16_nxv4i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vmerge.vim v8, v8, 9, v0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i16> @llvm.riscv.vmerge.nxv4i16.i16(
- <vscale x 4 x i16> undef,
- <vscale x 4 x i16> %0,
- i16 9,
- <vscale x 4 x i1> %1,
- i32 %2)
-
- ret <vscale x 4 x i16> %a
-}
-
-define <vscale x 8 x i16> @intrinsic_vmerge_vim_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, <vscale x 8 x i1> %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmerge_vim_nxv8i16_nxv8i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vmerge.vim v8, v8, 9, v0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i16> @llvm.riscv.vmerge.nxv8i16.i16(
- <vscale x 8 x i16> undef,
- <vscale x 8 x i16> %0,
- i16 9,
- <vscale x 8 x i1> %1,
- i32 %2)
-
- ret <vscale x 8 x i16> %a
-}
-
-define <vscale x 16 x i16> @intrinsic_vmerge_vim_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, <vscale x 16 x i1> %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmerge_vim_nxv16i16_nxv16i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
-; CHECK-NEXT: vmerge.vim v8, v8, 9, v0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i16> @llvm.riscv.vmerge.nxv16i16.i16(
- <vscale x 16 x i16> undef,
- <vscale x 16 x i16> %0,
- i16 9,
- <vscale x 16 x i1> %1,
- i32 %2)
-
- ret <vscale x 16 x i16> %a
-}
-
-define <vscale x 32 x i16> @intrinsic_vmerge_vim_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, <vscale x 32 x i1> %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmerge_vim_nxv32i16_nxv32i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, mu
-; CHECK-NEXT: vmerge.vim v8, v8, 9, v0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 32 x i16> @llvm.riscv.vmerge.nxv32i16.i16(
- <vscale x 32 x i16> undef,
- <vscale x 32 x i16> %0,
- i16 9,
- <vscale x 32 x i1> %1,
- i32 %2)
-
- ret <vscale x 32 x i16> %a
-}
-
-define <vscale x 1 x i32> @intrinsic_vmerge_vim_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 1 x i1> %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmerge_vim_nxv1i32_nxv1i32_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vmerge.vim v8, v8, 9, v0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i32> @llvm.riscv.vmerge.nxv1i32.i32(
- <vscale x 1 x i32> undef,
- <vscale x 1 x i32> %0,
- i32 9,
- <vscale x 1 x i1> %1,
- i32 %2)
-
- ret <vscale x 1 x i32> %a
-}
-
-define <vscale x 2 x i32> @intrinsic_vmerge_vim_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 2 x i1> %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmerge_vim_nxv2i32_nxv2i32_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vmerge.vim v8, v8, 9, v0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i32> @llvm.riscv.vmerge.nxv2i32.i32(
- <vscale x 2 x i32> undef,
- <vscale x 2 x i32> %0,
- i32 9,
- <vscale x 2 x i1> %1,
- i32 %2)
-
- ret <vscale x 2 x i32> %a
-}
-
-define <vscale x 4 x i32> @intrinsic_vmerge_vim_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 4 x i1> %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmerge_vim_nxv4i32_nxv4i32_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vmerge.vim v8, v8, 9, v0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i32> @llvm.riscv.vmerge.nxv4i32.i32(
- <vscale x 4 x i32> undef,
- <vscale x 4 x i32> %0,
- i32 9,
- <vscale x 4 x i1> %1,
- i32 %2)
-
- ret <vscale x 4 x i32> %a
-}
-
-define <vscale x 8 x i32> @intrinsic_vmerge_vim_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 8 x i1> %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmerge_vim_nxv8i32_nxv8i32_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
-; CHECK-NEXT: vmerge.vim v8, v8, 9, v0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i32> @llvm.riscv.vmerge.nxv8i32.i32(
- <vscale x 8 x i32> undef,
- <vscale x 8 x i32> %0,
- i32 9,
- <vscale x 8 x i1> %1,
- i32 %2)
-
- ret <vscale x 8 x i32> %a
-}
-
-define <vscale x 16 x i32> @intrinsic_vmerge_vim_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 16 x i1> %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmerge_vim_nxv16i32_nxv16i32_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu
-; CHECK-NEXT: vmerge.vim v8, v8, 9, v0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i32> @llvm.riscv.vmerge.nxv16i32.i32(
- <vscale x 16 x i32> undef,
- <vscale x 16 x i32> %0,
- i32 9,
- <vscale x 16 x i1> %1,
- i32 %2)
-
- ret <vscale x 16 x i32> %a
-}
-
-define <vscale x 1 x i64> @intrinsic_vmerge_vim_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i1> %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmerge_vim_nxv1i64_nxv1i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
-; CHECK-NEXT: vmerge.vim v8, v8, 9, v0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i64> @llvm.riscv.vmerge.nxv1i64.i64(
- <vscale x 1 x i64> undef,
- <vscale x 1 x i64> %0,
- i64 9,
- <vscale x 1 x i1> %1,
- i32 %2)
-
- ret <vscale x 1 x i64> %a
-}
-
-define <vscale x 2 x i64> @intrinsic_vmerge_vim_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, <vscale x 2 x i1> %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmerge_vim_nxv2i64_nxv2i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
-; CHECK-NEXT: vmerge.vim v8, v8, 9, v0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i64> @llvm.riscv.vmerge.nxv2i64.i64(
- <vscale x 2 x i64> undef,
- <vscale x 2 x i64> %0,
- i64 9,
- <vscale x 2 x i1> %1,
- i32 %2)
-
- ret <vscale x 2 x i64> %a
-}
-
-define <vscale x 4 x i64> @intrinsic_vmerge_vim_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, <vscale x 4 x i1> %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmerge_vim_nxv4i64_nxv4i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
-; CHECK-NEXT: vmerge.vim v8, v8, 9, v0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i64> @llvm.riscv.vmerge.nxv4i64.i64(
- <vscale x 4 x i64> undef,
- <vscale x 4 x i64> %0,
- i64 9,
- <vscale x 4 x i1> %1,
- i32 %2)
-
- ret <vscale x 4 x i64> %a
-}
-
-define <vscale x 8 x i64> @intrinsic_vmerge_vim_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, <vscale x 8 x i1> %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmerge_vim_nxv8i64_nxv8i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu
-; CHECK-NEXT: vmerge.vim v8, v8, 9, v0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i64> @llvm.riscv.vmerge.nxv8i64.i64(
- <vscale x 8 x i64> undef,
- <vscale x 8 x i64> %0,
- i64 9,
- <vscale x 8 x i1> %1,
- i32 %2)
-
- ret <vscale x 8 x i64> %a
-}
-
-declare <vscale x 1 x half> @llvm.riscv.vmerge.nxv1f16.nxv1f16(
- <vscale x 1 x half>,
- <vscale x 1 x half>,
- <vscale x 1 x half>,
- <vscale x 1 x i1>,
- i32);
-
-define <vscale x 1 x half> @intrinsic_vmerge_vvm_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
-; CHECK-LABEL: intrinsic_vmerge_vvm_nxv1f16_nxv1f16_nxv1f16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x half> @llvm.riscv.vmerge.nxv1f16.nxv1f16(
- <vscale x 1 x half> undef,
- <vscale x 1 x half> %0,
- <vscale x 1 x half> %1,
- <vscale x 1 x i1> %2,
- i32 %3)
-
- ret <vscale x 1 x half> %a
-}
-
-declare <vscale x 2 x half> @llvm.riscv.vmerge.nxv2f16.nxv2f16(
- <vscale x 2 x half>,
- <vscale x 2 x half>,
- <vscale x 2 x half>,
- <vscale x 2 x i1>,
- i32);
-
-define <vscale x 2 x half> @intrinsic_vmerge_vvm_nxv2f16_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
-; CHECK-LABEL: intrinsic_vmerge_vvm_nxv2f16_nxv2f16_nxv2f16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x half> @llvm.riscv.vmerge.nxv2f16.nxv2f16(
- <vscale x 2 x half> undef,
- <vscale x 2 x half> %0,
- <vscale x 2 x half> %1,
- <vscale x 2 x i1> %2,
- i32 %3)
-
- ret <vscale x 2 x half> %a
-}
-
-declare <vscale x 4 x half> @llvm.riscv.vmerge.nxv4f16.nxv4f16(
- <vscale x 4 x half>,
- <vscale x 4 x half>,
- <vscale x 4 x half>,
- <vscale x 4 x i1>,
- i32);
-
-define <vscale x 4 x half> @intrinsic_vmerge_vvm_nxv4f16_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
-; CHECK-LABEL: intrinsic_vmerge_vvm_nxv4f16_nxv4f16_nxv4f16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x half> @llvm.riscv.vmerge.nxv4f16.nxv4f16(
- <vscale x 4 x half> undef,
- <vscale x 4 x half> %0,
- <vscale x 4 x half> %1,
- <vscale x 4 x i1> %2,
- i32 %3)
-
- ret <vscale x 4 x half> %a
-}
-
-declare <vscale x 8 x half> @llvm.riscv.vmerge.nxv8f16.nxv8f16(
- <vscale x 8 x half>,
- <vscale x 8 x half>,
- <vscale x 8 x half>,
- <vscale x 8 x i1>,
- i32);
-
-define <vscale x 8 x half> @intrinsic_vmerge_vvm_nxv8f16_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
-; CHECK-LABEL: intrinsic_vmerge_vvm_nxv8f16_nxv8f16_nxv8f16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vmerge.vvm v8, v8, v10, v0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x half> @llvm.riscv.vmerge.nxv8f16.nxv8f16(
- <vscale x 8 x half> undef,
- <vscale x 8 x half> %0,
- <vscale x 8 x half> %1,
- <vscale x 8 x i1> %2,
- i32 %3)
-
- ret <vscale x 8 x half> %a
-}
-
-declare <vscale x 16 x half> @llvm.riscv.vmerge.nxv16f16.nxv16f16(
- <vscale x 16 x half>,
- <vscale x 16 x half>,
- <vscale x 16 x half>,
- <vscale x 16 x i1>,
- i32);
-
-define <vscale x 16 x half> @intrinsic_vmerge_vvm_nxv16f16_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x i1> %2, i32 %3) nounwind {
-; CHECK-LABEL: intrinsic_vmerge_vvm_nxv16f16_nxv16f16_nxv16f16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
-; CHECK-NEXT: vmerge.vvm v8, v8, v12, v0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x half> @llvm.riscv.vmerge.nxv16f16.nxv16f16(
- <vscale x 16 x half> undef,
- <vscale x 16 x half> %0,
- <vscale x 16 x half> %1,
- <vscale x 16 x i1> %2,
- i32 %3)
-
- ret <vscale x 16 x half> %a
-}
-
-declare <vscale x 32 x half> @llvm.riscv.vmerge.nxv32f16.nxv32f16(
- <vscale x 32 x half>,
- <vscale x 32 x half>,
- <vscale x 32 x half>,
- <vscale x 32 x i1>,
- i32);
-
-define <vscale x 32 x half> @intrinsic_vmerge_vvm_nxv32f16_nxv32f16_nxv32f16(<vscale x 32 x half> %0, <vscale x 32 x half> %1, <vscale x 32 x i1> %2, i32 %3) nounwind {
-; CHECK-LABEL: intrinsic_vmerge_vvm_nxv32f16_nxv32f16_nxv32f16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, mu
-; CHECK-NEXT: vmerge.vvm v8, v8, v16, v0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 32 x half> @llvm.riscv.vmerge.nxv32f16.nxv32f16(
- <vscale x 32 x half> undef,
- <vscale x 32 x half> %0,
- <vscale x 32 x half> %1,
- <vscale x 32 x i1> %2,
- i32 %3)
-
- ret <vscale x 32 x half> %a
-}
-
-declare <vscale x 1 x float> @llvm.riscv.vmerge.nxv1f32.nxv1f32(
- <vscale x 1 x float>,
- <vscale x 1 x float>,
- <vscale x 1 x float>,
- <vscale x 1 x i1>,
- i32);
-
-define <vscale x 1 x float> @intrinsic_vmerge_vvm_nxv1f32_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
-; CHECK-LABEL: intrinsic_vmerge_vvm_nxv1f32_nxv1f32_nxv1f32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x float> @llvm.riscv.vmerge.nxv1f32.nxv1f32(
- <vscale x 1 x float> undef,
- <vscale x 1 x float> %0,
- <vscale x 1 x float> %1,
- <vscale x 1 x i1> %2,
- i32 %3)
-
- ret <vscale x 1 x float> %a
-}
-
-declare <vscale x 2 x float> @llvm.riscv.vmerge.nxv2f32.nxv2f32(
- <vscale x 2 x float>,
- <vscale x 2 x float>,
- <vscale x 2 x float>,
- <vscale x 2 x i1>,
- i32);
-
-define <vscale x 2 x float> @intrinsic_vmerge_vvm_nxv2f32_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
-; CHECK-LABEL: intrinsic_vmerge_vvm_nxv2f32_nxv2f32_nxv2f32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x float> @llvm.riscv.vmerge.nxv2f32.nxv2f32(
- <vscale x 2 x float> undef,
- <vscale x 2 x float> %0,
- <vscale x 2 x float> %1,
- <vscale x 2 x i1> %2,
- i32 %3)
-
- ret <vscale x 2 x float> %a
-}
-
-declare <vscale x 4 x float> @llvm.riscv.vmerge.nxv4f32.nxv4f32(
- <vscale x 4 x float>,
- <vscale x 4 x float>,
- <vscale x 4 x float>,
- <vscale x 4 x i1>,
- i32);
-
-define <vscale x 4 x float> @intrinsic_vmerge_vvm_nxv4f32_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
-; CHECK-LABEL: intrinsic_vmerge_vvm_nxv4f32_nxv4f32_nxv4f32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vmerge.vvm v8, v8, v10, v0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x float> @llvm.riscv.vmerge.nxv4f32.nxv4f32(
- <vscale x 4 x float> undef,
- <vscale x 4 x float> %0,
- <vscale x 4 x float> %1,
- <vscale x 4 x i1> %2,
- i32 %3)
-
- ret <vscale x 4 x float> %a
-}
-
-declare <vscale x 8 x float> @llvm.riscv.vmerge.nxv8f32.nxv8f32(
- <vscale x 8 x float>,
- <vscale x 8 x float>,
- <vscale x 8 x float>,
- <vscale x 8 x i1>,
- i32);
-
-define <vscale x 8 x float> @intrinsic_vmerge_vvm_nxv8f32_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
-; CHECK-LABEL: intrinsic_vmerge_vvm_nxv8f32_nxv8f32_nxv8f32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
-; CHECK-NEXT: vmerge.vvm v8, v8, v12, v0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x float> @llvm.riscv.vmerge.nxv8f32.nxv8f32(
- <vscale x 8 x float> undef,
- <vscale x 8 x float> %0,
- <vscale x 8 x float> %1,
- <vscale x 8 x i1> %2,
- i32 %3)
-
- ret <vscale x 8 x float> %a
-}
-
-declare <vscale x 16 x float> @llvm.riscv.vmerge.nxv16f32.nxv16f32(
- <vscale x 16 x float>,
- <vscale x 16 x float>,
- <vscale x 16 x float>,
- <vscale x 16 x i1>,
- i32);
-
-define <vscale x 16 x float> @intrinsic_vmerge_vvm_nxv16f32_nxv16f32_nxv16f32(<vscale x 16 x float> %0, <vscale x 16 x float> %1, <vscale x 16 x i1> %2, i32 %3) nounwind {
-; CHECK-LABEL: intrinsic_vmerge_vvm_nxv16f32_nxv16f32_nxv16f32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu
-; CHECK-NEXT: vmerge.vvm v8, v8, v16, v0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x float> @llvm.riscv.vmerge.nxv16f32.nxv16f32(
- <vscale x 16 x float> undef,
- <vscale x 16 x float> %0,
- <vscale x 16 x float> %1,
- <vscale x 16 x i1> %2,
- i32 %3)
-
- ret <vscale x 16 x float> %a
-}
-
-declare <vscale x 1 x double> @llvm.riscv.vmerge.nxv1f64.nxv1f64(
- <vscale x 1 x double>,
- <vscale x 1 x double>,
- <vscale x 1 x double>,
- <vscale x 1 x i1>,
- i32);
-
-define <vscale x 1 x double> @intrinsic_vmerge_vvm_nxv1f64_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
-; CHECK-LABEL: intrinsic_vmerge_vvm_nxv1f64_nxv1f64_nxv1f64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
-; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x double> @llvm.riscv.vmerge.nxv1f64.nxv1f64(
- <vscale x 1 x double> undef,
- <vscale x 1 x double> %0,
- <vscale x 1 x double> %1,
- <vscale x 1 x i1> %2,
- i32 %3)
-
- ret <vscale x 1 x double> %a
-}
-
-declare <vscale x 2 x double> @llvm.riscv.vmerge.nxv2f64.nxv2f64(
- <vscale x 2 x double>,
- <vscale x 2 x double>,
- <vscale x 2 x double>,
- <vscale x 2 x i1>,
- i32);
-
-define <vscale x 2 x double> @intrinsic_vmerge_vvm_nxv2f64_nxv2f64_nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
-; CHECK-LABEL: intrinsic_vmerge_vvm_nxv2f64_nxv2f64_nxv2f64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
-; CHECK-NEXT: vmerge.vvm v8, v8, v10, v0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x double> @llvm.riscv.vmerge.nxv2f64.nxv2f64(
- <vscale x 2 x double> undef,
- <vscale x 2 x double> %0,
- <vscale x 2 x double> %1,
- <vscale x 2 x i1> %2,
- i32 %3)
-
- ret <vscale x 2 x double> %a
-}
-
-declare <vscale x 4 x double> @llvm.riscv.vmerge.nxv4f64.nxv4f64(
- <vscale x 4 x double>,
- <vscale x 4 x double>,
- <vscale x 4 x double>,
- <vscale x 4 x i1>,
- i32);
-
-define <vscale x 4 x double> @intrinsic_vmerge_vvm_nxv4f64_nxv4f64_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
-; CHECK-LABEL: intrinsic_vmerge_vvm_nxv4f64_nxv4f64_nxv4f64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
-; CHECK-NEXT: vmerge.vvm v8, v8, v12, v0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x double> @llvm.riscv.vmerge.nxv4f64.nxv4f64(
- <vscale x 4 x double> undef,
- <vscale x 4 x double> %0,
- <vscale x 4 x double> %1,
- <vscale x 4 x i1> %2,
- i32 %3)
-
- ret <vscale x 4 x double> %a
-}
-
-declare <vscale x 8 x double> @llvm.riscv.vmerge.nxv8f64.nxv8f64(
- <vscale x 8 x double>,
- <vscale x 8 x double>,
- <vscale x 8 x double>,
- <vscale x 8 x i1>,
- i32);
-
-define <vscale x 8 x double> @intrinsic_vmerge_vvm_nxv8f64_nxv8f64_nxv8f64(<vscale x 8 x double> %0, <vscale x 8 x double> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
-; CHECK-LABEL: intrinsic_vmerge_vvm_nxv8f64_nxv8f64_nxv8f64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu
-; CHECK-NEXT: vmerge.vvm v8, v8, v16, v0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x double> @llvm.riscv.vmerge.nxv8f64.nxv8f64(
- <vscale x 8 x double> undef,
- <vscale x 8 x double> %0,
- <vscale x 8 x double> %1,
- <vscale x 8 x i1> %2,
- i32 %3)
-
- ret <vscale x 8 x double> %a
-}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmerge-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vmerge.ll
similarity index 87%
rename from llvm/test/CodeGen/RISCV/rvv/vmerge-rv64.ll
rename to llvm/test/CodeGen/RISCV/rvv/vmerge.ll
index 60c56b6f0ef82..004ced71558b3 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vmerge-rv64.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vmerge.ll
@@ -1,14 +1,16 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv64 -mattr=+v,+d,+zfh -verify-machineinstrs \
-; RUN: < %s | FileCheck %s
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh \
+; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh \
+; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s
declare <vscale x 1 x i8> @llvm.riscv.vmerge.nxv1i8.nxv1i8(
<vscale x 1 x i8>,
<vscale x 1 x i8>,
<vscale x 1 x i8>,
<vscale x 1 x i1>,
- i64);
+ iXLen);
-define <vscale x 1 x i8> @intrinsic_vmerge_vvm_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
+define <vscale x 1 x i8> @intrinsic_vmerge_vvm_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vmerge_vvm_nxv1i8_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
@@ -20,7 +22,7 @@ entry:
<vscale x 1 x i8> %0,
<vscale x 1 x i8> %1,
<vscale x 1 x i1> %2,
- i64 %3)
+ iXLen %3)
ret <vscale x 1 x i8> %a
}
@@ -30,9 +32,9 @@ declare <vscale x 2 x i8> @llvm.riscv.vmerge.nxv2i8.nxv2i8(
<vscale x 2 x i8>,
<vscale x 2 x i8>,
<vscale x 2 x i1>,
- i64);
+ iXLen);
-define <vscale x 2 x i8> @intrinsic_vmerge_vvm_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
+define <vscale x 2 x i8> @intrinsic_vmerge_vvm_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vmerge_vvm_nxv2i8_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
@@ -44,7 +46,7 @@ entry:
<vscale x 2 x i8> %0,
<vscale x 2 x i8> %1,
<vscale x 2 x i1> %2,
- i64 %3)
+ iXLen %3)
ret <vscale x 2 x i8> %a
}
@@ -54,9 +56,9 @@ declare <vscale x 4 x i8> @llvm.riscv.vmerge.nxv4i8.nxv4i8(
<vscale x 4 x i8>,
<vscale x 4 x i8>,
<vscale x 4 x i1>,
- i64);
+ iXLen);
-define <vscale x 4 x i8> @intrinsic_vmerge_vvm_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
+define <vscale x 4 x i8> @intrinsic_vmerge_vvm_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vmerge_vvm_nxv4i8_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
@@ -68,7 +70,7 @@ entry:
<vscale x 4 x i8> %0,
<vscale x 4 x i8> %1,
<vscale x 4 x i1> %2,
- i64 %3)
+ iXLen %3)
ret <vscale x 4 x i8> %a
}
@@ -78,9 +80,9 @@ declare <vscale x 8 x i8> @llvm.riscv.vmerge.nxv8i8.nxv8i8(
<vscale x 8 x i8>,
<vscale x 8 x i8>,
<vscale x 8 x i1>,
- i64);
+ iXLen);
-define <vscale x 8 x i8> @intrinsic_vmerge_vvm_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
+define <vscale x 8 x i8> @intrinsic_vmerge_vvm_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vmerge_vvm_nxv8i8_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
@@ -92,7 +94,7 @@ entry:
<vscale x 8 x i8> %0,
<vscale x 8 x i8> %1,
<vscale x 8 x i1> %2,
- i64 %3)
+ iXLen %3)
ret <vscale x 8 x i8> %a
}
@@ -102,9 +104,9 @@ declare <vscale x 16 x i8> @llvm.riscv.vmerge.nxv16i8.nxv16i8(
<vscale x 16 x i8>,
<vscale x 16 x i8>,
<vscale x 16 x i1>,
- i64);
+ iXLen);
-define <vscale x 16 x i8> @intrinsic_vmerge_vvm_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i1> %2, i64 %3) nounwind {
+define <vscale x 16 x i8> @intrinsic_vmerge_vvm_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vmerge_vvm_nxv16i8_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
@@ -116,7 +118,7 @@ entry:
<vscale x 16 x i8> %0,
<vscale x 16 x i8> %1,
<vscale x 16 x i1> %2,
- i64 %3)
+ iXLen %3)
ret <vscale x 16 x i8> %a
}
@@ -126,9 +128,9 @@ declare <vscale x 32 x i8> @llvm.riscv.vmerge.nxv32i8.nxv32i8(
<vscale x 32 x i8>,
<vscale x 32 x i8>,
<vscale x 32 x i1>,
- i64);
+ iXLen);
-define <vscale x 32 x i8> @intrinsic_vmerge_vvm_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i1> %2, i64 %3) nounwind {
+define <vscale x 32 x i8> @intrinsic_vmerge_vvm_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vmerge_vvm_nxv32i8_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
@@ -140,7 +142,7 @@ entry:
<vscale x 32 x i8> %0,
<vscale x 32 x i8> %1,
<vscale x 32 x i1> %2,
- i64 %3)
+ iXLen %3)
ret <vscale x 32 x i8> %a
}
@@ -150,9 +152,9 @@ declare <vscale x 64 x i8> @llvm.riscv.vmerge.nxv64i8.nxv64i8(
<vscale x 64 x i8>,
<vscale x 64 x i8>,
<vscale x 64 x i1>,
- i64);
+ iXLen);
-define <vscale x 64 x i8> @intrinsic_vmerge_vvm_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i1> %2, i64 %3) nounwind {
+define <vscale x 64 x i8> @intrinsic_vmerge_vvm_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vmerge_vvm_nxv64i8_nxv64i8_nxv64i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, mu
@@ -164,7 +166,7 @@ entry:
<vscale x 64 x i8> %0,
<vscale x 64 x i8> %1,
<vscale x 64 x i1> %2,
- i64 %3)
+ iXLen %3)
ret <vscale x 64 x i8> %a
}
@@ -174,9 +176,9 @@ declare <vscale x 1 x i16> @llvm.riscv.vmerge.nxv1i16.nxv1i16(
<vscale x 1 x i16>,
<vscale x 1 x i16>,
<vscale x 1 x i1>,
- i64);
+ iXLen);
-define <vscale x 1 x i16> @intrinsic_vmerge_vvm_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
+define <vscale x 1 x i16> @intrinsic_vmerge_vvm_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vmerge_vvm_nxv1i16_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
@@ -188,7 +190,7 @@ entry:
<vscale x 1 x i16> %0,
<vscale x 1 x i16> %1,
<vscale x 1 x i1> %2,
- i64 %3)
+ iXLen %3)
ret <vscale x 1 x i16> %a
}
@@ -198,9 +200,9 @@ declare <vscale x 2 x i16> @llvm.riscv.vmerge.nxv2i16.nxv2i16(
<vscale x 2 x i16>,
<vscale x 2 x i16>,
<vscale x 2 x i1>,
- i64);
+ iXLen);
-define <vscale x 2 x i16> @intrinsic_vmerge_vvm_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
+define <vscale x 2 x i16> @intrinsic_vmerge_vvm_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vmerge_vvm_nxv2i16_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
@@ -212,7 +214,7 @@ entry:
<vscale x 2 x i16> %0,
<vscale x 2 x i16> %1,
<vscale x 2 x i1> %2,
- i64 %3)
+ iXLen %3)
ret <vscale x 2 x i16> %a
}
@@ -222,9 +224,9 @@ declare <vscale x 4 x i16> @llvm.riscv.vmerge.nxv4i16.nxv4i16(
<vscale x 4 x i16>,
<vscale x 4 x i16>,
<vscale x 4 x i1>,
- i64);
+ iXLen);
-define <vscale x 4 x i16> @intrinsic_vmerge_vvm_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
+define <vscale x 4 x i16> @intrinsic_vmerge_vvm_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vmerge_vvm_nxv4i16_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
@@ -236,7 +238,7 @@ entry:
<vscale x 4 x i16> %0,
<vscale x 4 x i16> %1,
<vscale x 4 x i1> %2,
- i64 %3)
+ iXLen %3)
ret <vscale x 4 x i16> %a
}
@@ -246,9 +248,9 @@ declare <vscale x 8 x i16> @llvm.riscv.vmerge.nxv8i16.nxv8i16(
<vscale x 8 x i16>,
<vscale x 8 x i16>,
<vscale x 8 x i1>,
- i64);
+ iXLen);
-define <vscale x 8 x i16> @intrinsic_vmerge_vvm_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
+define <vscale x 8 x i16> @intrinsic_vmerge_vvm_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vmerge_vvm_nxv8i16_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
@@ -260,7 +262,7 @@ entry:
<vscale x 8 x i16> %0,
<vscale x 8 x i16> %1,
<vscale x 8 x i1> %2,
- i64 %3)
+ iXLen %3)
ret <vscale x 8 x i16> %a
}
@@ -270,9 +272,9 @@ declare <vscale x 16 x i16> @llvm.riscv.vmerge.nxv16i16.nxv16i16(
<vscale x 16 x i16>,
<vscale x 16 x i16>,
<vscale x 16 x i1>,
- i64);
+ iXLen);
-define <vscale x 16 x i16> @intrinsic_vmerge_vvm_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i1> %2, i64 %3) nounwind {
+define <vscale x 16 x i16> @intrinsic_vmerge_vvm_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vmerge_vvm_nxv16i16_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
@@ -284,7 +286,7 @@ entry:
<vscale x 16 x i16> %0,
<vscale x 16 x i16> %1,
<vscale x 16 x i1> %2,
- i64 %3)
+ iXLen %3)
ret <vscale x 16 x i16> %a
}
@@ -294,9 +296,9 @@ declare <vscale x 32 x i16> @llvm.riscv.vmerge.nxv32i16.nxv32i16(
<vscale x 32 x i16>,
<vscale x 32 x i16>,
<vscale x 32 x i1>,
- i64);
+ iXLen);
-define <vscale x 32 x i16> @intrinsic_vmerge_vvm_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i1> %2, i64 %3) nounwind {
+define <vscale x 32 x i16> @intrinsic_vmerge_vvm_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vmerge_vvm_nxv32i16_nxv32i16_nxv32i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, mu
@@ -308,7 +310,7 @@ entry:
<vscale x 32 x i16> %0,
<vscale x 32 x i16> %1,
<vscale x 32 x i1> %2,
- i64 %3)
+ iXLen %3)
ret <vscale x 32 x i16> %a
}
@@ -318,9 +320,9 @@ declare <vscale x 1 x i32> @llvm.riscv.vmerge.nxv1i32.nxv1i32(
<vscale x 1 x i32>,
<vscale x 1 x i32>,
<vscale x 1 x i1>,
- i64);
+ iXLen);
-define <vscale x 1 x i32> @intrinsic_vmerge_vvm_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
+define <vscale x 1 x i32> @intrinsic_vmerge_vvm_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vmerge_vvm_nxv1i32_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
@@ -332,7 +334,7 @@ entry:
<vscale x 1 x i32> %0,
<vscale x 1 x i32> %1,
<vscale x 1 x i1> %2,
- i64 %3)
+ iXLen %3)
ret <vscale x 1 x i32> %a
}
@@ -342,9 +344,9 @@ declare <vscale x 2 x i32> @llvm.riscv.vmerge.nxv2i32.nxv2i32(
<vscale x 2 x i32>,
<vscale x 2 x i32>,
<vscale x 2 x i1>,
- i64);
+ iXLen);
-define <vscale x 2 x i32> @intrinsic_vmerge_vvm_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
+define <vscale x 2 x i32> @intrinsic_vmerge_vvm_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vmerge_vvm_nxv2i32_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
@@ -356,7 +358,7 @@ entry:
<vscale x 2 x i32> %0,
<vscale x 2 x i32> %1,
<vscale x 2 x i1> %2,
- i64 %3)
+ iXLen %3)
ret <vscale x 2 x i32> %a
}
@@ -366,9 +368,9 @@ declare <vscale x 4 x i32> @llvm.riscv.vmerge.nxv4i32.nxv4i32(
<vscale x 4 x i32>,
<vscale x 4 x i32>,
<vscale x 4 x i1>,
- i64);
+ iXLen);
-define <vscale x 4 x i32> @intrinsic_vmerge_vvm_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
+define <vscale x 4 x i32> @intrinsic_vmerge_vvm_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vmerge_vvm_nxv4i32_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
@@ -380,7 +382,7 @@ entry:
<vscale x 4 x i32> %0,
<vscale x 4 x i32> %1,
<vscale x 4 x i1> %2,
- i64 %3)
+ iXLen %3)
ret <vscale x 4 x i32> %a
}
@@ -390,9 +392,9 @@ declare <vscale x 8 x i32> @llvm.riscv.vmerge.nxv8i32.nxv8i32(
<vscale x 8 x i32>,
<vscale x 8 x i32>,
<vscale x 8 x i1>,
- i64);
+ iXLen);
-define <vscale x 8 x i32> @intrinsic_vmerge_vvm_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
+define <vscale x 8 x i32> @intrinsic_vmerge_vvm_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vmerge_vvm_nxv8i32_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
@@ -404,7 +406,7 @@ entry:
<vscale x 8 x i32> %0,
<vscale x 8 x i32> %1,
<vscale x 8 x i1> %2,
- i64 %3)
+ iXLen %3)
ret <vscale x 8 x i32> %a
}
@@ -414,9 +416,9 @@ declare <vscale x 16 x i32> @llvm.riscv.vmerge.nxv16i32.nxv16i32(
<vscale x 16 x i32>,
<vscale x 16 x i32>,
<vscale x 16 x i1>,
- i64);
+ iXLen);
-define <vscale x 16 x i32> @intrinsic_vmerge_vvm_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i1> %2, i64 %3) nounwind {
+define <vscale x 16 x i32> @intrinsic_vmerge_vvm_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vmerge_vvm_nxv16i32_nxv16i32_nxv16i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu
@@ -428,7 +430,7 @@ entry:
<vscale x 16 x i32> %0,
<vscale x 16 x i32> %1,
<vscale x 16 x i1> %2,
- i64 %3)
+ iXLen %3)
ret <vscale x 16 x i32> %a
}
@@ -438,9 +440,9 @@ declare <vscale x 1 x i64> @llvm.riscv.vmerge.nxv1i64.nxv1i64(
<vscale x 1 x i64>,
<vscale x 1 x i64>,
<vscale x 1 x i1>,
- i64);
+ iXLen);
-define <vscale x 1 x i64> @intrinsic_vmerge_vvm_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
+define <vscale x 1 x i64> @intrinsic_vmerge_vvm_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vmerge_vvm_nxv1i64_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
@@ -452,7 +454,7 @@ entry:
<vscale x 1 x i64> %0,
<vscale x 1 x i64> %1,
<vscale x 1 x i1> %2,
- i64 %3)
+ iXLen %3)
ret <vscale x 1 x i64> %a
}
@@ -462,9 +464,9 @@ declare <vscale x 2 x i64> @llvm.riscv.vmerge.nxv2i64.nxv2i64(
<vscale x 2 x i64>,
<vscale x 2 x i64>,
<vscale x 2 x i1>,
- i64);
+ iXLen);
-define <vscale x 2 x i64> @intrinsic_vmerge_vvm_nxv2i64_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
+define <vscale x 2 x i64> @intrinsic_vmerge_vvm_nxv2i64_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vmerge_vvm_nxv2i64_nxv2i64_nxv2i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
@@ -476,7 +478,7 @@ entry:
<vscale x 2 x i64> %0,
<vscale x 2 x i64> %1,
<vscale x 2 x i1> %2,
- i64 %3)
+ iXLen %3)
ret <vscale x 2 x i64> %a
}
@@ -486,9 +488,9 @@ declare <vscale x 4 x i64> @llvm.riscv.vmerge.nxv4i64.nxv4i64(
<vscale x 4 x i64>,
<vscale x 4 x i64>,
<vscale x 4 x i1>,
- i64);
+ iXLen);
-define <vscale x 4 x i64> @intrinsic_vmerge_vvm_nxv4i64_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
+define <vscale x 4 x i64> @intrinsic_vmerge_vvm_nxv4i64_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vmerge_vvm_nxv4i64_nxv4i64_nxv4i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
@@ -500,7 +502,7 @@ entry:
<vscale x 4 x i64> %0,
<vscale x 4 x i64> %1,
<vscale x 4 x i1> %2,
- i64 %3)
+ iXLen %3)
ret <vscale x 4 x i64> %a
}
@@ -510,9 +512,9 @@ declare <vscale x 8 x i64> @llvm.riscv.vmerge.nxv8i64.nxv8i64(
<vscale x 8 x i64>,
<vscale x 8 x i64>,
<vscale x 8 x i1>,
- i64);
+ iXLen);
-define <vscale x 8 x i64> @intrinsic_vmerge_vvm_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
+define <vscale x 8 x i64> @intrinsic_vmerge_vvm_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vmerge_vvm_nxv8i64_nxv8i64_nxv8i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu
@@ -524,7 +526,7 @@ entry:
<vscale x 8 x i64> %0,
<vscale x 8 x i64> %1,
<vscale x 8 x i1> %2,
- i64 %3)
+ iXLen %3)
ret <vscale x 8 x i64> %a
}
@@ -534,9 +536,9 @@ declare <vscale x 1 x i8> @llvm.riscv.vmerge.nxv1i8.i8(
<vscale x 1 x i8>,
i8,
<vscale x 1 x i1>,
- i64);
+ iXLen);
-define <vscale x 1 x i8> @intrinsic_vmerge_vxm_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
+define <vscale x 1 x i8> @intrinsic_vmerge_vxm_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vmerge_vxm_nxv1i8_nxv1i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
@@ -548,7 +550,7 @@ entry:
<vscale x 1 x i8> %0,
i8 %1,
<vscale x 1 x i1> %2,
- i64 %3)
+ iXLen %3)
ret <vscale x 1 x i8> %a
}
@@ -558,9 +560,9 @@ declare <vscale x 2 x i8> @llvm.riscv.vmerge.nxv2i8.i8(
<vscale x 2 x i8>,
i8,
<vscale x 2 x i1>,
- i64);
+ iXLen);
-define <vscale x 2 x i8> @intrinsic_vmerge_vxm_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, i8 %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
+define <vscale x 2 x i8> @intrinsic_vmerge_vxm_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, i8 %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vmerge_vxm_nxv2i8_nxv2i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
@@ -572,7 +574,7 @@ entry:
<vscale x 2 x i8> %0,
i8 %1,
<vscale x 2 x i1> %2,
- i64 %3)
+ iXLen %3)
ret <vscale x 2 x i8> %a
}
@@ -582,9 +584,9 @@ declare <vscale x 4 x i8> @llvm.riscv.vmerge.nxv4i8.i8(
<vscale x 4 x i8>,
i8,
<vscale x 4 x i1>,
- i64);
+ iXLen);
-define <vscale x 4 x i8> @intrinsic_vmerge_vxm_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, i8 %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
+define <vscale x 4 x i8> @intrinsic_vmerge_vxm_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, i8 %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vmerge_vxm_nxv4i8_nxv4i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
@@ -596,7 +598,7 @@ entry:
<vscale x 4 x i8> %0,
i8 %1,
<vscale x 4 x i1> %2,
- i64 %3)
+ iXLen %3)
ret <vscale x 4 x i8> %a
}
@@ -606,9 +608,9 @@ declare <vscale x 8 x i8> @llvm.riscv.vmerge.nxv8i8.i8(
<vscale x 8 x i8>,
i8,
<vscale x 8 x i1>,
- i64);
+ iXLen);
-define <vscale x 8 x i8> @intrinsic_vmerge_vxm_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, i8 %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
+define <vscale x 8 x i8> @intrinsic_vmerge_vxm_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, i8 %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vmerge_vxm_nxv8i8_nxv8i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
@@ -620,7 +622,7 @@ entry:
<vscale x 8 x i8> %0,
i8 %1,
<vscale x 8 x i1> %2,
- i64 %3)
+ iXLen %3)
ret <vscale x 8 x i8> %a
}
@@ -630,9 +632,9 @@ declare <vscale x 16 x i8> @llvm.riscv.vmerge.nxv16i8.i8(
<vscale x 16 x i8>,
i8,
<vscale x 16 x i1>,
- i64);
+ iXLen);
-define <vscale x 16 x i8> @intrinsic_vmerge_vxm_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, i8 %1, <vscale x 16 x i1> %2, i64 %3) nounwind {
+define <vscale x 16 x i8> @intrinsic_vmerge_vxm_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, i8 %1, <vscale x 16 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vmerge_vxm_nxv16i8_nxv16i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
@@ -644,7 +646,7 @@ entry:
<vscale x 16 x i8> %0,
i8 %1,
<vscale x 16 x i1> %2,
- i64 %3)
+ iXLen %3)
ret <vscale x 16 x i8> %a
}
@@ -654,9 +656,9 @@ declare <vscale x 32 x i8> @llvm.riscv.vmerge.nxv32i8.i8(
<vscale x 32 x i8>,
i8,
<vscale x 32 x i1>,
- i64);
+ iXLen);
-define <vscale x 32 x i8> @intrinsic_vmerge_vxm_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, i8 %1, <vscale x 32 x i1> %2, i64 %3) nounwind {
+define <vscale x 32 x i8> @intrinsic_vmerge_vxm_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, i8 %1, <vscale x 32 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vmerge_vxm_nxv32i8_nxv32i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
@@ -668,7 +670,7 @@ entry:
<vscale x 32 x i8> %0,
i8 %1,
<vscale x 32 x i1> %2,
- i64 %3)
+ iXLen %3)
ret <vscale x 32 x i8> %a
}
@@ -678,9 +680,9 @@ declare <vscale x 64 x i8> @llvm.riscv.vmerge.nxv64i8.i8(
<vscale x 64 x i8>,
i8,
<vscale x 64 x i1>,
- i64);
+ iXLen);
-define <vscale x 64 x i8> @intrinsic_vmerge_vxm_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, i8 %1, <vscale x 64 x i1> %2, i64 %3) nounwind {
+define <vscale x 64 x i8> @intrinsic_vmerge_vxm_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, i8 %1, <vscale x 64 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vmerge_vxm_nxv64i8_nxv64i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu
@@ -692,7 +694,7 @@ entry:
<vscale x 64 x i8> %0,
i8 %1,
<vscale x 64 x i1> %2,
- i64 %3)
+ iXLen %3)
ret <vscale x 64 x i8> %a
}
@@ -702,9 +704,9 @@ declare <vscale x 1 x i16> @llvm.riscv.vmerge.nxv1i16.i16(
<vscale x 1 x i16>,
i16,
<vscale x 1 x i1>,
- i64);
+ iXLen);
-define <vscale x 1 x i16> @intrinsic_vmerge_vxm_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, i16 %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
+define <vscale x 1 x i16> @intrinsic_vmerge_vxm_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, i16 %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vmerge_vxm_nxv1i16_nxv1i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
@@ -716,7 +718,7 @@ entry:
<vscale x 1 x i16> %0,
i16 %1,
<vscale x 1 x i1> %2,
- i64 %3)
+ iXLen %3)
ret <vscale x 1 x i16> %a
}
@@ -726,9 +728,9 @@ declare <vscale x 2 x i16> @llvm.riscv.vmerge.nxv2i16.i16(
<vscale x 2 x i16>,
i16,
<vscale x 2 x i1>,
- i64);
+ iXLen);
-define <vscale x 2 x i16> @intrinsic_vmerge_vxm_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, i16 %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
+define <vscale x 2 x i16> @intrinsic_vmerge_vxm_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, i16 %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vmerge_vxm_nxv2i16_nxv2i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
@@ -740,7 +742,7 @@ entry:
<vscale x 2 x i16> %0,
i16 %1,
<vscale x 2 x i1> %2,
- i64 %3)
+ iXLen %3)
ret <vscale x 2 x i16> %a
}
@@ -750,9 +752,9 @@ declare <vscale x 4 x i16> @llvm.riscv.vmerge.nxv4i16.i16(
<vscale x 4 x i16>,
i16,
<vscale x 4 x i1>,
- i64);
+ iXLen);
-define <vscale x 4 x i16> @intrinsic_vmerge_vxm_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, i16 %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
+define <vscale x 4 x i16> @intrinsic_vmerge_vxm_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, i16 %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vmerge_vxm_nxv4i16_nxv4i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
@@ -764,7 +766,7 @@ entry:
<vscale x 4 x i16> %0,
i16 %1,
<vscale x 4 x i1> %2,
- i64 %3)
+ iXLen %3)
ret <vscale x 4 x i16> %a
}
@@ -774,9 +776,9 @@ declare <vscale x 8 x i16> @llvm.riscv.vmerge.nxv8i16.i16(
<vscale x 8 x i16>,
i16,
<vscale x 8 x i1>,
- i64);
+ iXLen);
-define <vscale x 8 x i16> @intrinsic_vmerge_vxm_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, i16 %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
+define <vscale x 8 x i16> @intrinsic_vmerge_vxm_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, i16 %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vmerge_vxm_nxv8i16_nxv8i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
@@ -788,7 +790,7 @@ entry:
<vscale x 8 x i16> %0,
i16 %1,
<vscale x 8 x i1> %2,
- i64 %3)
+ iXLen %3)
ret <vscale x 8 x i16> %a
}
@@ -798,9 +800,9 @@ declare <vscale x 16 x i16> @llvm.riscv.vmerge.nxv16i16.i16(
<vscale x 16 x i16>,
i16,
<vscale x 16 x i1>,
- i64);
+ iXLen);
-define <vscale x 16 x i16> @intrinsic_vmerge_vxm_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, i16 %1, <vscale x 16 x i1> %2, i64 %3) nounwind {
+define <vscale x 16 x i16> @intrinsic_vmerge_vxm_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, i16 %1, <vscale x 16 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vmerge_vxm_nxv16i16_nxv16i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
@@ -812,7 +814,7 @@ entry:
<vscale x 16 x i16> %0,
i16 %1,
<vscale x 16 x i1> %2,
- i64 %3)
+ iXLen %3)
ret <vscale x 16 x i16> %a
}
@@ -822,9 +824,9 @@ declare <vscale x 32 x i16> @llvm.riscv.vmerge.nxv32i16.i16(
<vscale x 32 x i16>,
i16,
<vscale x 32 x i1>,
- i64);
+ iXLen);
-define <vscale x 32 x i16> @intrinsic_vmerge_vxm_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, i16 %1, <vscale x 32 x i1> %2, i64 %3) nounwind {
+define <vscale x 32 x i16> @intrinsic_vmerge_vxm_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, i16 %1, <vscale x 32 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vmerge_vxm_nxv32i16_nxv32i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu
@@ -836,7 +838,7 @@ entry:
<vscale x 32 x i16> %0,
i16 %1,
<vscale x 32 x i1> %2,
- i64 %3)
+ iXLen %3)
ret <vscale x 32 x i16> %a
}
@@ -846,9 +848,9 @@ declare <vscale x 1 x i32> @llvm.riscv.vmerge.nxv1i32.i32(
<vscale x 1 x i32>,
i32,
<vscale x 1 x i1>,
- i64);
+ iXLen);
-define <vscale x 1 x i32> @intrinsic_vmerge_vxm_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, i32 %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
+define <vscale x 1 x i32> @intrinsic_vmerge_vxm_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, i32 %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vmerge_vxm_nxv1i32_nxv1i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
@@ -860,7 +862,7 @@ entry:
<vscale x 1 x i32> %0,
i32 %1,
<vscale x 1 x i1> %2,
- i64 %3)
+ iXLen %3)
ret <vscale x 1 x i32> %a
}
@@ -870,9 +872,9 @@ declare <vscale x 2 x i32> @llvm.riscv.vmerge.nxv2i32.i32(
<vscale x 2 x i32>,
i32,
<vscale x 2 x i1>,
- i64);
+ iXLen);
-define <vscale x 2 x i32> @intrinsic_vmerge_vxm_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, i32 %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
+define <vscale x 2 x i32> @intrinsic_vmerge_vxm_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, i32 %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vmerge_vxm_nxv2i32_nxv2i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
@@ -884,7 +886,7 @@ entry:
<vscale x 2 x i32> %0,
i32 %1,
<vscale x 2 x i1> %2,
- i64 %3)
+ iXLen %3)
ret <vscale x 2 x i32> %a
}
@@ -894,9 +896,9 @@ declare <vscale x 4 x i32> @llvm.riscv.vmerge.nxv4i32.i32(
<vscale x 4 x i32>,
i32,
<vscale x 4 x i1>,
- i64);
+ iXLen);
-define <vscale x 4 x i32> @intrinsic_vmerge_vxm_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, i32 %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
+define <vscale x 4 x i32> @intrinsic_vmerge_vxm_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, i32 %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vmerge_vxm_nxv4i32_nxv4i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
@@ -908,7 +910,7 @@ entry:
<vscale x 4 x i32> %0,
i32 %1,
<vscale x 4 x i1> %2,
- i64 %3)
+ iXLen %3)
ret <vscale x 4 x i32> %a
}
@@ -918,9 +920,9 @@ declare <vscale x 8 x i32> @llvm.riscv.vmerge.nxv8i32.i32(
<vscale x 8 x i32>,
i32,
<vscale x 8 x i1>,
- i64);
+ iXLen);
-define <vscale x 8 x i32> @intrinsic_vmerge_vxm_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, i32 %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
+define <vscale x 8 x i32> @intrinsic_vmerge_vxm_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, i32 %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vmerge_vxm_nxv8i32_nxv8i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
@@ -932,7 +934,7 @@ entry:
<vscale x 8 x i32> %0,
i32 %1,
<vscale x 8 x i1> %2,
- i64 %3)
+ iXLen %3)
ret <vscale x 8 x i32> %a
}
@@ -942,9 +944,9 @@ declare <vscale x 16 x i32> @llvm.riscv.vmerge.nxv16i32.i32(
<vscale x 16 x i32>,
i32,
<vscale x 16 x i1>,
- i64);
+ iXLen);
-define <vscale x 16 x i32> @intrinsic_vmerge_vxm_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, i32 %1, <vscale x 16 x i1> %2, i64 %3) nounwind {
+define <vscale x 16 x i32> @intrinsic_vmerge_vxm_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, i32 %1, <vscale x 16 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vmerge_vxm_nxv16i32_nxv16i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu
@@ -956,7 +958,7 @@ entry:
<vscale x 16 x i32> %0,
i32 %1,
<vscale x 16 x i1> %2,
- i64 %3)
+ iXLen %3)
ret <vscale x 16 x i32> %a
}
@@ -966,21 +968,16 @@ declare <vscale x 1 x i64> @llvm.riscv.vmerge.nxv1i64.i64(
<vscale x 1 x i64>,
i64,
<vscale x 1 x i1>,
- i64);
+ iXLen);
-define <vscale x 1 x i64> @intrinsic_vmerge_vxm_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vmerge_vxm_nxv1i64_nxv1i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
-; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0
-; CHECK-NEXT: ret
+define <vscale x 1 x i64> @intrinsic_vmerge_vxm_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {
entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vmerge.nxv1i64.i64(
<vscale x 1 x i64> undef,
<vscale x 1 x i64> %0,
i64 %1,
<vscale x 1 x i1> %2,
- i64 %3)
+ iXLen %3)
ret <vscale x 1 x i64> %a
}
@@ -990,21 +987,16 @@ declare <vscale x 2 x i64> @llvm.riscv.vmerge.nxv2i64.i64(
<vscale x 2 x i64>,
i64,
<vscale x 2 x i1>,
- i64);
+ iXLen);
-define <vscale x 2 x i64> @intrinsic_vmerge_vxm_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vmerge_vxm_nxv2i64_nxv2i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
-; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0
-; CHECK-NEXT: ret
+define <vscale x 2 x i64> @intrinsic_vmerge_vxm_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {
entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vmerge.nxv2i64.i64(
<vscale x 2 x i64> undef,
<vscale x 2 x i64> %0,
i64 %1,
<vscale x 2 x i1> %2,
- i64 %3)
+ iXLen %3)
ret <vscale x 2 x i64> %a
}
@@ -1014,21 +1006,16 @@ declare <vscale x 4 x i64> @llvm.riscv.vmerge.nxv4i64.i64(
<vscale x 4 x i64>,
i64,
<vscale x 4 x i1>,
- i64);
+ iXLen);
-define <vscale x 4 x i64> @intrinsic_vmerge_vxm_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vmerge_vxm_nxv4i64_nxv4i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
-; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0
-; CHECK-NEXT: ret
+define <vscale x 4 x i64> @intrinsic_vmerge_vxm_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {
entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vmerge.nxv4i64.i64(
<vscale x 4 x i64> undef,
<vscale x 4 x i64> %0,
i64 %1,
<vscale x 4 x i1> %2,
- i64 %3)
+ iXLen %3)
ret <vscale x 4 x i64> %a
}
@@ -1038,26 +1025,21 @@ declare <vscale x 8 x i64> @llvm.riscv.vmerge.nxv8i64.i64(
<vscale x 8 x i64>,
i64,
<vscale x 8 x i1>,
- i64);
+ iXLen);
-define <vscale x 8 x i64> @intrinsic_vmerge_vxm_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, i64 %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vmerge_vxm_nxv8i64_nxv8i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu
-; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0
-; CHECK-NEXT: ret
+define <vscale x 8 x i64> @intrinsic_vmerge_vxm_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, i64 %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {
entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vmerge.nxv8i64.i64(
<vscale x 8 x i64> undef,
<vscale x 8 x i64> %0,
i64 %1,
<vscale x 8 x i1> %2,
- i64 %3)
+ iXLen %3)
ret <vscale x 8 x i64> %a
}
-define <vscale x 1 x i8> @intrinsic_vmerge_vim_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, <vscale x 1 x i1> %1, i64 %2) nounwind {
+define <vscale x 1 x i8> @intrinsic_vmerge_vim_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, <vscale x 1 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmerge_vim_nxv1i8_nxv1i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
@@ -1069,12 +1051,12 @@ entry:
<vscale x 1 x i8> %0,
i8 9,
<vscale x 1 x i1> %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 1 x i8> %a
}
-define <vscale x 2 x i8> @intrinsic_vmerge_vim_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, <vscale x 2 x i1> %1, i64 %2) nounwind {
+define <vscale x 2 x i8> @intrinsic_vmerge_vim_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, <vscale x 2 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmerge_vim_nxv2i8_nxv2i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
@@ -1086,12 +1068,12 @@ entry:
<vscale x 2 x i8> %0,
i8 9,
<vscale x 2 x i1> %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 2 x i8> %a
}
-define <vscale x 4 x i8> @intrinsic_vmerge_vim_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, <vscale x 4 x i1> %1, i64 %2) nounwind {
+define <vscale x 4 x i8> @intrinsic_vmerge_vim_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, <vscale x 4 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmerge_vim_nxv4i8_nxv4i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
@@ -1103,12 +1085,12 @@ entry:
<vscale x 4 x i8> %0,
i8 9,
<vscale x 4 x i1> %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 4 x i8> %a
}
-define <vscale x 8 x i8> @intrinsic_vmerge_vim_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, <vscale x 8 x i1> %1, i64 %2) nounwind {
+define <vscale x 8 x i8> @intrinsic_vmerge_vim_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, <vscale x 8 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmerge_vim_nxv8i8_nxv8i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
@@ -1120,12 +1102,12 @@ entry:
<vscale x 8 x i8> %0,
i8 9,
<vscale x 8 x i1> %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 8 x i8> %a
}
-define <vscale x 16 x i8> @intrinsic_vmerge_vim_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, <vscale x 16 x i1> %1, i64 %2) nounwind {
+define <vscale x 16 x i8> @intrinsic_vmerge_vim_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, <vscale x 16 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmerge_vim_nxv16i8_nxv16i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
@@ -1137,12 +1119,12 @@ entry:
<vscale x 16 x i8> %0,
i8 9,
<vscale x 16 x i1> %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 16 x i8> %a
}
-define <vscale x 32 x i8> @intrinsic_vmerge_vim_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, <vscale x 32 x i1> %1, i64 %2) nounwind {
+define <vscale x 32 x i8> @intrinsic_vmerge_vim_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, <vscale x 32 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmerge_vim_nxv32i8_nxv32i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
@@ -1154,12 +1136,12 @@ entry:
<vscale x 32 x i8> %0,
i8 9,
<vscale x 32 x i1> %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 32 x i8> %a
}
-define <vscale x 64 x i8> @intrinsic_vmerge_vim_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, <vscale x 64 x i1> %1, i64 %2) nounwind {
+define <vscale x 64 x i8> @intrinsic_vmerge_vim_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, <vscale x 64 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmerge_vim_nxv64i8_nxv64i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, mu
@@ -1171,12 +1153,12 @@ entry:
<vscale x 64 x i8> %0,
i8 9,
<vscale x 64 x i1> %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 64 x i8> %a
}
-define <vscale x 1 x i16> @intrinsic_vmerge_vim_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, <vscale x 1 x i1> %1, i64 %2) nounwind {
+define <vscale x 1 x i16> @intrinsic_vmerge_vim_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, <vscale x 1 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmerge_vim_nxv1i16_nxv1i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
@@ -1188,12 +1170,12 @@ entry:
<vscale x 1 x i16> %0,
i16 9,
<vscale x 1 x i1> %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 1 x i16> %a
}
-define <vscale x 2 x i16> @intrinsic_vmerge_vim_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, <vscale x 2 x i1> %1, i64 %2) nounwind {
+define <vscale x 2 x i16> @intrinsic_vmerge_vim_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, <vscale x 2 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmerge_vim_nxv2i16_nxv2i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
@@ -1205,12 +1187,12 @@ entry:
<vscale x 2 x i16> %0,
i16 9,
<vscale x 2 x i1> %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 2 x i16> %a
}
-define <vscale x 4 x i16> @intrinsic_vmerge_vim_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, <vscale x 4 x i1> %1, i64 %2) nounwind {
+define <vscale x 4 x i16> @intrinsic_vmerge_vim_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, <vscale x 4 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmerge_vim_nxv4i16_nxv4i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
@@ -1222,12 +1204,12 @@ entry:
<vscale x 4 x i16> %0,
i16 9,
<vscale x 4 x i1> %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 4 x i16> %a
}
-define <vscale x 8 x i16> @intrinsic_vmerge_vim_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, <vscale x 8 x i1> %1, i64 %2) nounwind {
+define <vscale x 8 x i16> @intrinsic_vmerge_vim_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, <vscale x 8 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmerge_vim_nxv8i16_nxv8i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
@@ -1239,12 +1221,12 @@ entry:
<vscale x 8 x i16> %0,
i16 9,
<vscale x 8 x i1> %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 8 x i16> %a
}
-define <vscale x 16 x i16> @intrinsic_vmerge_vim_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, <vscale x 16 x i1> %1, i64 %2) nounwind {
+define <vscale x 16 x i16> @intrinsic_vmerge_vim_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, <vscale x 16 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmerge_vim_nxv16i16_nxv16i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
@@ -1256,12 +1238,12 @@ entry:
<vscale x 16 x i16> %0,
i16 9,
<vscale x 16 x i1> %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 16 x i16> %a
}
-define <vscale x 32 x i16> @intrinsic_vmerge_vim_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, <vscale x 32 x i1> %1, i64 %2) nounwind {
+define <vscale x 32 x i16> @intrinsic_vmerge_vim_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, <vscale x 32 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmerge_vim_nxv32i16_nxv32i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, mu
@@ -1273,12 +1255,12 @@ entry:
<vscale x 32 x i16> %0,
i16 9,
<vscale x 32 x i1> %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 32 x i16> %a
}
-define <vscale x 1 x i32> @intrinsic_vmerge_vim_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 1 x i1> %1, i64 %2) nounwind {
+define <vscale x 1 x i32> @intrinsic_vmerge_vim_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 1 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmerge_vim_nxv1i32_nxv1i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
@@ -1290,12 +1272,12 @@ entry:
<vscale x 1 x i32> %0,
i32 9,
<vscale x 1 x i1> %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 1 x i32> %a
}
-define <vscale x 2 x i32> @intrinsic_vmerge_vim_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 2 x i1> %1, i64 %2) nounwind {
+define <vscale x 2 x i32> @intrinsic_vmerge_vim_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 2 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmerge_vim_nxv2i32_nxv2i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
@@ -1307,12 +1289,12 @@ entry:
<vscale x 2 x i32> %0,
i32 9,
<vscale x 2 x i1> %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 2 x i32> %a
}
-define <vscale x 4 x i32> @intrinsic_vmerge_vim_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 4 x i1> %1, i64 %2) nounwind {
+define <vscale x 4 x i32> @intrinsic_vmerge_vim_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 4 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmerge_vim_nxv4i32_nxv4i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
@@ -1324,12 +1306,12 @@ entry:
<vscale x 4 x i32> %0,
i32 9,
<vscale x 4 x i1> %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 4 x i32> %a
}
-define <vscale x 8 x i32> @intrinsic_vmerge_vim_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 8 x i1> %1, i64 %2) nounwind {
+define <vscale x 8 x i32> @intrinsic_vmerge_vim_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 8 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmerge_vim_nxv8i32_nxv8i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
@@ -1341,12 +1323,12 @@ entry:
<vscale x 8 x i32> %0,
i32 9,
<vscale x 8 x i1> %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 8 x i32> %a
}
-define <vscale x 16 x i32> @intrinsic_vmerge_vim_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 16 x i1> %1, i64 %2) nounwind {
+define <vscale x 16 x i32> @intrinsic_vmerge_vim_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 16 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmerge_vim_nxv16i32_nxv16i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu
@@ -1358,12 +1340,12 @@ entry:
<vscale x 16 x i32> %0,
i32 9,
<vscale x 16 x i1> %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 16 x i32> %a
}
-define <vscale x 1 x i64> @intrinsic_vmerge_vim_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i1> %1, i64 %2) nounwind {
+define <vscale x 1 x i64> @intrinsic_vmerge_vim_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmerge_vim_nxv1i64_nxv1i64_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
@@ -1375,12 +1357,12 @@ entry:
<vscale x 1 x i64> %0,
i64 9,
<vscale x 1 x i1> %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 1 x i64> %a
}
-define <vscale x 2 x i64> @intrinsic_vmerge_vim_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, <vscale x 2 x i1> %1, i64 %2) nounwind {
+define <vscale x 2 x i64> @intrinsic_vmerge_vim_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, <vscale x 2 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmerge_vim_nxv2i64_nxv2i64_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
@@ -1392,12 +1374,12 @@ entry:
<vscale x 2 x i64> %0,
i64 9,
<vscale x 2 x i1> %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 2 x i64> %a
}
-define <vscale x 4 x i64> @intrinsic_vmerge_vim_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, <vscale x 4 x i1> %1, i64 %2) nounwind {
+define <vscale x 4 x i64> @intrinsic_vmerge_vim_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, <vscale x 4 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmerge_vim_nxv4i64_nxv4i64_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
@@ -1409,12 +1391,12 @@ entry:
<vscale x 4 x i64> %0,
i64 9,
<vscale x 4 x i1> %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 4 x i64> %a
}
-define <vscale x 8 x i64> @intrinsic_vmerge_vim_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, <vscale x 8 x i1> %1, i64 %2) nounwind {
+define <vscale x 8 x i64> @intrinsic_vmerge_vim_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, <vscale x 8 x i1> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmerge_vim_nxv8i64_nxv8i64_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu
@@ -1426,7 +1408,7 @@ entry:
<vscale x 8 x i64> %0,
i64 9,
<vscale x 8 x i1> %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 8 x i64> %a
}
@@ -1436,9 +1418,9 @@ declare <vscale x 1 x half> @llvm.riscv.vmerge.nxv1f16.nxv1f16(
<vscale x 1 x half>,
<vscale x 1 x half>,
<vscale x 1 x i1>,
- i64);
+ iXLen);
-define <vscale x 1 x half> @intrinsic_vmerge_vvm_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
+define <vscale x 1 x half> @intrinsic_vmerge_vvm_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vmerge_vvm_nxv1f16_nxv1f16_nxv1f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
@@ -1450,7 +1432,7 @@ entry:
<vscale x 1 x half> %0,
<vscale x 1 x half> %1,
<vscale x 1 x i1> %2,
- i64 %3)
+ iXLen %3)
ret <vscale x 1 x half> %a
}
@@ -1460,9 +1442,9 @@ declare <vscale x 2 x half> @llvm.riscv.vmerge.nxv2f16.nxv2f16(
<vscale x 2 x half>,
<vscale x 2 x half>,
<vscale x 2 x i1>,
- i64);
+ iXLen);
-define <vscale x 2 x half> @intrinsic_vmerge_vvm_nxv2f16_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
+define <vscale x 2 x half> @intrinsic_vmerge_vvm_nxv2f16_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vmerge_vvm_nxv2f16_nxv2f16_nxv2f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
@@ -1474,7 +1456,7 @@ entry:
<vscale x 2 x half> %0,
<vscale x 2 x half> %1,
<vscale x 2 x i1> %2,
- i64 %3)
+ iXLen %3)
ret <vscale x 2 x half> %a
}
@@ -1484,9 +1466,9 @@ declare <vscale x 4 x half> @llvm.riscv.vmerge.nxv4f16.nxv4f16(
<vscale x 4 x half>,
<vscale x 4 x half>,
<vscale x 4 x i1>,
- i64);
+ iXLen);
-define <vscale x 4 x half> @intrinsic_vmerge_vvm_nxv4f16_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
+define <vscale x 4 x half> @intrinsic_vmerge_vvm_nxv4f16_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vmerge_vvm_nxv4f16_nxv4f16_nxv4f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
@@ -1498,7 +1480,7 @@ entry:
<vscale x 4 x half> %0,
<vscale x 4 x half> %1,
<vscale x 4 x i1> %2,
- i64 %3)
+ iXLen %3)
ret <vscale x 4 x half> %a
}
@@ -1508,9 +1490,9 @@ declare <vscale x 8 x half> @llvm.riscv.vmerge.nxv8f16.nxv8f16(
<vscale x 8 x half>,
<vscale x 8 x half>,
<vscale x 8 x i1>,
- i64);
+ iXLen);
-define <vscale x 8 x half> @intrinsic_vmerge_vvm_nxv8f16_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
+define <vscale x 8 x half> @intrinsic_vmerge_vvm_nxv8f16_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vmerge_vvm_nxv8f16_nxv8f16_nxv8f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
@@ -1522,7 +1504,7 @@ entry:
<vscale x 8 x half> %0,
<vscale x 8 x half> %1,
<vscale x 8 x i1> %2,
- i64 %3)
+ iXLen %3)
ret <vscale x 8 x half> %a
}
@@ -1532,9 +1514,9 @@ declare <vscale x 16 x half> @llvm.riscv.vmerge.nxv16f16.nxv16f16(
<vscale x 16 x half>,
<vscale x 16 x half>,
<vscale x 16 x i1>,
- i64);
+ iXLen);
-define <vscale x 16 x half> @intrinsic_vmerge_vvm_nxv16f16_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x i1> %2, i64 %3) nounwind {
+define <vscale x 16 x half> @intrinsic_vmerge_vvm_nxv16f16_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vmerge_vvm_nxv16f16_nxv16f16_nxv16f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
@@ -1546,7 +1528,7 @@ entry:
<vscale x 16 x half> %0,
<vscale x 16 x half> %1,
<vscale x 16 x i1> %2,
- i64 %3)
+ iXLen %3)
ret <vscale x 16 x half> %a
}
@@ -1556,9 +1538,9 @@ declare <vscale x 32 x half> @llvm.riscv.vmerge.nxv32f16.nxv32f16(
<vscale x 32 x half>,
<vscale x 32 x half>,
<vscale x 32 x i1>,
- i64);
+ iXLen);
-define <vscale x 32 x half> @intrinsic_vmerge_vvm_nxv32f16_nxv32f16_nxv32f16(<vscale x 32 x half> %0, <vscale x 32 x half> %1, <vscale x 32 x i1> %2, i64 %3) nounwind {
+define <vscale x 32 x half> @intrinsic_vmerge_vvm_nxv32f16_nxv32f16_nxv32f16(<vscale x 32 x half> %0, <vscale x 32 x half> %1, <vscale x 32 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vmerge_vvm_nxv32f16_nxv32f16_nxv32f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, mu
@@ -1570,7 +1552,7 @@ entry:
<vscale x 32 x half> %0,
<vscale x 32 x half> %1,
<vscale x 32 x i1> %2,
- i64 %3)
+ iXLen %3)
ret <vscale x 32 x half> %a
}
@@ -1580,9 +1562,9 @@ declare <vscale x 1 x float> @llvm.riscv.vmerge.nxv1f32.nxv1f32(
<vscale x 1 x float>,
<vscale x 1 x float>,
<vscale x 1 x i1>,
- i64);
+ iXLen);
-define <vscale x 1 x float> @intrinsic_vmerge_vvm_nxv1f32_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
+define <vscale x 1 x float> @intrinsic_vmerge_vvm_nxv1f32_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vmerge_vvm_nxv1f32_nxv1f32_nxv1f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
@@ -1594,7 +1576,7 @@ entry:
<vscale x 1 x float> %0,
<vscale x 1 x float> %1,
<vscale x 1 x i1> %2,
- i64 %3)
+ iXLen %3)
ret <vscale x 1 x float> %a
}
@@ -1604,9 +1586,9 @@ declare <vscale x 2 x float> @llvm.riscv.vmerge.nxv2f32.nxv2f32(
<vscale x 2 x float>,
<vscale x 2 x float>,
<vscale x 2 x i1>,
- i64);
+ iXLen);
-define <vscale x 2 x float> @intrinsic_vmerge_vvm_nxv2f32_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
+define <vscale x 2 x float> @intrinsic_vmerge_vvm_nxv2f32_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vmerge_vvm_nxv2f32_nxv2f32_nxv2f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
@@ -1618,7 +1600,7 @@ entry:
<vscale x 2 x float> %0,
<vscale x 2 x float> %1,
<vscale x 2 x i1> %2,
- i64 %3)
+ iXLen %3)
ret <vscale x 2 x float> %a
}
@@ -1628,9 +1610,9 @@ declare <vscale x 4 x float> @llvm.riscv.vmerge.nxv4f32.nxv4f32(
<vscale x 4 x float>,
<vscale x 4 x float>,
<vscale x 4 x i1>,
- i64);
+ iXLen);
-define <vscale x 4 x float> @intrinsic_vmerge_vvm_nxv4f32_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
+define <vscale x 4 x float> @intrinsic_vmerge_vvm_nxv4f32_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vmerge_vvm_nxv4f32_nxv4f32_nxv4f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
@@ -1642,7 +1624,7 @@ entry:
<vscale x 4 x float> %0,
<vscale x 4 x float> %1,
<vscale x 4 x i1> %2,
- i64 %3)
+ iXLen %3)
ret <vscale x 4 x float> %a
}
@@ -1652,9 +1634,9 @@ declare <vscale x 8 x float> @llvm.riscv.vmerge.nxv8f32.nxv8f32(
<vscale x 8 x float>,
<vscale x 8 x float>,
<vscale x 8 x i1>,
- i64);
+ iXLen);
-define <vscale x 8 x float> @intrinsic_vmerge_vvm_nxv8f32_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
+define <vscale x 8 x float> @intrinsic_vmerge_vvm_nxv8f32_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vmerge_vvm_nxv8f32_nxv8f32_nxv8f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
@@ -1666,7 +1648,7 @@ entry:
<vscale x 8 x float> %0,
<vscale x 8 x float> %1,
<vscale x 8 x i1> %2,
- i64 %3)
+ iXLen %3)
ret <vscale x 8 x float> %a
}
@@ -1676,9 +1658,9 @@ declare <vscale x 16 x float> @llvm.riscv.vmerge.nxv16f32.nxv16f32(
<vscale x 16 x float>,
<vscale x 16 x float>,
<vscale x 16 x i1>,
- i64);
+ iXLen);
-define <vscale x 16 x float> @intrinsic_vmerge_vvm_nxv16f32_nxv16f32_nxv16f32(<vscale x 16 x float> %0, <vscale x 16 x float> %1, <vscale x 16 x i1> %2, i64 %3) nounwind {
+define <vscale x 16 x float> @intrinsic_vmerge_vvm_nxv16f32_nxv16f32_nxv16f32(<vscale x 16 x float> %0, <vscale x 16 x float> %1, <vscale x 16 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vmerge_vvm_nxv16f32_nxv16f32_nxv16f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu
@@ -1690,7 +1672,7 @@ entry:
<vscale x 16 x float> %0,
<vscale x 16 x float> %1,
<vscale x 16 x i1> %2,
- i64 %3)
+ iXLen %3)
ret <vscale x 16 x float> %a
}
@@ -1700,9 +1682,9 @@ declare <vscale x 1 x double> @llvm.riscv.vmerge.nxv1f64.nxv1f64(
<vscale x 1 x double>,
<vscale x 1 x double>,
<vscale x 1 x i1>,
- i64);
+ iXLen);
-define <vscale x 1 x double> @intrinsic_vmerge_vvm_nxv1f64_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
+define <vscale x 1 x double> @intrinsic_vmerge_vvm_nxv1f64_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vmerge_vvm_nxv1f64_nxv1f64_nxv1f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
@@ -1714,7 +1696,7 @@ entry:
<vscale x 1 x double> %0,
<vscale x 1 x double> %1,
<vscale x 1 x i1> %2,
- i64 %3)
+ iXLen %3)
ret <vscale x 1 x double> %a
}
@@ -1724,9 +1706,9 @@ declare <vscale x 2 x double> @llvm.riscv.vmerge.nxv2f64.nxv2f64(
<vscale x 2 x double>,
<vscale x 2 x double>,
<vscale x 2 x i1>,
- i64);
+ iXLen);
-define <vscale x 2 x double> @intrinsic_vmerge_vvm_nxv2f64_nxv2f64_nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
+define <vscale x 2 x double> @intrinsic_vmerge_vvm_nxv2f64_nxv2f64_nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vmerge_vvm_nxv2f64_nxv2f64_nxv2f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
@@ -1738,7 +1720,7 @@ entry:
<vscale x 2 x double> %0,
<vscale x 2 x double> %1,
<vscale x 2 x i1> %2,
- i64 %3)
+ iXLen %3)
ret <vscale x 2 x double> %a
}
@@ -1748,9 +1730,9 @@ declare <vscale x 4 x double> @llvm.riscv.vmerge.nxv4f64.nxv4f64(
<vscale x 4 x double>,
<vscale x 4 x double>,
<vscale x 4 x i1>,
- i64);
+ iXLen);
-define <vscale x 4 x double> @intrinsic_vmerge_vvm_nxv4f64_nxv4f64_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
+define <vscale x 4 x double> @intrinsic_vmerge_vvm_nxv4f64_nxv4f64_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vmerge_vvm_nxv4f64_nxv4f64_nxv4f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
@@ -1762,7 +1744,7 @@ entry:
<vscale x 4 x double> %0,
<vscale x 4 x double> %1,
<vscale x 4 x i1> %2,
- i64 %3)
+ iXLen %3)
ret <vscale x 4 x double> %a
}
@@ -1772,9 +1754,9 @@ declare <vscale x 8 x double> @llvm.riscv.vmerge.nxv8f64.nxv8f64(
<vscale x 8 x double>,
<vscale x 8 x double>,
<vscale x 8 x i1>,
- i64);
+ iXLen);
-define <vscale x 8 x double> @intrinsic_vmerge_vvm_nxv8f64_nxv8f64_nxv8f64(<vscale x 8 x double> %0, <vscale x 8 x double> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
+define <vscale x 8 x double> @intrinsic_vmerge_vvm_nxv8f64_nxv8f64_nxv8f64(<vscale x 8 x double> %0, <vscale x 8 x double> %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vmerge_vvm_nxv8f64_nxv8f64_nxv8f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu
@@ -1786,7 +1768,7 @@ entry:
<vscale x 8 x double> %0,
<vscale x 8 x double> %1,
<vscale x 8 x i1> %2,
- i64 %3)
+ iXLen %3)
ret <vscale x 8 x double> %a
}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmfeq-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmfeq-rv32.ll
deleted file mode 100644
index ce679449f5a83..0000000000000
--- a/llvm/test/CodeGen/RISCV/rvv/vmfeq-rv32.ll
+++ /dev/null
@@ -1,1190 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -mattr=+v,+d,+zfh -verify-machineinstrs \
-; RUN: -target-abi=ilp32d < %s | FileCheck %s
-declare <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1f16(
- <vscale x 1 x half>,
- <vscale x 1 x half>,
- i32);
-
-define <vscale x 1 x i1> @intrinsic_vmfeq_vv_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmfeq_vv_nxv1f16_nxv1f16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vmfeq.vv v0, v8, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1f16(
- <vscale x 1 x half> %0,
- <vscale x 1 x half> %1,
- i32 %2)
-
- ret <vscale x 1 x i1> %a
-}
-
-declare <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1f16(
- <vscale x 1 x i1>,
- <vscale x 1 x half>,
- <vscale x 1 x half>,
- <vscale x 1 x i1>,
- i32);
-
-define <vscale x 1 x i1> @intrinsic_vmfeq_mask_vv_nxv1f16_nxv1f16(<vscale x 1 x i1> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x half> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv1f16_nxv1f16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vmfeq.vv v8, v8, v9
-; CHECK-NEXT: vmv1r.v v11, v0
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmfeq.vv v11, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v11
-; CHECK-NEXT: ret
-entry:
- %mask = call <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1f16(
- <vscale x 1 x half> %1,
- <vscale x 1 x half> %2,
- i32 %4)
- %a = call <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1f16(
- <vscale x 1 x i1> %0,
- <vscale x 1 x half> %2,
- <vscale x 1 x half> %3,
- <vscale x 1 x i1> %mask,
- i32 %4)
-
- ret <vscale x 1 x i1> %a
-}
-
-declare <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2f16(
- <vscale x 2 x half>,
- <vscale x 2 x half>,
- i32);
-
-define <vscale x 2 x i1> @intrinsic_vmfeq_vv_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmfeq_vv_nxv2f16_nxv2f16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vmfeq.vv v0, v8, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2f16(
- <vscale x 2 x half> %0,
- <vscale x 2 x half> %1,
- i32 %2)
-
- ret <vscale x 2 x i1> %a
-}
-
-declare <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2f16(
- <vscale x 2 x i1>,
- <vscale x 2 x half>,
- <vscale x 2 x half>,
- <vscale x 2 x i1>,
- i32);
-
-define <vscale x 2 x i1> @intrinsic_vmfeq_mask_vv_nxv2f16_nxv2f16(<vscale x 2 x i1> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, <vscale x 2 x half> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv2f16_nxv2f16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vmfeq.vv v8, v8, v9
-; CHECK-NEXT: vmv1r.v v11, v0
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmfeq.vv v11, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v11
-; CHECK-NEXT: ret
-entry:
- %mask = call <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2f16(
- <vscale x 2 x half> %1,
- <vscale x 2 x half> %2,
- i32 %4)
- %a = call <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2f16(
- <vscale x 2 x i1> %0,
- <vscale x 2 x half> %2,
- <vscale x 2 x half> %3,
- <vscale x 2 x i1> %mask,
- i32 %4)
-
- ret <vscale x 2 x i1> %a
-}
-
-declare <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4f16(
- <vscale x 4 x half>,
- <vscale x 4 x half>,
- i32);
-
-define <vscale x 4 x i1> @intrinsic_vmfeq_vv_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmfeq_vv_nxv4f16_nxv4f16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vmfeq.vv v0, v8, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4f16(
- <vscale x 4 x half> %0,
- <vscale x 4 x half> %1,
- i32 %2)
-
- ret <vscale x 4 x i1> %a
-}
-
-declare <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4f16(
- <vscale x 4 x i1>,
- <vscale x 4 x half>,
- <vscale x 4 x half>,
- <vscale x 4 x i1>,
- i32);
-
-define <vscale x 4 x i1> @intrinsic_vmfeq_mask_vv_nxv4f16_nxv4f16(<vscale x 4 x i1> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x half> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv4f16_nxv4f16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vmfeq.vv v8, v8, v9
-; CHECK-NEXT: vmv1r.v v11, v0
-; CHECK-NEXT: vmv.v.v v0, v8
-; CHECK-NEXT: vmfeq.vv v11, v9, v10, v0.t
-; CHECK-NEXT: vmv.v.v v0, v11
-; CHECK-NEXT: ret
-entry:
- %mask = call <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4f16(
- <vscale x 4 x half> %1,
- <vscale x 4 x half> %2,
- i32 %4)
- %a = call <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4f16(
- <vscale x 4 x i1> %0,
- <vscale x 4 x half> %2,
- <vscale x 4 x half> %3,
- <vscale x 4 x i1> %mask,
- i32 %4)
-
- ret <vscale x 4 x i1> %a
-}
-
-declare <vscale x 8 x i1> @llvm.riscv.vmfeq.nxv8f16(
- <vscale x 8 x half>,
- <vscale x 8 x half>,
- i32);
-
-define <vscale x 8 x i1> @intrinsic_vmfeq_vv_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmfeq_vv_nxv8f16_nxv8f16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vmfeq.vv v0, v8, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i1> @llvm.riscv.vmfeq.nxv8f16(
- <vscale x 8 x half> %0,
- <vscale x 8 x half> %1,
- i32 %2)
-
- ret <vscale x 8 x i1> %a
-}
-
-declare <vscale x 8 x i1> @llvm.riscv.vmfeq.mask.nxv8f16(
- <vscale x 8 x i1>,
- <vscale x 8 x half>,
- <vscale x 8 x half>,
- <vscale x 8 x i1>,
- i32);
-
-define <vscale x 8 x i1> @intrinsic_vmfeq_mask_vv_nxv8f16_nxv8f16(<vscale x 8 x i1> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x half> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv8f16_nxv8f16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vmfeq.vv v14, v8, v10
-; CHECK-NEXT: vmv1r.v v8, v0
-; CHECK-NEXT: vmv1r.v v0, v14
-; CHECK-NEXT: vmfeq.vv v8, v10, v12, v0.t
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: ret
-entry:
- %mask = call <vscale x 8 x i1> @llvm.riscv.vmfeq.nxv8f16(
- <vscale x 8 x half> %1,
- <vscale x 8 x half> %2,
- i32 %4)
- %a = call <vscale x 8 x i1> @llvm.riscv.vmfeq.mask.nxv8f16(
- <vscale x 8 x i1> %0,
- <vscale x 8 x half> %2,
- <vscale x 8 x half> %3,
- <vscale x 8 x i1> %mask,
- i32 %4)
-
- ret <vscale x 8 x i1> %a
-}
-
-declare <vscale x 16 x i1> @llvm.riscv.vmfeq.nxv16f16(
- <vscale x 16 x half>,
- <vscale x 16 x half>,
- i32);
-
-define <vscale x 16 x i1> @intrinsic_vmfeq_vv_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmfeq_vv_nxv16f16_nxv16f16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
-; CHECK-NEXT: vmfeq.vv v0, v8, v12
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i1> @llvm.riscv.vmfeq.nxv16f16(
- <vscale x 16 x half> %0,
- <vscale x 16 x half> %1,
- i32 %2)
-
- ret <vscale x 16 x i1> %a
-}
-
-declare <vscale x 16 x i1> @llvm.riscv.vmfeq.mask.nxv16f16(
- <vscale x 16 x i1>,
- <vscale x 16 x half>,
- <vscale x 16 x half>,
- <vscale x 16 x i1>,
- i32);
-
-define <vscale x 16 x i1> @intrinsic_vmfeq_mask_vv_nxv16f16_nxv16f16(<vscale x 16 x i1> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, <vscale x 16 x half> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv16f16_nxv16f16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
-; CHECK-NEXT: vmfeq.vv v20, v8, v12
-; CHECK-NEXT: vmv1r.v v8, v0
-; CHECK-NEXT: vmv1r.v v0, v20
-; CHECK-NEXT: vmfeq.vv v8, v12, v16, v0.t
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: ret
-entry:
- %mask = call <vscale x 16 x i1> @llvm.riscv.vmfeq.nxv16f16(
- <vscale x 16 x half> %1,
- <vscale x 16 x half> %2,
- i32 %4)
- %a = call <vscale x 16 x i1> @llvm.riscv.vmfeq.mask.nxv16f16(
- <vscale x 16 x i1> %0,
- <vscale x 16 x half> %2,
- <vscale x 16 x half> %3,
- <vscale x 16 x i1> %mask,
- i32 %4)
-
- ret <vscale x 16 x i1> %a
-}
-
-declare <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1f32(
- <vscale x 1 x float>,
- <vscale x 1 x float>,
- i32);
-
-define <vscale x 1 x i1> @intrinsic_vmfeq_vv_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmfeq_vv_nxv1f32_nxv1f32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vmfeq.vv v0, v8, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1f32(
- <vscale x 1 x float> %0,
- <vscale x 1 x float> %1,
- i32 %2)
-
- ret <vscale x 1 x i1> %a
-}
-
-declare <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1f32(
- <vscale x 1 x i1>,
- <vscale x 1 x float>,
- <vscale x 1 x float>,
- <vscale x 1 x i1>,
- i32);
-
-define <vscale x 1 x i1> @intrinsic_vmfeq_mask_vv_nxv1f32_nxv1f32(<vscale x 1 x i1> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, <vscale x 1 x float> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv1f32_nxv1f32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vmfeq.vv v8, v8, v9
-; CHECK-NEXT: vmv1r.v v11, v0
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmfeq.vv v11, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v11
-; CHECK-NEXT: ret
-entry:
- %mask = call <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1f32(
- <vscale x 1 x float> %1,
- <vscale x 1 x float> %2,
- i32 %4)
- %a = call <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1f32(
- <vscale x 1 x i1> %0,
- <vscale x 1 x float> %2,
- <vscale x 1 x float> %3,
- <vscale x 1 x i1> %mask,
- i32 %4)
-
- ret <vscale x 1 x i1> %a
-}
-
-declare <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2f32(
- <vscale x 2 x float>,
- <vscale x 2 x float>,
- i32);
-
-define <vscale x 2 x i1> @intrinsic_vmfeq_vv_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmfeq_vv_nxv2f32_nxv2f32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vmfeq.vv v0, v8, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2f32(
- <vscale x 2 x float> %0,
- <vscale x 2 x float> %1,
- i32 %2)
-
- ret <vscale x 2 x i1> %a
-}
-
-declare <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2f32(
- <vscale x 2 x i1>,
- <vscale x 2 x float>,
- <vscale x 2 x float>,
- <vscale x 2 x i1>,
- i32);
-
-define <vscale x 2 x i1> @intrinsic_vmfeq_mask_vv_nxv2f32_nxv2f32(<vscale x 2 x i1> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x float> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv2f32_nxv2f32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vmfeq.vv v8, v8, v9
-; CHECK-NEXT: vmv1r.v v11, v0
-; CHECK-NEXT: vmv.v.v v0, v8
-; CHECK-NEXT: vmfeq.vv v11, v9, v10, v0.t
-; CHECK-NEXT: vmv.v.v v0, v11
-; CHECK-NEXT: ret
-entry:
- %mask = call <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2f32(
- <vscale x 2 x float> %1,
- <vscale x 2 x float> %2,
- i32 %4)
- %a = call <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2f32(
- <vscale x 2 x i1> %0,
- <vscale x 2 x float> %2,
- <vscale x 2 x float> %3,
- <vscale x 2 x i1> %mask,
- i32 %4)
-
- ret <vscale x 2 x i1> %a
-}
-
-declare <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4f32(
- <vscale x 4 x float>,
- <vscale x 4 x float>,
- i32);
-
-define <vscale x 4 x i1> @intrinsic_vmfeq_vv_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmfeq_vv_nxv4f32_nxv4f32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vmfeq.vv v0, v8, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4f32(
- <vscale x 4 x float> %0,
- <vscale x 4 x float> %1,
- i32 %2)
-
- ret <vscale x 4 x i1> %a
-}
-
-declare <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4f32(
- <vscale x 4 x i1>,
- <vscale x 4 x float>,
- <vscale x 4 x float>,
- <vscale x 4 x i1>,
- i32);
-
-define <vscale x 4 x i1> @intrinsic_vmfeq_mask_vv_nxv4f32_nxv4f32(<vscale x 4 x i1> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x float> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv4f32_nxv4f32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vmfeq.vv v14, v8, v10
-; CHECK-NEXT: vmv1r.v v8, v0
-; CHECK-NEXT: vmv1r.v v0, v14
-; CHECK-NEXT: vmfeq.vv v8, v10, v12, v0.t
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: ret
-entry:
- %mask = call <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4f32(
- <vscale x 4 x float> %1,
- <vscale x 4 x float> %2,
- i32 %4)
- %a = call <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4f32(
- <vscale x 4 x i1> %0,
- <vscale x 4 x float> %2,
- <vscale x 4 x float> %3,
- <vscale x 4 x i1> %mask,
- i32 %4)
-
- ret <vscale x 4 x i1> %a
-}
-
-declare <vscale x 8 x i1> @llvm.riscv.vmfeq.nxv8f32(
- <vscale x 8 x float>,
- <vscale x 8 x float>,
- i32);
-
-define <vscale x 8 x i1> @intrinsic_vmfeq_vv_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmfeq_vv_nxv8f32_nxv8f32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
-; CHECK-NEXT: vmfeq.vv v0, v8, v12
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i1> @llvm.riscv.vmfeq.nxv8f32(
- <vscale x 8 x float> %0,
- <vscale x 8 x float> %1,
- i32 %2)
-
- ret <vscale x 8 x i1> %a
-}
-
-declare <vscale x 8 x i1> @llvm.riscv.vmfeq.mask.nxv8f32(
- <vscale x 8 x i1>,
- <vscale x 8 x float>,
- <vscale x 8 x float>,
- <vscale x 8 x i1>,
- i32);
-
-define <vscale x 8 x i1> @intrinsic_vmfeq_mask_vv_nxv8f32_nxv8f32(<vscale x 8 x i1> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, <vscale x 8 x float> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv8f32_nxv8f32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
-; CHECK-NEXT: vmfeq.vv v20, v8, v12
-; CHECK-NEXT: vmv1r.v v8, v0
-; CHECK-NEXT: vmv1r.v v0, v20
-; CHECK-NEXT: vmfeq.vv v8, v12, v16, v0.t
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: ret
-entry:
- %mask = call <vscale x 8 x i1> @llvm.riscv.vmfeq.nxv8f32(
- <vscale x 8 x float> %1,
- <vscale x 8 x float> %2,
- i32 %4)
- %a = call <vscale x 8 x i1> @llvm.riscv.vmfeq.mask.nxv8f32(
- <vscale x 8 x i1> %0,
- <vscale x 8 x float> %2,
- <vscale x 8 x float> %3,
- <vscale x 8 x i1> %mask,
- i32 %4)
-
- ret <vscale x 8 x i1> %a
-}
-
-declare <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1f64(
- <vscale x 1 x double>,
- <vscale x 1 x double>,
- i32);
-
-define <vscale x 1 x i1> @intrinsic_vmfeq_vv_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmfeq_vv_nxv1f64_nxv1f64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
-; CHECK-NEXT: vmfeq.vv v0, v8, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1f64(
- <vscale x 1 x double> %0,
- <vscale x 1 x double> %1,
- i32 %2)
-
- ret <vscale x 1 x i1> %a
-}
-
-declare <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1f64(
- <vscale x 1 x i1>,
- <vscale x 1 x double>,
- <vscale x 1 x double>,
- <vscale x 1 x i1>,
- i32);
-
-define <vscale x 1 x i1> @intrinsic_vmfeq_mask_vv_nxv1f64_nxv1f64(<vscale x 1 x i1> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, <vscale x 1 x double> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv1f64_nxv1f64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
-; CHECK-NEXT: vmfeq.vv v8, v8, v9
-; CHECK-NEXT: vmv1r.v v11, v0
-; CHECK-NEXT: vmv.v.v v0, v8
-; CHECK-NEXT: vmfeq.vv v11, v9, v10, v0.t
-; CHECK-NEXT: vmv.v.v v0, v11
-; CHECK-NEXT: ret
-entry:
- %mask = call <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1f64(
- <vscale x 1 x double> %1,
- <vscale x 1 x double> %2,
- i32 %4)
- %a = call <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1f64(
- <vscale x 1 x i1> %0,
- <vscale x 1 x double> %2,
- <vscale x 1 x double> %3,
- <vscale x 1 x i1> %mask,
- i32 %4)
-
- ret <vscale x 1 x i1> %a
-}
-
-declare <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2f64(
- <vscale x 2 x double>,
- <vscale x 2 x double>,
- i32);
-
-define <vscale x 2 x i1> @intrinsic_vmfeq_vv_nxv2f64_nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmfeq_vv_nxv2f64_nxv2f64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
-; CHECK-NEXT: vmfeq.vv v0, v8, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2f64(
- <vscale x 2 x double> %0,
- <vscale x 2 x double> %1,
- i32 %2)
-
- ret <vscale x 2 x i1> %a
-}
-
-declare <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2f64(
- <vscale x 2 x i1>,
- <vscale x 2 x double>,
- <vscale x 2 x double>,
- <vscale x 2 x i1>,
- i32);
-
-define <vscale x 2 x i1> @intrinsic_vmfeq_mask_vv_nxv2f64_nxv2f64(<vscale x 2 x i1> %0, <vscale x 2 x double> %1, <vscale x 2 x double> %2, <vscale x 2 x double> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv2f64_nxv2f64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
-; CHECK-NEXT: vmfeq.vv v14, v8, v10
-; CHECK-NEXT: vmv1r.v v8, v0
-; CHECK-NEXT: vmv1r.v v0, v14
-; CHECK-NEXT: vmfeq.vv v8, v10, v12, v0.t
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: ret
-entry:
- %mask = call <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2f64(
- <vscale x 2 x double> %1,
- <vscale x 2 x double> %2,
- i32 %4)
- %a = call <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2f64(
- <vscale x 2 x i1> %0,
- <vscale x 2 x double> %2,
- <vscale x 2 x double> %3,
- <vscale x 2 x i1> %mask,
- i32 %4)
-
- ret <vscale x 2 x i1> %a
-}
-
-declare <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4f64(
- <vscale x 4 x double>,
- <vscale x 4 x double>,
- i32);
-
-define <vscale x 4 x i1> @intrinsic_vmfeq_vv_nxv4f64_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmfeq_vv_nxv4f64_nxv4f64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
-; CHECK-NEXT: vmfeq.vv v0, v8, v12
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4f64(
- <vscale x 4 x double> %0,
- <vscale x 4 x double> %1,
- i32 %2)
-
- ret <vscale x 4 x i1> %a
-}
-
-declare <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4f64(
- <vscale x 4 x i1>,
- <vscale x 4 x double>,
- <vscale x 4 x double>,
- <vscale x 4 x i1>,
- i32);
-
-define <vscale x 4 x i1> @intrinsic_vmfeq_mask_vv_nxv4f64_nxv4f64(<vscale x 4 x i1> %0, <vscale x 4 x double> %1, <vscale x 4 x double> %2, <vscale x 4 x double> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv4f64_nxv4f64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
-; CHECK-NEXT: vmfeq.vv v20, v8, v12
-; CHECK-NEXT: vmv1r.v v8, v0
-; CHECK-NEXT: vmv1r.v v0, v20
-; CHECK-NEXT: vmfeq.vv v8, v12, v16, v0.t
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: ret
-entry:
- %mask = call <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4f64(
- <vscale x 4 x double> %1,
- <vscale x 4 x double> %2,
- i32 %4)
- %a = call <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4f64(
- <vscale x 4 x i1> %0,
- <vscale x 4 x double> %2,
- <vscale x 4 x double> %3,
- <vscale x 4 x i1> %mask,
- i32 %4)
-
- ret <vscale x 4 x i1> %a
-}
-
-declare <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1f16.f16(
- <vscale x 1 x half>,
- half,
- i32);
-
-define <vscale x 1 x i1> @intrinsic_vmfeq_vf_nxv1f16_f16(<vscale x 1 x half> %0, half %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmfeq_vf_nxv1f16_f16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vmfeq.vf v0, v8, fa0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1f16.f16(
- <vscale x 1 x half> %0,
- half %1,
- i32 %2)
-
- ret <vscale x 1 x i1> %a
-}
-
-declare <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1f16.f16(
- <vscale x 1 x i1>,
- <vscale x 1 x half>,
- half,
- <vscale x 1 x i1>,
- i32);
-
-define <vscale x 1 x i1> @intrinsic_vmfeq_mask_vf_nxv1f16_f16(<vscale x 1 x i1> %0, <vscale x 1 x half> %1, half %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv1f16_f16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v10, v0
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmfeq.vf v10, v8, fa0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1f16.f16(
- <vscale x 1 x i1> %0,
- <vscale x 1 x half> %1,
- half %2,
- <vscale x 1 x i1> %3,
- i32 %4)
-
- ret <vscale x 1 x i1> %a
-}
-
-declare <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2f16.f16(
- <vscale x 2 x half>,
- half,
- i32);
-
-define <vscale x 2 x i1> @intrinsic_vmfeq_vf_nxv2f16_f16(<vscale x 2 x half> %0, half %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmfeq_vf_nxv2f16_f16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vmfeq.vf v0, v8, fa0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2f16.f16(
- <vscale x 2 x half> %0,
- half %1,
- i32 %2)
-
- ret <vscale x 2 x i1> %a
-}
-
-declare <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2f16.f16(
- <vscale x 2 x i1>,
- <vscale x 2 x half>,
- half,
- <vscale x 2 x i1>,
- i32);
-
-define <vscale x 2 x i1> @intrinsic_vmfeq_mask_vf_nxv2f16_f16(<vscale x 2 x i1> %0, <vscale x 2 x half> %1, half %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv2f16_f16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v10, v0
-; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmfeq.vf v10, v8, fa0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2f16.f16(
- <vscale x 2 x i1> %0,
- <vscale x 2 x half> %1,
- half %2,
- <vscale x 2 x i1> %3,
- i32 %4)
-
- ret <vscale x 2 x i1> %a
-}
-
-declare <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4f16.f16(
- <vscale x 4 x half>,
- half,
- i32);
-
-define <vscale x 4 x i1> @intrinsic_vmfeq_vf_nxv4f16_f16(<vscale x 4 x half> %0, half %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmfeq_vf_nxv4f16_f16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vmfeq.vf v0, v8, fa0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4f16.f16(
- <vscale x 4 x half> %0,
- half %1,
- i32 %2)
-
- ret <vscale x 4 x i1> %a
-}
-
-declare <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4f16.f16(
- <vscale x 4 x i1>,
- <vscale x 4 x half>,
- half,
- <vscale x 4 x i1>,
- i32);
-
-define <vscale x 4 x i1> @intrinsic_vmfeq_mask_vf_nxv4f16_f16(<vscale x 4 x i1> %0, <vscale x 4 x half> %1, half %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv4f16_f16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v10, v0
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmfeq.vf v10, v8, fa0, v0.t
-; CHECK-NEXT: vmv.v.v v0, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4f16.f16(
- <vscale x 4 x i1> %0,
- <vscale x 4 x half> %1,
- half %2,
- <vscale x 4 x i1> %3,
- i32 %4)
-
- ret <vscale x 4 x i1> %a
-}
-
-declare <vscale x 8 x i1> @llvm.riscv.vmfeq.nxv8f16.f16(
- <vscale x 8 x half>,
- half,
- i32);
-
-define <vscale x 8 x i1> @intrinsic_vmfeq_vf_nxv8f16_f16(<vscale x 8 x half> %0, half %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmfeq_vf_nxv8f16_f16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vmfeq.vf v0, v8, fa0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i1> @llvm.riscv.vmfeq.nxv8f16.f16(
- <vscale x 8 x half> %0,
- half %1,
- i32 %2)
-
- ret <vscale x 8 x i1> %a
-}
-
-declare <vscale x 8 x i1> @llvm.riscv.vmfeq.mask.nxv8f16.f16(
- <vscale x 8 x i1>,
- <vscale x 8 x half>,
- half,
- <vscale x 8 x i1>,
- i32);
-
-define <vscale x 8 x i1> @intrinsic_vmfeq_mask_vf_nxv8f16_f16(<vscale x 8 x i1> %0, <vscale x 8 x half> %1, half %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv8f16_f16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v11, v0
-; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmfeq.vf v11, v8, fa0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v11
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i1> @llvm.riscv.vmfeq.mask.nxv8f16.f16(
- <vscale x 8 x i1> %0,
- <vscale x 8 x half> %1,
- half %2,
- <vscale x 8 x i1> %3,
- i32 %4)
-
- ret <vscale x 8 x i1> %a
-}
-
-declare <vscale x 16 x i1> @llvm.riscv.vmfeq.nxv16f16.f16(
- <vscale x 16 x half>,
- half,
- i32);
-
-define <vscale x 16 x i1> @intrinsic_vmfeq_vf_nxv16f16_f16(<vscale x 16 x half> %0, half %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmfeq_vf_nxv16f16_f16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
-; CHECK-NEXT: vmfeq.vf v0, v8, fa0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i1> @llvm.riscv.vmfeq.nxv16f16.f16(
- <vscale x 16 x half> %0,
- half %1,
- i32 %2)
-
- ret <vscale x 16 x i1> %a
-}
-
-declare <vscale x 16 x i1> @llvm.riscv.vmfeq.mask.nxv16f16.f16(
- <vscale x 16 x i1>,
- <vscale x 16 x half>,
- half,
- <vscale x 16 x i1>,
- i32);
-
-define <vscale x 16 x i1> @intrinsic_vmfeq_mask_vf_nxv16f16_f16(<vscale x 16 x i1> %0, <vscale x 16 x half> %1, half %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv16f16_f16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v13, v0
-; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
-; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmfeq.vf v13, v8, fa0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v13
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i1> @llvm.riscv.vmfeq.mask.nxv16f16.f16(
- <vscale x 16 x i1> %0,
- <vscale x 16 x half> %1,
- half %2,
- <vscale x 16 x i1> %3,
- i32 %4)
-
- ret <vscale x 16 x i1> %a
-}
-
-declare <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1f32.f32(
- <vscale x 1 x float>,
- float,
- i32);
-
-define <vscale x 1 x i1> @intrinsic_vmfeq_vf_nxv1f32_f32(<vscale x 1 x float> %0, float %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmfeq_vf_nxv1f32_f32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vmfeq.vf v0, v8, fa0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1f32.f32(
- <vscale x 1 x float> %0,
- float %1,
- i32 %2)
-
- ret <vscale x 1 x i1> %a
-}
-
-declare <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1f32.f32(
- <vscale x 1 x i1>,
- <vscale x 1 x float>,
- float,
- <vscale x 1 x i1>,
- i32);
-
-define <vscale x 1 x i1> @intrinsic_vmfeq_mask_vf_nxv1f32_f32(<vscale x 1 x i1> %0, <vscale x 1 x float> %1, float %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv1f32_f32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v10, v0
-; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmfeq.vf v10, v8, fa0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1f32.f32(
- <vscale x 1 x i1> %0,
- <vscale x 1 x float> %1,
- float %2,
- <vscale x 1 x i1> %3,
- i32 %4)
-
- ret <vscale x 1 x i1> %a
-}
-
-declare <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2f32.f32(
- <vscale x 2 x float>,
- float,
- i32);
-
-define <vscale x 2 x i1> @intrinsic_vmfeq_vf_nxv2f32_f32(<vscale x 2 x float> %0, float %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmfeq_vf_nxv2f32_f32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vmfeq.vf v0, v8, fa0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2f32.f32(
- <vscale x 2 x float> %0,
- float %1,
- i32 %2)
-
- ret <vscale x 2 x i1> %a
-}
-
-declare <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2f32.f32(
- <vscale x 2 x i1>,
- <vscale x 2 x float>,
- float,
- <vscale x 2 x i1>,
- i32);
-
-define <vscale x 2 x i1> @intrinsic_vmfeq_mask_vf_nxv2f32_f32(<vscale x 2 x i1> %0, <vscale x 2 x float> %1, float %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv2f32_f32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v10, v0
-; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmfeq.vf v10, v8, fa0, v0.t
-; CHECK-NEXT: vmv.v.v v0, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2f32.f32(
- <vscale x 2 x i1> %0,
- <vscale x 2 x float> %1,
- float %2,
- <vscale x 2 x i1> %3,
- i32 %4)
-
- ret <vscale x 2 x i1> %a
-}
-
-declare <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4f32.f32(
- <vscale x 4 x float>,
- float,
- i32);
-
-define <vscale x 4 x i1> @intrinsic_vmfeq_vf_nxv4f32_f32(<vscale x 4 x float> %0, float %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmfeq_vf_nxv4f32_f32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vmfeq.vf v0, v8, fa0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4f32.f32(
- <vscale x 4 x float> %0,
- float %1,
- i32 %2)
-
- ret <vscale x 4 x i1> %a
-}
-
-declare <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4f32.f32(
- <vscale x 4 x i1>,
- <vscale x 4 x float>,
- float,
- <vscale x 4 x i1>,
- i32);
-
-define <vscale x 4 x i1> @intrinsic_vmfeq_mask_vf_nxv4f32_f32(<vscale x 4 x i1> %0, <vscale x 4 x float> %1, float %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv4f32_f32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v11, v0
-; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmfeq.vf v11, v8, fa0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v11
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4f32.f32(
- <vscale x 4 x i1> %0,
- <vscale x 4 x float> %1,
- float %2,
- <vscale x 4 x i1> %3,
- i32 %4)
-
- ret <vscale x 4 x i1> %a
-}
-
-declare <vscale x 8 x i1> @llvm.riscv.vmfeq.nxv8f32.f32(
- <vscale x 8 x float>,
- float,
- i32);
-
-define <vscale x 8 x i1> @intrinsic_vmfeq_vf_nxv8f32_f32(<vscale x 8 x float> %0, float %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmfeq_vf_nxv8f32_f32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
-; CHECK-NEXT: vmfeq.vf v0, v8, fa0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i1> @llvm.riscv.vmfeq.nxv8f32.f32(
- <vscale x 8 x float> %0,
- float %1,
- i32 %2)
-
- ret <vscale x 8 x i1> %a
-}
-
-declare <vscale x 8 x i1> @llvm.riscv.vmfeq.mask.nxv8f32.f32(
- <vscale x 8 x i1>,
- <vscale x 8 x float>,
- float,
- <vscale x 8 x i1>,
- i32);
-
-define <vscale x 8 x i1> @intrinsic_vmfeq_mask_vf_nxv8f32_f32(<vscale x 8 x i1> %0, <vscale x 8 x float> %1, float %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv8f32_f32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v13, v0
-; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
-; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmfeq.vf v13, v8, fa0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v13
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i1> @llvm.riscv.vmfeq.mask.nxv8f32.f32(
- <vscale x 8 x i1> %0,
- <vscale x 8 x float> %1,
- float %2,
- <vscale x 8 x i1> %3,
- i32 %4)
-
- ret <vscale x 8 x i1> %a
-}
-
-declare <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1f64.f64(
- <vscale x 1 x double>,
- double,
- i32);
-
-define <vscale x 1 x i1> @intrinsic_vmfeq_vf_nxv1f64_f64(<vscale x 1 x double> %0, double %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmfeq_vf_nxv1f64_f64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
-; CHECK-NEXT: vmfeq.vf v0, v8, fa0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1f64.f64(
- <vscale x 1 x double> %0,
- double %1,
- i32 %2)
-
- ret <vscale x 1 x i1> %a
-}
-
-declare <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1f64.f64(
- <vscale x 1 x i1>,
- <vscale x 1 x double>,
- double,
- <vscale x 1 x i1>,
- i32);
-
-define <vscale x 1 x i1> @intrinsic_vmfeq_mask_vf_nxv1f64_f64(<vscale x 1 x i1> %0, <vscale x 1 x double> %1, double %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv1f64_f64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v10, v0
-; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
-; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmfeq.vf v10, v8, fa0, v0.t
-; CHECK-NEXT: vmv.v.v v0, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1f64.f64(
- <vscale x 1 x i1> %0,
- <vscale x 1 x double> %1,
- double %2,
- <vscale x 1 x i1> %3,
- i32 %4)
-
- ret <vscale x 1 x i1> %a
-}
-
-declare <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2f64.f64(
- <vscale x 2 x double>,
- double,
- i32);
-
-define <vscale x 2 x i1> @intrinsic_vmfeq_vf_nxv2f64_f64(<vscale x 2 x double> %0, double %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmfeq_vf_nxv2f64_f64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
-; CHECK-NEXT: vmfeq.vf v0, v8, fa0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2f64.f64(
- <vscale x 2 x double> %0,
- double %1,
- i32 %2)
-
- ret <vscale x 2 x i1> %a
-}
-
-declare <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2f64.f64(
- <vscale x 2 x i1>,
- <vscale x 2 x double>,
- double,
- <vscale x 2 x i1>,
- i32);
-
-define <vscale x 2 x i1> @intrinsic_vmfeq_mask_vf_nxv2f64_f64(<vscale x 2 x i1> %0, <vscale x 2 x double> %1, double %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv2f64_f64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v11, v0
-; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
-; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmfeq.vf v11, v8, fa0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v11
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2f64.f64(
- <vscale x 2 x i1> %0,
- <vscale x 2 x double> %1,
- double %2,
- <vscale x 2 x i1> %3,
- i32 %4)
-
- ret <vscale x 2 x i1> %a
-}
-
-declare <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4f64.f64(
- <vscale x 4 x double>,
- double,
- i32);
-
-define <vscale x 4 x i1> @intrinsic_vmfeq_vf_nxv4f64_f64(<vscale x 4 x double> %0, double %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmfeq_vf_nxv4f64_f64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
-; CHECK-NEXT: vmfeq.vf v0, v8, fa0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4f64.f64(
- <vscale x 4 x double> %0,
- double %1,
- i32 %2)
-
- ret <vscale x 4 x i1> %a
-}
-
-declare <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4f64.f64(
- <vscale x 4 x i1>,
- <vscale x 4 x double>,
- double,
- <vscale x 4 x i1>,
- i32);
-
-define <vscale x 4 x i1> @intrinsic_vmfeq_mask_vf_nxv4f64_f64(<vscale x 4 x i1> %0, <vscale x 4 x double> %1, double %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv4f64_f64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v13, v0
-; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
-; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmfeq.vf v13, v8, fa0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v13
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4f64.f64(
- <vscale x 4 x i1> %0,
- <vscale x 4 x double> %1,
- double %2,
- <vscale x 4 x i1> %3,
- i32 %4)
-
- ret <vscale x 4 x i1> %a
-}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmfeq-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vmfeq.ll
similarity index 88%
rename from llvm/test/CodeGen/RISCV/rvv/vmfeq-rv64.ll
rename to llvm/test/CodeGen/RISCV/rvv/vmfeq.ll
index e9c03b9739a6a..36d8d469c53a8 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vmfeq-rv64.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vmfeq.ll
@@ -1,12 +1,14 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv64 -mattr=+v,+d,+zfh -verify-machineinstrs \
-; RUN: -target-abi=lp64d < %s | FileCheck %s
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh \
+; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh \
+; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s
declare <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1f16(
<vscale x 1 x half>,
<vscale x 1 x half>,
- i64);
+ iXLen);
-define <vscale x 1 x i1> @intrinsic_vmfeq_vv_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2) nounwind {
+define <vscale x 1 x i1> @intrinsic_vmfeq_vv_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmfeq_vv_nxv1f16_nxv1f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
@@ -16,7 +18,7 @@ entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1f16(
<vscale x 1 x half> %0,
<vscale x 1 x half> %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 1 x i1> %a
}
@@ -26,9 +28,9 @@ declare <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1f16(
<vscale x 1 x half>,
<vscale x 1 x half>,
<vscale x 1 x i1>,
- i64);
+ iXLen);
-define <vscale x 1 x i1> @intrinsic_vmfeq_mask_vv_nxv1f16_nxv1f16(<vscale x 1 x i1> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x half> %3, i64 %4) nounwind {
+define <vscale x 1 x i1> @intrinsic_vmfeq_mask_vv_nxv1f16_nxv1f16(<vscale x 1 x i1> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x half> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv1f16_nxv1f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
@@ -42,13 +44,13 @@ entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1f16(
<vscale x 1 x half> %1,
<vscale x 1 x half> %2,
- i64 %4)
+ iXLen %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1f16(
<vscale x 1 x i1> %0,
<vscale x 1 x half> %2,
<vscale x 1 x half> %3,
<vscale x 1 x i1> %mask,
- i64 %4)
+ iXLen %4)
ret <vscale x 1 x i1> %a
}
@@ -56,9 +58,9 @@ entry:
declare <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2f16(
<vscale x 2 x half>,
<vscale x 2 x half>,
- i64);
+ iXLen);
-define <vscale x 2 x i1> @intrinsic_vmfeq_vv_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2) nounwind {
+define <vscale x 2 x i1> @intrinsic_vmfeq_vv_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmfeq_vv_nxv2f16_nxv2f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
@@ -68,7 +70,7 @@ entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2f16(
<vscale x 2 x half> %0,
<vscale x 2 x half> %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 2 x i1> %a
}
@@ -78,9 +80,9 @@ declare <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2f16(
<vscale x 2 x half>,
<vscale x 2 x half>,
<vscale x 2 x i1>,
- i64);
+ iXLen);
-define <vscale x 2 x i1> @intrinsic_vmfeq_mask_vv_nxv2f16_nxv2f16(<vscale x 2 x i1> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, <vscale x 2 x half> %3, i64 %4) nounwind {
+define <vscale x 2 x i1> @intrinsic_vmfeq_mask_vv_nxv2f16_nxv2f16(<vscale x 2 x i1> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, <vscale x 2 x half> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv2f16_nxv2f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
@@ -94,13 +96,13 @@ entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2f16(
<vscale x 2 x half> %1,
<vscale x 2 x half> %2,
- i64 %4)
+ iXLen %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2f16(
<vscale x 2 x i1> %0,
<vscale x 2 x half> %2,
<vscale x 2 x half> %3,
<vscale x 2 x i1> %mask,
- i64 %4)
+ iXLen %4)
ret <vscale x 2 x i1> %a
}
@@ -108,9 +110,9 @@ entry:
declare <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4f16(
<vscale x 4 x half>,
<vscale x 4 x half>,
- i64);
+ iXLen);
-define <vscale x 4 x i1> @intrinsic_vmfeq_vv_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2) nounwind {
+define <vscale x 4 x i1> @intrinsic_vmfeq_vv_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmfeq_vv_nxv4f16_nxv4f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
@@ -120,7 +122,7 @@ entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4f16(
<vscale x 4 x half> %0,
<vscale x 4 x half> %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 4 x i1> %a
}
@@ -130,9 +132,9 @@ declare <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4f16(
<vscale x 4 x half>,
<vscale x 4 x half>,
<vscale x 4 x i1>,
- i64);
+ iXLen);
-define <vscale x 4 x i1> @intrinsic_vmfeq_mask_vv_nxv4f16_nxv4f16(<vscale x 4 x i1> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x half> %3, i64 %4) nounwind {
+define <vscale x 4 x i1> @intrinsic_vmfeq_mask_vv_nxv4f16_nxv4f16(<vscale x 4 x i1> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x half> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv4f16_nxv4f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
@@ -146,13 +148,13 @@ entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4f16(
<vscale x 4 x half> %1,
<vscale x 4 x half> %2,
- i64 %4)
+ iXLen %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4f16(
<vscale x 4 x i1> %0,
<vscale x 4 x half> %2,
<vscale x 4 x half> %3,
<vscale x 4 x i1> %mask,
- i64 %4)
+ iXLen %4)
ret <vscale x 4 x i1> %a
}
@@ -160,9 +162,9 @@ entry:
declare <vscale x 8 x i1> @llvm.riscv.vmfeq.nxv8f16(
<vscale x 8 x half>,
<vscale x 8 x half>,
- i64);
+ iXLen);
-define <vscale x 8 x i1> @intrinsic_vmfeq_vv_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2) nounwind {
+define <vscale x 8 x i1> @intrinsic_vmfeq_vv_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmfeq_vv_nxv8f16_nxv8f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
@@ -172,7 +174,7 @@ entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmfeq.nxv8f16(
<vscale x 8 x half> %0,
<vscale x 8 x half> %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 8 x i1> %a
}
@@ -182,9 +184,9 @@ declare <vscale x 8 x i1> @llvm.riscv.vmfeq.mask.nxv8f16(
<vscale x 8 x half>,
<vscale x 8 x half>,
<vscale x 8 x i1>,
- i64);
+ iXLen);
-define <vscale x 8 x i1> @intrinsic_vmfeq_mask_vv_nxv8f16_nxv8f16(<vscale x 8 x i1> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x half> %3, i64 %4) nounwind {
+define <vscale x 8 x i1> @intrinsic_vmfeq_mask_vv_nxv8f16_nxv8f16(<vscale x 8 x i1> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x half> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv8f16_nxv8f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
@@ -198,13 +200,13 @@ entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmfeq.nxv8f16(
<vscale x 8 x half> %1,
<vscale x 8 x half> %2,
- i64 %4)
+ iXLen %4)
%a = call <vscale x 8 x i1> @llvm.riscv.vmfeq.mask.nxv8f16(
<vscale x 8 x i1> %0,
<vscale x 8 x half> %2,
<vscale x 8 x half> %3,
<vscale x 8 x i1> %mask,
- i64 %4)
+ iXLen %4)
ret <vscale x 8 x i1> %a
}
@@ -212,9 +214,9 @@ entry:
declare <vscale x 16 x i1> @llvm.riscv.vmfeq.nxv16f16(
<vscale x 16 x half>,
<vscale x 16 x half>,
- i64);
+ iXLen);
-define <vscale x 16 x i1> @intrinsic_vmfeq_vv_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2) nounwind {
+define <vscale x 16 x i1> @intrinsic_vmfeq_vv_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmfeq_vv_nxv16f16_nxv16f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
@@ -224,7 +226,7 @@ entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmfeq.nxv16f16(
<vscale x 16 x half> %0,
<vscale x 16 x half> %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 16 x i1> %a
}
@@ -234,9 +236,9 @@ declare <vscale x 16 x i1> @llvm.riscv.vmfeq.mask.nxv16f16(
<vscale x 16 x half>,
<vscale x 16 x half>,
<vscale x 16 x i1>,
- i64);
+ iXLen);
-define <vscale x 16 x i1> @intrinsic_vmfeq_mask_vv_nxv16f16_nxv16f16(<vscale x 16 x i1> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, <vscale x 16 x half> %3, i64 %4) nounwind {
+define <vscale x 16 x i1> @intrinsic_vmfeq_mask_vv_nxv16f16_nxv16f16(<vscale x 16 x i1> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, <vscale x 16 x half> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv16f16_nxv16f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
@@ -250,13 +252,13 @@ entry:
%mask = call <vscale x 16 x i1> @llvm.riscv.vmfeq.nxv16f16(
<vscale x 16 x half> %1,
<vscale x 16 x half> %2,
- i64 %4)
+ iXLen %4)
%a = call <vscale x 16 x i1> @llvm.riscv.vmfeq.mask.nxv16f16(
<vscale x 16 x i1> %0,
<vscale x 16 x half> %2,
<vscale x 16 x half> %3,
<vscale x 16 x i1> %mask,
- i64 %4)
+ iXLen %4)
ret <vscale x 16 x i1> %a
}
@@ -264,9 +266,9 @@ entry:
declare <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1f32(
<vscale x 1 x float>,
<vscale x 1 x float>,
- i64);
+ iXLen);
-define <vscale x 1 x i1> @intrinsic_vmfeq_vv_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, i64 %2) nounwind {
+define <vscale x 1 x i1> @intrinsic_vmfeq_vv_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmfeq_vv_nxv1f32_nxv1f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
@@ -276,7 +278,7 @@ entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1f32(
<vscale x 1 x float> %0,
<vscale x 1 x float> %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 1 x i1> %a
}
@@ -286,9 +288,9 @@ declare <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1f32(
<vscale x 1 x float>,
<vscale x 1 x float>,
<vscale x 1 x i1>,
- i64);
+ iXLen);
-define <vscale x 1 x i1> @intrinsic_vmfeq_mask_vv_nxv1f32_nxv1f32(<vscale x 1 x i1> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, <vscale x 1 x float> %3, i64 %4) nounwind {
+define <vscale x 1 x i1> @intrinsic_vmfeq_mask_vv_nxv1f32_nxv1f32(<vscale x 1 x i1> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, <vscale x 1 x float> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv1f32_nxv1f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
@@ -302,13 +304,13 @@ entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1f32(
<vscale x 1 x float> %1,
<vscale x 1 x float> %2,
- i64 %4)
+ iXLen %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1f32(
<vscale x 1 x i1> %0,
<vscale x 1 x float> %2,
<vscale x 1 x float> %3,
<vscale x 1 x i1> %mask,
- i64 %4)
+ iXLen %4)
ret <vscale x 1 x i1> %a
}
@@ -316,9 +318,9 @@ entry:
declare <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2f32(
<vscale x 2 x float>,
<vscale x 2 x float>,
- i64);
+ iXLen);
-define <vscale x 2 x i1> @intrinsic_vmfeq_vv_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 %2) nounwind {
+define <vscale x 2 x i1> @intrinsic_vmfeq_vv_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmfeq_vv_nxv2f32_nxv2f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
@@ -328,7 +330,7 @@ entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2f32(
<vscale x 2 x float> %0,
<vscale x 2 x float> %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 2 x i1> %a
}
@@ -338,9 +340,9 @@ declare <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2f32(
<vscale x 2 x float>,
<vscale x 2 x float>,
<vscale x 2 x i1>,
- i64);
+ iXLen);
-define <vscale x 2 x i1> @intrinsic_vmfeq_mask_vv_nxv2f32_nxv2f32(<vscale x 2 x i1> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x float> %3, i64 %4) nounwind {
+define <vscale x 2 x i1> @intrinsic_vmfeq_mask_vv_nxv2f32_nxv2f32(<vscale x 2 x i1> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x float> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv2f32_nxv2f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
@@ -354,13 +356,13 @@ entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2f32(
<vscale x 2 x float> %1,
<vscale x 2 x float> %2,
- i64 %4)
+ iXLen %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2f32(
<vscale x 2 x i1> %0,
<vscale x 2 x float> %2,
<vscale x 2 x float> %3,
<vscale x 2 x i1> %mask,
- i64 %4)
+ iXLen %4)
ret <vscale x 2 x i1> %a
}
@@ -368,9 +370,9 @@ entry:
declare <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4f32(
<vscale x 4 x float>,
<vscale x 4 x float>,
- i64);
+ iXLen);
-define <vscale x 4 x i1> @intrinsic_vmfeq_vv_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, i64 %2) nounwind {
+define <vscale x 4 x i1> @intrinsic_vmfeq_vv_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmfeq_vv_nxv4f32_nxv4f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
@@ -380,7 +382,7 @@ entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4f32(
<vscale x 4 x float> %0,
<vscale x 4 x float> %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 4 x i1> %a
}
@@ -390,9 +392,9 @@ declare <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4f32(
<vscale x 4 x float>,
<vscale x 4 x float>,
<vscale x 4 x i1>,
- i64);
+ iXLen);
-define <vscale x 4 x i1> @intrinsic_vmfeq_mask_vv_nxv4f32_nxv4f32(<vscale x 4 x i1> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x float> %3, i64 %4) nounwind {
+define <vscale x 4 x i1> @intrinsic_vmfeq_mask_vv_nxv4f32_nxv4f32(<vscale x 4 x i1> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x float> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv4f32_nxv4f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
@@ -406,13 +408,13 @@ entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4f32(
<vscale x 4 x float> %1,
<vscale x 4 x float> %2,
- i64 %4)
+ iXLen %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4f32(
<vscale x 4 x i1> %0,
<vscale x 4 x float> %2,
<vscale x 4 x float> %3,
<vscale x 4 x i1> %mask,
- i64 %4)
+ iXLen %4)
ret <vscale x 4 x i1> %a
}
@@ -420,9 +422,9 @@ entry:
declare <vscale x 8 x i1> @llvm.riscv.vmfeq.nxv8f32(
<vscale x 8 x float>,
<vscale x 8 x float>,
- i64);
+ iXLen);
-define <vscale x 8 x i1> @intrinsic_vmfeq_vv_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, i64 %2) nounwind {
+define <vscale x 8 x i1> @intrinsic_vmfeq_vv_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmfeq_vv_nxv8f32_nxv8f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
@@ -432,7 +434,7 @@ entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmfeq.nxv8f32(
<vscale x 8 x float> %0,
<vscale x 8 x float> %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 8 x i1> %a
}
@@ -442,9 +444,9 @@ declare <vscale x 8 x i1> @llvm.riscv.vmfeq.mask.nxv8f32(
<vscale x 8 x float>,
<vscale x 8 x float>,
<vscale x 8 x i1>,
- i64);
+ iXLen);
-define <vscale x 8 x i1> @intrinsic_vmfeq_mask_vv_nxv8f32_nxv8f32(<vscale x 8 x i1> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, <vscale x 8 x float> %3, i64 %4) nounwind {
+define <vscale x 8 x i1> @intrinsic_vmfeq_mask_vv_nxv8f32_nxv8f32(<vscale x 8 x i1> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, <vscale x 8 x float> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv8f32_nxv8f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
@@ -458,13 +460,13 @@ entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmfeq.nxv8f32(
<vscale x 8 x float> %1,
<vscale x 8 x float> %2,
- i64 %4)
+ iXLen %4)
%a = call <vscale x 8 x i1> @llvm.riscv.vmfeq.mask.nxv8f32(
<vscale x 8 x i1> %0,
<vscale x 8 x float> %2,
<vscale x 8 x float> %3,
<vscale x 8 x i1> %mask,
- i64 %4)
+ iXLen %4)
ret <vscale x 8 x i1> %a
}
@@ -472,9 +474,9 @@ entry:
declare <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1f64(
<vscale x 1 x double>,
<vscale x 1 x double>,
- i64);
+ iXLen);
-define <vscale x 1 x i1> @intrinsic_vmfeq_vv_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, i64 %2) nounwind {
+define <vscale x 1 x i1> @intrinsic_vmfeq_vv_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmfeq_vv_nxv1f64_nxv1f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
@@ -484,7 +486,7 @@ entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1f64(
<vscale x 1 x double> %0,
<vscale x 1 x double> %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 1 x i1> %a
}
@@ -494,9 +496,9 @@ declare <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1f64(
<vscale x 1 x double>,
<vscale x 1 x double>,
<vscale x 1 x i1>,
- i64);
+ iXLen);
-define <vscale x 1 x i1> @intrinsic_vmfeq_mask_vv_nxv1f64_nxv1f64(<vscale x 1 x i1> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, <vscale x 1 x double> %3, i64 %4) nounwind {
+define <vscale x 1 x i1> @intrinsic_vmfeq_mask_vv_nxv1f64_nxv1f64(<vscale x 1 x i1> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, <vscale x 1 x double> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv1f64_nxv1f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
@@ -510,13 +512,13 @@ entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1f64(
<vscale x 1 x double> %1,
<vscale x 1 x double> %2,
- i64 %4)
+ iXLen %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1f64(
<vscale x 1 x i1> %0,
<vscale x 1 x double> %2,
<vscale x 1 x double> %3,
<vscale x 1 x i1> %mask,
- i64 %4)
+ iXLen %4)
ret <vscale x 1 x i1> %a
}
@@ -524,9 +526,9 @@ entry:
declare <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2f64(
<vscale x 2 x double>,
<vscale x 2 x double>,
- i64);
+ iXLen);
-define <vscale x 2 x i1> @intrinsic_vmfeq_vv_nxv2f64_nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, i64 %2) nounwind {
+define <vscale x 2 x i1> @intrinsic_vmfeq_vv_nxv2f64_nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmfeq_vv_nxv2f64_nxv2f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
@@ -536,7 +538,7 @@ entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2f64(
<vscale x 2 x double> %0,
<vscale x 2 x double> %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 2 x i1> %a
}
@@ -546,9 +548,9 @@ declare <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2f64(
<vscale x 2 x double>,
<vscale x 2 x double>,
<vscale x 2 x i1>,
- i64);
+ iXLen);
-define <vscale x 2 x i1> @intrinsic_vmfeq_mask_vv_nxv2f64_nxv2f64(<vscale x 2 x i1> %0, <vscale x 2 x double> %1, <vscale x 2 x double> %2, <vscale x 2 x double> %3, i64 %4) nounwind {
+define <vscale x 2 x i1> @intrinsic_vmfeq_mask_vv_nxv2f64_nxv2f64(<vscale x 2 x i1> %0, <vscale x 2 x double> %1, <vscale x 2 x double> %2, <vscale x 2 x double> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv2f64_nxv2f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
@@ -562,13 +564,13 @@ entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2f64(
<vscale x 2 x double> %1,
<vscale x 2 x double> %2,
- i64 %4)
+ iXLen %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2f64(
<vscale x 2 x i1> %0,
<vscale x 2 x double> %2,
<vscale x 2 x double> %3,
<vscale x 2 x i1> %mask,
- i64 %4)
+ iXLen %4)
ret <vscale x 2 x i1> %a
}
@@ -576,9 +578,9 @@ entry:
declare <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4f64(
<vscale x 4 x double>,
<vscale x 4 x double>,
- i64);
+ iXLen);
-define <vscale x 4 x i1> @intrinsic_vmfeq_vv_nxv4f64_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, i64 %2) nounwind {
+define <vscale x 4 x i1> @intrinsic_vmfeq_vv_nxv4f64_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmfeq_vv_nxv4f64_nxv4f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
@@ -588,7 +590,7 @@ entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4f64(
<vscale x 4 x double> %0,
<vscale x 4 x double> %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 4 x i1> %a
}
@@ -598,9 +600,9 @@ declare <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4f64(
<vscale x 4 x double>,
<vscale x 4 x double>,
<vscale x 4 x i1>,
- i64);
+ iXLen);
-define <vscale x 4 x i1> @intrinsic_vmfeq_mask_vv_nxv4f64_nxv4f64(<vscale x 4 x i1> %0, <vscale x 4 x double> %1, <vscale x 4 x double> %2, <vscale x 4 x double> %3, i64 %4) nounwind {
+define <vscale x 4 x i1> @intrinsic_vmfeq_mask_vv_nxv4f64_nxv4f64(<vscale x 4 x i1> %0, <vscale x 4 x double> %1, <vscale x 4 x double> %2, <vscale x 4 x double> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv4f64_nxv4f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
@@ -614,13 +616,13 @@ entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4f64(
<vscale x 4 x double> %1,
<vscale x 4 x double> %2,
- i64 %4)
+ iXLen %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4f64(
<vscale x 4 x i1> %0,
<vscale x 4 x double> %2,
<vscale x 4 x double> %3,
<vscale x 4 x i1> %mask,
- i64 %4)
+ iXLen %4)
ret <vscale x 4 x i1> %a
}
@@ -628,9 +630,9 @@ entry:
declare <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1f16.f16(
<vscale x 1 x half>,
half,
- i64);
+ iXLen);
-define <vscale x 1 x i1> @intrinsic_vmfeq_vf_nxv1f16_f16(<vscale x 1 x half> %0, half %1, i64 %2) nounwind {
+define <vscale x 1 x i1> @intrinsic_vmfeq_vf_nxv1f16_f16(<vscale x 1 x half> %0, half %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmfeq_vf_nxv1f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
@@ -640,7 +642,7 @@ entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1f16.f16(
<vscale x 1 x half> %0,
half %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 1 x i1> %a
}
@@ -650,9 +652,9 @@ declare <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1f16.f16(
<vscale x 1 x half>,
half,
<vscale x 1 x i1>,
- i64);
+ iXLen);
-define <vscale x 1 x i1> @intrinsic_vmfeq_mask_vf_nxv1f16_f16(<vscale x 1 x i1> %0, <vscale x 1 x half> %1, half %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+define <vscale x 1 x i1> @intrinsic_vmfeq_mask_vf_nxv1f16_f16(<vscale x 1 x i1> %0, <vscale x 1 x half> %1, half %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv1f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0
@@ -667,7 +669,7 @@ entry:
<vscale x 1 x half> %1,
half %2,
<vscale x 1 x i1> %3,
- i64 %4)
+ iXLen %4)
ret <vscale x 1 x i1> %a
}
@@ -675,9 +677,9 @@ entry:
declare <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2f16.f16(
<vscale x 2 x half>,
half,
- i64);
+ iXLen);
-define <vscale x 2 x i1> @intrinsic_vmfeq_vf_nxv2f16_f16(<vscale x 2 x half> %0, half %1, i64 %2) nounwind {
+define <vscale x 2 x i1> @intrinsic_vmfeq_vf_nxv2f16_f16(<vscale x 2 x half> %0, half %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmfeq_vf_nxv2f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
@@ -687,7 +689,7 @@ entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2f16.f16(
<vscale x 2 x half> %0,
half %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 2 x i1> %a
}
@@ -697,9 +699,9 @@ declare <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2f16.f16(
<vscale x 2 x half>,
half,
<vscale x 2 x i1>,
- i64);
+ iXLen);
-define <vscale x 2 x i1> @intrinsic_vmfeq_mask_vf_nxv2f16_f16(<vscale x 2 x i1> %0, <vscale x 2 x half> %1, half %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+define <vscale x 2 x i1> @intrinsic_vmfeq_mask_vf_nxv2f16_f16(<vscale x 2 x i1> %0, <vscale x 2 x half> %1, half %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv2f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0
@@ -714,7 +716,7 @@ entry:
<vscale x 2 x half> %1,
half %2,
<vscale x 2 x i1> %3,
- i64 %4)
+ iXLen %4)
ret <vscale x 2 x i1> %a
}
@@ -722,9 +724,9 @@ entry:
declare <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4f16.f16(
<vscale x 4 x half>,
half,
- i64);
+ iXLen);
-define <vscale x 4 x i1> @intrinsic_vmfeq_vf_nxv4f16_f16(<vscale x 4 x half> %0, half %1, i64 %2) nounwind {
+define <vscale x 4 x i1> @intrinsic_vmfeq_vf_nxv4f16_f16(<vscale x 4 x half> %0, half %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmfeq_vf_nxv4f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
@@ -734,7 +736,7 @@ entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4f16.f16(
<vscale x 4 x half> %0,
half %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 4 x i1> %a
}
@@ -744,9 +746,9 @@ declare <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4f16.f16(
<vscale x 4 x half>,
half,
<vscale x 4 x i1>,
- i64);
+ iXLen);
-define <vscale x 4 x i1> @intrinsic_vmfeq_mask_vf_nxv4f16_f16(<vscale x 4 x i1> %0, <vscale x 4 x half> %1, half %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+define <vscale x 4 x i1> @intrinsic_vmfeq_mask_vf_nxv4f16_f16(<vscale x 4 x i1> %0, <vscale x 4 x half> %1, half %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv4f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0
@@ -761,7 +763,7 @@ entry:
<vscale x 4 x half> %1,
half %2,
<vscale x 4 x i1> %3,
- i64 %4)
+ iXLen %4)
ret <vscale x 4 x i1> %a
}
@@ -769,9 +771,9 @@ entry:
declare <vscale x 8 x i1> @llvm.riscv.vmfeq.nxv8f16.f16(
<vscale x 8 x half>,
half,
- i64);
+ iXLen);
-define <vscale x 8 x i1> @intrinsic_vmfeq_vf_nxv8f16_f16(<vscale x 8 x half> %0, half %1, i64 %2) nounwind {
+define <vscale x 8 x i1> @intrinsic_vmfeq_vf_nxv8f16_f16(<vscale x 8 x half> %0, half %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmfeq_vf_nxv8f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
@@ -781,7 +783,7 @@ entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmfeq.nxv8f16.f16(
<vscale x 8 x half> %0,
half %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 8 x i1> %a
}
@@ -791,9 +793,9 @@ declare <vscale x 8 x i1> @llvm.riscv.vmfeq.mask.nxv8f16.f16(
<vscale x 8 x half>,
half,
<vscale x 8 x i1>,
- i64);
+ iXLen);
-define <vscale x 8 x i1> @intrinsic_vmfeq_mask_vf_nxv8f16_f16(<vscale x 8 x i1> %0, <vscale x 8 x half> %1, half %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+define <vscale x 8 x i1> @intrinsic_vmfeq_mask_vf_nxv8f16_f16(<vscale x 8 x i1> %0, <vscale x 8 x half> %1, half %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv8f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v11, v0
@@ -808,7 +810,7 @@ entry:
<vscale x 8 x half> %1,
half %2,
<vscale x 8 x i1> %3,
- i64 %4)
+ iXLen %4)
ret <vscale x 8 x i1> %a
}
@@ -816,9 +818,9 @@ entry:
declare <vscale x 16 x i1> @llvm.riscv.vmfeq.nxv16f16.f16(
<vscale x 16 x half>,
half,
- i64);
+ iXLen);
-define <vscale x 16 x i1> @intrinsic_vmfeq_vf_nxv16f16_f16(<vscale x 16 x half> %0, half %1, i64 %2) nounwind {
+define <vscale x 16 x i1> @intrinsic_vmfeq_vf_nxv16f16_f16(<vscale x 16 x half> %0, half %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmfeq_vf_nxv16f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
@@ -828,7 +830,7 @@ entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmfeq.nxv16f16.f16(
<vscale x 16 x half> %0,
half %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 16 x i1> %a
}
@@ -838,9 +840,9 @@ declare <vscale x 16 x i1> @llvm.riscv.vmfeq.mask.nxv16f16.f16(
<vscale x 16 x half>,
half,
<vscale x 16 x i1>,
- i64);
+ iXLen);
-define <vscale x 16 x i1> @intrinsic_vmfeq_mask_vf_nxv16f16_f16(<vscale x 16 x i1> %0, <vscale x 16 x half> %1, half %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+define <vscale x 16 x i1> @intrinsic_vmfeq_mask_vf_nxv16f16_f16(<vscale x 16 x i1> %0, <vscale x 16 x half> %1, half %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv16f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v13, v0
@@ -855,7 +857,7 @@ entry:
<vscale x 16 x half> %1,
half %2,
<vscale x 16 x i1> %3,
- i64 %4)
+ iXLen %4)
ret <vscale x 16 x i1> %a
}
@@ -863,9 +865,9 @@ entry:
declare <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1f32.f32(
<vscale x 1 x float>,
float,
- i64);
+ iXLen);
-define <vscale x 1 x i1> @intrinsic_vmfeq_vf_nxv1f32_f32(<vscale x 1 x float> %0, float %1, i64 %2) nounwind {
+define <vscale x 1 x i1> @intrinsic_vmfeq_vf_nxv1f32_f32(<vscale x 1 x float> %0, float %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmfeq_vf_nxv1f32_f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
@@ -875,7 +877,7 @@ entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1f32.f32(
<vscale x 1 x float> %0,
float %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 1 x i1> %a
}
@@ -885,9 +887,9 @@ declare <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1f32.f32(
<vscale x 1 x float>,
float,
<vscale x 1 x i1>,
- i64);
+ iXLen);
-define <vscale x 1 x i1> @intrinsic_vmfeq_mask_vf_nxv1f32_f32(<vscale x 1 x i1> %0, <vscale x 1 x float> %1, float %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+define <vscale x 1 x i1> @intrinsic_vmfeq_mask_vf_nxv1f32_f32(<vscale x 1 x i1> %0, <vscale x 1 x float> %1, float %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv1f32_f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0
@@ -902,7 +904,7 @@ entry:
<vscale x 1 x float> %1,
float %2,
<vscale x 1 x i1> %3,
- i64 %4)
+ iXLen %4)
ret <vscale x 1 x i1> %a
}
@@ -910,9 +912,9 @@ entry:
declare <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2f32.f32(
<vscale x 2 x float>,
float,
- i64);
+ iXLen);
-define <vscale x 2 x i1> @intrinsic_vmfeq_vf_nxv2f32_f32(<vscale x 2 x float> %0, float %1, i64 %2) nounwind {
+define <vscale x 2 x i1> @intrinsic_vmfeq_vf_nxv2f32_f32(<vscale x 2 x float> %0, float %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmfeq_vf_nxv2f32_f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
@@ -922,7 +924,7 @@ entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2f32.f32(
<vscale x 2 x float> %0,
float %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 2 x i1> %a
}
@@ -932,9 +934,9 @@ declare <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2f32.f32(
<vscale x 2 x float>,
float,
<vscale x 2 x i1>,
- i64);
+ iXLen);
-define <vscale x 2 x i1> @intrinsic_vmfeq_mask_vf_nxv2f32_f32(<vscale x 2 x i1> %0, <vscale x 2 x float> %1, float %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+define <vscale x 2 x i1> @intrinsic_vmfeq_mask_vf_nxv2f32_f32(<vscale x 2 x i1> %0, <vscale x 2 x float> %1, float %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv2f32_f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0
@@ -949,7 +951,7 @@ entry:
<vscale x 2 x float> %1,
float %2,
<vscale x 2 x i1> %3,
- i64 %4)
+ iXLen %4)
ret <vscale x 2 x i1> %a
}
@@ -957,9 +959,9 @@ entry:
declare <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4f32.f32(
<vscale x 4 x float>,
float,
- i64);
+ iXLen);
-define <vscale x 4 x i1> @intrinsic_vmfeq_vf_nxv4f32_f32(<vscale x 4 x float> %0, float %1, i64 %2) nounwind {
+define <vscale x 4 x i1> @intrinsic_vmfeq_vf_nxv4f32_f32(<vscale x 4 x float> %0, float %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmfeq_vf_nxv4f32_f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
@@ -969,7 +971,7 @@ entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4f32.f32(
<vscale x 4 x float> %0,
float %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 4 x i1> %a
}
@@ -979,9 +981,9 @@ declare <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4f32.f32(
<vscale x 4 x float>,
float,
<vscale x 4 x i1>,
- i64);
+ iXLen);
-define <vscale x 4 x i1> @intrinsic_vmfeq_mask_vf_nxv4f32_f32(<vscale x 4 x i1> %0, <vscale x 4 x float> %1, float %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+define <vscale x 4 x i1> @intrinsic_vmfeq_mask_vf_nxv4f32_f32(<vscale x 4 x i1> %0, <vscale x 4 x float> %1, float %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv4f32_f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v11, v0
@@ -996,7 +998,7 @@ entry:
<vscale x 4 x float> %1,
float %2,
<vscale x 4 x i1> %3,
- i64 %4)
+ iXLen %4)
ret <vscale x 4 x i1> %a
}
@@ -1004,9 +1006,9 @@ entry:
declare <vscale x 8 x i1> @llvm.riscv.vmfeq.nxv8f32.f32(
<vscale x 8 x float>,
float,
- i64);
+ iXLen);
-define <vscale x 8 x i1> @intrinsic_vmfeq_vf_nxv8f32_f32(<vscale x 8 x float> %0, float %1, i64 %2) nounwind {
+define <vscale x 8 x i1> @intrinsic_vmfeq_vf_nxv8f32_f32(<vscale x 8 x float> %0, float %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmfeq_vf_nxv8f32_f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
@@ -1016,7 +1018,7 @@ entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmfeq.nxv8f32.f32(
<vscale x 8 x float> %0,
float %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 8 x i1> %a
}
@@ -1026,9 +1028,9 @@ declare <vscale x 8 x i1> @llvm.riscv.vmfeq.mask.nxv8f32.f32(
<vscale x 8 x float>,
float,
<vscale x 8 x i1>,
- i64);
+ iXLen);
-define <vscale x 8 x i1> @intrinsic_vmfeq_mask_vf_nxv8f32_f32(<vscale x 8 x i1> %0, <vscale x 8 x float> %1, float %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+define <vscale x 8 x i1> @intrinsic_vmfeq_mask_vf_nxv8f32_f32(<vscale x 8 x i1> %0, <vscale x 8 x float> %1, float %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv8f32_f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v13, v0
@@ -1043,7 +1045,7 @@ entry:
<vscale x 8 x float> %1,
float %2,
<vscale x 8 x i1> %3,
- i64 %4)
+ iXLen %4)
ret <vscale x 8 x i1> %a
}
@@ -1051,9 +1053,9 @@ entry:
declare <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1f64.f64(
<vscale x 1 x double>,
double,
- i64);
+ iXLen);
-define <vscale x 1 x i1> @intrinsic_vmfeq_vf_nxv1f64_f64(<vscale x 1 x double> %0, double %1, i64 %2) nounwind {
+define <vscale x 1 x i1> @intrinsic_vmfeq_vf_nxv1f64_f64(<vscale x 1 x double> %0, double %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmfeq_vf_nxv1f64_f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
@@ -1063,7 +1065,7 @@ entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1f64.f64(
<vscale x 1 x double> %0,
double %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 1 x i1> %a
}
@@ -1073,9 +1075,9 @@ declare <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1f64.f64(
<vscale x 1 x double>,
double,
<vscale x 1 x i1>,
- i64);
+ iXLen);
-define <vscale x 1 x i1> @intrinsic_vmfeq_mask_vf_nxv1f64_f64(<vscale x 1 x i1> %0, <vscale x 1 x double> %1, double %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+define <vscale x 1 x i1> @intrinsic_vmfeq_mask_vf_nxv1f64_f64(<vscale x 1 x i1> %0, <vscale x 1 x double> %1, double %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv1f64_f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0
@@ -1090,7 +1092,7 @@ entry:
<vscale x 1 x double> %1,
double %2,
<vscale x 1 x i1> %3,
- i64 %4)
+ iXLen %4)
ret <vscale x 1 x i1> %a
}
@@ -1098,9 +1100,9 @@ entry:
declare <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2f64.f64(
<vscale x 2 x double>,
double,
- i64);
+ iXLen);
-define <vscale x 2 x i1> @intrinsic_vmfeq_vf_nxv2f64_f64(<vscale x 2 x double> %0, double %1, i64 %2) nounwind {
+define <vscale x 2 x i1> @intrinsic_vmfeq_vf_nxv2f64_f64(<vscale x 2 x double> %0, double %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmfeq_vf_nxv2f64_f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
@@ -1110,7 +1112,7 @@ entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2f64.f64(
<vscale x 2 x double> %0,
double %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 2 x i1> %a
}
@@ -1120,9 +1122,9 @@ declare <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2f64.f64(
<vscale x 2 x double>,
double,
<vscale x 2 x i1>,
- i64);
+ iXLen);
-define <vscale x 2 x i1> @intrinsic_vmfeq_mask_vf_nxv2f64_f64(<vscale x 2 x i1> %0, <vscale x 2 x double> %1, double %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+define <vscale x 2 x i1> @intrinsic_vmfeq_mask_vf_nxv2f64_f64(<vscale x 2 x i1> %0, <vscale x 2 x double> %1, double %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv2f64_f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v11, v0
@@ -1137,7 +1139,7 @@ entry:
<vscale x 2 x double> %1,
double %2,
<vscale x 2 x i1> %3,
- i64 %4)
+ iXLen %4)
ret <vscale x 2 x i1> %a
}
@@ -1145,9 +1147,9 @@ entry:
declare <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4f64.f64(
<vscale x 4 x double>,
double,
- i64);
+ iXLen);
-define <vscale x 4 x i1> @intrinsic_vmfeq_vf_nxv4f64_f64(<vscale x 4 x double> %0, double %1, i64 %2) nounwind {
+define <vscale x 4 x i1> @intrinsic_vmfeq_vf_nxv4f64_f64(<vscale x 4 x double> %0, double %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmfeq_vf_nxv4f64_f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
@@ -1157,7 +1159,7 @@ entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4f64.f64(
<vscale x 4 x double> %0,
double %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 4 x i1> %a
}
@@ -1167,9 +1169,9 @@ declare <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4f64.f64(
<vscale x 4 x double>,
double,
<vscale x 4 x i1>,
- i64);
+ iXLen);
-define <vscale x 4 x i1> @intrinsic_vmfeq_mask_vf_nxv4f64_f64(<vscale x 4 x i1> %0, <vscale x 4 x double> %1, double %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+define <vscale x 4 x i1> @intrinsic_vmfeq_mask_vf_nxv4f64_f64(<vscale x 4 x i1> %0, <vscale x 4 x double> %1, double %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv4f64_f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v13, v0
@@ -1184,7 +1186,7 @@ entry:
<vscale x 4 x double> %1,
double %2,
<vscale x 4 x i1> %3,
- i64 %4)
+ iXLen %4)
ret <vscale x 4 x i1> %a
}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmfge-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vmfge-rv64.ll
deleted file mode 100644
index f1b29f7e30b21..0000000000000
--- a/llvm/test/CodeGen/RISCV/rvv/vmfge-rv64.ll
+++ /dev/null
@@ -1,1190 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv64 -mattr=+v,+d,+zfh -verify-machineinstrs \
-; RUN: -target-abi=lp64d < %s | FileCheck %s
-declare <vscale x 1 x i1> @llvm.riscv.vmfge.nxv1f16(
- <vscale x 1 x half>,
- <vscale x 1 x half>,
- i64);
-
-define <vscale x 1 x i1> @intrinsic_vmfge_vv_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmfge_vv_nxv1f16_nxv1f16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vmfle.vv v0, v9, v8
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i1> @llvm.riscv.vmfge.nxv1f16(
- <vscale x 1 x half> %0,
- <vscale x 1 x half> %1,
- i64 %2)
-
- ret <vscale x 1 x i1> %a
-}
-
-declare <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1f16(
- <vscale x 1 x i1>,
- <vscale x 1 x half>,
- <vscale x 1 x half>,
- <vscale x 1 x i1>,
- i64);
-
-define <vscale x 1 x i1> @intrinsic_vmfge_mask_vv_nxv1f16_nxv1f16(<vscale x 1 x i1> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x half> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmfge_mask_vv_nxv1f16_nxv1f16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vmfle.vv v8, v9, v8
-; CHECK-NEXT: vmv1r.v v11, v0
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmfle.vv v11, v10, v9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v11
-; CHECK-NEXT: ret
-entry:
- %mask = call <vscale x 1 x i1> @llvm.riscv.vmfge.nxv1f16(
- <vscale x 1 x half> %1,
- <vscale x 1 x half> %2,
- i64 %4)
- %a = call <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1f16(
- <vscale x 1 x i1> %0,
- <vscale x 1 x half> %2,
- <vscale x 1 x half> %3,
- <vscale x 1 x i1> %mask,
- i64 %4)
-
- ret <vscale x 1 x i1> %a
-}
-
-declare <vscale x 2 x i1> @llvm.riscv.vmfge.nxv2f16(
- <vscale x 2 x half>,
- <vscale x 2 x half>,
- i64);
-
-define <vscale x 2 x i1> @intrinsic_vmfge_vv_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmfge_vv_nxv2f16_nxv2f16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vmfle.vv v0, v9, v8
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i1> @llvm.riscv.vmfge.nxv2f16(
- <vscale x 2 x half> %0,
- <vscale x 2 x half> %1,
- i64 %2)
-
- ret <vscale x 2 x i1> %a
-}
-
-declare <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2f16(
- <vscale x 2 x i1>,
- <vscale x 2 x half>,
- <vscale x 2 x half>,
- <vscale x 2 x i1>,
- i64);
-
-define <vscale x 2 x i1> @intrinsic_vmfge_mask_vv_nxv2f16_nxv2f16(<vscale x 2 x i1> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, <vscale x 2 x half> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmfge_mask_vv_nxv2f16_nxv2f16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vmfle.vv v8, v9, v8
-; CHECK-NEXT: vmv1r.v v11, v0
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmfle.vv v11, v10, v9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v11
-; CHECK-NEXT: ret
-entry:
- %mask = call <vscale x 2 x i1> @llvm.riscv.vmfge.nxv2f16(
- <vscale x 2 x half> %1,
- <vscale x 2 x half> %2,
- i64 %4)
- %a = call <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2f16(
- <vscale x 2 x i1> %0,
- <vscale x 2 x half> %2,
- <vscale x 2 x half> %3,
- <vscale x 2 x i1> %mask,
- i64 %4)
-
- ret <vscale x 2 x i1> %a
-}
-
-declare <vscale x 4 x i1> @llvm.riscv.vmfge.nxv4f16(
- <vscale x 4 x half>,
- <vscale x 4 x half>,
- i64);
-
-define <vscale x 4 x i1> @intrinsic_vmfge_vv_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmfge_vv_nxv4f16_nxv4f16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vmfle.vv v0, v9, v8
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i1> @llvm.riscv.vmfge.nxv4f16(
- <vscale x 4 x half> %0,
- <vscale x 4 x half> %1,
- i64 %2)
-
- ret <vscale x 4 x i1> %a
-}
-
-declare <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4f16(
- <vscale x 4 x i1>,
- <vscale x 4 x half>,
- <vscale x 4 x half>,
- <vscale x 4 x i1>,
- i64);
-
-define <vscale x 4 x i1> @intrinsic_vmfge_mask_vv_nxv4f16_nxv4f16(<vscale x 4 x i1> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x half> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmfge_mask_vv_nxv4f16_nxv4f16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vmfle.vv v8, v9, v8
-; CHECK-NEXT: vmv1r.v v11, v0
-; CHECK-NEXT: vmv.v.v v0, v8
-; CHECK-NEXT: vmfle.vv v11, v10, v9, v0.t
-; CHECK-NEXT: vmv.v.v v0, v11
-; CHECK-NEXT: ret
-entry:
- %mask = call <vscale x 4 x i1> @llvm.riscv.vmfge.nxv4f16(
- <vscale x 4 x half> %1,
- <vscale x 4 x half> %2,
- i64 %4)
- %a = call <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4f16(
- <vscale x 4 x i1> %0,
- <vscale x 4 x half> %2,
- <vscale x 4 x half> %3,
- <vscale x 4 x i1> %mask,
- i64 %4)
-
- ret <vscale x 4 x i1> %a
-}
-
-declare <vscale x 8 x i1> @llvm.riscv.vmfge.nxv8f16(
- <vscale x 8 x half>,
- <vscale x 8 x half>,
- i64);
-
-define <vscale x 8 x i1> @intrinsic_vmfge_vv_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmfge_vv_nxv8f16_nxv8f16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vmfle.vv v0, v10, v8
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i1> @llvm.riscv.vmfge.nxv8f16(
- <vscale x 8 x half> %0,
- <vscale x 8 x half> %1,
- i64 %2)
-
- ret <vscale x 8 x i1> %a
-}
-
-declare <vscale x 8 x i1> @llvm.riscv.vmfge.mask.nxv8f16(
- <vscale x 8 x i1>,
- <vscale x 8 x half>,
- <vscale x 8 x half>,
- <vscale x 8 x i1>,
- i64);
-
-define <vscale x 8 x i1> @intrinsic_vmfge_mask_vv_nxv8f16_nxv8f16(<vscale x 8 x i1> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x half> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmfge_mask_vv_nxv8f16_nxv8f16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vmfle.vv v14, v10, v8
-; CHECK-NEXT: vmv1r.v v8, v0
-; CHECK-NEXT: vmv1r.v v0, v14
-; CHECK-NEXT: vmfle.vv v8, v12, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: ret
-entry:
- %mask = call <vscale x 8 x i1> @llvm.riscv.vmfge.nxv8f16(
- <vscale x 8 x half> %1,
- <vscale x 8 x half> %2,
- i64 %4)
- %a = call <vscale x 8 x i1> @llvm.riscv.vmfge.mask.nxv8f16(
- <vscale x 8 x i1> %0,
- <vscale x 8 x half> %2,
- <vscale x 8 x half> %3,
- <vscale x 8 x i1> %mask,
- i64 %4)
-
- ret <vscale x 8 x i1> %a
-}
-
-declare <vscale x 16 x i1> @llvm.riscv.vmfge.nxv16f16(
- <vscale x 16 x half>,
- <vscale x 16 x half>,
- i64);
-
-define <vscale x 16 x i1> @intrinsic_vmfge_vv_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmfge_vv_nxv16f16_nxv16f16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
-; CHECK-NEXT: vmfle.vv v0, v12, v8
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i1> @llvm.riscv.vmfge.nxv16f16(
- <vscale x 16 x half> %0,
- <vscale x 16 x half> %1,
- i64 %2)
-
- ret <vscale x 16 x i1> %a
-}
-
-declare <vscale x 16 x i1> @llvm.riscv.vmfge.mask.nxv16f16(
- <vscale x 16 x i1>,
- <vscale x 16 x half>,
- <vscale x 16 x half>,
- <vscale x 16 x i1>,
- i64);
-
-define <vscale x 16 x i1> @intrinsic_vmfge_mask_vv_nxv16f16_nxv16f16(<vscale x 16 x i1> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, <vscale x 16 x half> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmfge_mask_vv_nxv16f16_nxv16f16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
-; CHECK-NEXT: vmfle.vv v20, v12, v8
-; CHECK-NEXT: vmv1r.v v8, v0
-; CHECK-NEXT: vmv1r.v v0, v20
-; CHECK-NEXT: vmfle.vv v8, v16, v12, v0.t
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: ret
-entry:
- %mask = call <vscale x 16 x i1> @llvm.riscv.vmfge.nxv16f16(
- <vscale x 16 x half> %1,
- <vscale x 16 x half> %2,
- i64 %4)
- %a = call <vscale x 16 x i1> @llvm.riscv.vmfge.mask.nxv16f16(
- <vscale x 16 x i1> %0,
- <vscale x 16 x half> %2,
- <vscale x 16 x half> %3,
- <vscale x 16 x i1> %mask,
- i64 %4)
-
- ret <vscale x 16 x i1> %a
-}
-
-declare <vscale x 1 x i1> @llvm.riscv.vmfge.nxv1f32(
- <vscale x 1 x float>,
- <vscale x 1 x float>,
- i64);
-
-define <vscale x 1 x i1> @intrinsic_vmfge_vv_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmfge_vv_nxv1f32_nxv1f32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vmfle.vv v0, v9, v8
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i1> @llvm.riscv.vmfge.nxv1f32(
- <vscale x 1 x float> %0,
- <vscale x 1 x float> %1,
- i64 %2)
-
- ret <vscale x 1 x i1> %a
-}
-
-declare <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1f32(
- <vscale x 1 x i1>,
- <vscale x 1 x float>,
- <vscale x 1 x float>,
- <vscale x 1 x i1>,
- i64);
-
-define <vscale x 1 x i1> @intrinsic_vmfge_mask_vv_nxv1f32_nxv1f32(<vscale x 1 x i1> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, <vscale x 1 x float> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmfge_mask_vv_nxv1f32_nxv1f32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vmfle.vv v8, v9, v8
-; CHECK-NEXT: vmv1r.v v11, v0
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmfle.vv v11, v10, v9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v11
-; CHECK-NEXT: ret
-entry:
- %mask = call <vscale x 1 x i1> @llvm.riscv.vmfge.nxv1f32(
- <vscale x 1 x float> %1,
- <vscale x 1 x float> %2,
- i64 %4)
- %a = call <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1f32(
- <vscale x 1 x i1> %0,
- <vscale x 1 x float> %2,
- <vscale x 1 x float> %3,
- <vscale x 1 x i1> %mask,
- i64 %4)
-
- ret <vscale x 1 x i1> %a
-}
-
-declare <vscale x 2 x i1> @llvm.riscv.vmfge.nxv2f32(
- <vscale x 2 x float>,
- <vscale x 2 x float>,
- i64);
-
-define <vscale x 2 x i1> @intrinsic_vmfge_vv_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmfge_vv_nxv2f32_nxv2f32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vmfle.vv v0, v9, v8
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i1> @llvm.riscv.vmfge.nxv2f32(
- <vscale x 2 x float> %0,
- <vscale x 2 x float> %1,
- i64 %2)
-
- ret <vscale x 2 x i1> %a
-}
-
-declare <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2f32(
- <vscale x 2 x i1>,
- <vscale x 2 x float>,
- <vscale x 2 x float>,
- <vscale x 2 x i1>,
- i64);
-
-define <vscale x 2 x i1> @intrinsic_vmfge_mask_vv_nxv2f32_nxv2f32(<vscale x 2 x i1> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x float> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmfge_mask_vv_nxv2f32_nxv2f32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vmfle.vv v8, v9, v8
-; CHECK-NEXT: vmv1r.v v11, v0
-; CHECK-NEXT: vmv.v.v v0, v8
-; CHECK-NEXT: vmfle.vv v11, v10, v9, v0.t
-; CHECK-NEXT: vmv.v.v v0, v11
-; CHECK-NEXT: ret
-entry:
- %mask = call <vscale x 2 x i1> @llvm.riscv.vmfge.nxv2f32(
- <vscale x 2 x float> %1,
- <vscale x 2 x float> %2,
- i64 %4)
- %a = call <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2f32(
- <vscale x 2 x i1> %0,
- <vscale x 2 x float> %2,
- <vscale x 2 x float> %3,
- <vscale x 2 x i1> %mask,
- i64 %4)
-
- ret <vscale x 2 x i1> %a
-}
-
-declare <vscale x 4 x i1> @llvm.riscv.vmfge.nxv4f32(
- <vscale x 4 x float>,
- <vscale x 4 x float>,
- i64);
-
-define <vscale x 4 x i1> @intrinsic_vmfge_vv_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmfge_vv_nxv4f32_nxv4f32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vmfle.vv v0, v10, v8
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i1> @llvm.riscv.vmfge.nxv4f32(
- <vscale x 4 x float> %0,
- <vscale x 4 x float> %1,
- i64 %2)
-
- ret <vscale x 4 x i1> %a
-}
-
-declare <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4f32(
- <vscale x 4 x i1>,
- <vscale x 4 x float>,
- <vscale x 4 x float>,
- <vscale x 4 x i1>,
- i64);
-
-define <vscale x 4 x i1> @intrinsic_vmfge_mask_vv_nxv4f32_nxv4f32(<vscale x 4 x i1> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x float> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmfge_mask_vv_nxv4f32_nxv4f32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vmfle.vv v14, v10, v8
-; CHECK-NEXT: vmv1r.v v8, v0
-; CHECK-NEXT: vmv1r.v v0, v14
-; CHECK-NEXT: vmfle.vv v8, v12, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: ret
-entry:
- %mask = call <vscale x 4 x i1> @llvm.riscv.vmfge.nxv4f32(
- <vscale x 4 x float> %1,
- <vscale x 4 x float> %2,
- i64 %4)
- %a = call <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4f32(
- <vscale x 4 x i1> %0,
- <vscale x 4 x float> %2,
- <vscale x 4 x float> %3,
- <vscale x 4 x i1> %mask,
- i64 %4)
-
- ret <vscale x 4 x i1> %a
-}
-
-declare <vscale x 8 x i1> @llvm.riscv.vmfge.nxv8f32(
- <vscale x 8 x float>,
- <vscale x 8 x float>,
- i64);
-
-define <vscale x 8 x i1> @intrinsic_vmfge_vv_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmfge_vv_nxv8f32_nxv8f32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
-; CHECK-NEXT: vmfle.vv v0, v12, v8
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i1> @llvm.riscv.vmfge.nxv8f32(
- <vscale x 8 x float> %0,
- <vscale x 8 x float> %1,
- i64 %2)
-
- ret <vscale x 8 x i1> %a
-}
-
-declare <vscale x 8 x i1> @llvm.riscv.vmfge.mask.nxv8f32(
- <vscale x 8 x i1>,
- <vscale x 8 x float>,
- <vscale x 8 x float>,
- <vscale x 8 x i1>,
- i64);
-
-define <vscale x 8 x i1> @intrinsic_vmfge_mask_vv_nxv8f32_nxv8f32(<vscale x 8 x i1> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, <vscale x 8 x float> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmfge_mask_vv_nxv8f32_nxv8f32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
-; CHECK-NEXT: vmfle.vv v20, v12, v8
-; CHECK-NEXT: vmv1r.v v8, v0
-; CHECK-NEXT: vmv1r.v v0, v20
-; CHECK-NEXT: vmfle.vv v8, v16, v12, v0.t
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: ret
-entry:
- %mask = call <vscale x 8 x i1> @llvm.riscv.vmfge.nxv8f32(
- <vscale x 8 x float> %1,
- <vscale x 8 x float> %2,
- i64 %4)
- %a = call <vscale x 8 x i1> @llvm.riscv.vmfge.mask.nxv8f32(
- <vscale x 8 x i1> %0,
- <vscale x 8 x float> %2,
- <vscale x 8 x float> %3,
- <vscale x 8 x i1> %mask,
- i64 %4)
-
- ret <vscale x 8 x i1> %a
-}
-
-declare <vscale x 1 x i1> @llvm.riscv.vmfge.nxv1f64(
- <vscale x 1 x double>,
- <vscale x 1 x double>,
- i64);
-
-define <vscale x 1 x i1> @intrinsic_vmfge_vv_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmfge_vv_nxv1f64_nxv1f64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
-; CHECK-NEXT: vmfle.vv v0, v9, v8
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i1> @llvm.riscv.vmfge.nxv1f64(
- <vscale x 1 x double> %0,
- <vscale x 1 x double> %1,
- i64 %2)
-
- ret <vscale x 1 x i1> %a
-}
-
-declare <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1f64(
- <vscale x 1 x i1>,
- <vscale x 1 x double>,
- <vscale x 1 x double>,
- <vscale x 1 x i1>,
- i64);
-
-define <vscale x 1 x i1> @intrinsic_vmfge_mask_vv_nxv1f64_nxv1f64(<vscale x 1 x i1> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, <vscale x 1 x double> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmfge_mask_vv_nxv1f64_nxv1f64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
-; CHECK-NEXT: vmfle.vv v8, v9, v8
-; CHECK-NEXT: vmv1r.v v11, v0
-; CHECK-NEXT: vmv.v.v v0, v8
-; CHECK-NEXT: vmfle.vv v11, v10, v9, v0.t
-; CHECK-NEXT: vmv.v.v v0, v11
-; CHECK-NEXT: ret
-entry:
- %mask = call <vscale x 1 x i1> @llvm.riscv.vmfge.nxv1f64(
- <vscale x 1 x double> %1,
- <vscale x 1 x double> %2,
- i64 %4)
- %a = call <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1f64(
- <vscale x 1 x i1> %0,
- <vscale x 1 x double> %2,
- <vscale x 1 x double> %3,
- <vscale x 1 x i1> %mask,
- i64 %4)
-
- ret <vscale x 1 x i1> %a
-}
-
-declare <vscale x 2 x i1> @llvm.riscv.vmfge.nxv2f64(
- <vscale x 2 x double>,
- <vscale x 2 x double>,
- i64);
-
-define <vscale x 2 x i1> @intrinsic_vmfge_vv_nxv2f64_nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmfge_vv_nxv2f64_nxv2f64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
-; CHECK-NEXT: vmfle.vv v0, v10, v8
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i1> @llvm.riscv.vmfge.nxv2f64(
- <vscale x 2 x double> %0,
- <vscale x 2 x double> %1,
- i64 %2)
-
- ret <vscale x 2 x i1> %a
-}
-
-declare <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2f64(
- <vscale x 2 x i1>,
- <vscale x 2 x double>,
- <vscale x 2 x double>,
- <vscale x 2 x i1>,
- i64);
-
-define <vscale x 2 x i1> @intrinsic_vmfge_mask_vv_nxv2f64_nxv2f64(<vscale x 2 x i1> %0, <vscale x 2 x double> %1, <vscale x 2 x double> %2, <vscale x 2 x double> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmfge_mask_vv_nxv2f64_nxv2f64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
-; CHECK-NEXT: vmfle.vv v14, v10, v8
-; CHECK-NEXT: vmv1r.v v8, v0
-; CHECK-NEXT: vmv1r.v v0, v14
-; CHECK-NEXT: vmfle.vv v8, v12, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: ret
-entry:
- %mask = call <vscale x 2 x i1> @llvm.riscv.vmfge.nxv2f64(
- <vscale x 2 x double> %1,
- <vscale x 2 x double> %2,
- i64 %4)
- %a = call <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2f64(
- <vscale x 2 x i1> %0,
- <vscale x 2 x double> %2,
- <vscale x 2 x double> %3,
- <vscale x 2 x i1> %mask,
- i64 %4)
-
- ret <vscale x 2 x i1> %a
-}
-
-declare <vscale x 4 x i1> @llvm.riscv.vmfge.nxv4f64(
- <vscale x 4 x double>,
- <vscale x 4 x double>,
- i64);
-
-define <vscale x 4 x i1> @intrinsic_vmfge_vv_nxv4f64_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmfge_vv_nxv4f64_nxv4f64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
-; CHECK-NEXT: vmfle.vv v0, v12, v8
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i1> @llvm.riscv.vmfge.nxv4f64(
- <vscale x 4 x double> %0,
- <vscale x 4 x double> %1,
- i64 %2)
-
- ret <vscale x 4 x i1> %a
-}
-
-declare <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4f64(
- <vscale x 4 x i1>,
- <vscale x 4 x double>,
- <vscale x 4 x double>,
- <vscale x 4 x i1>,
- i64);
-
-define <vscale x 4 x i1> @intrinsic_vmfge_mask_vv_nxv4f64_nxv4f64(<vscale x 4 x i1> %0, <vscale x 4 x double> %1, <vscale x 4 x double> %2, <vscale x 4 x double> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmfge_mask_vv_nxv4f64_nxv4f64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
-; CHECK-NEXT: vmfle.vv v20, v12, v8
-; CHECK-NEXT: vmv1r.v v8, v0
-; CHECK-NEXT: vmv1r.v v0, v20
-; CHECK-NEXT: vmfle.vv v8, v16, v12, v0.t
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: ret
-entry:
- %mask = call <vscale x 4 x i1> @llvm.riscv.vmfge.nxv4f64(
- <vscale x 4 x double> %1,
- <vscale x 4 x double> %2,
- i64 %4)
- %a = call <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4f64(
- <vscale x 4 x i1> %0,
- <vscale x 4 x double> %2,
- <vscale x 4 x double> %3,
- <vscale x 4 x i1> %mask,
- i64 %4)
-
- ret <vscale x 4 x i1> %a
-}
-
-declare <vscale x 1 x i1> @llvm.riscv.vmfge.nxv1f16.f16(
- <vscale x 1 x half>,
- half,
- i64);
-
-define <vscale x 1 x i1> @intrinsic_vmfge_vf_nxv1f16_f16(<vscale x 1 x half> %0, half %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmfge_vf_nxv1f16_f16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vmfge.vf v0, v8, fa0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i1> @llvm.riscv.vmfge.nxv1f16.f16(
- <vscale x 1 x half> %0,
- half %1,
- i64 %2)
-
- ret <vscale x 1 x i1> %a
-}
-
-declare <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1f16.f16(
- <vscale x 1 x i1>,
- <vscale x 1 x half>,
- half,
- <vscale x 1 x i1>,
- i64);
-
-define <vscale x 1 x i1> @intrinsic_vmfge_mask_vf_nxv1f16_f16(<vscale x 1 x i1> %0, <vscale x 1 x half> %1, half %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv1f16_f16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v10, v0
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmfge.vf v10, v8, fa0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1f16.f16(
- <vscale x 1 x i1> %0,
- <vscale x 1 x half> %1,
- half %2,
- <vscale x 1 x i1> %3,
- i64 %4)
-
- ret <vscale x 1 x i1> %a
-}
-
-declare <vscale x 2 x i1> @llvm.riscv.vmfge.nxv2f16.f16(
- <vscale x 2 x half>,
- half,
- i64);
-
-define <vscale x 2 x i1> @intrinsic_vmfge_vf_nxv2f16_f16(<vscale x 2 x half> %0, half %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmfge_vf_nxv2f16_f16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vmfge.vf v0, v8, fa0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i1> @llvm.riscv.vmfge.nxv2f16.f16(
- <vscale x 2 x half> %0,
- half %1,
- i64 %2)
-
- ret <vscale x 2 x i1> %a
-}
-
-declare <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2f16.f16(
- <vscale x 2 x i1>,
- <vscale x 2 x half>,
- half,
- <vscale x 2 x i1>,
- i64);
-
-define <vscale x 2 x i1> @intrinsic_vmfge_mask_vf_nxv2f16_f16(<vscale x 2 x i1> %0, <vscale x 2 x half> %1, half %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv2f16_f16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v10, v0
-; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmfge.vf v10, v8, fa0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2f16.f16(
- <vscale x 2 x i1> %0,
- <vscale x 2 x half> %1,
- half %2,
- <vscale x 2 x i1> %3,
- i64 %4)
-
- ret <vscale x 2 x i1> %a
-}
-
-declare <vscale x 4 x i1> @llvm.riscv.vmfge.nxv4f16.f16(
- <vscale x 4 x half>,
- half,
- i64);
-
-define <vscale x 4 x i1> @intrinsic_vmfge_vf_nxv4f16_f16(<vscale x 4 x half> %0, half %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmfge_vf_nxv4f16_f16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vmfge.vf v0, v8, fa0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i1> @llvm.riscv.vmfge.nxv4f16.f16(
- <vscale x 4 x half> %0,
- half %1,
- i64 %2)
-
- ret <vscale x 4 x i1> %a
-}
-
-declare <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4f16.f16(
- <vscale x 4 x i1>,
- <vscale x 4 x half>,
- half,
- <vscale x 4 x i1>,
- i64);
-
-define <vscale x 4 x i1> @intrinsic_vmfge_mask_vf_nxv4f16_f16(<vscale x 4 x i1> %0, <vscale x 4 x half> %1, half %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv4f16_f16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v10, v0
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmfge.vf v10, v8, fa0, v0.t
-; CHECK-NEXT: vmv.v.v v0, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4f16.f16(
- <vscale x 4 x i1> %0,
- <vscale x 4 x half> %1,
- half %2,
- <vscale x 4 x i1> %3,
- i64 %4)
-
- ret <vscale x 4 x i1> %a
-}
-
-declare <vscale x 8 x i1> @llvm.riscv.vmfge.nxv8f16.f16(
- <vscale x 8 x half>,
- half,
- i64);
-
-define <vscale x 8 x i1> @intrinsic_vmfge_vf_nxv8f16_f16(<vscale x 8 x half> %0, half %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmfge_vf_nxv8f16_f16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vmfge.vf v0, v8, fa0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i1> @llvm.riscv.vmfge.nxv8f16.f16(
- <vscale x 8 x half> %0,
- half %1,
- i64 %2)
-
- ret <vscale x 8 x i1> %a
-}
-
-declare <vscale x 8 x i1> @llvm.riscv.vmfge.mask.nxv8f16.f16(
- <vscale x 8 x i1>,
- <vscale x 8 x half>,
- half,
- <vscale x 8 x i1>,
- i64);
-
-define <vscale x 8 x i1> @intrinsic_vmfge_mask_vf_nxv8f16_f16(<vscale x 8 x i1> %0, <vscale x 8 x half> %1, half %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv8f16_f16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v11, v0
-; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmfge.vf v11, v8, fa0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v11
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i1> @llvm.riscv.vmfge.mask.nxv8f16.f16(
- <vscale x 8 x i1> %0,
- <vscale x 8 x half> %1,
- half %2,
- <vscale x 8 x i1> %3,
- i64 %4)
-
- ret <vscale x 8 x i1> %a
-}
-
-declare <vscale x 16 x i1> @llvm.riscv.vmfge.nxv16f16.f16(
- <vscale x 16 x half>,
- half,
- i64);
-
-define <vscale x 16 x i1> @intrinsic_vmfge_vf_nxv16f16_f16(<vscale x 16 x half> %0, half %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmfge_vf_nxv16f16_f16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
-; CHECK-NEXT: vmfge.vf v0, v8, fa0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i1> @llvm.riscv.vmfge.nxv16f16.f16(
- <vscale x 16 x half> %0,
- half %1,
- i64 %2)
-
- ret <vscale x 16 x i1> %a
-}
-
-declare <vscale x 16 x i1> @llvm.riscv.vmfge.mask.nxv16f16.f16(
- <vscale x 16 x i1>,
- <vscale x 16 x half>,
- half,
- <vscale x 16 x i1>,
- i64);
-
-define <vscale x 16 x i1> @intrinsic_vmfge_mask_vf_nxv16f16_f16(<vscale x 16 x i1> %0, <vscale x 16 x half> %1, half %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv16f16_f16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v13, v0
-; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
-; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmfge.vf v13, v8, fa0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v13
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i1> @llvm.riscv.vmfge.mask.nxv16f16.f16(
- <vscale x 16 x i1> %0,
- <vscale x 16 x half> %1,
- half %2,
- <vscale x 16 x i1> %3,
- i64 %4)
-
- ret <vscale x 16 x i1> %a
-}
-
-declare <vscale x 1 x i1> @llvm.riscv.vmfge.nxv1f32.f32(
- <vscale x 1 x float>,
- float,
- i64);
-
-define <vscale x 1 x i1> @intrinsic_vmfge_vf_nxv1f32_f32(<vscale x 1 x float> %0, float %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmfge_vf_nxv1f32_f32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vmfge.vf v0, v8, fa0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i1> @llvm.riscv.vmfge.nxv1f32.f32(
- <vscale x 1 x float> %0,
- float %1,
- i64 %2)
-
- ret <vscale x 1 x i1> %a
-}
-
-declare <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1f32.f32(
- <vscale x 1 x i1>,
- <vscale x 1 x float>,
- float,
- <vscale x 1 x i1>,
- i64);
-
-define <vscale x 1 x i1> @intrinsic_vmfge_mask_vf_nxv1f32_f32(<vscale x 1 x i1> %0, <vscale x 1 x float> %1, float %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv1f32_f32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v10, v0
-; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmfge.vf v10, v8, fa0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1f32.f32(
- <vscale x 1 x i1> %0,
- <vscale x 1 x float> %1,
- float %2,
- <vscale x 1 x i1> %3,
- i64 %4)
-
- ret <vscale x 1 x i1> %a
-}
-
-declare <vscale x 2 x i1> @llvm.riscv.vmfge.nxv2f32.f32(
- <vscale x 2 x float>,
- float,
- i64);
-
-define <vscale x 2 x i1> @intrinsic_vmfge_vf_nxv2f32_f32(<vscale x 2 x float> %0, float %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmfge_vf_nxv2f32_f32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vmfge.vf v0, v8, fa0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i1> @llvm.riscv.vmfge.nxv2f32.f32(
- <vscale x 2 x float> %0,
- float %1,
- i64 %2)
-
- ret <vscale x 2 x i1> %a
-}
-
-declare <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2f32.f32(
- <vscale x 2 x i1>,
- <vscale x 2 x float>,
- float,
- <vscale x 2 x i1>,
- i64);
-
-define <vscale x 2 x i1> @intrinsic_vmfge_mask_vf_nxv2f32_f32(<vscale x 2 x i1> %0, <vscale x 2 x float> %1, float %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv2f32_f32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v10, v0
-; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmfge.vf v10, v8, fa0, v0.t
-; CHECK-NEXT: vmv.v.v v0, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2f32.f32(
- <vscale x 2 x i1> %0,
- <vscale x 2 x float> %1,
- float %2,
- <vscale x 2 x i1> %3,
- i64 %4)
-
- ret <vscale x 2 x i1> %a
-}
-
-declare <vscale x 4 x i1> @llvm.riscv.vmfge.nxv4f32.f32(
- <vscale x 4 x float>,
- float,
- i64);
-
-define <vscale x 4 x i1> @intrinsic_vmfge_vf_nxv4f32_f32(<vscale x 4 x float> %0, float %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmfge_vf_nxv4f32_f32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vmfge.vf v0, v8, fa0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i1> @llvm.riscv.vmfge.nxv4f32.f32(
- <vscale x 4 x float> %0,
- float %1,
- i64 %2)
-
- ret <vscale x 4 x i1> %a
-}
-
-declare <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4f32.f32(
- <vscale x 4 x i1>,
- <vscale x 4 x float>,
- float,
- <vscale x 4 x i1>,
- i64);
-
-define <vscale x 4 x i1> @intrinsic_vmfge_mask_vf_nxv4f32_f32(<vscale x 4 x i1> %0, <vscale x 4 x float> %1, float %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv4f32_f32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v11, v0
-; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmfge.vf v11, v8, fa0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v11
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4f32.f32(
- <vscale x 4 x i1> %0,
- <vscale x 4 x float> %1,
- float %2,
- <vscale x 4 x i1> %3,
- i64 %4)
-
- ret <vscale x 4 x i1> %a
-}
-
-declare <vscale x 8 x i1> @llvm.riscv.vmfge.nxv8f32.f32(
- <vscale x 8 x float>,
- float,
- i64);
-
-define <vscale x 8 x i1> @intrinsic_vmfge_vf_nxv8f32_f32(<vscale x 8 x float> %0, float %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmfge_vf_nxv8f32_f32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
-; CHECK-NEXT: vmfge.vf v0, v8, fa0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i1> @llvm.riscv.vmfge.nxv8f32.f32(
- <vscale x 8 x float> %0,
- float %1,
- i64 %2)
-
- ret <vscale x 8 x i1> %a
-}
-
-declare <vscale x 8 x i1> @llvm.riscv.vmfge.mask.nxv8f32.f32(
- <vscale x 8 x i1>,
- <vscale x 8 x float>,
- float,
- <vscale x 8 x i1>,
- i64);
-
-define <vscale x 8 x i1> @intrinsic_vmfge_mask_vf_nxv8f32_f32(<vscale x 8 x i1> %0, <vscale x 8 x float> %1, float %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv8f32_f32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v13, v0
-; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
-; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmfge.vf v13, v8, fa0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v13
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i1> @llvm.riscv.vmfge.mask.nxv8f32.f32(
- <vscale x 8 x i1> %0,
- <vscale x 8 x float> %1,
- float %2,
- <vscale x 8 x i1> %3,
- i64 %4)
-
- ret <vscale x 8 x i1> %a
-}
-
-declare <vscale x 1 x i1> @llvm.riscv.vmfge.nxv1f64.f64(
- <vscale x 1 x double>,
- double,
- i64);
-
-define <vscale x 1 x i1> @intrinsic_vmfge_vf_nxv1f64_f64(<vscale x 1 x double> %0, double %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmfge_vf_nxv1f64_f64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
-; CHECK-NEXT: vmfge.vf v0, v8, fa0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i1> @llvm.riscv.vmfge.nxv1f64.f64(
- <vscale x 1 x double> %0,
- double %1,
- i64 %2)
-
- ret <vscale x 1 x i1> %a
-}
-
-declare <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1f64.f64(
- <vscale x 1 x i1>,
- <vscale x 1 x double>,
- double,
- <vscale x 1 x i1>,
- i64);
-
-define <vscale x 1 x i1> @intrinsic_vmfge_mask_vf_nxv1f64_f64(<vscale x 1 x i1> %0, <vscale x 1 x double> %1, double %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv1f64_f64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v10, v0
-; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
-; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmfge.vf v10, v8, fa0, v0.t
-; CHECK-NEXT: vmv.v.v v0, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1f64.f64(
- <vscale x 1 x i1> %0,
- <vscale x 1 x double> %1,
- double %2,
- <vscale x 1 x i1> %3,
- i64 %4)
-
- ret <vscale x 1 x i1> %a
-}
-
-declare <vscale x 2 x i1> @llvm.riscv.vmfge.nxv2f64.f64(
- <vscale x 2 x double>,
- double,
- i64);
-
-define <vscale x 2 x i1> @intrinsic_vmfge_vf_nxv2f64_f64(<vscale x 2 x double> %0, double %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmfge_vf_nxv2f64_f64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
-; CHECK-NEXT: vmfge.vf v0, v8, fa0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i1> @llvm.riscv.vmfge.nxv2f64.f64(
- <vscale x 2 x double> %0,
- double %1,
- i64 %2)
-
- ret <vscale x 2 x i1> %a
-}
-
-declare <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2f64.f64(
- <vscale x 2 x i1>,
- <vscale x 2 x double>,
- double,
- <vscale x 2 x i1>,
- i64);
-
-define <vscale x 2 x i1> @intrinsic_vmfge_mask_vf_nxv2f64_f64(<vscale x 2 x i1> %0, <vscale x 2 x double> %1, double %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv2f64_f64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v11, v0
-; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
-; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmfge.vf v11, v8, fa0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v11
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2f64.f64(
- <vscale x 2 x i1> %0,
- <vscale x 2 x double> %1,
- double %2,
- <vscale x 2 x i1> %3,
- i64 %4)
-
- ret <vscale x 2 x i1> %a
-}
-
-declare <vscale x 4 x i1> @llvm.riscv.vmfge.nxv4f64.f64(
- <vscale x 4 x double>,
- double,
- i64);
-
-define <vscale x 4 x i1> @intrinsic_vmfge_vf_nxv4f64_f64(<vscale x 4 x double> %0, double %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmfge_vf_nxv4f64_f64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
-; CHECK-NEXT: vmfge.vf v0, v8, fa0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i1> @llvm.riscv.vmfge.nxv4f64.f64(
- <vscale x 4 x double> %0,
- double %1,
- i64 %2)
-
- ret <vscale x 4 x i1> %a
-}
-
-declare <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4f64.f64(
- <vscale x 4 x i1>,
- <vscale x 4 x double>,
- double,
- <vscale x 4 x i1>,
- i64);
-
-define <vscale x 4 x i1> @intrinsic_vmfge_mask_vf_nxv4f64_f64(<vscale x 4 x i1> %0, <vscale x 4 x double> %1, double %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv4f64_f64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v13, v0
-; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
-; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmfge.vf v13, v8, fa0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v13
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4f64.f64(
- <vscale x 4 x i1> %0,
- <vscale x 4 x double> %1,
- double %2,
- <vscale x 4 x i1> %3,
- i64 %4)
-
- ret <vscale x 4 x i1> %a
-}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmfge-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmfge.ll
similarity index 88%
rename from llvm/test/CodeGen/RISCV/rvv/vmfge-rv32.ll
rename to llvm/test/CodeGen/RISCV/rvv/vmfge.ll
index 8a74567808f62..e8b4ba7b10c27 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vmfge-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vmfge.ll
@@ -1,12 +1,14 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -mattr=+v,+d,+zfh -verify-machineinstrs \
-; RUN: -target-abi=ilp32d < %s | FileCheck %s
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh \
+; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh \
+; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s
declare <vscale x 1 x i1> @llvm.riscv.vmfge.nxv1f16(
<vscale x 1 x half>,
<vscale x 1 x half>,
- i32);
+ iXLen);
-define <vscale x 1 x i1> @intrinsic_vmfge_vv_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i32 %2) nounwind {
+define <vscale x 1 x i1> @intrinsic_vmfge_vv_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmfge_vv_nxv1f16_nxv1f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
@@ -16,7 +18,7 @@ entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmfge.nxv1f16(
<vscale x 1 x half> %0,
<vscale x 1 x half> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 1 x i1> %a
}
@@ -26,9 +28,9 @@ declare <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1f16(
<vscale x 1 x half>,
<vscale x 1 x half>,
<vscale x 1 x i1>,
- i32);
+ iXLen);
-define <vscale x 1 x i1> @intrinsic_vmfge_mask_vv_nxv1f16_nxv1f16(<vscale x 1 x i1> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x half> %3, i32 %4) nounwind {
+define <vscale x 1 x i1> @intrinsic_vmfge_mask_vv_nxv1f16_nxv1f16(<vscale x 1 x i1> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x half> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfge_mask_vv_nxv1f16_nxv1f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
@@ -42,13 +44,13 @@ entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmfge.nxv1f16(
<vscale x 1 x half> %1,
<vscale x 1 x half> %2,
- i32 %4)
+ iXLen %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1f16(
<vscale x 1 x i1> %0,
<vscale x 1 x half> %2,
<vscale x 1 x half> %3,
<vscale x 1 x i1> %mask,
- i32 %4)
+ iXLen %4)
ret <vscale x 1 x i1> %a
}
@@ -56,9 +58,9 @@ entry:
declare <vscale x 2 x i1> @llvm.riscv.vmfge.nxv2f16(
<vscale x 2 x half>,
<vscale x 2 x half>,
- i32);
+ iXLen);
-define <vscale x 2 x i1> @intrinsic_vmfge_vv_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i32 %2) nounwind {
+define <vscale x 2 x i1> @intrinsic_vmfge_vv_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmfge_vv_nxv2f16_nxv2f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
@@ -68,7 +70,7 @@ entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmfge.nxv2f16(
<vscale x 2 x half> %0,
<vscale x 2 x half> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 2 x i1> %a
}
@@ -78,9 +80,9 @@ declare <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2f16(
<vscale x 2 x half>,
<vscale x 2 x half>,
<vscale x 2 x i1>,
- i32);
+ iXLen);
-define <vscale x 2 x i1> @intrinsic_vmfge_mask_vv_nxv2f16_nxv2f16(<vscale x 2 x i1> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, <vscale x 2 x half> %3, i32 %4) nounwind {
+define <vscale x 2 x i1> @intrinsic_vmfge_mask_vv_nxv2f16_nxv2f16(<vscale x 2 x i1> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, <vscale x 2 x half> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfge_mask_vv_nxv2f16_nxv2f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
@@ -94,13 +96,13 @@ entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmfge.nxv2f16(
<vscale x 2 x half> %1,
<vscale x 2 x half> %2,
- i32 %4)
+ iXLen %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2f16(
<vscale x 2 x i1> %0,
<vscale x 2 x half> %2,
<vscale x 2 x half> %3,
<vscale x 2 x i1> %mask,
- i32 %4)
+ iXLen %4)
ret <vscale x 2 x i1> %a
}
@@ -108,9 +110,9 @@ entry:
declare <vscale x 4 x i1> @llvm.riscv.vmfge.nxv4f16(
<vscale x 4 x half>,
<vscale x 4 x half>,
- i32);
+ iXLen);
-define <vscale x 4 x i1> @intrinsic_vmfge_vv_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i32 %2) nounwind {
+define <vscale x 4 x i1> @intrinsic_vmfge_vv_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmfge_vv_nxv4f16_nxv4f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
@@ -120,7 +122,7 @@ entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmfge.nxv4f16(
<vscale x 4 x half> %0,
<vscale x 4 x half> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 4 x i1> %a
}
@@ -130,9 +132,9 @@ declare <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4f16(
<vscale x 4 x half>,
<vscale x 4 x half>,
<vscale x 4 x i1>,
- i32);
+ iXLen);
-define <vscale x 4 x i1> @intrinsic_vmfge_mask_vv_nxv4f16_nxv4f16(<vscale x 4 x i1> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x half> %3, i32 %4) nounwind {
+define <vscale x 4 x i1> @intrinsic_vmfge_mask_vv_nxv4f16_nxv4f16(<vscale x 4 x i1> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x half> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfge_mask_vv_nxv4f16_nxv4f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
@@ -146,13 +148,13 @@ entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmfge.nxv4f16(
<vscale x 4 x half> %1,
<vscale x 4 x half> %2,
- i32 %4)
+ iXLen %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4f16(
<vscale x 4 x i1> %0,
<vscale x 4 x half> %2,
<vscale x 4 x half> %3,
<vscale x 4 x i1> %mask,
- i32 %4)
+ iXLen %4)
ret <vscale x 4 x i1> %a
}
@@ -160,9 +162,9 @@ entry:
declare <vscale x 8 x i1> @llvm.riscv.vmfge.nxv8f16(
<vscale x 8 x half>,
<vscale x 8 x half>,
- i32);
+ iXLen);
-define <vscale x 8 x i1> @intrinsic_vmfge_vv_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i32 %2) nounwind {
+define <vscale x 8 x i1> @intrinsic_vmfge_vv_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmfge_vv_nxv8f16_nxv8f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
@@ -172,7 +174,7 @@ entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmfge.nxv8f16(
<vscale x 8 x half> %0,
<vscale x 8 x half> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 8 x i1> %a
}
@@ -182,9 +184,9 @@ declare <vscale x 8 x i1> @llvm.riscv.vmfge.mask.nxv8f16(
<vscale x 8 x half>,
<vscale x 8 x half>,
<vscale x 8 x i1>,
- i32);
+ iXLen);
-define <vscale x 8 x i1> @intrinsic_vmfge_mask_vv_nxv8f16_nxv8f16(<vscale x 8 x i1> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x half> %3, i32 %4) nounwind {
+define <vscale x 8 x i1> @intrinsic_vmfge_mask_vv_nxv8f16_nxv8f16(<vscale x 8 x i1> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x half> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfge_mask_vv_nxv8f16_nxv8f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
@@ -198,13 +200,13 @@ entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmfge.nxv8f16(
<vscale x 8 x half> %1,
<vscale x 8 x half> %2,
- i32 %4)
+ iXLen %4)
%a = call <vscale x 8 x i1> @llvm.riscv.vmfge.mask.nxv8f16(
<vscale x 8 x i1> %0,
<vscale x 8 x half> %2,
<vscale x 8 x half> %3,
<vscale x 8 x i1> %mask,
- i32 %4)
+ iXLen %4)
ret <vscale x 8 x i1> %a
}
@@ -212,9 +214,9 @@ entry:
declare <vscale x 16 x i1> @llvm.riscv.vmfge.nxv16f16(
<vscale x 16 x half>,
<vscale x 16 x half>,
- i32);
+ iXLen);
-define <vscale x 16 x i1> @intrinsic_vmfge_vv_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i32 %2) nounwind {
+define <vscale x 16 x i1> @intrinsic_vmfge_vv_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmfge_vv_nxv16f16_nxv16f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
@@ -224,7 +226,7 @@ entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmfge.nxv16f16(
<vscale x 16 x half> %0,
<vscale x 16 x half> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 16 x i1> %a
}
@@ -234,9 +236,9 @@ declare <vscale x 16 x i1> @llvm.riscv.vmfge.mask.nxv16f16(
<vscale x 16 x half>,
<vscale x 16 x half>,
<vscale x 16 x i1>,
- i32);
+ iXLen);
-define <vscale x 16 x i1> @intrinsic_vmfge_mask_vv_nxv16f16_nxv16f16(<vscale x 16 x i1> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, <vscale x 16 x half> %3, i32 %4) nounwind {
+define <vscale x 16 x i1> @intrinsic_vmfge_mask_vv_nxv16f16_nxv16f16(<vscale x 16 x i1> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, <vscale x 16 x half> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfge_mask_vv_nxv16f16_nxv16f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
@@ -250,13 +252,13 @@ entry:
%mask = call <vscale x 16 x i1> @llvm.riscv.vmfge.nxv16f16(
<vscale x 16 x half> %1,
<vscale x 16 x half> %2,
- i32 %4)
+ iXLen %4)
%a = call <vscale x 16 x i1> @llvm.riscv.vmfge.mask.nxv16f16(
<vscale x 16 x i1> %0,
<vscale x 16 x half> %2,
<vscale x 16 x half> %3,
<vscale x 16 x i1> %mask,
- i32 %4)
+ iXLen %4)
ret <vscale x 16 x i1> %a
}
@@ -264,9 +266,9 @@ entry:
declare <vscale x 1 x i1> @llvm.riscv.vmfge.nxv1f32(
<vscale x 1 x float>,
<vscale x 1 x float>,
- i32);
+ iXLen);
-define <vscale x 1 x i1> @intrinsic_vmfge_vv_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, i32 %2) nounwind {
+define <vscale x 1 x i1> @intrinsic_vmfge_vv_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmfge_vv_nxv1f32_nxv1f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
@@ -276,7 +278,7 @@ entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmfge.nxv1f32(
<vscale x 1 x float> %0,
<vscale x 1 x float> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 1 x i1> %a
}
@@ -286,9 +288,9 @@ declare <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1f32(
<vscale x 1 x float>,
<vscale x 1 x float>,
<vscale x 1 x i1>,
- i32);
+ iXLen);
-define <vscale x 1 x i1> @intrinsic_vmfge_mask_vv_nxv1f32_nxv1f32(<vscale x 1 x i1> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, <vscale x 1 x float> %3, i32 %4) nounwind {
+define <vscale x 1 x i1> @intrinsic_vmfge_mask_vv_nxv1f32_nxv1f32(<vscale x 1 x i1> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, <vscale x 1 x float> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfge_mask_vv_nxv1f32_nxv1f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
@@ -302,13 +304,13 @@ entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmfge.nxv1f32(
<vscale x 1 x float> %1,
<vscale x 1 x float> %2,
- i32 %4)
+ iXLen %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1f32(
<vscale x 1 x i1> %0,
<vscale x 1 x float> %2,
<vscale x 1 x float> %3,
<vscale x 1 x i1> %mask,
- i32 %4)
+ iXLen %4)
ret <vscale x 1 x i1> %a
}
@@ -316,9 +318,9 @@ entry:
declare <vscale x 2 x i1> @llvm.riscv.vmfge.nxv2f32(
<vscale x 2 x float>,
<vscale x 2 x float>,
- i32);
+ iXLen);
-define <vscale x 2 x i1> @intrinsic_vmfge_vv_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, i32 %2) nounwind {
+define <vscale x 2 x i1> @intrinsic_vmfge_vv_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmfge_vv_nxv2f32_nxv2f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
@@ -328,7 +330,7 @@ entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmfge.nxv2f32(
<vscale x 2 x float> %0,
<vscale x 2 x float> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 2 x i1> %a
}
@@ -338,9 +340,9 @@ declare <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2f32(
<vscale x 2 x float>,
<vscale x 2 x float>,
<vscale x 2 x i1>,
- i32);
+ iXLen);
-define <vscale x 2 x i1> @intrinsic_vmfge_mask_vv_nxv2f32_nxv2f32(<vscale x 2 x i1> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x float> %3, i32 %4) nounwind {
+define <vscale x 2 x i1> @intrinsic_vmfge_mask_vv_nxv2f32_nxv2f32(<vscale x 2 x i1> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x float> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfge_mask_vv_nxv2f32_nxv2f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
@@ -354,13 +356,13 @@ entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmfge.nxv2f32(
<vscale x 2 x float> %1,
<vscale x 2 x float> %2,
- i32 %4)
+ iXLen %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2f32(
<vscale x 2 x i1> %0,
<vscale x 2 x float> %2,
<vscale x 2 x float> %3,
<vscale x 2 x i1> %mask,
- i32 %4)
+ iXLen %4)
ret <vscale x 2 x i1> %a
}
@@ -368,9 +370,9 @@ entry:
declare <vscale x 4 x i1> @llvm.riscv.vmfge.nxv4f32(
<vscale x 4 x float>,
<vscale x 4 x float>,
- i32);
+ iXLen);
-define <vscale x 4 x i1> @intrinsic_vmfge_vv_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, i32 %2) nounwind {
+define <vscale x 4 x i1> @intrinsic_vmfge_vv_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmfge_vv_nxv4f32_nxv4f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
@@ -380,7 +382,7 @@ entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmfge.nxv4f32(
<vscale x 4 x float> %0,
<vscale x 4 x float> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 4 x i1> %a
}
@@ -390,9 +392,9 @@ declare <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4f32(
<vscale x 4 x float>,
<vscale x 4 x float>,
<vscale x 4 x i1>,
- i32);
+ iXLen);
-define <vscale x 4 x i1> @intrinsic_vmfge_mask_vv_nxv4f32_nxv4f32(<vscale x 4 x i1> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x float> %3, i32 %4) nounwind {
+define <vscale x 4 x i1> @intrinsic_vmfge_mask_vv_nxv4f32_nxv4f32(<vscale x 4 x i1> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x float> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfge_mask_vv_nxv4f32_nxv4f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
@@ -406,13 +408,13 @@ entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmfge.nxv4f32(
<vscale x 4 x float> %1,
<vscale x 4 x float> %2,
- i32 %4)
+ iXLen %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4f32(
<vscale x 4 x i1> %0,
<vscale x 4 x float> %2,
<vscale x 4 x float> %3,
<vscale x 4 x i1> %mask,
- i32 %4)
+ iXLen %4)
ret <vscale x 4 x i1> %a
}
@@ -420,9 +422,9 @@ entry:
declare <vscale x 8 x i1> @llvm.riscv.vmfge.nxv8f32(
<vscale x 8 x float>,
<vscale x 8 x float>,
- i32);
+ iXLen);
-define <vscale x 8 x i1> @intrinsic_vmfge_vv_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, i32 %2) nounwind {
+define <vscale x 8 x i1> @intrinsic_vmfge_vv_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmfge_vv_nxv8f32_nxv8f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
@@ -432,7 +434,7 @@ entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmfge.nxv8f32(
<vscale x 8 x float> %0,
<vscale x 8 x float> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 8 x i1> %a
}
@@ -442,9 +444,9 @@ declare <vscale x 8 x i1> @llvm.riscv.vmfge.mask.nxv8f32(
<vscale x 8 x float>,
<vscale x 8 x float>,
<vscale x 8 x i1>,
- i32);
+ iXLen);
-define <vscale x 8 x i1> @intrinsic_vmfge_mask_vv_nxv8f32_nxv8f32(<vscale x 8 x i1> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, <vscale x 8 x float> %3, i32 %4) nounwind {
+define <vscale x 8 x i1> @intrinsic_vmfge_mask_vv_nxv8f32_nxv8f32(<vscale x 8 x i1> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, <vscale x 8 x float> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfge_mask_vv_nxv8f32_nxv8f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
@@ -458,13 +460,13 @@ entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmfge.nxv8f32(
<vscale x 8 x float> %1,
<vscale x 8 x float> %2,
- i32 %4)
+ iXLen %4)
%a = call <vscale x 8 x i1> @llvm.riscv.vmfge.mask.nxv8f32(
<vscale x 8 x i1> %0,
<vscale x 8 x float> %2,
<vscale x 8 x float> %3,
<vscale x 8 x i1> %mask,
- i32 %4)
+ iXLen %4)
ret <vscale x 8 x i1> %a
}
@@ -472,9 +474,9 @@ entry:
declare <vscale x 1 x i1> @llvm.riscv.vmfge.nxv1f64(
<vscale x 1 x double>,
<vscale x 1 x double>,
- i32);
+ iXLen);
-define <vscale x 1 x i1> @intrinsic_vmfge_vv_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, i32 %2) nounwind {
+define <vscale x 1 x i1> @intrinsic_vmfge_vv_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmfge_vv_nxv1f64_nxv1f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
@@ -484,7 +486,7 @@ entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmfge.nxv1f64(
<vscale x 1 x double> %0,
<vscale x 1 x double> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 1 x i1> %a
}
@@ -494,9 +496,9 @@ declare <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1f64(
<vscale x 1 x double>,
<vscale x 1 x double>,
<vscale x 1 x i1>,
- i32);
+ iXLen);
-define <vscale x 1 x i1> @intrinsic_vmfge_mask_vv_nxv1f64_nxv1f64(<vscale x 1 x i1> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, <vscale x 1 x double> %3, i32 %4) nounwind {
+define <vscale x 1 x i1> @intrinsic_vmfge_mask_vv_nxv1f64_nxv1f64(<vscale x 1 x i1> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, <vscale x 1 x double> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfge_mask_vv_nxv1f64_nxv1f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
@@ -510,13 +512,13 @@ entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmfge.nxv1f64(
<vscale x 1 x double> %1,
<vscale x 1 x double> %2,
- i32 %4)
+ iXLen %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1f64(
<vscale x 1 x i1> %0,
<vscale x 1 x double> %2,
<vscale x 1 x double> %3,
<vscale x 1 x i1> %mask,
- i32 %4)
+ iXLen %4)
ret <vscale x 1 x i1> %a
}
@@ -524,9 +526,9 @@ entry:
declare <vscale x 2 x i1> @llvm.riscv.vmfge.nxv2f64(
<vscale x 2 x double>,
<vscale x 2 x double>,
- i32);
+ iXLen);
-define <vscale x 2 x i1> @intrinsic_vmfge_vv_nxv2f64_nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, i32 %2) nounwind {
+define <vscale x 2 x i1> @intrinsic_vmfge_vv_nxv2f64_nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmfge_vv_nxv2f64_nxv2f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
@@ -536,7 +538,7 @@ entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmfge.nxv2f64(
<vscale x 2 x double> %0,
<vscale x 2 x double> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 2 x i1> %a
}
@@ -546,9 +548,9 @@ declare <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2f64(
<vscale x 2 x double>,
<vscale x 2 x double>,
<vscale x 2 x i1>,
- i32);
+ iXLen);
-define <vscale x 2 x i1> @intrinsic_vmfge_mask_vv_nxv2f64_nxv2f64(<vscale x 2 x i1> %0, <vscale x 2 x double> %1, <vscale x 2 x double> %2, <vscale x 2 x double> %3, i32 %4) nounwind {
+define <vscale x 2 x i1> @intrinsic_vmfge_mask_vv_nxv2f64_nxv2f64(<vscale x 2 x i1> %0, <vscale x 2 x double> %1, <vscale x 2 x double> %2, <vscale x 2 x double> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfge_mask_vv_nxv2f64_nxv2f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
@@ -562,13 +564,13 @@ entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmfge.nxv2f64(
<vscale x 2 x double> %1,
<vscale x 2 x double> %2,
- i32 %4)
+ iXLen %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2f64(
<vscale x 2 x i1> %0,
<vscale x 2 x double> %2,
<vscale x 2 x double> %3,
<vscale x 2 x i1> %mask,
- i32 %4)
+ iXLen %4)
ret <vscale x 2 x i1> %a
}
@@ -576,9 +578,9 @@ entry:
declare <vscale x 4 x i1> @llvm.riscv.vmfge.nxv4f64(
<vscale x 4 x double>,
<vscale x 4 x double>,
- i32);
+ iXLen);
-define <vscale x 4 x i1> @intrinsic_vmfge_vv_nxv4f64_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, i32 %2) nounwind {
+define <vscale x 4 x i1> @intrinsic_vmfge_vv_nxv4f64_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmfge_vv_nxv4f64_nxv4f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
@@ -588,7 +590,7 @@ entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmfge.nxv4f64(
<vscale x 4 x double> %0,
<vscale x 4 x double> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 4 x i1> %a
}
@@ -598,9 +600,9 @@ declare <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4f64(
<vscale x 4 x double>,
<vscale x 4 x double>,
<vscale x 4 x i1>,
- i32);
+ iXLen);
-define <vscale x 4 x i1> @intrinsic_vmfge_mask_vv_nxv4f64_nxv4f64(<vscale x 4 x i1> %0, <vscale x 4 x double> %1, <vscale x 4 x double> %2, <vscale x 4 x double> %3, i32 %4) nounwind {
+define <vscale x 4 x i1> @intrinsic_vmfge_mask_vv_nxv4f64_nxv4f64(<vscale x 4 x i1> %0, <vscale x 4 x double> %1, <vscale x 4 x double> %2, <vscale x 4 x double> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfge_mask_vv_nxv4f64_nxv4f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
@@ -614,13 +616,13 @@ entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmfge.nxv4f64(
<vscale x 4 x double> %1,
<vscale x 4 x double> %2,
- i32 %4)
+ iXLen %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4f64(
<vscale x 4 x i1> %0,
<vscale x 4 x double> %2,
<vscale x 4 x double> %3,
<vscale x 4 x i1> %mask,
- i32 %4)
+ iXLen %4)
ret <vscale x 4 x i1> %a
}
@@ -628,9 +630,9 @@ entry:
declare <vscale x 1 x i1> @llvm.riscv.vmfge.nxv1f16.f16(
<vscale x 1 x half>,
half,
- i32);
+ iXLen);
-define <vscale x 1 x i1> @intrinsic_vmfge_vf_nxv1f16_f16(<vscale x 1 x half> %0, half %1, i32 %2) nounwind {
+define <vscale x 1 x i1> @intrinsic_vmfge_vf_nxv1f16_f16(<vscale x 1 x half> %0, half %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmfge_vf_nxv1f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
@@ -640,7 +642,7 @@ entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmfge.nxv1f16.f16(
<vscale x 1 x half> %0,
half %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 1 x i1> %a
}
@@ -650,9 +652,9 @@ declare <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1f16.f16(
<vscale x 1 x half>,
half,
<vscale x 1 x i1>,
- i32);
+ iXLen);
-define <vscale x 1 x i1> @intrinsic_vmfge_mask_vf_nxv1f16_f16(<vscale x 1 x i1> %0, <vscale x 1 x half> %1, half %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+define <vscale x 1 x i1> @intrinsic_vmfge_mask_vf_nxv1f16_f16(<vscale x 1 x i1> %0, <vscale x 1 x half> %1, half %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv1f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0
@@ -667,7 +669,7 @@ entry:
<vscale x 1 x half> %1,
half %2,
<vscale x 1 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 1 x i1> %a
}
@@ -675,9 +677,9 @@ entry:
declare <vscale x 2 x i1> @llvm.riscv.vmfge.nxv2f16.f16(
<vscale x 2 x half>,
half,
- i32);
+ iXLen);
-define <vscale x 2 x i1> @intrinsic_vmfge_vf_nxv2f16_f16(<vscale x 2 x half> %0, half %1, i32 %2) nounwind {
+define <vscale x 2 x i1> @intrinsic_vmfge_vf_nxv2f16_f16(<vscale x 2 x half> %0, half %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmfge_vf_nxv2f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
@@ -687,7 +689,7 @@ entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmfge.nxv2f16.f16(
<vscale x 2 x half> %0,
half %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 2 x i1> %a
}
@@ -697,9 +699,9 @@ declare <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2f16.f16(
<vscale x 2 x half>,
half,
<vscale x 2 x i1>,
- i32);
+ iXLen);
-define <vscale x 2 x i1> @intrinsic_vmfge_mask_vf_nxv2f16_f16(<vscale x 2 x i1> %0, <vscale x 2 x half> %1, half %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+define <vscale x 2 x i1> @intrinsic_vmfge_mask_vf_nxv2f16_f16(<vscale x 2 x i1> %0, <vscale x 2 x half> %1, half %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv2f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0
@@ -714,7 +716,7 @@ entry:
<vscale x 2 x half> %1,
half %2,
<vscale x 2 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 2 x i1> %a
}
@@ -722,9 +724,9 @@ entry:
declare <vscale x 4 x i1> @llvm.riscv.vmfge.nxv4f16.f16(
<vscale x 4 x half>,
half,
- i32);
+ iXLen);
-define <vscale x 4 x i1> @intrinsic_vmfge_vf_nxv4f16_f16(<vscale x 4 x half> %0, half %1, i32 %2) nounwind {
+define <vscale x 4 x i1> @intrinsic_vmfge_vf_nxv4f16_f16(<vscale x 4 x half> %0, half %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmfge_vf_nxv4f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
@@ -734,7 +736,7 @@ entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmfge.nxv4f16.f16(
<vscale x 4 x half> %0,
half %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 4 x i1> %a
}
@@ -744,9 +746,9 @@ declare <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4f16.f16(
<vscale x 4 x half>,
half,
<vscale x 4 x i1>,
- i32);
+ iXLen);
-define <vscale x 4 x i1> @intrinsic_vmfge_mask_vf_nxv4f16_f16(<vscale x 4 x i1> %0, <vscale x 4 x half> %1, half %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+define <vscale x 4 x i1> @intrinsic_vmfge_mask_vf_nxv4f16_f16(<vscale x 4 x i1> %0, <vscale x 4 x half> %1, half %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv4f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0
@@ -761,7 +763,7 @@ entry:
<vscale x 4 x half> %1,
half %2,
<vscale x 4 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 4 x i1> %a
}
@@ -769,9 +771,9 @@ entry:
declare <vscale x 8 x i1> @llvm.riscv.vmfge.nxv8f16.f16(
<vscale x 8 x half>,
half,
- i32);
+ iXLen);
-define <vscale x 8 x i1> @intrinsic_vmfge_vf_nxv8f16_f16(<vscale x 8 x half> %0, half %1, i32 %2) nounwind {
+define <vscale x 8 x i1> @intrinsic_vmfge_vf_nxv8f16_f16(<vscale x 8 x half> %0, half %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmfge_vf_nxv8f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
@@ -781,7 +783,7 @@ entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmfge.nxv8f16.f16(
<vscale x 8 x half> %0,
half %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 8 x i1> %a
}
@@ -791,9 +793,9 @@ declare <vscale x 8 x i1> @llvm.riscv.vmfge.mask.nxv8f16.f16(
<vscale x 8 x half>,
half,
<vscale x 8 x i1>,
- i32);
+ iXLen);
-define <vscale x 8 x i1> @intrinsic_vmfge_mask_vf_nxv8f16_f16(<vscale x 8 x i1> %0, <vscale x 8 x half> %1, half %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+define <vscale x 8 x i1> @intrinsic_vmfge_mask_vf_nxv8f16_f16(<vscale x 8 x i1> %0, <vscale x 8 x half> %1, half %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv8f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v11, v0
@@ -808,7 +810,7 @@ entry:
<vscale x 8 x half> %1,
half %2,
<vscale x 8 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 8 x i1> %a
}
@@ -816,9 +818,9 @@ entry:
declare <vscale x 16 x i1> @llvm.riscv.vmfge.nxv16f16.f16(
<vscale x 16 x half>,
half,
- i32);
+ iXLen);
-define <vscale x 16 x i1> @intrinsic_vmfge_vf_nxv16f16_f16(<vscale x 16 x half> %0, half %1, i32 %2) nounwind {
+define <vscale x 16 x i1> @intrinsic_vmfge_vf_nxv16f16_f16(<vscale x 16 x half> %0, half %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmfge_vf_nxv16f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
@@ -828,7 +830,7 @@ entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmfge.nxv16f16.f16(
<vscale x 16 x half> %0,
half %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 16 x i1> %a
}
@@ -838,9 +840,9 @@ declare <vscale x 16 x i1> @llvm.riscv.vmfge.mask.nxv16f16.f16(
<vscale x 16 x half>,
half,
<vscale x 16 x i1>,
- i32);
+ iXLen);
-define <vscale x 16 x i1> @intrinsic_vmfge_mask_vf_nxv16f16_f16(<vscale x 16 x i1> %0, <vscale x 16 x half> %1, half %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+define <vscale x 16 x i1> @intrinsic_vmfge_mask_vf_nxv16f16_f16(<vscale x 16 x i1> %0, <vscale x 16 x half> %1, half %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv16f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v13, v0
@@ -855,7 +857,7 @@ entry:
<vscale x 16 x half> %1,
half %2,
<vscale x 16 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 16 x i1> %a
}
@@ -863,9 +865,9 @@ entry:
declare <vscale x 1 x i1> @llvm.riscv.vmfge.nxv1f32.f32(
<vscale x 1 x float>,
float,
- i32);
+ iXLen);
-define <vscale x 1 x i1> @intrinsic_vmfge_vf_nxv1f32_f32(<vscale x 1 x float> %0, float %1, i32 %2) nounwind {
+define <vscale x 1 x i1> @intrinsic_vmfge_vf_nxv1f32_f32(<vscale x 1 x float> %0, float %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmfge_vf_nxv1f32_f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
@@ -875,7 +877,7 @@ entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmfge.nxv1f32.f32(
<vscale x 1 x float> %0,
float %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 1 x i1> %a
}
@@ -885,9 +887,9 @@ declare <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1f32.f32(
<vscale x 1 x float>,
float,
<vscale x 1 x i1>,
- i32);
+ iXLen);
-define <vscale x 1 x i1> @intrinsic_vmfge_mask_vf_nxv1f32_f32(<vscale x 1 x i1> %0, <vscale x 1 x float> %1, float %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+define <vscale x 1 x i1> @intrinsic_vmfge_mask_vf_nxv1f32_f32(<vscale x 1 x i1> %0, <vscale x 1 x float> %1, float %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv1f32_f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0
@@ -902,7 +904,7 @@ entry:
<vscale x 1 x float> %1,
float %2,
<vscale x 1 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 1 x i1> %a
}
@@ -910,9 +912,9 @@ entry:
declare <vscale x 2 x i1> @llvm.riscv.vmfge.nxv2f32.f32(
<vscale x 2 x float>,
float,
- i32);
+ iXLen);
-define <vscale x 2 x i1> @intrinsic_vmfge_vf_nxv2f32_f32(<vscale x 2 x float> %0, float %1, i32 %2) nounwind {
+define <vscale x 2 x i1> @intrinsic_vmfge_vf_nxv2f32_f32(<vscale x 2 x float> %0, float %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmfge_vf_nxv2f32_f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
@@ -922,7 +924,7 @@ entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmfge.nxv2f32.f32(
<vscale x 2 x float> %0,
float %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 2 x i1> %a
}
@@ -932,9 +934,9 @@ declare <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2f32.f32(
<vscale x 2 x float>,
float,
<vscale x 2 x i1>,
- i32);
+ iXLen);
-define <vscale x 2 x i1> @intrinsic_vmfge_mask_vf_nxv2f32_f32(<vscale x 2 x i1> %0, <vscale x 2 x float> %1, float %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+define <vscale x 2 x i1> @intrinsic_vmfge_mask_vf_nxv2f32_f32(<vscale x 2 x i1> %0, <vscale x 2 x float> %1, float %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv2f32_f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0
@@ -949,7 +951,7 @@ entry:
<vscale x 2 x float> %1,
float %2,
<vscale x 2 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 2 x i1> %a
}
@@ -957,9 +959,9 @@ entry:
declare <vscale x 4 x i1> @llvm.riscv.vmfge.nxv4f32.f32(
<vscale x 4 x float>,
float,
- i32);
+ iXLen);
-define <vscale x 4 x i1> @intrinsic_vmfge_vf_nxv4f32_f32(<vscale x 4 x float> %0, float %1, i32 %2) nounwind {
+define <vscale x 4 x i1> @intrinsic_vmfge_vf_nxv4f32_f32(<vscale x 4 x float> %0, float %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmfge_vf_nxv4f32_f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
@@ -969,7 +971,7 @@ entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmfge.nxv4f32.f32(
<vscale x 4 x float> %0,
float %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 4 x i1> %a
}
@@ -979,9 +981,9 @@ declare <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4f32.f32(
<vscale x 4 x float>,
float,
<vscale x 4 x i1>,
- i32);
+ iXLen);
-define <vscale x 4 x i1> @intrinsic_vmfge_mask_vf_nxv4f32_f32(<vscale x 4 x i1> %0, <vscale x 4 x float> %1, float %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+define <vscale x 4 x i1> @intrinsic_vmfge_mask_vf_nxv4f32_f32(<vscale x 4 x i1> %0, <vscale x 4 x float> %1, float %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv4f32_f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v11, v0
@@ -996,7 +998,7 @@ entry:
<vscale x 4 x float> %1,
float %2,
<vscale x 4 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 4 x i1> %a
}
@@ -1004,9 +1006,9 @@ entry:
declare <vscale x 8 x i1> @llvm.riscv.vmfge.nxv8f32.f32(
<vscale x 8 x float>,
float,
- i32);
+ iXLen);
-define <vscale x 8 x i1> @intrinsic_vmfge_vf_nxv8f32_f32(<vscale x 8 x float> %0, float %1, i32 %2) nounwind {
+define <vscale x 8 x i1> @intrinsic_vmfge_vf_nxv8f32_f32(<vscale x 8 x float> %0, float %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmfge_vf_nxv8f32_f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
@@ -1016,7 +1018,7 @@ entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmfge.nxv8f32.f32(
<vscale x 8 x float> %0,
float %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 8 x i1> %a
}
@@ -1026,9 +1028,9 @@ declare <vscale x 8 x i1> @llvm.riscv.vmfge.mask.nxv8f32.f32(
<vscale x 8 x float>,
float,
<vscale x 8 x i1>,
- i32);
+ iXLen);
-define <vscale x 8 x i1> @intrinsic_vmfge_mask_vf_nxv8f32_f32(<vscale x 8 x i1> %0, <vscale x 8 x float> %1, float %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+define <vscale x 8 x i1> @intrinsic_vmfge_mask_vf_nxv8f32_f32(<vscale x 8 x i1> %0, <vscale x 8 x float> %1, float %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv8f32_f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v13, v0
@@ -1043,7 +1045,7 @@ entry:
<vscale x 8 x float> %1,
float %2,
<vscale x 8 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 8 x i1> %a
}
@@ -1051,9 +1053,9 @@ entry:
declare <vscale x 1 x i1> @llvm.riscv.vmfge.nxv1f64.f64(
<vscale x 1 x double>,
double,
- i32);
+ iXLen);
-define <vscale x 1 x i1> @intrinsic_vmfge_vf_nxv1f64_f64(<vscale x 1 x double> %0, double %1, i32 %2) nounwind {
+define <vscale x 1 x i1> @intrinsic_vmfge_vf_nxv1f64_f64(<vscale x 1 x double> %0, double %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmfge_vf_nxv1f64_f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
@@ -1063,7 +1065,7 @@ entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmfge.nxv1f64.f64(
<vscale x 1 x double> %0,
double %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 1 x i1> %a
}
@@ -1073,9 +1075,9 @@ declare <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1f64.f64(
<vscale x 1 x double>,
double,
<vscale x 1 x i1>,
- i32);
+ iXLen);
-define <vscale x 1 x i1> @intrinsic_vmfge_mask_vf_nxv1f64_f64(<vscale x 1 x i1> %0, <vscale x 1 x double> %1, double %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+define <vscale x 1 x i1> @intrinsic_vmfge_mask_vf_nxv1f64_f64(<vscale x 1 x i1> %0, <vscale x 1 x double> %1, double %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv1f64_f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0
@@ -1090,7 +1092,7 @@ entry:
<vscale x 1 x double> %1,
double %2,
<vscale x 1 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 1 x i1> %a
}
@@ -1098,9 +1100,9 @@ entry:
declare <vscale x 2 x i1> @llvm.riscv.vmfge.nxv2f64.f64(
<vscale x 2 x double>,
double,
- i32);
+ iXLen);
-define <vscale x 2 x i1> @intrinsic_vmfge_vf_nxv2f64_f64(<vscale x 2 x double> %0, double %1, i32 %2) nounwind {
+define <vscale x 2 x i1> @intrinsic_vmfge_vf_nxv2f64_f64(<vscale x 2 x double> %0, double %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmfge_vf_nxv2f64_f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
@@ -1110,7 +1112,7 @@ entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmfge.nxv2f64.f64(
<vscale x 2 x double> %0,
double %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 2 x i1> %a
}
@@ -1120,9 +1122,9 @@ declare <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2f64.f64(
<vscale x 2 x double>,
double,
<vscale x 2 x i1>,
- i32);
+ iXLen);
-define <vscale x 2 x i1> @intrinsic_vmfge_mask_vf_nxv2f64_f64(<vscale x 2 x i1> %0, <vscale x 2 x double> %1, double %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+define <vscale x 2 x i1> @intrinsic_vmfge_mask_vf_nxv2f64_f64(<vscale x 2 x i1> %0, <vscale x 2 x double> %1, double %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv2f64_f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v11, v0
@@ -1137,7 +1139,7 @@ entry:
<vscale x 2 x double> %1,
double %2,
<vscale x 2 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 2 x i1> %a
}
@@ -1145,9 +1147,9 @@ entry:
declare <vscale x 4 x i1> @llvm.riscv.vmfge.nxv4f64.f64(
<vscale x 4 x double>,
double,
- i32);
+ iXLen);
-define <vscale x 4 x i1> @intrinsic_vmfge_vf_nxv4f64_f64(<vscale x 4 x double> %0, double %1, i32 %2) nounwind {
+define <vscale x 4 x i1> @intrinsic_vmfge_vf_nxv4f64_f64(<vscale x 4 x double> %0, double %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmfge_vf_nxv4f64_f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
@@ -1157,7 +1159,7 @@ entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmfge.nxv4f64.f64(
<vscale x 4 x double> %0,
double %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 4 x i1> %a
}
@@ -1167,9 +1169,9 @@ declare <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4f64.f64(
<vscale x 4 x double>,
double,
<vscale x 4 x i1>,
- i32);
+ iXLen);
-define <vscale x 4 x i1> @intrinsic_vmfge_mask_vf_nxv4f64_f64(<vscale x 4 x i1> %0, <vscale x 4 x double> %1, double %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+define <vscale x 4 x i1> @intrinsic_vmfge_mask_vf_nxv4f64_f64(<vscale x 4 x i1> %0, <vscale x 4 x double> %1, double %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv4f64_f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v13, v0
@@ -1184,7 +1186,7 @@ entry:
<vscale x 4 x double> %1,
double %2,
<vscale x 4 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 4 x i1> %a
}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmfgt-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vmfgt-rv64.ll
deleted file mode 100644
index 89866057c90d3..0000000000000
--- a/llvm/test/CodeGen/RISCV/rvv/vmfgt-rv64.ll
+++ /dev/null
@@ -1,1190 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv64 -mattr=+v,+d,+zfh -verify-machineinstrs \
-; RUN: -target-abi=lp64d < %s | FileCheck %s
-declare <vscale x 1 x i1> @llvm.riscv.vmfgt.nxv1f16(
- <vscale x 1 x half>,
- <vscale x 1 x half>,
- i64);
-
-define <vscale x 1 x i1> @intrinsic_vmfgt_vv_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmfgt_vv_nxv1f16_nxv1f16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vmflt.vv v0, v9, v8
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i1> @llvm.riscv.vmfgt.nxv1f16(
- <vscale x 1 x half> %0,
- <vscale x 1 x half> %1,
- i64 %2)
-
- ret <vscale x 1 x i1> %a
-}
-
-declare <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1f16(
- <vscale x 1 x i1>,
- <vscale x 1 x half>,
- <vscale x 1 x half>,
- <vscale x 1 x i1>,
- i64);
-
-define <vscale x 1 x i1> @intrinsic_vmfgt_mask_vv_nxv1f16_nxv1f16(<vscale x 1 x i1> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x half> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmfgt_mask_vv_nxv1f16_nxv1f16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vmflt.vv v8, v9, v8
-; CHECK-NEXT: vmv1r.v v11, v0
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmflt.vv v11, v10, v9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v11
-; CHECK-NEXT: ret
-entry:
- %mask = call <vscale x 1 x i1> @llvm.riscv.vmfgt.nxv1f16(
- <vscale x 1 x half> %1,
- <vscale x 1 x half> %2,
- i64 %4)
- %a = call <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1f16(
- <vscale x 1 x i1> %0,
- <vscale x 1 x half> %2,
- <vscale x 1 x half> %3,
- <vscale x 1 x i1> %mask,
- i64 %4)
-
- ret <vscale x 1 x i1> %a
-}
-
-declare <vscale x 2 x i1> @llvm.riscv.vmfgt.nxv2f16(
- <vscale x 2 x half>,
- <vscale x 2 x half>,
- i64);
-
-define <vscale x 2 x i1> @intrinsic_vmfgt_vv_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmfgt_vv_nxv2f16_nxv2f16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vmflt.vv v0, v9, v8
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i1> @llvm.riscv.vmfgt.nxv2f16(
- <vscale x 2 x half> %0,
- <vscale x 2 x half> %1,
- i64 %2)
-
- ret <vscale x 2 x i1> %a
-}
-
-declare <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2f16(
- <vscale x 2 x i1>,
- <vscale x 2 x half>,
- <vscale x 2 x half>,
- <vscale x 2 x i1>,
- i64);
-
-define <vscale x 2 x i1> @intrinsic_vmfgt_mask_vv_nxv2f16_nxv2f16(<vscale x 2 x i1> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, <vscale x 2 x half> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmfgt_mask_vv_nxv2f16_nxv2f16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vmflt.vv v8, v9, v8
-; CHECK-NEXT: vmv1r.v v11, v0
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmflt.vv v11, v10, v9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v11
-; CHECK-NEXT: ret
-entry:
- %mask = call <vscale x 2 x i1> @llvm.riscv.vmfgt.nxv2f16(
- <vscale x 2 x half> %1,
- <vscale x 2 x half> %2,
- i64 %4)
- %a = call <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2f16(
- <vscale x 2 x i1> %0,
- <vscale x 2 x half> %2,
- <vscale x 2 x half> %3,
- <vscale x 2 x i1> %mask,
- i64 %4)
-
- ret <vscale x 2 x i1> %a
-}
-
-declare <vscale x 4 x i1> @llvm.riscv.vmfgt.nxv4f16(
- <vscale x 4 x half>,
- <vscale x 4 x half>,
- i64);
-
-define <vscale x 4 x i1> @intrinsic_vmfgt_vv_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmfgt_vv_nxv4f16_nxv4f16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vmflt.vv v0, v9, v8
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i1> @llvm.riscv.vmfgt.nxv4f16(
- <vscale x 4 x half> %0,
- <vscale x 4 x half> %1,
- i64 %2)
-
- ret <vscale x 4 x i1> %a
-}
-
-declare <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4f16(
- <vscale x 4 x i1>,
- <vscale x 4 x half>,
- <vscale x 4 x half>,
- <vscale x 4 x i1>,
- i64);
-
-define <vscale x 4 x i1> @intrinsic_vmfgt_mask_vv_nxv4f16_nxv4f16(<vscale x 4 x i1> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x half> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmfgt_mask_vv_nxv4f16_nxv4f16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vmflt.vv v8, v9, v8
-; CHECK-NEXT: vmv1r.v v11, v0
-; CHECK-NEXT: vmv.v.v v0, v8
-; CHECK-NEXT: vmflt.vv v11, v10, v9, v0.t
-; CHECK-NEXT: vmv.v.v v0, v11
-; CHECK-NEXT: ret
-entry:
- %mask = call <vscale x 4 x i1> @llvm.riscv.vmfgt.nxv4f16(
- <vscale x 4 x half> %1,
- <vscale x 4 x half> %2,
- i64 %4)
- %a = call <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4f16(
- <vscale x 4 x i1> %0,
- <vscale x 4 x half> %2,
- <vscale x 4 x half> %3,
- <vscale x 4 x i1> %mask,
- i64 %4)
-
- ret <vscale x 4 x i1> %a
-}
-
-declare <vscale x 8 x i1> @llvm.riscv.vmfgt.nxv8f16(
- <vscale x 8 x half>,
- <vscale x 8 x half>,
- i64);
-
-define <vscale x 8 x i1> @intrinsic_vmfgt_vv_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmfgt_vv_nxv8f16_nxv8f16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vmflt.vv v0, v10, v8
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i1> @llvm.riscv.vmfgt.nxv8f16(
- <vscale x 8 x half> %0,
- <vscale x 8 x half> %1,
- i64 %2)
-
- ret <vscale x 8 x i1> %a
-}
-
-declare <vscale x 8 x i1> @llvm.riscv.vmfgt.mask.nxv8f16(
- <vscale x 8 x i1>,
- <vscale x 8 x half>,
- <vscale x 8 x half>,
- <vscale x 8 x i1>,
- i64);
-
-define <vscale x 8 x i1> @intrinsic_vmfgt_mask_vv_nxv8f16_nxv8f16(<vscale x 8 x i1> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x half> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmfgt_mask_vv_nxv8f16_nxv8f16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vmflt.vv v14, v10, v8
-; CHECK-NEXT: vmv1r.v v8, v0
-; CHECK-NEXT: vmv1r.v v0, v14
-; CHECK-NEXT: vmflt.vv v8, v12, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: ret
-entry:
- %mask = call <vscale x 8 x i1> @llvm.riscv.vmfgt.nxv8f16(
- <vscale x 8 x half> %1,
- <vscale x 8 x half> %2,
- i64 %4)
- %a = call <vscale x 8 x i1> @llvm.riscv.vmfgt.mask.nxv8f16(
- <vscale x 8 x i1> %0,
- <vscale x 8 x half> %2,
- <vscale x 8 x half> %3,
- <vscale x 8 x i1> %mask,
- i64 %4)
-
- ret <vscale x 8 x i1> %a
-}
-
-declare <vscale x 16 x i1> @llvm.riscv.vmfgt.nxv16f16(
- <vscale x 16 x half>,
- <vscale x 16 x half>,
- i64);
-
-define <vscale x 16 x i1> @intrinsic_vmfgt_vv_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmfgt_vv_nxv16f16_nxv16f16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
-; CHECK-NEXT: vmflt.vv v0, v12, v8
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i1> @llvm.riscv.vmfgt.nxv16f16(
- <vscale x 16 x half> %0,
- <vscale x 16 x half> %1,
- i64 %2)
-
- ret <vscale x 16 x i1> %a
-}
-
-declare <vscale x 16 x i1> @llvm.riscv.vmfgt.mask.nxv16f16(
- <vscale x 16 x i1>,
- <vscale x 16 x half>,
- <vscale x 16 x half>,
- <vscale x 16 x i1>,
- i64);
-
-define <vscale x 16 x i1> @intrinsic_vmfgt_mask_vv_nxv16f16_nxv16f16(<vscale x 16 x i1> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, <vscale x 16 x half> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmfgt_mask_vv_nxv16f16_nxv16f16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
-; CHECK-NEXT: vmflt.vv v20, v12, v8
-; CHECK-NEXT: vmv1r.v v8, v0
-; CHECK-NEXT: vmv1r.v v0, v20
-; CHECK-NEXT: vmflt.vv v8, v16, v12, v0.t
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: ret
-entry:
- %mask = call <vscale x 16 x i1> @llvm.riscv.vmfgt.nxv16f16(
- <vscale x 16 x half> %1,
- <vscale x 16 x half> %2,
- i64 %4)
- %a = call <vscale x 16 x i1> @llvm.riscv.vmfgt.mask.nxv16f16(
- <vscale x 16 x i1> %0,
- <vscale x 16 x half> %2,
- <vscale x 16 x half> %3,
- <vscale x 16 x i1> %mask,
- i64 %4)
-
- ret <vscale x 16 x i1> %a
-}
-
-declare <vscale x 1 x i1> @llvm.riscv.vmfgt.nxv1f32(
- <vscale x 1 x float>,
- <vscale x 1 x float>,
- i64);
-
-define <vscale x 1 x i1> @intrinsic_vmfgt_vv_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmfgt_vv_nxv1f32_nxv1f32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vmflt.vv v0, v9, v8
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i1> @llvm.riscv.vmfgt.nxv1f32(
- <vscale x 1 x float> %0,
- <vscale x 1 x float> %1,
- i64 %2)
-
- ret <vscale x 1 x i1> %a
-}
-
-declare <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1f32(
- <vscale x 1 x i1>,
- <vscale x 1 x float>,
- <vscale x 1 x float>,
- <vscale x 1 x i1>,
- i64);
-
-define <vscale x 1 x i1> @intrinsic_vmfgt_mask_vv_nxv1f32_nxv1f32(<vscale x 1 x i1> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, <vscale x 1 x float> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmfgt_mask_vv_nxv1f32_nxv1f32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vmflt.vv v8, v9, v8
-; CHECK-NEXT: vmv1r.v v11, v0
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmflt.vv v11, v10, v9, v0.t
-; CHECK-NEXT: vmv1r.v v0, v11
-; CHECK-NEXT: ret
-entry:
- %mask = call <vscale x 1 x i1> @llvm.riscv.vmfgt.nxv1f32(
- <vscale x 1 x float> %1,
- <vscale x 1 x float> %2,
- i64 %4)
- %a = call <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1f32(
- <vscale x 1 x i1> %0,
- <vscale x 1 x float> %2,
- <vscale x 1 x float> %3,
- <vscale x 1 x i1> %mask,
- i64 %4)
-
- ret <vscale x 1 x i1> %a
-}
-
-declare <vscale x 2 x i1> @llvm.riscv.vmfgt.nxv2f32(
- <vscale x 2 x float>,
- <vscale x 2 x float>,
- i64);
-
-define <vscale x 2 x i1> @intrinsic_vmfgt_vv_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmfgt_vv_nxv2f32_nxv2f32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vmflt.vv v0, v9, v8
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i1> @llvm.riscv.vmfgt.nxv2f32(
- <vscale x 2 x float> %0,
- <vscale x 2 x float> %1,
- i64 %2)
-
- ret <vscale x 2 x i1> %a
-}
-
-declare <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2f32(
- <vscale x 2 x i1>,
- <vscale x 2 x float>,
- <vscale x 2 x float>,
- <vscale x 2 x i1>,
- i64);
-
-define <vscale x 2 x i1> @intrinsic_vmfgt_mask_vv_nxv2f32_nxv2f32(<vscale x 2 x i1> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x float> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmfgt_mask_vv_nxv2f32_nxv2f32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vmflt.vv v8, v9, v8
-; CHECK-NEXT: vmv1r.v v11, v0
-; CHECK-NEXT: vmv.v.v v0, v8
-; CHECK-NEXT: vmflt.vv v11, v10, v9, v0.t
-; CHECK-NEXT: vmv.v.v v0, v11
-; CHECK-NEXT: ret
-entry:
- %mask = call <vscale x 2 x i1> @llvm.riscv.vmfgt.nxv2f32(
- <vscale x 2 x float> %1,
- <vscale x 2 x float> %2,
- i64 %4)
- %a = call <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2f32(
- <vscale x 2 x i1> %0,
- <vscale x 2 x float> %2,
- <vscale x 2 x float> %3,
- <vscale x 2 x i1> %mask,
- i64 %4)
-
- ret <vscale x 2 x i1> %a
-}
-
-declare <vscale x 4 x i1> @llvm.riscv.vmfgt.nxv4f32(
- <vscale x 4 x float>,
- <vscale x 4 x float>,
- i64);
-
-define <vscale x 4 x i1> @intrinsic_vmfgt_vv_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmfgt_vv_nxv4f32_nxv4f32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vmflt.vv v0, v10, v8
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i1> @llvm.riscv.vmfgt.nxv4f32(
- <vscale x 4 x float> %0,
- <vscale x 4 x float> %1,
- i64 %2)
-
- ret <vscale x 4 x i1> %a
-}
-
-declare <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4f32(
- <vscale x 4 x i1>,
- <vscale x 4 x float>,
- <vscale x 4 x float>,
- <vscale x 4 x i1>,
- i64);
-
-define <vscale x 4 x i1> @intrinsic_vmfgt_mask_vv_nxv4f32_nxv4f32(<vscale x 4 x i1> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x float> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmfgt_mask_vv_nxv4f32_nxv4f32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vmflt.vv v14, v10, v8
-; CHECK-NEXT: vmv1r.v v8, v0
-; CHECK-NEXT: vmv1r.v v0, v14
-; CHECK-NEXT: vmflt.vv v8, v12, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: ret
-entry:
- %mask = call <vscale x 4 x i1> @llvm.riscv.vmfgt.nxv4f32(
- <vscale x 4 x float> %1,
- <vscale x 4 x float> %2,
- i64 %4)
- %a = call <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4f32(
- <vscale x 4 x i1> %0,
- <vscale x 4 x float> %2,
- <vscale x 4 x float> %3,
- <vscale x 4 x i1> %mask,
- i64 %4)
-
- ret <vscale x 4 x i1> %a
-}
-
-declare <vscale x 8 x i1> @llvm.riscv.vmfgt.nxv8f32(
- <vscale x 8 x float>,
- <vscale x 8 x float>,
- i64);
-
-define <vscale x 8 x i1> @intrinsic_vmfgt_vv_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmfgt_vv_nxv8f32_nxv8f32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
-; CHECK-NEXT: vmflt.vv v0, v12, v8
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i1> @llvm.riscv.vmfgt.nxv8f32(
- <vscale x 8 x float> %0,
- <vscale x 8 x float> %1,
- i64 %2)
-
- ret <vscale x 8 x i1> %a
-}
-
-declare <vscale x 8 x i1> @llvm.riscv.vmfgt.mask.nxv8f32(
- <vscale x 8 x i1>,
- <vscale x 8 x float>,
- <vscale x 8 x float>,
- <vscale x 8 x i1>,
- i64);
-
-define <vscale x 8 x i1> @intrinsic_vmfgt_mask_vv_nxv8f32_nxv8f32(<vscale x 8 x i1> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, <vscale x 8 x float> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmfgt_mask_vv_nxv8f32_nxv8f32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
-; CHECK-NEXT: vmflt.vv v20, v12, v8
-; CHECK-NEXT: vmv1r.v v8, v0
-; CHECK-NEXT: vmv1r.v v0, v20
-; CHECK-NEXT: vmflt.vv v8, v16, v12, v0.t
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: ret
-entry:
- %mask = call <vscale x 8 x i1> @llvm.riscv.vmfgt.nxv8f32(
- <vscale x 8 x float> %1,
- <vscale x 8 x float> %2,
- i64 %4)
- %a = call <vscale x 8 x i1> @llvm.riscv.vmfgt.mask.nxv8f32(
- <vscale x 8 x i1> %0,
- <vscale x 8 x float> %2,
- <vscale x 8 x float> %3,
- <vscale x 8 x i1> %mask,
- i64 %4)
-
- ret <vscale x 8 x i1> %a
-}
-
-declare <vscale x 1 x i1> @llvm.riscv.vmfgt.nxv1f64(
- <vscale x 1 x double>,
- <vscale x 1 x double>,
- i64);
-
-define <vscale x 1 x i1> @intrinsic_vmfgt_vv_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmfgt_vv_nxv1f64_nxv1f64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
-; CHECK-NEXT: vmflt.vv v0, v9, v8
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i1> @llvm.riscv.vmfgt.nxv1f64(
- <vscale x 1 x double> %0,
- <vscale x 1 x double> %1,
- i64 %2)
-
- ret <vscale x 1 x i1> %a
-}
-
-declare <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1f64(
- <vscale x 1 x i1>,
- <vscale x 1 x double>,
- <vscale x 1 x double>,
- <vscale x 1 x i1>,
- i64);
-
-define <vscale x 1 x i1> @intrinsic_vmfgt_mask_vv_nxv1f64_nxv1f64(<vscale x 1 x i1> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, <vscale x 1 x double> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmfgt_mask_vv_nxv1f64_nxv1f64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
-; CHECK-NEXT: vmflt.vv v8, v9, v8
-; CHECK-NEXT: vmv1r.v v11, v0
-; CHECK-NEXT: vmv.v.v v0, v8
-; CHECK-NEXT: vmflt.vv v11, v10, v9, v0.t
-; CHECK-NEXT: vmv.v.v v0, v11
-; CHECK-NEXT: ret
-entry:
- %mask = call <vscale x 1 x i1> @llvm.riscv.vmfgt.nxv1f64(
- <vscale x 1 x double> %1,
- <vscale x 1 x double> %2,
- i64 %4)
- %a = call <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1f64(
- <vscale x 1 x i1> %0,
- <vscale x 1 x double> %2,
- <vscale x 1 x double> %3,
- <vscale x 1 x i1> %mask,
- i64 %4)
-
- ret <vscale x 1 x i1> %a
-}
-
-declare <vscale x 2 x i1> @llvm.riscv.vmfgt.nxv2f64(
- <vscale x 2 x double>,
- <vscale x 2 x double>,
- i64);
-
-define <vscale x 2 x i1> @intrinsic_vmfgt_vv_nxv2f64_nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmfgt_vv_nxv2f64_nxv2f64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
-; CHECK-NEXT: vmflt.vv v0, v10, v8
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i1> @llvm.riscv.vmfgt.nxv2f64(
- <vscale x 2 x double> %0,
- <vscale x 2 x double> %1,
- i64 %2)
-
- ret <vscale x 2 x i1> %a
-}
-
-declare <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2f64(
- <vscale x 2 x i1>,
- <vscale x 2 x double>,
- <vscale x 2 x double>,
- <vscale x 2 x i1>,
- i64);
-
-define <vscale x 2 x i1> @intrinsic_vmfgt_mask_vv_nxv2f64_nxv2f64(<vscale x 2 x i1> %0, <vscale x 2 x double> %1, <vscale x 2 x double> %2, <vscale x 2 x double> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmfgt_mask_vv_nxv2f64_nxv2f64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
-; CHECK-NEXT: vmflt.vv v14, v10, v8
-; CHECK-NEXT: vmv1r.v v8, v0
-; CHECK-NEXT: vmv1r.v v0, v14
-; CHECK-NEXT: vmflt.vv v8, v12, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: ret
-entry:
- %mask = call <vscale x 2 x i1> @llvm.riscv.vmfgt.nxv2f64(
- <vscale x 2 x double> %1,
- <vscale x 2 x double> %2,
- i64 %4)
- %a = call <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2f64(
- <vscale x 2 x i1> %0,
- <vscale x 2 x double> %2,
- <vscale x 2 x double> %3,
- <vscale x 2 x i1> %mask,
- i64 %4)
-
- ret <vscale x 2 x i1> %a
-}
-
-declare <vscale x 4 x i1> @llvm.riscv.vmfgt.nxv4f64(
- <vscale x 4 x double>,
- <vscale x 4 x double>,
- i64);
-
-define <vscale x 4 x i1> @intrinsic_vmfgt_vv_nxv4f64_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmfgt_vv_nxv4f64_nxv4f64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
-; CHECK-NEXT: vmflt.vv v0, v12, v8
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i1> @llvm.riscv.vmfgt.nxv4f64(
- <vscale x 4 x double> %0,
- <vscale x 4 x double> %1,
- i64 %2)
-
- ret <vscale x 4 x i1> %a
-}
-
-declare <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4f64(
- <vscale x 4 x i1>,
- <vscale x 4 x double>,
- <vscale x 4 x double>,
- <vscale x 4 x i1>,
- i64);
-
-define <vscale x 4 x i1> @intrinsic_vmfgt_mask_vv_nxv4f64_nxv4f64(<vscale x 4 x i1> %0, <vscale x 4 x double> %1, <vscale x 4 x double> %2, <vscale x 4 x double> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmfgt_mask_vv_nxv4f64_nxv4f64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
-; CHECK-NEXT: vmflt.vv v20, v12, v8
-; CHECK-NEXT: vmv1r.v v8, v0
-; CHECK-NEXT: vmv1r.v v0, v20
-; CHECK-NEXT: vmflt.vv v8, v16, v12, v0.t
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: ret
-entry:
- %mask = call <vscale x 4 x i1> @llvm.riscv.vmfgt.nxv4f64(
- <vscale x 4 x double> %1,
- <vscale x 4 x double> %2,
- i64 %4)
- %a = call <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4f64(
- <vscale x 4 x i1> %0,
- <vscale x 4 x double> %2,
- <vscale x 4 x double> %3,
- <vscale x 4 x i1> %mask,
- i64 %4)
-
- ret <vscale x 4 x i1> %a
-}
-
-declare <vscale x 1 x i1> @llvm.riscv.vmfgt.nxv1f16.f16(
- <vscale x 1 x half>,
- half,
- i64);
-
-define <vscale x 1 x i1> @intrinsic_vmfgt_vf_nxv1f16_f16(<vscale x 1 x half> %0, half %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmfgt_vf_nxv1f16_f16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vmfgt.vf v0, v8, fa0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i1> @llvm.riscv.vmfgt.nxv1f16.f16(
- <vscale x 1 x half> %0,
- half %1,
- i64 %2)
-
- ret <vscale x 1 x i1> %a
-}
-
-declare <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1f16.f16(
- <vscale x 1 x i1>,
- <vscale x 1 x half>,
- half,
- <vscale x 1 x i1>,
- i64);
-
-define <vscale x 1 x i1> @intrinsic_vmfgt_mask_vf_nxv1f16_f16(<vscale x 1 x i1> %0, <vscale x 1 x half> %1, half %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv1f16_f16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v10, v0
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmfgt.vf v10, v8, fa0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1f16.f16(
- <vscale x 1 x i1> %0,
- <vscale x 1 x half> %1,
- half %2,
- <vscale x 1 x i1> %3,
- i64 %4)
-
- ret <vscale x 1 x i1> %a
-}
-
-declare <vscale x 2 x i1> @llvm.riscv.vmfgt.nxv2f16.f16(
- <vscale x 2 x half>,
- half,
- i64);
-
-define <vscale x 2 x i1> @intrinsic_vmfgt_vf_nxv2f16_f16(<vscale x 2 x half> %0, half %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmfgt_vf_nxv2f16_f16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vmfgt.vf v0, v8, fa0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i1> @llvm.riscv.vmfgt.nxv2f16.f16(
- <vscale x 2 x half> %0,
- half %1,
- i64 %2)
-
- ret <vscale x 2 x i1> %a
-}
-
-declare <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2f16.f16(
- <vscale x 2 x i1>,
- <vscale x 2 x half>,
- half,
- <vscale x 2 x i1>,
- i64);
-
-define <vscale x 2 x i1> @intrinsic_vmfgt_mask_vf_nxv2f16_f16(<vscale x 2 x i1> %0, <vscale x 2 x half> %1, half %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv2f16_f16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v10, v0
-; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmfgt.vf v10, v8, fa0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2f16.f16(
- <vscale x 2 x i1> %0,
- <vscale x 2 x half> %1,
- half %2,
- <vscale x 2 x i1> %3,
- i64 %4)
-
- ret <vscale x 2 x i1> %a
-}
-
-declare <vscale x 4 x i1> @llvm.riscv.vmfgt.nxv4f16.f16(
- <vscale x 4 x half>,
- half,
- i64);
-
-define <vscale x 4 x i1> @intrinsic_vmfgt_vf_nxv4f16_f16(<vscale x 4 x half> %0, half %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmfgt_vf_nxv4f16_f16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vmfgt.vf v0, v8, fa0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i1> @llvm.riscv.vmfgt.nxv4f16.f16(
- <vscale x 4 x half> %0,
- half %1,
- i64 %2)
-
- ret <vscale x 4 x i1> %a
-}
-
-declare <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4f16.f16(
- <vscale x 4 x i1>,
- <vscale x 4 x half>,
- half,
- <vscale x 4 x i1>,
- i64);
-
-define <vscale x 4 x i1> @intrinsic_vmfgt_mask_vf_nxv4f16_f16(<vscale x 4 x i1> %0, <vscale x 4 x half> %1, half %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv4f16_f16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v10, v0
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmfgt.vf v10, v8, fa0, v0.t
-; CHECK-NEXT: vmv.v.v v0, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4f16.f16(
- <vscale x 4 x i1> %0,
- <vscale x 4 x half> %1,
- half %2,
- <vscale x 4 x i1> %3,
- i64 %4)
-
- ret <vscale x 4 x i1> %a
-}
-
-declare <vscale x 8 x i1> @llvm.riscv.vmfgt.nxv8f16.f16(
- <vscale x 8 x half>,
- half,
- i64);
-
-define <vscale x 8 x i1> @intrinsic_vmfgt_vf_nxv8f16_f16(<vscale x 8 x half> %0, half %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmfgt_vf_nxv8f16_f16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vmfgt.vf v0, v8, fa0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i1> @llvm.riscv.vmfgt.nxv8f16.f16(
- <vscale x 8 x half> %0,
- half %1,
- i64 %2)
-
- ret <vscale x 8 x i1> %a
-}
-
-declare <vscale x 8 x i1> @llvm.riscv.vmfgt.mask.nxv8f16.f16(
- <vscale x 8 x i1>,
- <vscale x 8 x half>,
- half,
- <vscale x 8 x i1>,
- i64);
-
-define <vscale x 8 x i1> @intrinsic_vmfgt_mask_vf_nxv8f16_f16(<vscale x 8 x i1> %0, <vscale x 8 x half> %1, half %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv8f16_f16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v11, v0
-; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmfgt.vf v11, v8, fa0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v11
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i1> @llvm.riscv.vmfgt.mask.nxv8f16.f16(
- <vscale x 8 x i1> %0,
- <vscale x 8 x half> %1,
- half %2,
- <vscale x 8 x i1> %3,
- i64 %4)
-
- ret <vscale x 8 x i1> %a
-}
-
-declare <vscale x 16 x i1> @llvm.riscv.vmfgt.nxv16f16.f16(
- <vscale x 16 x half>,
- half,
- i64);
-
-define <vscale x 16 x i1> @intrinsic_vmfgt_vf_nxv16f16_f16(<vscale x 16 x half> %0, half %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmfgt_vf_nxv16f16_f16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
-; CHECK-NEXT: vmfgt.vf v0, v8, fa0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i1> @llvm.riscv.vmfgt.nxv16f16.f16(
- <vscale x 16 x half> %0,
- half %1,
- i64 %2)
-
- ret <vscale x 16 x i1> %a
-}
-
-declare <vscale x 16 x i1> @llvm.riscv.vmfgt.mask.nxv16f16.f16(
- <vscale x 16 x i1>,
- <vscale x 16 x half>,
- half,
- <vscale x 16 x i1>,
- i64);
-
-define <vscale x 16 x i1> @intrinsic_vmfgt_mask_vf_nxv16f16_f16(<vscale x 16 x i1> %0, <vscale x 16 x half> %1, half %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv16f16_f16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v13, v0
-; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
-; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmfgt.vf v13, v8, fa0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v13
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i1> @llvm.riscv.vmfgt.mask.nxv16f16.f16(
- <vscale x 16 x i1> %0,
- <vscale x 16 x half> %1,
- half %2,
- <vscale x 16 x i1> %3,
- i64 %4)
-
- ret <vscale x 16 x i1> %a
-}
-
-declare <vscale x 1 x i1> @llvm.riscv.vmfgt.nxv1f32.f32(
- <vscale x 1 x float>,
- float,
- i64);
-
-define <vscale x 1 x i1> @intrinsic_vmfgt_vf_nxv1f32_f32(<vscale x 1 x float> %0, float %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmfgt_vf_nxv1f32_f32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vmfgt.vf v0, v8, fa0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i1> @llvm.riscv.vmfgt.nxv1f32.f32(
- <vscale x 1 x float> %0,
- float %1,
- i64 %2)
-
- ret <vscale x 1 x i1> %a
-}
-
-declare <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1f32.f32(
- <vscale x 1 x i1>,
- <vscale x 1 x float>,
- float,
- <vscale x 1 x i1>,
- i64);
-
-define <vscale x 1 x i1> @intrinsic_vmfgt_mask_vf_nxv1f32_f32(<vscale x 1 x i1> %0, <vscale x 1 x float> %1, float %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv1f32_f32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v10, v0
-; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmfgt.vf v10, v8, fa0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1f32.f32(
- <vscale x 1 x i1> %0,
- <vscale x 1 x float> %1,
- float %2,
- <vscale x 1 x i1> %3,
- i64 %4)
-
- ret <vscale x 1 x i1> %a
-}
-
-declare <vscale x 2 x i1> @llvm.riscv.vmfgt.nxv2f32.f32(
- <vscale x 2 x float>,
- float,
- i64);
-
-define <vscale x 2 x i1> @intrinsic_vmfgt_vf_nxv2f32_f32(<vscale x 2 x float> %0, float %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmfgt_vf_nxv2f32_f32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vmfgt.vf v0, v8, fa0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i1> @llvm.riscv.vmfgt.nxv2f32.f32(
- <vscale x 2 x float> %0,
- float %1,
- i64 %2)
-
- ret <vscale x 2 x i1> %a
-}
-
-declare <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2f32.f32(
- <vscale x 2 x i1>,
- <vscale x 2 x float>,
- float,
- <vscale x 2 x i1>,
- i64);
-
-define <vscale x 2 x i1> @intrinsic_vmfgt_mask_vf_nxv2f32_f32(<vscale x 2 x i1> %0, <vscale x 2 x float> %1, float %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv2f32_f32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v10, v0
-; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmfgt.vf v10, v8, fa0, v0.t
-; CHECK-NEXT: vmv.v.v v0, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2f32.f32(
- <vscale x 2 x i1> %0,
- <vscale x 2 x float> %1,
- float %2,
- <vscale x 2 x i1> %3,
- i64 %4)
-
- ret <vscale x 2 x i1> %a
-}
-
-declare <vscale x 4 x i1> @llvm.riscv.vmfgt.nxv4f32.f32(
- <vscale x 4 x float>,
- float,
- i64);
-
-define <vscale x 4 x i1> @intrinsic_vmfgt_vf_nxv4f32_f32(<vscale x 4 x float> %0, float %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmfgt_vf_nxv4f32_f32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vmfgt.vf v0, v8, fa0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i1> @llvm.riscv.vmfgt.nxv4f32.f32(
- <vscale x 4 x float> %0,
- float %1,
- i64 %2)
-
- ret <vscale x 4 x i1> %a
-}
-
-declare <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4f32.f32(
- <vscale x 4 x i1>,
- <vscale x 4 x float>,
- float,
- <vscale x 4 x i1>,
- i64);
-
-define <vscale x 4 x i1> @intrinsic_vmfgt_mask_vf_nxv4f32_f32(<vscale x 4 x i1> %0, <vscale x 4 x float> %1, float %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv4f32_f32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v11, v0
-; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmfgt.vf v11, v8, fa0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v11
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4f32.f32(
- <vscale x 4 x i1> %0,
- <vscale x 4 x float> %1,
- float %2,
- <vscale x 4 x i1> %3,
- i64 %4)
-
- ret <vscale x 4 x i1> %a
-}
-
-declare <vscale x 8 x i1> @llvm.riscv.vmfgt.nxv8f32.f32(
- <vscale x 8 x float>,
- float,
- i64);
-
-define <vscale x 8 x i1> @intrinsic_vmfgt_vf_nxv8f32_f32(<vscale x 8 x float> %0, float %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmfgt_vf_nxv8f32_f32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
-; CHECK-NEXT: vmfgt.vf v0, v8, fa0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i1> @llvm.riscv.vmfgt.nxv8f32.f32(
- <vscale x 8 x float> %0,
- float %1,
- i64 %2)
-
- ret <vscale x 8 x i1> %a
-}
-
-declare <vscale x 8 x i1> @llvm.riscv.vmfgt.mask.nxv8f32.f32(
- <vscale x 8 x i1>,
- <vscale x 8 x float>,
- float,
- <vscale x 8 x i1>,
- i64);
-
-define <vscale x 8 x i1> @intrinsic_vmfgt_mask_vf_nxv8f32_f32(<vscale x 8 x i1> %0, <vscale x 8 x float> %1, float %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv8f32_f32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v13, v0
-; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
-; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmfgt.vf v13, v8, fa0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v13
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i1> @llvm.riscv.vmfgt.mask.nxv8f32.f32(
- <vscale x 8 x i1> %0,
- <vscale x 8 x float> %1,
- float %2,
- <vscale x 8 x i1> %3,
- i64 %4)
-
- ret <vscale x 8 x i1> %a
-}
-
-declare <vscale x 1 x i1> @llvm.riscv.vmfgt.nxv1f64.f64(
- <vscale x 1 x double>,
- double,
- i64);
-
-define <vscale x 1 x i1> @intrinsic_vmfgt_vf_nxv1f64_f64(<vscale x 1 x double> %0, double %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmfgt_vf_nxv1f64_f64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
-; CHECK-NEXT: vmfgt.vf v0, v8, fa0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i1> @llvm.riscv.vmfgt.nxv1f64.f64(
- <vscale x 1 x double> %0,
- double %1,
- i64 %2)
-
- ret <vscale x 1 x i1> %a
-}
-
-declare <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1f64.f64(
- <vscale x 1 x i1>,
- <vscale x 1 x double>,
- double,
- <vscale x 1 x i1>,
- i64);
-
-define <vscale x 1 x i1> @intrinsic_vmfgt_mask_vf_nxv1f64_f64(<vscale x 1 x i1> %0, <vscale x 1 x double> %1, double %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv1f64_f64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v10, v0
-; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
-; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmfgt.vf v10, v8, fa0, v0.t
-; CHECK-NEXT: vmv.v.v v0, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1f64.f64(
- <vscale x 1 x i1> %0,
- <vscale x 1 x double> %1,
- double %2,
- <vscale x 1 x i1> %3,
- i64 %4)
-
- ret <vscale x 1 x i1> %a
-}
-
-declare <vscale x 2 x i1> @llvm.riscv.vmfgt.nxv2f64.f64(
- <vscale x 2 x double>,
- double,
- i64);
-
-define <vscale x 2 x i1> @intrinsic_vmfgt_vf_nxv2f64_f64(<vscale x 2 x double> %0, double %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmfgt_vf_nxv2f64_f64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
-; CHECK-NEXT: vmfgt.vf v0, v8, fa0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i1> @llvm.riscv.vmfgt.nxv2f64.f64(
- <vscale x 2 x double> %0,
- double %1,
- i64 %2)
-
- ret <vscale x 2 x i1> %a
-}
-
-declare <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2f64.f64(
- <vscale x 2 x i1>,
- <vscale x 2 x double>,
- double,
- <vscale x 2 x i1>,
- i64);
-
-define <vscale x 2 x i1> @intrinsic_vmfgt_mask_vf_nxv2f64_f64(<vscale x 2 x i1> %0, <vscale x 2 x double> %1, double %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv2f64_f64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v11, v0
-; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
-; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmfgt.vf v11, v8, fa0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v11
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2f64.f64(
- <vscale x 2 x i1> %0,
- <vscale x 2 x double> %1,
- double %2,
- <vscale x 2 x i1> %3,
- i64 %4)
-
- ret <vscale x 2 x i1> %a
-}
-
-declare <vscale x 4 x i1> @llvm.riscv.vmfgt.nxv4f64.f64(
- <vscale x 4 x double>,
- double,
- i64);
-
-define <vscale x 4 x i1> @intrinsic_vmfgt_vf_nxv4f64_f64(<vscale x 4 x double> %0, double %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmfgt_vf_nxv4f64_f64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
-; CHECK-NEXT: vmfgt.vf v0, v8, fa0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i1> @llvm.riscv.vmfgt.nxv4f64.f64(
- <vscale x 4 x double> %0,
- double %1,
- i64 %2)
-
- ret <vscale x 4 x i1> %a
-}
-
-declare <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4f64.f64(
- <vscale x 4 x i1>,
- <vscale x 4 x double>,
- double,
- <vscale x 4 x i1>,
- i64);
-
-define <vscale x 4 x i1> @intrinsic_vmfgt_mask_vf_nxv4f64_f64(<vscale x 4 x i1> %0, <vscale x 4 x double> %1, double %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv4f64_f64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v13, v0
-; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
-; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmfgt.vf v13, v8, fa0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v13
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4f64.f64(
- <vscale x 4 x i1> %0,
- <vscale x 4 x double> %1,
- double %2,
- <vscale x 4 x i1> %3,
- i64 %4)
-
- ret <vscale x 4 x i1> %a
-}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmfgt-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmfgt.ll
similarity index 88%
rename from llvm/test/CodeGen/RISCV/rvv/vmfgt-rv32.ll
rename to llvm/test/CodeGen/RISCV/rvv/vmfgt.ll
index 2d2567a6b644c..e78a36d37652c 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vmfgt-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vmfgt.ll
@@ -1,12 +1,14 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -mattr=+v,+d,+zfh -verify-machineinstrs \
-; RUN: -target-abi=ilp32d < %s | FileCheck %s
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh \
+; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh \
+; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s
declare <vscale x 1 x i1> @llvm.riscv.vmfgt.nxv1f16(
<vscale x 1 x half>,
<vscale x 1 x half>,
- i32);
+ iXLen);
-define <vscale x 1 x i1> @intrinsic_vmfgt_vv_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i32 %2) nounwind {
+define <vscale x 1 x i1> @intrinsic_vmfgt_vv_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmfgt_vv_nxv1f16_nxv1f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
@@ -16,7 +18,7 @@ entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmfgt.nxv1f16(
<vscale x 1 x half> %0,
<vscale x 1 x half> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 1 x i1> %a
}
@@ -26,9 +28,9 @@ declare <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1f16(
<vscale x 1 x half>,
<vscale x 1 x half>,
<vscale x 1 x i1>,
- i32);
+ iXLen);
-define <vscale x 1 x i1> @intrinsic_vmfgt_mask_vv_nxv1f16_nxv1f16(<vscale x 1 x i1> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x half> %3, i32 %4) nounwind {
+define <vscale x 1 x i1> @intrinsic_vmfgt_mask_vv_nxv1f16_nxv1f16(<vscale x 1 x i1> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x half> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfgt_mask_vv_nxv1f16_nxv1f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
@@ -42,13 +44,13 @@ entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmfgt.nxv1f16(
<vscale x 1 x half> %1,
<vscale x 1 x half> %2,
- i32 %4)
+ iXLen %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1f16(
<vscale x 1 x i1> %0,
<vscale x 1 x half> %2,
<vscale x 1 x half> %3,
<vscale x 1 x i1> %mask,
- i32 %4)
+ iXLen %4)
ret <vscale x 1 x i1> %a
}
@@ -56,9 +58,9 @@ entry:
declare <vscale x 2 x i1> @llvm.riscv.vmfgt.nxv2f16(
<vscale x 2 x half>,
<vscale x 2 x half>,
- i32);
+ iXLen);
-define <vscale x 2 x i1> @intrinsic_vmfgt_vv_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i32 %2) nounwind {
+define <vscale x 2 x i1> @intrinsic_vmfgt_vv_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmfgt_vv_nxv2f16_nxv2f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
@@ -68,7 +70,7 @@ entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmfgt.nxv2f16(
<vscale x 2 x half> %0,
<vscale x 2 x half> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 2 x i1> %a
}
@@ -78,9 +80,9 @@ declare <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2f16(
<vscale x 2 x half>,
<vscale x 2 x half>,
<vscale x 2 x i1>,
- i32);
+ iXLen);
-define <vscale x 2 x i1> @intrinsic_vmfgt_mask_vv_nxv2f16_nxv2f16(<vscale x 2 x i1> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, <vscale x 2 x half> %3, i32 %4) nounwind {
+define <vscale x 2 x i1> @intrinsic_vmfgt_mask_vv_nxv2f16_nxv2f16(<vscale x 2 x i1> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, <vscale x 2 x half> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfgt_mask_vv_nxv2f16_nxv2f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
@@ -94,13 +96,13 @@ entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmfgt.nxv2f16(
<vscale x 2 x half> %1,
<vscale x 2 x half> %2,
- i32 %4)
+ iXLen %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2f16(
<vscale x 2 x i1> %0,
<vscale x 2 x half> %2,
<vscale x 2 x half> %3,
<vscale x 2 x i1> %mask,
- i32 %4)
+ iXLen %4)
ret <vscale x 2 x i1> %a
}
@@ -108,9 +110,9 @@ entry:
declare <vscale x 4 x i1> @llvm.riscv.vmfgt.nxv4f16(
<vscale x 4 x half>,
<vscale x 4 x half>,
- i32);
+ iXLen);
-define <vscale x 4 x i1> @intrinsic_vmfgt_vv_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i32 %2) nounwind {
+define <vscale x 4 x i1> @intrinsic_vmfgt_vv_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmfgt_vv_nxv4f16_nxv4f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
@@ -120,7 +122,7 @@ entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmfgt.nxv4f16(
<vscale x 4 x half> %0,
<vscale x 4 x half> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 4 x i1> %a
}
@@ -130,9 +132,9 @@ declare <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4f16(
<vscale x 4 x half>,
<vscale x 4 x half>,
<vscale x 4 x i1>,
- i32);
+ iXLen);
-define <vscale x 4 x i1> @intrinsic_vmfgt_mask_vv_nxv4f16_nxv4f16(<vscale x 4 x i1> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x half> %3, i32 %4) nounwind {
+define <vscale x 4 x i1> @intrinsic_vmfgt_mask_vv_nxv4f16_nxv4f16(<vscale x 4 x i1> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x half> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfgt_mask_vv_nxv4f16_nxv4f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
@@ -146,13 +148,13 @@ entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmfgt.nxv4f16(
<vscale x 4 x half> %1,
<vscale x 4 x half> %2,
- i32 %4)
+ iXLen %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4f16(
<vscale x 4 x i1> %0,
<vscale x 4 x half> %2,
<vscale x 4 x half> %3,
<vscale x 4 x i1> %mask,
- i32 %4)
+ iXLen %4)
ret <vscale x 4 x i1> %a
}
@@ -160,9 +162,9 @@ entry:
declare <vscale x 8 x i1> @llvm.riscv.vmfgt.nxv8f16(
<vscale x 8 x half>,
<vscale x 8 x half>,
- i32);
+ iXLen);
-define <vscale x 8 x i1> @intrinsic_vmfgt_vv_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i32 %2) nounwind {
+define <vscale x 8 x i1> @intrinsic_vmfgt_vv_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmfgt_vv_nxv8f16_nxv8f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
@@ -172,7 +174,7 @@ entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmfgt.nxv8f16(
<vscale x 8 x half> %0,
<vscale x 8 x half> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 8 x i1> %a
}
@@ -182,9 +184,9 @@ declare <vscale x 8 x i1> @llvm.riscv.vmfgt.mask.nxv8f16(
<vscale x 8 x half>,
<vscale x 8 x half>,
<vscale x 8 x i1>,
- i32);
+ iXLen);
-define <vscale x 8 x i1> @intrinsic_vmfgt_mask_vv_nxv8f16_nxv8f16(<vscale x 8 x i1> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x half> %3, i32 %4) nounwind {
+define <vscale x 8 x i1> @intrinsic_vmfgt_mask_vv_nxv8f16_nxv8f16(<vscale x 8 x i1> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x half> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfgt_mask_vv_nxv8f16_nxv8f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
@@ -198,13 +200,13 @@ entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmfgt.nxv8f16(
<vscale x 8 x half> %1,
<vscale x 8 x half> %2,
- i32 %4)
+ iXLen %4)
%a = call <vscale x 8 x i1> @llvm.riscv.vmfgt.mask.nxv8f16(
<vscale x 8 x i1> %0,
<vscale x 8 x half> %2,
<vscale x 8 x half> %3,
<vscale x 8 x i1> %mask,
- i32 %4)
+ iXLen %4)
ret <vscale x 8 x i1> %a
}
@@ -212,9 +214,9 @@ entry:
declare <vscale x 16 x i1> @llvm.riscv.vmfgt.nxv16f16(
<vscale x 16 x half>,
<vscale x 16 x half>,
- i32);
+ iXLen);
-define <vscale x 16 x i1> @intrinsic_vmfgt_vv_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i32 %2) nounwind {
+define <vscale x 16 x i1> @intrinsic_vmfgt_vv_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmfgt_vv_nxv16f16_nxv16f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
@@ -224,7 +226,7 @@ entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmfgt.nxv16f16(
<vscale x 16 x half> %0,
<vscale x 16 x half> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 16 x i1> %a
}
@@ -234,9 +236,9 @@ declare <vscale x 16 x i1> @llvm.riscv.vmfgt.mask.nxv16f16(
<vscale x 16 x half>,
<vscale x 16 x half>,
<vscale x 16 x i1>,
- i32);
+ iXLen);
-define <vscale x 16 x i1> @intrinsic_vmfgt_mask_vv_nxv16f16_nxv16f16(<vscale x 16 x i1> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, <vscale x 16 x half> %3, i32 %4) nounwind {
+define <vscale x 16 x i1> @intrinsic_vmfgt_mask_vv_nxv16f16_nxv16f16(<vscale x 16 x i1> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, <vscale x 16 x half> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfgt_mask_vv_nxv16f16_nxv16f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
@@ -250,13 +252,13 @@ entry:
%mask = call <vscale x 16 x i1> @llvm.riscv.vmfgt.nxv16f16(
<vscale x 16 x half> %1,
<vscale x 16 x half> %2,
- i32 %4)
+ iXLen %4)
%a = call <vscale x 16 x i1> @llvm.riscv.vmfgt.mask.nxv16f16(
<vscale x 16 x i1> %0,
<vscale x 16 x half> %2,
<vscale x 16 x half> %3,
<vscale x 16 x i1> %mask,
- i32 %4)
+ iXLen %4)
ret <vscale x 16 x i1> %a
}
@@ -264,9 +266,9 @@ entry:
declare <vscale x 1 x i1> @llvm.riscv.vmfgt.nxv1f32(
<vscale x 1 x float>,
<vscale x 1 x float>,
- i32);
+ iXLen);
-define <vscale x 1 x i1> @intrinsic_vmfgt_vv_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, i32 %2) nounwind {
+define <vscale x 1 x i1> @intrinsic_vmfgt_vv_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmfgt_vv_nxv1f32_nxv1f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
@@ -276,7 +278,7 @@ entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmfgt.nxv1f32(
<vscale x 1 x float> %0,
<vscale x 1 x float> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 1 x i1> %a
}
@@ -286,9 +288,9 @@ declare <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1f32(
<vscale x 1 x float>,
<vscale x 1 x float>,
<vscale x 1 x i1>,
- i32);
+ iXLen);
-define <vscale x 1 x i1> @intrinsic_vmfgt_mask_vv_nxv1f32_nxv1f32(<vscale x 1 x i1> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, <vscale x 1 x float> %3, i32 %4) nounwind {
+define <vscale x 1 x i1> @intrinsic_vmfgt_mask_vv_nxv1f32_nxv1f32(<vscale x 1 x i1> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, <vscale x 1 x float> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfgt_mask_vv_nxv1f32_nxv1f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
@@ -302,13 +304,13 @@ entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmfgt.nxv1f32(
<vscale x 1 x float> %1,
<vscale x 1 x float> %2,
- i32 %4)
+ iXLen %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1f32(
<vscale x 1 x i1> %0,
<vscale x 1 x float> %2,
<vscale x 1 x float> %3,
<vscale x 1 x i1> %mask,
- i32 %4)
+ iXLen %4)
ret <vscale x 1 x i1> %a
}
@@ -316,9 +318,9 @@ entry:
declare <vscale x 2 x i1> @llvm.riscv.vmfgt.nxv2f32(
<vscale x 2 x float>,
<vscale x 2 x float>,
- i32);
+ iXLen);
-define <vscale x 2 x i1> @intrinsic_vmfgt_vv_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, i32 %2) nounwind {
+define <vscale x 2 x i1> @intrinsic_vmfgt_vv_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmfgt_vv_nxv2f32_nxv2f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
@@ -328,7 +330,7 @@ entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmfgt.nxv2f32(
<vscale x 2 x float> %0,
<vscale x 2 x float> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 2 x i1> %a
}
@@ -338,9 +340,9 @@ declare <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2f32(
<vscale x 2 x float>,
<vscale x 2 x float>,
<vscale x 2 x i1>,
- i32);
+ iXLen);
-define <vscale x 2 x i1> @intrinsic_vmfgt_mask_vv_nxv2f32_nxv2f32(<vscale x 2 x i1> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x float> %3, i32 %4) nounwind {
+define <vscale x 2 x i1> @intrinsic_vmfgt_mask_vv_nxv2f32_nxv2f32(<vscale x 2 x i1> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x float> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfgt_mask_vv_nxv2f32_nxv2f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
@@ -354,13 +356,13 @@ entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmfgt.nxv2f32(
<vscale x 2 x float> %1,
<vscale x 2 x float> %2,
- i32 %4)
+ iXLen %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2f32(
<vscale x 2 x i1> %0,
<vscale x 2 x float> %2,
<vscale x 2 x float> %3,
<vscale x 2 x i1> %mask,
- i32 %4)
+ iXLen %4)
ret <vscale x 2 x i1> %a
}
@@ -368,9 +370,9 @@ entry:
declare <vscale x 4 x i1> @llvm.riscv.vmfgt.nxv4f32(
<vscale x 4 x float>,
<vscale x 4 x float>,
- i32);
+ iXLen);
-define <vscale x 4 x i1> @intrinsic_vmfgt_vv_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, i32 %2) nounwind {
+define <vscale x 4 x i1> @intrinsic_vmfgt_vv_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmfgt_vv_nxv4f32_nxv4f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
@@ -380,7 +382,7 @@ entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmfgt.nxv4f32(
<vscale x 4 x float> %0,
<vscale x 4 x float> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 4 x i1> %a
}
@@ -390,9 +392,9 @@ declare <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4f32(
<vscale x 4 x float>,
<vscale x 4 x float>,
<vscale x 4 x i1>,
- i32);
+ iXLen);
-define <vscale x 4 x i1> @intrinsic_vmfgt_mask_vv_nxv4f32_nxv4f32(<vscale x 4 x i1> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x float> %3, i32 %4) nounwind {
+define <vscale x 4 x i1> @intrinsic_vmfgt_mask_vv_nxv4f32_nxv4f32(<vscale x 4 x i1> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x float> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfgt_mask_vv_nxv4f32_nxv4f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
@@ -406,13 +408,13 @@ entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmfgt.nxv4f32(
<vscale x 4 x float> %1,
<vscale x 4 x float> %2,
- i32 %4)
+ iXLen %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4f32(
<vscale x 4 x i1> %0,
<vscale x 4 x float> %2,
<vscale x 4 x float> %3,
<vscale x 4 x i1> %mask,
- i32 %4)
+ iXLen %4)
ret <vscale x 4 x i1> %a
}
@@ -420,9 +422,9 @@ entry:
declare <vscale x 8 x i1> @llvm.riscv.vmfgt.nxv8f32(
<vscale x 8 x float>,
<vscale x 8 x float>,
- i32);
+ iXLen);
-define <vscale x 8 x i1> @intrinsic_vmfgt_vv_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, i32 %2) nounwind {
+define <vscale x 8 x i1> @intrinsic_vmfgt_vv_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmfgt_vv_nxv8f32_nxv8f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
@@ -432,7 +434,7 @@ entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmfgt.nxv8f32(
<vscale x 8 x float> %0,
<vscale x 8 x float> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 8 x i1> %a
}
@@ -442,9 +444,9 @@ declare <vscale x 8 x i1> @llvm.riscv.vmfgt.mask.nxv8f32(
<vscale x 8 x float>,
<vscale x 8 x float>,
<vscale x 8 x i1>,
- i32);
+ iXLen);
-define <vscale x 8 x i1> @intrinsic_vmfgt_mask_vv_nxv8f32_nxv8f32(<vscale x 8 x i1> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, <vscale x 8 x float> %3, i32 %4) nounwind {
+define <vscale x 8 x i1> @intrinsic_vmfgt_mask_vv_nxv8f32_nxv8f32(<vscale x 8 x i1> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, <vscale x 8 x float> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfgt_mask_vv_nxv8f32_nxv8f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
@@ -458,13 +460,13 @@ entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmfgt.nxv8f32(
<vscale x 8 x float> %1,
<vscale x 8 x float> %2,
- i32 %4)
+ iXLen %4)
%a = call <vscale x 8 x i1> @llvm.riscv.vmfgt.mask.nxv8f32(
<vscale x 8 x i1> %0,
<vscale x 8 x float> %2,
<vscale x 8 x float> %3,
<vscale x 8 x i1> %mask,
- i32 %4)
+ iXLen %4)
ret <vscale x 8 x i1> %a
}
@@ -472,9 +474,9 @@ entry:
declare <vscale x 1 x i1> @llvm.riscv.vmfgt.nxv1f64(
<vscale x 1 x double>,
<vscale x 1 x double>,
- i32);
+ iXLen);
-define <vscale x 1 x i1> @intrinsic_vmfgt_vv_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, i32 %2) nounwind {
+define <vscale x 1 x i1> @intrinsic_vmfgt_vv_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmfgt_vv_nxv1f64_nxv1f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
@@ -484,7 +486,7 @@ entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmfgt.nxv1f64(
<vscale x 1 x double> %0,
<vscale x 1 x double> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 1 x i1> %a
}
@@ -494,9 +496,9 @@ declare <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1f64(
<vscale x 1 x double>,
<vscale x 1 x double>,
<vscale x 1 x i1>,
- i32);
+ iXLen);
-define <vscale x 1 x i1> @intrinsic_vmfgt_mask_vv_nxv1f64_nxv1f64(<vscale x 1 x i1> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, <vscale x 1 x double> %3, i32 %4) nounwind {
+define <vscale x 1 x i1> @intrinsic_vmfgt_mask_vv_nxv1f64_nxv1f64(<vscale x 1 x i1> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, <vscale x 1 x double> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfgt_mask_vv_nxv1f64_nxv1f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
@@ -510,13 +512,13 @@ entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmfgt.nxv1f64(
<vscale x 1 x double> %1,
<vscale x 1 x double> %2,
- i32 %4)
+ iXLen %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1f64(
<vscale x 1 x i1> %0,
<vscale x 1 x double> %2,
<vscale x 1 x double> %3,
<vscale x 1 x i1> %mask,
- i32 %4)
+ iXLen %4)
ret <vscale x 1 x i1> %a
}
@@ -524,9 +526,9 @@ entry:
declare <vscale x 2 x i1> @llvm.riscv.vmfgt.nxv2f64(
<vscale x 2 x double>,
<vscale x 2 x double>,
- i32);
+ iXLen);
-define <vscale x 2 x i1> @intrinsic_vmfgt_vv_nxv2f64_nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, i32 %2) nounwind {
+define <vscale x 2 x i1> @intrinsic_vmfgt_vv_nxv2f64_nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmfgt_vv_nxv2f64_nxv2f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
@@ -536,7 +538,7 @@ entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmfgt.nxv2f64(
<vscale x 2 x double> %0,
<vscale x 2 x double> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 2 x i1> %a
}
@@ -546,9 +548,9 @@ declare <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2f64(
<vscale x 2 x double>,
<vscale x 2 x double>,
<vscale x 2 x i1>,
- i32);
+ iXLen);
-define <vscale x 2 x i1> @intrinsic_vmfgt_mask_vv_nxv2f64_nxv2f64(<vscale x 2 x i1> %0, <vscale x 2 x double> %1, <vscale x 2 x double> %2, <vscale x 2 x double> %3, i32 %4) nounwind {
+define <vscale x 2 x i1> @intrinsic_vmfgt_mask_vv_nxv2f64_nxv2f64(<vscale x 2 x i1> %0, <vscale x 2 x double> %1, <vscale x 2 x double> %2, <vscale x 2 x double> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfgt_mask_vv_nxv2f64_nxv2f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
@@ -562,13 +564,13 @@ entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmfgt.nxv2f64(
<vscale x 2 x double> %1,
<vscale x 2 x double> %2,
- i32 %4)
+ iXLen %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2f64(
<vscale x 2 x i1> %0,
<vscale x 2 x double> %2,
<vscale x 2 x double> %3,
<vscale x 2 x i1> %mask,
- i32 %4)
+ iXLen %4)
ret <vscale x 2 x i1> %a
}
@@ -576,9 +578,9 @@ entry:
declare <vscale x 4 x i1> @llvm.riscv.vmfgt.nxv4f64(
<vscale x 4 x double>,
<vscale x 4 x double>,
- i32);
+ iXLen);
-define <vscale x 4 x i1> @intrinsic_vmfgt_vv_nxv4f64_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, i32 %2) nounwind {
+define <vscale x 4 x i1> @intrinsic_vmfgt_vv_nxv4f64_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmfgt_vv_nxv4f64_nxv4f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
@@ -588,7 +590,7 @@ entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmfgt.nxv4f64(
<vscale x 4 x double> %0,
<vscale x 4 x double> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 4 x i1> %a
}
@@ -598,9 +600,9 @@ declare <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4f64(
<vscale x 4 x double>,
<vscale x 4 x double>,
<vscale x 4 x i1>,
- i32);
+ iXLen);
-define <vscale x 4 x i1> @intrinsic_vmfgt_mask_vv_nxv4f64_nxv4f64(<vscale x 4 x i1> %0, <vscale x 4 x double> %1, <vscale x 4 x double> %2, <vscale x 4 x double> %3, i32 %4) nounwind {
+define <vscale x 4 x i1> @intrinsic_vmfgt_mask_vv_nxv4f64_nxv4f64(<vscale x 4 x i1> %0, <vscale x 4 x double> %1, <vscale x 4 x double> %2, <vscale x 4 x double> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfgt_mask_vv_nxv4f64_nxv4f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
@@ -614,13 +616,13 @@ entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmfgt.nxv4f64(
<vscale x 4 x double> %1,
<vscale x 4 x double> %2,
- i32 %4)
+ iXLen %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4f64(
<vscale x 4 x i1> %0,
<vscale x 4 x double> %2,
<vscale x 4 x double> %3,
<vscale x 4 x i1> %mask,
- i32 %4)
+ iXLen %4)
ret <vscale x 4 x i1> %a
}
@@ -628,9 +630,9 @@ entry:
declare <vscale x 1 x i1> @llvm.riscv.vmfgt.nxv1f16.f16(
<vscale x 1 x half>,
half,
- i32);
+ iXLen);
-define <vscale x 1 x i1> @intrinsic_vmfgt_vf_nxv1f16_f16(<vscale x 1 x half> %0, half %1, i32 %2) nounwind {
+define <vscale x 1 x i1> @intrinsic_vmfgt_vf_nxv1f16_f16(<vscale x 1 x half> %0, half %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmfgt_vf_nxv1f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
@@ -640,7 +642,7 @@ entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmfgt.nxv1f16.f16(
<vscale x 1 x half> %0,
half %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 1 x i1> %a
}
@@ -650,9 +652,9 @@ declare <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1f16.f16(
<vscale x 1 x half>,
half,
<vscale x 1 x i1>,
- i32);
+ iXLen);
-define <vscale x 1 x i1> @intrinsic_vmfgt_mask_vf_nxv1f16_f16(<vscale x 1 x i1> %0, <vscale x 1 x half> %1, half %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+define <vscale x 1 x i1> @intrinsic_vmfgt_mask_vf_nxv1f16_f16(<vscale x 1 x i1> %0, <vscale x 1 x half> %1, half %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv1f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0
@@ -667,7 +669,7 @@ entry:
<vscale x 1 x half> %1,
half %2,
<vscale x 1 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 1 x i1> %a
}
@@ -675,9 +677,9 @@ entry:
declare <vscale x 2 x i1> @llvm.riscv.vmfgt.nxv2f16.f16(
<vscale x 2 x half>,
half,
- i32);
+ iXLen);
-define <vscale x 2 x i1> @intrinsic_vmfgt_vf_nxv2f16_f16(<vscale x 2 x half> %0, half %1, i32 %2) nounwind {
+define <vscale x 2 x i1> @intrinsic_vmfgt_vf_nxv2f16_f16(<vscale x 2 x half> %0, half %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmfgt_vf_nxv2f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
@@ -687,7 +689,7 @@ entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmfgt.nxv2f16.f16(
<vscale x 2 x half> %0,
half %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 2 x i1> %a
}
@@ -697,9 +699,9 @@ declare <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2f16.f16(
<vscale x 2 x half>,
half,
<vscale x 2 x i1>,
- i32);
+ iXLen);
-define <vscale x 2 x i1> @intrinsic_vmfgt_mask_vf_nxv2f16_f16(<vscale x 2 x i1> %0, <vscale x 2 x half> %1, half %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+define <vscale x 2 x i1> @intrinsic_vmfgt_mask_vf_nxv2f16_f16(<vscale x 2 x i1> %0, <vscale x 2 x half> %1, half %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv2f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0
@@ -714,7 +716,7 @@ entry:
<vscale x 2 x half> %1,
half %2,
<vscale x 2 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 2 x i1> %a
}
@@ -722,9 +724,9 @@ entry:
declare <vscale x 4 x i1> @llvm.riscv.vmfgt.nxv4f16.f16(
<vscale x 4 x half>,
half,
- i32);
+ iXLen);
-define <vscale x 4 x i1> @intrinsic_vmfgt_vf_nxv4f16_f16(<vscale x 4 x half> %0, half %1, i32 %2) nounwind {
+define <vscale x 4 x i1> @intrinsic_vmfgt_vf_nxv4f16_f16(<vscale x 4 x half> %0, half %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmfgt_vf_nxv4f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
@@ -734,7 +736,7 @@ entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmfgt.nxv4f16.f16(
<vscale x 4 x half> %0,
half %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 4 x i1> %a
}
@@ -744,9 +746,9 @@ declare <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4f16.f16(
<vscale x 4 x half>,
half,
<vscale x 4 x i1>,
- i32);
+ iXLen);
-define <vscale x 4 x i1> @intrinsic_vmfgt_mask_vf_nxv4f16_f16(<vscale x 4 x i1> %0, <vscale x 4 x half> %1, half %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+define <vscale x 4 x i1> @intrinsic_vmfgt_mask_vf_nxv4f16_f16(<vscale x 4 x i1> %0, <vscale x 4 x half> %1, half %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv4f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0
@@ -761,7 +763,7 @@ entry:
<vscale x 4 x half> %1,
half %2,
<vscale x 4 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 4 x i1> %a
}
@@ -769,9 +771,9 @@ entry:
declare <vscale x 8 x i1> @llvm.riscv.vmfgt.nxv8f16.f16(
<vscale x 8 x half>,
half,
- i32);
+ iXLen);
-define <vscale x 8 x i1> @intrinsic_vmfgt_vf_nxv8f16_f16(<vscale x 8 x half> %0, half %1, i32 %2) nounwind {
+define <vscale x 8 x i1> @intrinsic_vmfgt_vf_nxv8f16_f16(<vscale x 8 x half> %0, half %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmfgt_vf_nxv8f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
@@ -781,7 +783,7 @@ entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmfgt.nxv8f16.f16(
<vscale x 8 x half> %0,
half %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 8 x i1> %a
}
@@ -791,9 +793,9 @@ declare <vscale x 8 x i1> @llvm.riscv.vmfgt.mask.nxv8f16.f16(
<vscale x 8 x half>,
half,
<vscale x 8 x i1>,
- i32);
+ iXLen);
-define <vscale x 8 x i1> @intrinsic_vmfgt_mask_vf_nxv8f16_f16(<vscale x 8 x i1> %0, <vscale x 8 x half> %1, half %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+define <vscale x 8 x i1> @intrinsic_vmfgt_mask_vf_nxv8f16_f16(<vscale x 8 x i1> %0, <vscale x 8 x half> %1, half %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv8f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v11, v0
@@ -808,7 +810,7 @@ entry:
<vscale x 8 x half> %1,
half %2,
<vscale x 8 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 8 x i1> %a
}
@@ -816,9 +818,9 @@ entry:
declare <vscale x 16 x i1> @llvm.riscv.vmfgt.nxv16f16.f16(
<vscale x 16 x half>,
half,
- i32);
+ iXLen);
-define <vscale x 16 x i1> @intrinsic_vmfgt_vf_nxv16f16_f16(<vscale x 16 x half> %0, half %1, i32 %2) nounwind {
+define <vscale x 16 x i1> @intrinsic_vmfgt_vf_nxv16f16_f16(<vscale x 16 x half> %0, half %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmfgt_vf_nxv16f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
@@ -828,7 +830,7 @@ entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmfgt.nxv16f16.f16(
<vscale x 16 x half> %0,
half %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 16 x i1> %a
}
@@ -838,9 +840,9 @@ declare <vscale x 16 x i1> @llvm.riscv.vmfgt.mask.nxv16f16.f16(
<vscale x 16 x half>,
half,
<vscale x 16 x i1>,
- i32);
+ iXLen);
-define <vscale x 16 x i1> @intrinsic_vmfgt_mask_vf_nxv16f16_f16(<vscale x 16 x i1> %0, <vscale x 16 x half> %1, half %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+define <vscale x 16 x i1> @intrinsic_vmfgt_mask_vf_nxv16f16_f16(<vscale x 16 x i1> %0, <vscale x 16 x half> %1, half %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv16f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v13, v0
@@ -855,7 +857,7 @@ entry:
<vscale x 16 x half> %1,
half %2,
<vscale x 16 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 16 x i1> %a
}
@@ -863,9 +865,9 @@ entry:
declare <vscale x 1 x i1> @llvm.riscv.vmfgt.nxv1f32.f32(
<vscale x 1 x float>,
float,
- i32);
+ iXLen);
-define <vscale x 1 x i1> @intrinsic_vmfgt_vf_nxv1f32_f32(<vscale x 1 x float> %0, float %1, i32 %2) nounwind {
+define <vscale x 1 x i1> @intrinsic_vmfgt_vf_nxv1f32_f32(<vscale x 1 x float> %0, float %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmfgt_vf_nxv1f32_f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
@@ -875,7 +877,7 @@ entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmfgt.nxv1f32.f32(
<vscale x 1 x float> %0,
float %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 1 x i1> %a
}
@@ -885,9 +887,9 @@ declare <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1f32.f32(
<vscale x 1 x float>,
float,
<vscale x 1 x i1>,
- i32);
+ iXLen);
-define <vscale x 1 x i1> @intrinsic_vmfgt_mask_vf_nxv1f32_f32(<vscale x 1 x i1> %0, <vscale x 1 x float> %1, float %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+define <vscale x 1 x i1> @intrinsic_vmfgt_mask_vf_nxv1f32_f32(<vscale x 1 x i1> %0, <vscale x 1 x float> %1, float %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv1f32_f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0
@@ -902,7 +904,7 @@ entry:
<vscale x 1 x float> %1,
float %2,
<vscale x 1 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 1 x i1> %a
}
@@ -910,9 +912,9 @@ entry:
declare <vscale x 2 x i1> @llvm.riscv.vmfgt.nxv2f32.f32(
<vscale x 2 x float>,
float,
- i32);
+ iXLen);
-define <vscale x 2 x i1> @intrinsic_vmfgt_vf_nxv2f32_f32(<vscale x 2 x float> %0, float %1, i32 %2) nounwind {
+define <vscale x 2 x i1> @intrinsic_vmfgt_vf_nxv2f32_f32(<vscale x 2 x float> %0, float %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmfgt_vf_nxv2f32_f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
@@ -922,7 +924,7 @@ entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmfgt.nxv2f32.f32(
<vscale x 2 x float> %0,
float %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 2 x i1> %a
}
@@ -932,9 +934,9 @@ declare <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2f32.f32(
<vscale x 2 x float>,
float,
<vscale x 2 x i1>,
- i32);
+ iXLen);
-define <vscale x 2 x i1> @intrinsic_vmfgt_mask_vf_nxv2f32_f32(<vscale x 2 x i1> %0, <vscale x 2 x float> %1, float %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+define <vscale x 2 x i1> @intrinsic_vmfgt_mask_vf_nxv2f32_f32(<vscale x 2 x i1> %0, <vscale x 2 x float> %1, float %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv2f32_f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0
@@ -949,7 +951,7 @@ entry:
<vscale x 2 x float> %1,
float %2,
<vscale x 2 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 2 x i1> %a
}
@@ -957,9 +959,9 @@ entry:
declare <vscale x 4 x i1> @llvm.riscv.vmfgt.nxv4f32.f32(
<vscale x 4 x float>,
float,
- i32);
+ iXLen);
-define <vscale x 4 x i1> @intrinsic_vmfgt_vf_nxv4f32_f32(<vscale x 4 x float> %0, float %1, i32 %2) nounwind {
+define <vscale x 4 x i1> @intrinsic_vmfgt_vf_nxv4f32_f32(<vscale x 4 x float> %0, float %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmfgt_vf_nxv4f32_f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
@@ -969,7 +971,7 @@ entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmfgt.nxv4f32.f32(
<vscale x 4 x float> %0,
float %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 4 x i1> %a
}
@@ -979,9 +981,9 @@ declare <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4f32.f32(
<vscale x 4 x float>,
float,
<vscale x 4 x i1>,
- i32);
+ iXLen);
-define <vscale x 4 x i1> @intrinsic_vmfgt_mask_vf_nxv4f32_f32(<vscale x 4 x i1> %0, <vscale x 4 x float> %1, float %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+define <vscale x 4 x i1> @intrinsic_vmfgt_mask_vf_nxv4f32_f32(<vscale x 4 x i1> %0, <vscale x 4 x float> %1, float %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv4f32_f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v11, v0
@@ -996,7 +998,7 @@ entry:
<vscale x 4 x float> %1,
float %2,
<vscale x 4 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 4 x i1> %a
}
@@ -1004,9 +1006,9 @@ entry:
declare <vscale x 8 x i1> @llvm.riscv.vmfgt.nxv8f32.f32(
<vscale x 8 x float>,
float,
- i32);
+ iXLen);
-define <vscale x 8 x i1> @intrinsic_vmfgt_vf_nxv8f32_f32(<vscale x 8 x float> %0, float %1, i32 %2) nounwind {
+define <vscale x 8 x i1> @intrinsic_vmfgt_vf_nxv8f32_f32(<vscale x 8 x float> %0, float %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmfgt_vf_nxv8f32_f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
@@ -1016,7 +1018,7 @@ entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmfgt.nxv8f32.f32(
<vscale x 8 x float> %0,
float %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 8 x i1> %a
}
@@ -1026,9 +1028,9 @@ declare <vscale x 8 x i1> @llvm.riscv.vmfgt.mask.nxv8f32.f32(
<vscale x 8 x float>,
float,
<vscale x 8 x i1>,
- i32);
+ iXLen);
-define <vscale x 8 x i1> @intrinsic_vmfgt_mask_vf_nxv8f32_f32(<vscale x 8 x i1> %0, <vscale x 8 x float> %1, float %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+define <vscale x 8 x i1> @intrinsic_vmfgt_mask_vf_nxv8f32_f32(<vscale x 8 x i1> %0, <vscale x 8 x float> %1, float %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv8f32_f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v13, v0
@@ -1043,7 +1045,7 @@ entry:
<vscale x 8 x float> %1,
float %2,
<vscale x 8 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 8 x i1> %a
}
@@ -1051,9 +1053,9 @@ entry:
declare <vscale x 1 x i1> @llvm.riscv.vmfgt.nxv1f64.f64(
<vscale x 1 x double>,
double,
- i32);
+ iXLen);
-define <vscale x 1 x i1> @intrinsic_vmfgt_vf_nxv1f64_f64(<vscale x 1 x double> %0, double %1, i32 %2) nounwind {
+define <vscale x 1 x i1> @intrinsic_vmfgt_vf_nxv1f64_f64(<vscale x 1 x double> %0, double %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmfgt_vf_nxv1f64_f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
@@ -1063,7 +1065,7 @@ entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmfgt.nxv1f64.f64(
<vscale x 1 x double> %0,
double %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 1 x i1> %a
}
@@ -1073,9 +1075,9 @@ declare <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1f64.f64(
<vscale x 1 x double>,
double,
<vscale x 1 x i1>,
- i32);
+ iXLen);
-define <vscale x 1 x i1> @intrinsic_vmfgt_mask_vf_nxv1f64_f64(<vscale x 1 x i1> %0, <vscale x 1 x double> %1, double %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+define <vscale x 1 x i1> @intrinsic_vmfgt_mask_vf_nxv1f64_f64(<vscale x 1 x i1> %0, <vscale x 1 x double> %1, double %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv1f64_f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0
@@ -1090,7 +1092,7 @@ entry:
<vscale x 1 x double> %1,
double %2,
<vscale x 1 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 1 x i1> %a
}
@@ -1098,9 +1100,9 @@ entry:
declare <vscale x 2 x i1> @llvm.riscv.vmfgt.nxv2f64.f64(
<vscale x 2 x double>,
double,
- i32);
+ iXLen);
-define <vscale x 2 x i1> @intrinsic_vmfgt_vf_nxv2f64_f64(<vscale x 2 x double> %0, double %1, i32 %2) nounwind {
+define <vscale x 2 x i1> @intrinsic_vmfgt_vf_nxv2f64_f64(<vscale x 2 x double> %0, double %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmfgt_vf_nxv2f64_f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
@@ -1110,7 +1112,7 @@ entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmfgt.nxv2f64.f64(
<vscale x 2 x double> %0,
double %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 2 x i1> %a
}
@@ -1120,9 +1122,9 @@ declare <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2f64.f64(
<vscale x 2 x double>,
double,
<vscale x 2 x i1>,
- i32);
+ iXLen);
-define <vscale x 2 x i1> @intrinsic_vmfgt_mask_vf_nxv2f64_f64(<vscale x 2 x i1> %0, <vscale x 2 x double> %1, double %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+define <vscale x 2 x i1> @intrinsic_vmfgt_mask_vf_nxv2f64_f64(<vscale x 2 x i1> %0, <vscale x 2 x double> %1, double %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv2f64_f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v11, v0
@@ -1137,7 +1139,7 @@ entry:
<vscale x 2 x double> %1,
double %2,
<vscale x 2 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 2 x i1> %a
}
@@ -1145,9 +1147,9 @@ entry:
declare <vscale x 4 x i1> @llvm.riscv.vmfgt.nxv4f64.f64(
<vscale x 4 x double>,
double,
- i32);
+ iXLen);
-define <vscale x 4 x i1> @intrinsic_vmfgt_vf_nxv4f64_f64(<vscale x 4 x double> %0, double %1, i32 %2) nounwind {
+define <vscale x 4 x i1> @intrinsic_vmfgt_vf_nxv4f64_f64(<vscale x 4 x double> %0, double %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmfgt_vf_nxv4f64_f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
@@ -1157,7 +1159,7 @@ entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmfgt.nxv4f64.f64(
<vscale x 4 x double> %0,
double %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 4 x i1> %a
}
@@ -1167,9 +1169,9 @@ declare <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4f64.f64(
<vscale x 4 x double>,
double,
<vscale x 4 x i1>,
- i32);
+ iXLen);
-define <vscale x 4 x i1> @intrinsic_vmfgt_mask_vf_nxv4f64_f64(<vscale x 4 x i1> %0, <vscale x 4 x double> %1, double %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+define <vscale x 4 x i1> @intrinsic_vmfgt_mask_vf_nxv4f64_f64(<vscale x 4 x i1> %0, <vscale x 4 x double> %1, double %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv4f64_f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v13, v0
@@ -1184,7 +1186,7 @@ entry:
<vscale x 4 x double> %1,
double %2,
<vscale x 4 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 4 x i1> %a
}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmfle-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vmfle-rv64.ll
deleted file mode 100644
index 0fa7e7ae6c265..0000000000000
--- a/llvm/test/CodeGen/RISCV/rvv/vmfle-rv64.ll
+++ /dev/null
@@ -1,1190 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv64 -mattr=+v,+d,+zfh -verify-machineinstrs \
-; RUN: -target-abi=lp64d < %s | FileCheck %s
-declare <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f16(
- <vscale x 1 x half>,
- <vscale x 1 x half>,
- i64);
-
-define <vscale x 1 x i1> @intrinsic_vmfle_vv_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmfle_vv_nxv1f16_nxv1f16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vmfle.vv v0, v8, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f16(
- <vscale x 1 x half> %0,
- <vscale x 1 x half> %1,
- i64 %2)
-
- ret <vscale x 1 x i1> %a
-}
-
-declare <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f16(
- <vscale x 1 x i1>,
- <vscale x 1 x half>,
- <vscale x 1 x half>,
- <vscale x 1 x i1>,
- i64);
-
-define <vscale x 1 x i1> @intrinsic_vmfle_mask_vv_nxv1f16_nxv1f16(<vscale x 1 x i1> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x half> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv1f16_nxv1f16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vmfle.vv v8, v8, v9
-; CHECK-NEXT: vmv1r.v v11, v0
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmfle.vv v11, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v11
-; CHECK-NEXT: ret
-entry:
- %mask = call <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f16(
- <vscale x 1 x half> %1,
- <vscale x 1 x half> %2,
- i64 %4)
- %a = call <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f16(
- <vscale x 1 x i1> %0,
- <vscale x 1 x half> %2,
- <vscale x 1 x half> %3,
- <vscale x 1 x i1> %mask,
- i64 %4)
-
- ret <vscale x 1 x i1> %a
-}
-
-declare <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2f16(
- <vscale x 2 x half>,
- <vscale x 2 x half>,
- i64);
-
-define <vscale x 2 x i1> @intrinsic_vmfle_vv_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmfle_vv_nxv2f16_nxv2f16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vmfle.vv v0, v8, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2f16(
- <vscale x 2 x half> %0,
- <vscale x 2 x half> %1,
- i64 %2)
-
- ret <vscale x 2 x i1> %a
-}
-
-declare <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2f16(
- <vscale x 2 x i1>,
- <vscale x 2 x half>,
- <vscale x 2 x half>,
- <vscale x 2 x i1>,
- i64);
-
-define <vscale x 2 x i1> @intrinsic_vmfle_mask_vv_nxv2f16_nxv2f16(<vscale x 2 x i1> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, <vscale x 2 x half> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv2f16_nxv2f16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vmfle.vv v8, v8, v9
-; CHECK-NEXT: vmv1r.v v11, v0
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmfle.vv v11, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v11
-; CHECK-NEXT: ret
-entry:
- %mask = call <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2f16(
- <vscale x 2 x half> %1,
- <vscale x 2 x half> %2,
- i64 %4)
- %a = call <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2f16(
- <vscale x 2 x i1> %0,
- <vscale x 2 x half> %2,
- <vscale x 2 x half> %3,
- <vscale x 2 x i1> %mask,
- i64 %4)
-
- ret <vscale x 2 x i1> %a
-}
-
-declare <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4f16(
- <vscale x 4 x half>,
- <vscale x 4 x half>,
- i64);
-
-define <vscale x 4 x i1> @intrinsic_vmfle_vv_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmfle_vv_nxv4f16_nxv4f16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vmfle.vv v0, v8, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4f16(
- <vscale x 4 x half> %0,
- <vscale x 4 x half> %1,
- i64 %2)
-
- ret <vscale x 4 x i1> %a
-}
-
-declare <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4f16(
- <vscale x 4 x i1>,
- <vscale x 4 x half>,
- <vscale x 4 x half>,
- <vscale x 4 x i1>,
- i64);
-
-define <vscale x 4 x i1> @intrinsic_vmfle_mask_vv_nxv4f16_nxv4f16(<vscale x 4 x i1> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x half> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv4f16_nxv4f16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vmfle.vv v8, v8, v9
-; CHECK-NEXT: vmv1r.v v11, v0
-; CHECK-NEXT: vmv.v.v v0, v8
-; CHECK-NEXT: vmfle.vv v11, v9, v10, v0.t
-; CHECK-NEXT: vmv.v.v v0, v11
-; CHECK-NEXT: ret
-entry:
- %mask = call <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4f16(
- <vscale x 4 x half> %1,
- <vscale x 4 x half> %2,
- i64 %4)
- %a = call <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4f16(
- <vscale x 4 x i1> %0,
- <vscale x 4 x half> %2,
- <vscale x 4 x half> %3,
- <vscale x 4 x i1> %mask,
- i64 %4)
-
- ret <vscale x 4 x i1> %a
-}
-
-declare <vscale x 8 x i1> @llvm.riscv.vmfle.nxv8f16(
- <vscale x 8 x half>,
- <vscale x 8 x half>,
- i64);
-
-define <vscale x 8 x i1> @intrinsic_vmfle_vv_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmfle_vv_nxv8f16_nxv8f16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vmfle.vv v0, v8, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i1> @llvm.riscv.vmfle.nxv8f16(
- <vscale x 8 x half> %0,
- <vscale x 8 x half> %1,
- i64 %2)
-
- ret <vscale x 8 x i1> %a
-}
-
-declare <vscale x 8 x i1> @llvm.riscv.vmfle.mask.nxv8f16(
- <vscale x 8 x i1>,
- <vscale x 8 x half>,
- <vscale x 8 x half>,
- <vscale x 8 x i1>,
- i64);
-
-define <vscale x 8 x i1> @intrinsic_vmfle_mask_vv_nxv8f16_nxv8f16(<vscale x 8 x i1> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x half> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv8f16_nxv8f16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vmfle.vv v14, v8, v10
-; CHECK-NEXT: vmv1r.v v8, v0
-; CHECK-NEXT: vmv1r.v v0, v14
-; CHECK-NEXT: vmfle.vv v8, v10, v12, v0.t
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: ret
-entry:
- %mask = call <vscale x 8 x i1> @llvm.riscv.vmfle.nxv8f16(
- <vscale x 8 x half> %1,
- <vscale x 8 x half> %2,
- i64 %4)
- %a = call <vscale x 8 x i1> @llvm.riscv.vmfle.mask.nxv8f16(
- <vscale x 8 x i1> %0,
- <vscale x 8 x half> %2,
- <vscale x 8 x half> %3,
- <vscale x 8 x i1> %mask,
- i64 %4)
-
- ret <vscale x 8 x i1> %a
-}
-
-declare <vscale x 16 x i1> @llvm.riscv.vmfle.nxv16f16(
- <vscale x 16 x half>,
- <vscale x 16 x half>,
- i64);
-
-define <vscale x 16 x i1> @intrinsic_vmfle_vv_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmfle_vv_nxv16f16_nxv16f16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
-; CHECK-NEXT: vmfle.vv v0, v8, v12
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i1> @llvm.riscv.vmfle.nxv16f16(
- <vscale x 16 x half> %0,
- <vscale x 16 x half> %1,
- i64 %2)
-
- ret <vscale x 16 x i1> %a
-}
-
-declare <vscale x 16 x i1> @llvm.riscv.vmfle.mask.nxv16f16(
- <vscale x 16 x i1>,
- <vscale x 16 x half>,
- <vscale x 16 x half>,
- <vscale x 16 x i1>,
- i64);
-
-define <vscale x 16 x i1> @intrinsic_vmfle_mask_vv_nxv16f16_nxv16f16(<vscale x 16 x i1> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, <vscale x 16 x half> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv16f16_nxv16f16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
-; CHECK-NEXT: vmfle.vv v20, v8, v12
-; CHECK-NEXT: vmv1r.v v8, v0
-; CHECK-NEXT: vmv1r.v v0, v20
-; CHECK-NEXT: vmfle.vv v8, v12, v16, v0.t
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: ret
-entry:
- %mask = call <vscale x 16 x i1> @llvm.riscv.vmfle.nxv16f16(
- <vscale x 16 x half> %1,
- <vscale x 16 x half> %2,
- i64 %4)
- %a = call <vscale x 16 x i1> @llvm.riscv.vmfle.mask.nxv16f16(
- <vscale x 16 x i1> %0,
- <vscale x 16 x half> %2,
- <vscale x 16 x half> %3,
- <vscale x 16 x i1> %mask,
- i64 %4)
-
- ret <vscale x 16 x i1> %a
-}
-
-declare <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f32(
- <vscale x 1 x float>,
- <vscale x 1 x float>,
- i64);
-
-define <vscale x 1 x i1> @intrinsic_vmfle_vv_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmfle_vv_nxv1f32_nxv1f32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vmfle.vv v0, v8, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f32(
- <vscale x 1 x float> %0,
- <vscale x 1 x float> %1,
- i64 %2)
-
- ret <vscale x 1 x i1> %a
-}
-
-declare <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f32(
- <vscale x 1 x i1>,
- <vscale x 1 x float>,
- <vscale x 1 x float>,
- <vscale x 1 x i1>,
- i64);
-
-define <vscale x 1 x i1> @intrinsic_vmfle_mask_vv_nxv1f32_nxv1f32(<vscale x 1 x i1> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, <vscale x 1 x float> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv1f32_nxv1f32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vmfle.vv v8, v8, v9
-; CHECK-NEXT: vmv1r.v v11, v0
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmfle.vv v11, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v11
-; CHECK-NEXT: ret
-entry:
- %mask = call <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f32(
- <vscale x 1 x float> %1,
- <vscale x 1 x float> %2,
- i64 %4)
- %a = call <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f32(
- <vscale x 1 x i1> %0,
- <vscale x 1 x float> %2,
- <vscale x 1 x float> %3,
- <vscale x 1 x i1> %mask,
- i64 %4)
-
- ret <vscale x 1 x i1> %a
-}
-
-declare <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2f32(
- <vscale x 2 x float>,
- <vscale x 2 x float>,
- i64);
-
-define <vscale x 2 x i1> @intrinsic_vmfle_vv_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmfle_vv_nxv2f32_nxv2f32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vmfle.vv v0, v8, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2f32(
- <vscale x 2 x float> %0,
- <vscale x 2 x float> %1,
- i64 %2)
-
- ret <vscale x 2 x i1> %a
-}
-
-declare <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2f32(
- <vscale x 2 x i1>,
- <vscale x 2 x float>,
- <vscale x 2 x float>,
- <vscale x 2 x i1>,
- i64);
-
-define <vscale x 2 x i1> @intrinsic_vmfle_mask_vv_nxv2f32_nxv2f32(<vscale x 2 x i1> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x float> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv2f32_nxv2f32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vmfle.vv v8, v8, v9
-; CHECK-NEXT: vmv1r.v v11, v0
-; CHECK-NEXT: vmv.v.v v0, v8
-; CHECK-NEXT: vmfle.vv v11, v9, v10, v0.t
-; CHECK-NEXT: vmv.v.v v0, v11
-; CHECK-NEXT: ret
-entry:
- %mask = call <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2f32(
- <vscale x 2 x float> %1,
- <vscale x 2 x float> %2,
- i64 %4)
- %a = call <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2f32(
- <vscale x 2 x i1> %0,
- <vscale x 2 x float> %2,
- <vscale x 2 x float> %3,
- <vscale x 2 x i1> %mask,
- i64 %4)
-
- ret <vscale x 2 x i1> %a
-}
-
-declare <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4f32(
- <vscale x 4 x float>,
- <vscale x 4 x float>,
- i64);
-
-define <vscale x 4 x i1> @intrinsic_vmfle_vv_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmfle_vv_nxv4f32_nxv4f32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vmfle.vv v0, v8, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4f32(
- <vscale x 4 x float> %0,
- <vscale x 4 x float> %1,
- i64 %2)
-
- ret <vscale x 4 x i1> %a
-}
-
-declare <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4f32(
- <vscale x 4 x i1>,
- <vscale x 4 x float>,
- <vscale x 4 x float>,
- <vscale x 4 x i1>,
- i64);
-
-define <vscale x 4 x i1> @intrinsic_vmfle_mask_vv_nxv4f32_nxv4f32(<vscale x 4 x i1> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x float> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv4f32_nxv4f32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vmfle.vv v14, v8, v10
-; CHECK-NEXT: vmv1r.v v8, v0
-; CHECK-NEXT: vmv1r.v v0, v14
-; CHECK-NEXT: vmfle.vv v8, v10, v12, v0.t
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: ret
-entry:
- %mask = call <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4f32(
- <vscale x 4 x float> %1,
- <vscale x 4 x float> %2,
- i64 %4)
- %a = call <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4f32(
- <vscale x 4 x i1> %0,
- <vscale x 4 x float> %2,
- <vscale x 4 x float> %3,
- <vscale x 4 x i1> %mask,
- i64 %4)
-
- ret <vscale x 4 x i1> %a
-}
-
-declare <vscale x 8 x i1> @llvm.riscv.vmfle.nxv8f32(
- <vscale x 8 x float>,
- <vscale x 8 x float>,
- i64);
-
-define <vscale x 8 x i1> @intrinsic_vmfle_vv_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmfle_vv_nxv8f32_nxv8f32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
-; CHECK-NEXT: vmfle.vv v0, v8, v12
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i1> @llvm.riscv.vmfle.nxv8f32(
- <vscale x 8 x float> %0,
- <vscale x 8 x float> %1,
- i64 %2)
-
- ret <vscale x 8 x i1> %a
-}
-
-declare <vscale x 8 x i1> @llvm.riscv.vmfle.mask.nxv8f32(
- <vscale x 8 x i1>,
- <vscale x 8 x float>,
- <vscale x 8 x float>,
- <vscale x 8 x i1>,
- i64);
-
-define <vscale x 8 x i1> @intrinsic_vmfle_mask_vv_nxv8f32_nxv8f32(<vscale x 8 x i1> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, <vscale x 8 x float> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv8f32_nxv8f32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
-; CHECK-NEXT: vmfle.vv v20, v8, v12
-; CHECK-NEXT: vmv1r.v v8, v0
-; CHECK-NEXT: vmv1r.v v0, v20
-; CHECK-NEXT: vmfle.vv v8, v12, v16, v0.t
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: ret
-entry:
- %mask = call <vscale x 8 x i1> @llvm.riscv.vmfle.nxv8f32(
- <vscale x 8 x float> %1,
- <vscale x 8 x float> %2,
- i64 %4)
- %a = call <vscale x 8 x i1> @llvm.riscv.vmfle.mask.nxv8f32(
- <vscale x 8 x i1> %0,
- <vscale x 8 x float> %2,
- <vscale x 8 x float> %3,
- <vscale x 8 x i1> %mask,
- i64 %4)
-
- ret <vscale x 8 x i1> %a
-}
-
-declare <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f64(
- <vscale x 1 x double>,
- <vscale x 1 x double>,
- i64);
-
-define <vscale x 1 x i1> @intrinsic_vmfle_vv_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmfle_vv_nxv1f64_nxv1f64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
-; CHECK-NEXT: vmfle.vv v0, v8, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f64(
- <vscale x 1 x double> %0,
- <vscale x 1 x double> %1,
- i64 %2)
-
- ret <vscale x 1 x i1> %a
-}
-
-declare <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f64(
- <vscale x 1 x i1>,
- <vscale x 1 x double>,
- <vscale x 1 x double>,
- <vscale x 1 x i1>,
- i64);
-
-define <vscale x 1 x i1> @intrinsic_vmfle_mask_vv_nxv1f64_nxv1f64(<vscale x 1 x i1> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, <vscale x 1 x double> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv1f64_nxv1f64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
-; CHECK-NEXT: vmfle.vv v8, v8, v9
-; CHECK-NEXT: vmv1r.v v11, v0
-; CHECK-NEXT: vmv.v.v v0, v8
-; CHECK-NEXT: vmfle.vv v11, v9, v10, v0.t
-; CHECK-NEXT: vmv.v.v v0, v11
-; CHECK-NEXT: ret
-entry:
- %mask = call <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f64(
- <vscale x 1 x double> %1,
- <vscale x 1 x double> %2,
- i64 %4)
- %a = call <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f64(
- <vscale x 1 x i1> %0,
- <vscale x 1 x double> %2,
- <vscale x 1 x double> %3,
- <vscale x 1 x i1> %mask,
- i64 %4)
-
- ret <vscale x 1 x i1> %a
-}
-
-declare <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2f64(
- <vscale x 2 x double>,
- <vscale x 2 x double>,
- i64);
-
-define <vscale x 2 x i1> @intrinsic_vmfle_vv_nxv2f64_nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmfle_vv_nxv2f64_nxv2f64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
-; CHECK-NEXT: vmfle.vv v0, v8, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2f64(
- <vscale x 2 x double> %0,
- <vscale x 2 x double> %1,
- i64 %2)
-
- ret <vscale x 2 x i1> %a
-}
-
-declare <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2f64(
- <vscale x 2 x i1>,
- <vscale x 2 x double>,
- <vscale x 2 x double>,
- <vscale x 2 x i1>,
- i64);
-
-define <vscale x 2 x i1> @intrinsic_vmfle_mask_vv_nxv2f64_nxv2f64(<vscale x 2 x i1> %0, <vscale x 2 x double> %1, <vscale x 2 x double> %2, <vscale x 2 x double> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv2f64_nxv2f64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
-; CHECK-NEXT: vmfle.vv v14, v8, v10
-; CHECK-NEXT: vmv1r.v v8, v0
-; CHECK-NEXT: vmv1r.v v0, v14
-; CHECK-NEXT: vmfle.vv v8, v10, v12, v0.t
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: ret
-entry:
- %mask = call <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2f64(
- <vscale x 2 x double> %1,
- <vscale x 2 x double> %2,
- i64 %4)
- %a = call <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2f64(
- <vscale x 2 x i1> %0,
- <vscale x 2 x double> %2,
- <vscale x 2 x double> %3,
- <vscale x 2 x i1> %mask,
- i64 %4)
-
- ret <vscale x 2 x i1> %a
-}
-
-declare <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4f64(
- <vscale x 4 x double>,
- <vscale x 4 x double>,
- i64);
-
-define <vscale x 4 x i1> @intrinsic_vmfle_vv_nxv4f64_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmfle_vv_nxv4f64_nxv4f64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
-; CHECK-NEXT: vmfle.vv v0, v8, v12
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4f64(
- <vscale x 4 x double> %0,
- <vscale x 4 x double> %1,
- i64 %2)
-
- ret <vscale x 4 x i1> %a
-}
-
-declare <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4f64(
- <vscale x 4 x i1>,
- <vscale x 4 x double>,
- <vscale x 4 x double>,
- <vscale x 4 x i1>,
- i64);
-
-define <vscale x 4 x i1> @intrinsic_vmfle_mask_vv_nxv4f64_nxv4f64(<vscale x 4 x i1> %0, <vscale x 4 x double> %1, <vscale x 4 x double> %2, <vscale x 4 x double> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv4f64_nxv4f64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
-; CHECK-NEXT: vmfle.vv v20, v8, v12
-; CHECK-NEXT: vmv1r.v v8, v0
-; CHECK-NEXT: vmv1r.v v0, v20
-; CHECK-NEXT: vmfle.vv v8, v12, v16, v0.t
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: ret
-entry:
- %mask = call <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4f64(
- <vscale x 4 x double> %1,
- <vscale x 4 x double> %2,
- i64 %4)
- %a = call <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4f64(
- <vscale x 4 x i1> %0,
- <vscale x 4 x double> %2,
- <vscale x 4 x double> %3,
- <vscale x 4 x i1> %mask,
- i64 %4)
-
- ret <vscale x 4 x i1> %a
-}
-
-declare <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f16.f16(
- <vscale x 1 x half>,
- half,
- i64);
-
-define <vscale x 1 x i1> @intrinsic_vmfle_vf_nxv1f16_f16(<vscale x 1 x half> %0, half %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmfle_vf_nxv1f16_f16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vmfle.vf v0, v8, fa0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f16.f16(
- <vscale x 1 x half> %0,
- half %1,
- i64 %2)
-
- ret <vscale x 1 x i1> %a
-}
-
-declare <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f16.f16(
- <vscale x 1 x i1>,
- <vscale x 1 x half>,
- half,
- <vscale x 1 x i1>,
- i64);
-
-define <vscale x 1 x i1> @intrinsic_vmfle_mask_vf_nxv1f16_f16(<vscale x 1 x i1> %0, <vscale x 1 x half> %1, half %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv1f16_f16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v10, v0
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmfle.vf v10, v8, fa0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f16.f16(
- <vscale x 1 x i1> %0,
- <vscale x 1 x half> %1,
- half %2,
- <vscale x 1 x i1> %3,
- i64 %4)
-
- ret <vscale x 1 x i1> %a
-}
-
-declare <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2f16.f16(
- <vscale x 2 x half>,
- half,
- i64);
-
-define <vscale x 2 x i1> @intrinsic_vmfle_vf_nxv2f16_f16(<vscale x 2 x half> %0, half %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmfle_vf_nxv2f16_f16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vmfle.vf v0, v8, fa0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2f16.f16(
- <vscale x 2 x half> %0,
- half %1,
- i64 %2)
-
- ret <vscale x 2 x i1> %a
-}
-
-declare <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2f16.f16(
- <vscale x 2 x i1>,
- <vscale x 2 x half>,
- half,
- <vscale x 2 x i1>,
- i64);
-
-define <vscale x 2 x i1> @intrinsic_vmfle_mask_vf_nxv2f16_f16(<vscale x 2 x i1> %0, <vscale x 2 x half> %1, half %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv2f16_f16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v10, v0
-; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmfle.vf v10, v8, fa0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2f16.f16(
- <vscale x 2 x i1> %0,
- <vscale x 2 x half> %1,
- half %2,
- <vscale x 2 x i1> %3,
- i64 %4)
-
- ret <vscale x 2 x i1> %a
-}
-
-declare <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4f16.f16(
- <vscale x 4 x half>,
- half,
- i64);
-
-define <vscale x 4 x i1> @intrinsic_vmfle_vf_nxv4f16_f16(<vscale x 4 x half> %0, half %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmfle_vf_nxv4f16_f16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vmfle.vf v0, v8, fa0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4f16.f16(
- <vscale x 4 x half> %0,
- half %1,
- i64 %2)
-
- ret <vscale x 4 x i1> %a
-}
-
-declare <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4f16.f16(
- <vscale x 4 x i1>,
- <vscale x 4 x half>,
- half,
- <vscale x 4 x i1>,
- i64);
-
-define <vscale x 4 x i1> @intrinsic_vmfle_mask_vf_nxv4f16_f16(<vscale x 4 x i1> %0, <vscale x 4 x half> %1, half %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv4f16_f16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v10, v0
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmfle.vf v10, v8, fa0, v0.t
-; CHECK-NEXT: vmv.v.v v0, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4f16.f16(
- <vscale x 4 x i1> %0,
- <vscale x 4 x half> %1,
- half %2,
- <vscale x 4 x i1> %3,
- i64 %4)
-
- ret <vscale x 4 x i1> %a
-}
-
-declare <vscale x 8 x i1> @llvm.riscv.vmfle.nxv8f16.f16(
- <vscale x 8 x half>,
- half,
- i64);
-
-define <vscale x 8 x i1> @intrinsic_vmfle_vf_nxv8f16_f16(<vscale x 8 x half> %0, half %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmfle_vf_nxv8f16_f16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vmfle.vf v0, v8, fa0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i1> @llvm.riscv.vmfle.nxv8f16.f16(
- <vscale x 8 x half> %0,
- half %1,
- i64 %2)
-
- ret <vscale x 8 x i1> %a
-}
-
-declare <vscale x 8 x i1> @llvm.riscv.vmfle.mask.nxv8f16.f16(
- <vscale x 8 x i1>,
- <vscale x 8 x half>,
- half,
- <vscale x 8 x i1>,
- i64);
-
-define <vscale x 8 x i1> @intrinsic_vmfle_mask_vf_nxv8f16_f16(<vscale x 8 x i1> %0, <vscale x 8 x half> %1, half %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv8f16_f16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v11, v0
-; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmfle.vf v11, v8, fa0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v11
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i1> @llvm.riscv.vmfle.mask.nxv8f16.f16(
- <vscale x 8 x i1> %0,
- <vscale x 8 x half> %1,
- half %2,
- <vscale x 8 x i1> %3,
- i64 %4)
-
- ret <vscale x 8 x i1> %a
-}
-
-declare <vscale x 16 x i1> @llvm.riscv.vmfle.nxv16f16.f16(
- <vscale x 16 x half>,
- half,
- i64);
-
-define <vscale x 16 x i1> @intrinsic_vmfle_vf_nxv16f16_f16(<vscale x 16 x half> %0, half %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmfle_vf_nxv16f16_f16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
-; CHECK-NEXT: vmfle.vf v0, v8, fa0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i1> @llvm.riscv.vmfle.nxv16f16.f16(
- <vscale x 16 x half> %0,
- half %1,
- i64 %2)
-
- ret <vscale x 16 x i1> %a
-}
-
-declare <vscale x 16 x i1> @llvm.riscv.vmfle.mask.nxv16f16.f16(
- <vscale x 16 x i1>,
- <vscale x 16 x half>,
- half,
- <vscale x 16 x i1>,
- i64);
-
-define <vscale x 16 x i1> @intrinsic_vmfle_mask_vf_nxv16f16_f16(<vscale x 16 x i1> %0, <vscale x 16 x half> %1, half %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv16f16_f16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v13, v0
-; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
-; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmfle.vf v13, v8, fa0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v13
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i1> @llvm.riscv.vmfle.mask.nxv16f16.f16(
- <vscale x 16 x i1> %0,
- <vscale x 16 x half> %1,
- half %2,
- <vscale x 16 x i1> %3,
- i64 %4)
-
- ret <vscale x 16 x i1> %a
-}
-
-declare <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f32.f32(
- <vscale x 1 x float>,
- float,
- i64);
-
-define <vscale x 1 x i1> @intrinsic_vmfle_vf_nxv1f32_f32(<vscale x 1 x float> %0, float %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmfle_vf_nxv1f32_f32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vmfle.vf v0, v8, fa0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f32.f32(
- <vscale x 1 x float> %0,
- float %1,
- i64 %2)
-
- ret <vscale x 1 x i1> %a
-}
-
-declare <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f32.f32(
- <vscale x 1 x i1>,
- <vscale x 1 x float>,
- float,
- <vscale x 1 x i1>,
- i64);
-
-define <vscale x 1 x i1> @intrinsic_vmfle_mask_vf_nxv1f32_f32(<vscale x 1 x i1> %0, <vscale x 1 x float> %1, float %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv1f32_f32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v10, v0
-; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmfle.vf v10, v8, fa0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f32.f32(
- <vscale x 1 x i1> %0,
- <vscale x 1 x float> %1,
- float %2,
- <vscale x 1 x i1> %3,
- i64 %4)
-
- ret <vscale x 1 x i1> %a
-}
-
-declare <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2f32.f32(
- <vscale x 2 x float>,
- float,
- i64);
-
-define <vscale x 2 x i1> @intrinsic_vmfle_vf_nxv2f32_f32(<vscale x 2 x float> %0, float %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmfle_vf_nxv2f32_f32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vmfle.vf v0, v8, fa0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2f32.f32(
- <vscale x 2 x float> %0,
- float %1,
- i64 %2)
-
- ret <vscale x 2 x i1> %a
-}
-
-declare <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2f32.f32(
- <vscale x 2 x i1>,
- <vscale x 2 x float>,
- float,
- <vscale x 2 x i1>,
- i64);
-
-define <vscale x 2 x i1> @intrinsic_vmfle_mask_vf_nxv2f32_f32(<vscale x 2 x i1> %0, <vscale x 2 x float> %1, float %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv2f32_f32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v10, v0
-; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmfle.vf v10, v8, fa0, v0.t
-; CHECK-NEXT: vmv.v.v v0, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2f32.f32(
- <vscale x 2 x i1> %0,
- <vscale x 2 x float> %1,
- float %2,
- <vscale x 2 x i1> %3,
- i64 %4)
-
- ret <vscale x 2 x i1> %a
-}
-
-declare <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4f32.f32(
- <vscale x 4 x float>,
- float,
- i64);
-
-define <vscale x 4 x i1> @intrinsic_vmfle_vf_nxv4f32_f32(<vscale x 4 x float> %0, float %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmfle_vf_nxv4f32_f32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vmfle.vf v0, v8, fa0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4f32.f32(
- <vscale x 4 x float> %0,
- float %1,
- i64 %2)
-
- ret <vscale x 4 x i1> %a
-}
-
-declare <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4f32.f32(
- <vscale x 4 x i1>,
- <vscale x 4 x float>,
- float,
- <vscale x 4 x i1>,
- i64);
-
-define <vscale x 4 x i1> @intrinsic_vmfle_mask_vf_nxv4f32_f32(<vscale x 4 x i1> %0, <vscale x 4 x float> %1, float %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv4f32_f32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v11, v0
-; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmfle.vf v11, v8, fa0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v11
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4f32.f32(
- <vscale x 4 x i1> %0,
- <vscale x 4 x float> %1,
- float %2,
- <vscale x 4 x i1> %3,
- i64 %4)
-
- ret <vscale x 4 x i1> %a
-}
-
-declare <vscale x 8 x i1> @llvm.riscv.vmfle.nxv8f32.f32(
- <vscale x 8 x float>,
- float,
- i64);
-
-define <vscale x 8 x i1> @intrinsic_vmfle_vf_nxv8f32_f32(<vscale x 8 x float> %0, float %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmfle_vf_nxv8f32_f32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
-; CHECK-NEXT: vmfle.vf v0, v8, fa0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i1> @llvm.riscv.vmfle.nxv8f32.f32(
- <vscale x 8 x float> %0,
- float %1,
- i64 %2)
-
- ret <vscale x 8 x i1> %a
-}
-
-declare <vscale x 8 x i1> @llvm.riscv.vmfle.mask.nxv8f32.f32(
- <vscale x 8 x i1>,
- <vscale x 8 x float>,
- float,
- <vscale x 8 x i1>,
- i64);
-
-define <vscale x 8 x i1> @intrinsic_vmfle_mask_vf_nxv8f32_f32(<vscale x 8 x i1> %0, <vscale x 8 x float> %1, float %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv8f32_f32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v13, v0
-; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
-; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmfle.vf v13, v8, fa0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v13
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i1> @llvm.riscv.vmfle.mask.nxv8f32.f32(
- <vscale x 8 x i1> %0,
- <vscale x 8 x float> %1,
- float %2,
- <vscale x 8 x i1> %3,
- i64 %4)
-
- ret <vscale x 8 x i1> %a
-}
-
-declare <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f64.f64(
- <vscale x 1 x double>,
- double,
- i64);
-
-define <vscale x 1 x i1> @intrinsic_vmfle_vf_nxv1f64_f64(<vscale x 1 x double> %0, double %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmfle_vf_nxv1f64_f64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
-; CHECK-NEXT: vmfle.vf v0, v8, fa0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f64.f64(
- <vscale x 1 x double> %0,
- double %1,
- i64 %2)
-
- ret <vscale x 1 x i1> %a
-}
-
-declare <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f64.f64(
- <vscale x 1 x i1>,
- <vscale x 1 x double>,
- double,
- <vscale x 1 x i1>,
- i64);
-
-define <vscale x 1 x i1> @intrinsic_vmfle_mask_vf_nxv1f64_f64(<vscale x 1 x i1> %0, <vscale x 1 x double> %1, double %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv1f64_f64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v10, v0
-; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
-; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmfle.vf v10, v8, fa0, v0.t
-; CHECK-NEXT: vmv.v.v v0, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f64.f64(
- <vscale x 1 x i1> %0,
- <vscale x 1 x double> %1,
- double %2,
- <vscale x 1 x i1> %3,
- i64 %4)
-
- ret <vscale x 1 x i1> %a
-}
-
-declare <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2f64.f64(
- <vscale x 2 x double>,
- double,
- i64);
-
-define <vscale x 2 x i1> @intrinsic_vmfle_vf_nxv2f64_f64(<vscale x 2 x double> %0, double %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmfle_vf_nxv2f64_f64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
-; CHECK-NEXT: vmfle.vf v0, v8, fa0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2f64.f64(
- <vscale x 2 x double> %0,
- double %1,
- i64 %2)
-
- ret <vscale x 2 x i1> %a
-}
-
-declare <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2f64.f64(
- <vscale x 2 x i1>,
- <vscale x 2 x double>,
- double,
- <vscale x 2 x i1>,
- i64);
-
-define <vscale x 2 x i1> @intrinsic_vmfle_mask_vf_nxv2f64_f64(<vscale x 2 x i1> %0, <vscale x 2 x double> %1, double %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv2f64_f64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v11, v0
-; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
-; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmfle.vf v11, v8, fa0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v11
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2f64.f64(
- <vscale x 2 x i1> %0,
- <vscale x 2 x double> %1,
- double %2,
- <vscale x 2 x i1> %3,
- i64 %4)
-
- ret <vscale x 2 x i1> %a
-}
-
-declare <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4f64.f64(
- <vscale x 4 x double>,
- double,
- i64);
-
-define <vscale x 4 x i1> @intrinsic_vmfle_vf_nxv4f64_f64(<vscale x 4 x double> %0, double %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmfle_vf_nxv4f64_f64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
-; CHECK-NEXT: vmfle.vf v0, v8, fa0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4f64.f64(
- <vscale x 4 x double> %0,
- double %1,
- i64 %2)
-
- ret <vscale x 4 x i1> %a
-}
-
-declare <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4f64.f64(
- <vscale x 4 x i1>,
- <vscale x 4 x double>,
- double,
- <vscale x 4 x i1>,
- i64);
-
-define <vscale x 4 x i1> @intrinsic_vmfle_mask_vf_nxv4f64_f64(<vscale x 4 x i1> %0, <vscale x 4 x double> %1, double %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv4f64_f64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v13, v0
-; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
-; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmfle.vf v13, v8, fa0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v13
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4f64.f64(
- <vscale x 4 x i1> %0,
- <vscale x 4 x double> %1,
- double %2,
- <vscale x 4 x i1> %3,
- i64 %4)
-
- ret <vscale x 4 x i1> %a
-}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmfle-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmfle.ll
similarity index 88%
rename from llvm/test/CodeGen/RISCV/rvv/vmfle-rv32.ll
rename to llvm/test/CodeGen/RISCV/rvv/vmfle.ll
index ba8e5c560958d..70e3c9907602e 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vmfle-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vmfle.ll
@@ -1,12 +1,14 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -mattr=+v,+d,+zfh -verify-machineinstrs \
-; RUN: -target-abi=ilp32d < %s | FileCheck %s
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh \
+; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh \
+; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s
declare <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f16(
<vscale x 1 x half>,
<vscale x 1 x half>,
- i32);
+ iXLen);
-define <vscale x 1 x i1> @intrinsic_vmfle_vv_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i32 %2) nounwind {
+define <vscale x 1 x i1> @intrinsic_vmfle_vv_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmfle_vv_nxv1f16_nxv1f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
@@ -16,7 +18,7 @@ entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f16(
<vscale x 1 x half> %0,
<vscale x 1 x half> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 1 x i1> %a
}
@@ -26,9 +28,9 @@ declare <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f16(
<vscale x 1 x half>,
<vscale x 1 x half>,
<vscale x 1 x i1>,
- i32);
+ iXLen);
-define <vscale x 1 x i1> @intrinsic_vmfle_mask_vv_nxv1f16_nxv1f16(<vscale x 1 x i1> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x half> %3, i32 %4) nounwind {
+define <vscale x 1 x i1> @intrinsic_vmfle_mask_vv_nxv1f16_nxv1f16(<vscale x 1 x i1> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x half> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv1f16_nxv1f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
@@ -42,13 +44,13 @@ entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f16(
<vscale x 1 x half> %1,
<vscale x 1 x half> %2,
- i32 %4)
+ iXLen %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f16(
<vscale x 1 x i1> %0,
<vscale x 1 x half> %2,
<vscale x 1 x half> %3,
<vscale x 1 x i1> %mask,
- i32 %4)
+ iXLen %4)
ret <vscale x 1 x i1> %a
}
@@ -56,9 +58,9 @@ entry:
declare <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2f16(
<vscale x 2 x half>,
<vscale x 2 x half>,
- i32);
+ iXLen);
-define <vscale x 2 x i1> @intrinsic_vmfle_vv_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i32 %2) nounwind {
+define <vscale x 2 x i1> @intrinsic_vmfle_vv_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmfle_vv_nxv2f16_nxv2f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
@@ -68,7 +70,7 @@ entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2f16(
<vscale x 2 x half> %0,
<vscale x 2 x half> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 2 x i1> %a
}
@@ -78,9 +80,9 @@ declare <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2f16(
<vscale x 2 x half>,
<vscale x 2 x half>,
<vscale x 2 x i1>,
- i32);
+ iXLen);
-define <vscale x 2 x i1> @intrinsic_vmfle_mask_vv_nxv2f16_nxv2f16(<vscale x 2 x i1> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, <vscale x 2 x half> %3, i32 %4) nounwind {
+define <vscale x 2 x i1> @intrinsic_vmfle_mask_vv_nxv2f16_nxv2f16(<vscale x 2 x i1> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, <vscale x 2 x half> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv2f16_nxv2f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
@@ -94,13 +96,13 @@ entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2f16(
<vscale x 2 x half> %1,
<vscale x 2 x half> %2,
- i32 %4)
+ iXLen %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2f16(
<vscale x 2 x i1> %0,
<vscale x 2 x half> %2,
<vscale x 2 x half> %3,
<vscale x 2 x i1> %mask,
- i32 %4)
+ iXLen %4)
ret <vscale x 2 x i1> %a
}
@@ -108,9 +110,9 @@ entry:
declare <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4f16(
<vscale x 4 x half>,
<vscale x 4 x half>,
- i32);
+ iXLen);
-define <vscale x 4 x i1> @intrinsic_vmfle_vv_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i32 %2) nounwind {
+define <vscale x 4 x i1> @intrinsic_vmfle_vv_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmfle_vv_nxv4f16_nxv4f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
@@ -120,7 +122,7 @@ entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4f16(
<vscale x 4 x half> %0,
<vscale x 4 x half> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 4 x i1> %a
}
@@ -130,9 +132,9 @@ declare <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4f16(
<vscale x 4 x half>,
<vscale x 4 x half>,
<vscale x 4 x i1>,
- i32);
+ iXLen);
-define <vscale x 4 x i1> @intrinsic_vmfle_mask_vv_nxv4f16_nxv4f16(<vscale x 4 x i1> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x half> %3, i32 %4) nounwind {
+define <vscale x 4 x i1> @intrinsic_vmfle_mask_vv_nxv4f16_nxv4f16(<vscale x 4 x i1> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x half> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv4f16_nxv4f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
@@ -146,13 +148,13 @@ entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4f16(
<vscale x 4 x half> %1,
<vscale x 4 x half> %2,
- i32 %4)
+ iXLen %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4f16(
<vscale x 4 x i1> %0,
<vscale x 4 x half> %2,
<vscale x 4 x half> %3,
<vscale x 4 x i1> %mask,
- i32 %4)
+ iXLen %4)
ret <vscale x 4 x i1> %a
}
@@ -160,9 +162,9 @@ entry:
declare <vscale x 8 x i1> @llvm.riscv.vmfle.nxv8f16(
<vscale x 8 x half>,
<vscale x 8 x half>,
- i32);
+ iXLen);
-define <vscale x 8 x i1> @intrinsic_vmfle_vv_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i32 %2) nounwind {
+define <vscale x 8 x i1> @intrinsic_vmfle_vv_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmfle_vv_nxv8f16_nxv8f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
@@ -172,7 +174,7 @@ entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmfle.nxv8f16(
<vscale x 8 x half> %0,
<vscale x 8 x half> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 8 x i1> %a
}
@@ -182,9 +184,9 @@ declare <vscale x 8 x i1> @llvm.riscv.vmfle.mask.nxv8f16(
<vscale x 8 x half>,
<vscale x 8 x half>,
<vscale x 8 x i1>,
- i32);
+ iXLen);
-define <vscale x 8 x i1> @intrinsic_vmfle_mask_vv_nxv8f16_nxv8f16(<vscale x 8 x i1> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x half> %3, i32 %4) nounwind {
+define <vscale x 8 x i1> @intrinsic_vmfle_mask_vv_nxv8f16_nxv8f16(<vscale x 8 x i1> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x half> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv8f16_nxv8f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
@@ -198,13 +200,13 @@ entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmfle.nxv8f16(
<vscale x 8 x half> %1,
<vscale x 8 x half> %2,
- i32 %4)
+ iXLen %4)
%a = call <vscale x 8 x i1> @llvm.riscv.vmfle.mask.nxv8f16(
<vscale x 8 x i1> %0,
<vscale x 8 x half> %2,
<vscale x 8 x half> %3,
<vscale x 8 x i1> %mask,
- i32 %4)
+ iXLen %4)
ret <vscale x 8 x i1> %a
}
@@ -212,9 +214,9 @@ entry:
declare <vscale x 16 x i1> @llvm.riscv.vmfle.nxv16f16(
<vscale x 16 x half>,
<vscale x 16 x half>,
- i32);
+ iXLen);
-define <vscale x 16 x i1> @intrinsic_vmfle_vv_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i32 %2) nounwind {
+define <vscale x 16 x i1> @intrinsic_vmfle_vv_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmfle_vv_nxv16f16_nxv16f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
@@ -224,7 +226,7 @@ entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmfle.nxv16f16(
<vscale x 16 x half> %0,
<vscale x 16 x half> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 16 x i1> %a
}
@@ -234,9 +236,9 @@ declare <vscale x 16 x i1> @llvm.riscv.vmfle.mask.nxv16f16(
<vscale x 16 x half>,
<vscale x 16 x half>,
<vscale x 16 x i1>,
- i32);
+ iXLen);
-define <vscale x 16 x i1> @intrinsic_vmfle_mask_vv_nxv16f16_nxv16f16(<vscale x 16 x i1> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, <vscale x 16 x half> %3, i32 %4) nounwind {
+define <vscale x 16 x i1> @intrinsic_vmfle_mask_vv_nxv16f16_nxv16f16(<vscale x 16 x i1> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, <vscale x 16 x half> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv16f16_nxv16f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
@@ -250,13 +252,13 @@ entry:
%mask = call <vscale x 16 x i1> @llvm.riscv.vmfle.nxv16f16(
<vscale x 16 x half> %1,
<vscale x 16 x half> %2,
- i32 %4)
+ iXLen %4)
%a = call <vscale x 16 x i1> @llvm.riscv.vmfle.mask.nxv16f16(
<vscale x 16 x i1> %0,
<vscale x 16 x half> %2,
<vscale x 16 x half> %3,
<vscale x 16 x i1> %mask,
- i32 %4)
+ iXLen %4)
ret <vscale x 16 x i1> %a
}
@@ -264,9 +266,9 @@ entry:
declare <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f32(
<vscale x 1 x float>,
<vscale x 1 x float>,
- i32);
+ iXLen);
-define <vscale x 1 x i1> @intrinsic_vmfle_vv_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, i32 %2) nounwind {
+define <vscale x 1 x i1> @intrinsic_vmfle_vv_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmfle_vv_nxv1f32_nxv1f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
@@ -276,7 +278,7 @@ entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f32(
<vscale x 1 x float> %0,
<vscale x 1 x float> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 1 x i1> %a
}
@@ -286,9 +288,9 @@ declare <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f32(
<vscale x 1 x float>,
<vscale x 1 x float>,
<vscale x 1 x i1>,
- i32);
+ iXLen);
-define <vscale x 1 x i1> @intrinsic_vmfle_mask_vv_nxv1f32_nxv1f32(<vscale x 1 x i1> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, <vscale x 1 x float> %3, i32 %4) nounwind {
+define <vscale x 1 x i1> @intrinsic_vmfle_mask_vv_nxv1f32_nxv1f32(<vscale x 1 x i1> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, <vscale x 1 x float> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv1f32_nxv1f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
@@ -302,13 +304,13 @@ entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f32(
<vscale x 1 x float> %1,
<vscale x 1 x float> %2,
- i32 %4)
+ iXLen %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f32(
<vscale x 1 x i1> %0,
<vscale x 1 x float> %2,
<vscale x 1 x float> %3,
<vscale x 1 x i1> %mask,
- i32 %4)
+ iXLen %4)
ret <vscale x 1 x i1> %a
}
@@ -316,9 +318,9 @@ entry:
declare <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2f32(
<vscale x 2 x float>,
<vscale x 2 x float>,
- i32);
+ iXLen);
-define <vscale x 2 x i1> @intrinsic_vmfle_vv_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, i32 %2) nounwind {
+define <vscale x 2 x i1> @intrinsic_vmfle_vv_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmfle_vv_nxv2f32_nxv2f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
@@ -328,7 +330,7 @@ entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2f32(
<vscale x 2 x float> %0,
<vscale x 2 x float> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 2 x i1> %a
}
@@ -338,9 +340,9 @@ declare <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2f32(
<vscale x 2 x float>,
<vscale x 2 x float>,
<vscale x 2 x i1>,
- i32);
+ iXLen);
-define <vscale x 2 x i1> @intrinsic_vmfle_mask_vv_nxv2f32_nxv2f32(<vscale x 2 x i1> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x float> %3, i32 %4) nounwind {
+define <vscale x 2 x i1> @intrinsic_vmfle_mask_vv_nxv2f32_nxv2f32(<vscale x 2 x i1> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x float> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv2f32_nxv2f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
@@ -354,13 +356,13 @@ entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2f32(
<vscale x 2 x float> %1,
<vscale x 2 x float> %2,
- i32 %4)
+ iXLen %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2f32(
<vscale x 2 x i1> %0,
<vscale x 2 x float> %2,
<vscale x 2 x float> %3,
<vscale x 2 x i1> %mask,
- i32 %4)
+ iXLen %4)
ret <vscale x 2 x i1> %a
}
@@ -368,9 +370,9 @@ entry:
declare <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4f32(
<vscale x 4 x float>,
<vscale x 4 x float>,
- i32);
+ iXLen);
-define <vscale x 4 x i1> @intrinsic_vmfle_vv_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, i32 %2) nounwind {
+define <vscale x 4 x i1> @intrinsic_vmfle_vv_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmfle_vv_nxv4f32_nxv4f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
@@ -380,7 +382,7 @@ entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4f32(
<vscale x 4 x float> %0,
<vscale x 4 x float> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 4 x i1> %a
}
@@ -390,9 +392,9 @@ declare <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4f32(
<vscale x 4 x float>,
<vscale x 4 x float>,
<vscale x 4 x i1>,
- i32);
+ iXLen);
-define <vscale x 4 x i1> @intrinsic_vmfle_mask_vv_nxv4f32_nxv4f32(<vscale x 4 x i1> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x float> %3, i32 %4) nounwind {
+define <vscale x 4 x i1> @intrinsic_vmfle_mask_vv_nxv4f32_nxv4f32(<vscale x 4 x i1> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x float> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv4f32_nxv4f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
@@ -406,13 +408,13 @@ entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4f32(
<vscale x 4 x float> %1,
<vscale x 4 x float> %2,
- i32 %4)
+ iXLen %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4f32(
<vscale x 4 x i1> %0,
<vscale x 4 x float> %2,
<vscale x 4 x float> %3,
<vscale x 4 x i1> %mask,
- i32 %4)
+ iXLen %4)
ret <vscale x 4 x i1> %a
}
@@ -420,9 +422,9 @@ entry:
declare <vscale x 8 x i1> @llvm.riscv.vmfle.nxv8f32(
<vscale x 8 x float>,
<vscale x 8 x float>,
- i32);
+ iXLen);
-define <vscale x 8 x i1> @intrinsic_vmfle_vv_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, i32 %2) nounwind {
+define <vscale x 8 x i1> @intrinsic_vmfle_vv_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmfle_vv_nxv8f32_nxv8f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
@@ -432,7 +434,7 @@ entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmfle.nxv8f32(
<vscale x 8 x float> %0,
<vscale x 8 x float> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 8 x i1> %a
}
@@ -442,9 +444,9 @@ declare <vscale x 8 x i1> @llvm.riscv.vmfle.mask.nxv8f32(
<vscale x 8 x float>,
<vscale x 8 x float>,
<vscale x 8 x i1>,
- i32);
+ iXLen);
-define <vscale x 8 x i1> @intrinsic_vmfle_mask_vv_nxv8f32_nxv8f32(<vscale x 8 x i1> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, <vscale x 8 x float> %3, i32 %4) nounwind {
+define <vscale x 8 x i1> @intrinsic_vmfle_mask_vv_nxv8f32_nxv8f32(<vscale x 8 x i1> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, <vscale x 8 x float> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv8f32_nxv8f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
@@ -458,13 +460,13 @@ entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmfle.nxv8f32(
<vscale x 8 x float> %1,
<vscale x 8 x float> %2,
- i32 %4)
+ iXLen %4)
%a = call <vscale x 8 x i1> @llvm.riscv.vmfle.mask.nxv8f32(
<vscale x 8 x i1> %0,
<vscale x 8 x float> %2,
<vscale x 8 x float> %3,
<vscale x 8 x i1> %mask,
- i32 %4)
+ iXLen %4)
ret <vscale x 8 x i1> %a
}
@@ -472,9 +474,9 @@ entry:
declare <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f64(
<vscale x 1 x double>,
<vscale x 1 x double>,
- i32);
+ iXLen);
-define <vscale x 1 x i1> @intrinsic_vmfle_vv_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, i32 %2) nounwind {
+define <vscale x 1 x i1> @intrinsic_vmfle_vv_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmfle_vv_nxv1f64_nxv1f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
@@ -484,7 +486,7 @@ entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f64(
<vscale x 1 x double> %0,
<vscale x 1 x double> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 1 x i1> %a
}
@@ -494,9 +496,9 @@ declare <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f64(
<vscale x 1 x double>,
<vscale x 1 x double>,
<vscale x 1 x i1>,
- i32);
+ iXLen);
-define <vscale x 1 x i1> @intrinsic_vmfle_mask_vv_nxv1f64_nxv1f64(<vscale x 1 x i1> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, <vscale x 1 x double> %3, i32 %4) nounwind {
+define <vscale x 1 x i1> @intrinsic_vmfle_mask_vv_nxv1f64_nxv1f64(<vscale x 1 x i1> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, <vscale x 1 x double> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv1f64_nxv1f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
@@ -510,13 +512,13 @@ entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f64(
<vscale x 1 x double> %1,
<vscale x 1 x double> %2,
- i32 %4)
+ iXLen %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f64(
<vscale x 1 x i1> %0,
<vscale x 1 x double> %2,
<vscale x 1 x double> %3,
<vscale x 1 x i1> %mask,
- i32 %4)
+ iXLen %4)
ret <vscale x 1 x i1> %a
}
@@ -524,9 +526,9 @@ entry:
declare <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2f64(
<vscale x 2 x double>,
<vscale x 2 x double>,
- i32);
+ iXLen);
-define <vscale x 2 x i1> @intrinsic_vmfle_vv_nxv2f64_nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, i32 %2) nounwind {
+define <vscale x 2 x i1> @intrinsic_vmfle_vv_nxv2f64_nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmfle_vv_nxv2f64_nxv2f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
@@ -536,7 +538,7 @@ entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2f64(
<vscale x 2 x double> %0,
<vscale x 2 x double> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 2 x i1> %a
}
@@ -546,9 +548,9 @@ declare <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2f64(
<vscale x 2 x double>,
<vscale x 2 x double>,
<vscale x 2 x i1>,
- i32);
+ iXLen);
-define <vscale x 2 x i1> @intrinsic_vmfle_mask_vv_nxv2f64_nxv2f64(<vscale x 2 x i1> %0, <vscale x 2 x double> %1, <vscale x 2 x double> %2, <vscale x 2 x double> %3, i32 %4) nounwind {
+define <vscale x 2 x i1> @intrinsic_vmfle_mask_vv_nxv2f64_nxv2f64(<vscale x 2 x i1> %0, <vscale x 2 x double> %1, <vscale x 2 x double> %2, <vscale x 2 x double> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv2f64_nxv2f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
@@ -562,13 +564,13 @@ entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2f64(
<vscale x 2 x double> %1,
<vscale x 2 x double> %2,
- i32 %4)
+ iXLen %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2f64(
<vscale x 2 x i1> %0,
<vscale x 2 x double> %2,
<vscale x 2 x double> %3,
<vscale x 2 x i1> %mask,
- i32 %4)
+ iXLen %4)
ret <vscale x 2 x i1> %a
}
@@ -576,9 +578,9 @@ entry:
declare <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4f64(
<vscale x 4 x double>,
<vscale x 4 x double>,
- i32);
+ iXLen);
-define <vscale x 4 x i1> @intrinsic_vmfle_vv_nxv4f64_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, i32 %2) nounwind {
+define <vscale x 4 x i1> @intrinsic_vmfle_vv_nxv4f64_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmfle_vv_nxv4f64_nxv4f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
@@ -588,7 +590,7 @@ entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4f64(
<vscale x 4 x double> %0,
<vscale x 4 x double> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 4 x i1> %a
}
@@ -598,9 +600,9 @@ declare <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4f64(
<vscale x 4 x double>,
<vscale x 4 x double>,
<vscale x 4 x i1>,
- i32);
+ iXLen);
-define <vscale x 4 x i1> @intrinsic_vmfle_mask_vv_nxv4f64_nxv4f64(<vscale x 4 x i1> %0, <vscale x 4 x double> %1, <vscale x 4 x double> %2, <vscale x 4 x double> %3, i32 %4) nounwind {
+define <vscale x 4 x i1> @intrinsic_vmfle_mask_vv_nxv4f64_nxv4f64(<vscale x 4 x i1> %0, <vscale x 4 x double> %1, <vscale x 4 x double> %2, <vscale x 4 x double> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv4f64_nxv4f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
@@ -614,13 +616,13 @@ entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4f64(
<vscale x 4 x double> %1,
<vscale x 4 x double> %2,
- i32 %4)
+ iXLen %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4f64(
<vscale x 4 x i1> %0,
<vscale x 4 x double> %2,
<vscale x 4 x double> %3,
<vscale x 4 x i1> %mask,
- i32 %4)
+ iXLen %4)
ret <vscale x 4 x i1> %a
}
@@ -628,9 +630,9 @@ entry:
declare <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f16.f16(
<vscale x 1 x half>,
half,
- i32);
+ iXLen);
-define <vscale x 1 x i1> @intrinsic_vmfle_vf_nxv1f16_f16(<vscale x 1 x half> %0, half %1, i32 %2) nounwind {
+define <vscale x 1 x i1> @intrinsic_vmfle_vf_nxv1f16_f16(<vscale x 1 x half> %0, half %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmfle_vf_nxv1f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
@@ -640,7 +642,7 @@ entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f16.f16(
<vscale x 1 x half> %0,
half %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 1 x i1> %a
}
@@ -650,9 +652,9 @@ declare <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f16.f16(
<vscale x 1 x half>,
half,
<vscale x 1 x i1>,
- i32);
+ iXLen);
-define <vscale x 1 x i1> @intrinsic_vmfle_mask_vf_nxv1f16_f16(<vscale x 1 x i1> %0, <vscale x 1 x half> %1, half %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+define <vscale x 1 x i1> @intrinsic_vmfle_mask_vf_nxv1f16_f16(<vscale x 1 x i1> %0, <vscale x 1 x half> %1, half %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv1f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0
@@ -667,7 +669,7 @@ entry:
<vscale x 1 x half> %1,
half %2,
<vscale x 1 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 1 x i1> %a
}
@@ -675,9 +677,9 @@ entry:
declare <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2f16.f16(
<vscale x 2 x half>,
half,
- i32);
+ iXLen);
-define <vscale x 2 x i1> @intrinsic_vmfle_vf_nxv2f16_f16(<vscale x 2 x half> %0, half %1, i32 %2) nounwind {
+define <vscale x 2 x i1> @intrinsic_vmfle_vf_nxv2f16_f16(<vscale x 2 x half> %0, half %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmfle_vf_nxv2f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
@@ -687,7 +689,7 @@ entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2f16.f16(
<vscale x 2 x half> %0,
half %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 2 x i1> %a
}
@@ -697,9 +699,9 @@ declare <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2f16.f16(
<vscale x 2 x half>,
half,
<vscale x 2 x i1>,
- i32);
+ iXLen);
-define <vscale x 2 x i1> @intrinsic_vmfle_mask_vf_nxv2f16_f16(<vscale x 2 x i1> %0, <vscale x 2 x half> %1, half %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+define <vscale x 2 x i1> @intrinsic_vmfle_mask_vf_nxv2f16_f16(<vscale x 2 x i1> %0, <vscale x 2 x half> %1, half %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv2f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0
@@ -714,7 +716,7 @@ entry:
<vscale x 2 x half> %1,
half %2,
<vscale x 2 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 2 x i1> %a
}
@@ -722,9 +724,9 @@ entry:
declare <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4f16.f16(
<vscale x 4 x half>,
half,
- i32);
+ iXLen);
-define <vscale x 4 x i1> @intrinsic_vmfle_vf_nxv4f16_f16(<vscale x 4 x half> %0, half %1, i32 %2) nounwind {
+define <vscale x 4 x i1> @intrinsic_vmfle_vf_nxv4f16_f16(<vscale x 4 x half> %0, half %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmfle_vf_nxv4f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
@@ -734,7 +736,7 @@ entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4f16.f16(
<vscale x 4 x half> %0,
half %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 4 x i1> %a
}
@@ -744,9 +746,9 @@ declare <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4f16.f16(
<vscale x 4 x half>,
half,
<vscale x 4 x i1>,
- i32);
+ iXLen);
-define <vscale x 4 x i1> @intrinsic_vmfle_mask_vf_nxv4f16_f16(<vscale x 4 x i1> %0, <vscale x 4 x half> %1, half %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+define <vscale x 4 x i1> @intrinsic_vmfle_mask_vf_nxv4f16_f16(<vscale x 4 x i1> %0, <vscale x 4 x half> %1, half %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv4f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0
@@ -761,7 +763,7 @@ entry:
<vscale x 4 x half> %1,
half %2,
<vscale x 4 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 4 x i1> %a
}
@@ -769,9 +771,9 @@ entry:
declare <vscale x 8 x i1> @llvm.riscv.vmfle.nxv8f16.f16(
<vscale x 8 x half>,
half,
- i32);
+ iXLen);
-define <vscale x 8 x i1> @intrinsic_vmfle_vf_nxv8f16_f16(<vscale x 8 x half> %0, half %1, i32 %2) nounwind {
+define <vscale x 8 x i1> @intrinsic_vmfle_vf_nxv8f16_f16(<vscale x 8 x half> %0, half %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmfle_vf_nxv8f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
@@ -781,7 +783,7 @@ entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmfle.nxv8f16.f16(
<vscale x 8 x half> %0,
half %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 8 x i1> %a
}
@@ -791,9 +793,9 @@ declare <vscale x 8 x i1> @llvm.riscv.vmfle.mask.nxv8f16.f16(
<vscale x 8 x half>,
half,
<vscale x 8 x i1>,
- i32);
+ iXLen);
-define <vscale x 8 x i1> @intrinsic_vmfle_mask_vf_nxv8f16_f16(<vscale x 8 x i1> %0, <vscale x 8 x half> %1, half %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+define <vscale x 8 x i1> @intrinsic_vmfle_mask_vf_nxv8f16_f16(<vscale x 8 x i1> %0, <vscale x 8 x half> %1, half %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv8f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v11, v0
@@ -808,7 +810,7 @@ entry:
<vscale x 8 x half> %1,
half %2,
<vscale x 8 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 8 x i1> %a
}
@@ -816,9 +818,9 @@ entry:
declare <vscale x 16 x i1> @llvm.riscv.vmfle.nxv16f16.f16(
<vscale x 16 x half>,
half,
- i32);
+ iXLen);
-define <vscale x 16 x i1> @intrinsic_vmfle_vf_nxv16f16_f16(<vscale x 16 x half> %0, half %1, i32 %2) nounwind {
+define <vscale x 16 x i1> @intrinsic_vmfle_vf_nxv16f16_f16(<vscale x 16 x half> %0, half %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmfle_vf_nxv16f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
@@ -828,7 +830,7 @@ entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmfle.nxv16f16.f16(
<vscale x 16 x half> %0,
half %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 16 x i1> %a
}
@@ -838,9 +840,9 @@ declare <vscale x 16 x i1> @llvm.riscv.vmfle.mask.nxv16f16.f16(
<vscale x 16 x half>,
half,
<vscale x 16 x i1>,
- i32);
+ iXLen);
-define <vscale x 16 x i1> @intrinsic_vmfle_mask_vf_nxv16f16_f16(<vscale x 16 x i1> %0, <vscale x 16 x half> %1, half %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+define <vscale x 16 x i1> @intrinsic_vmfle_mask_vf_nxv16f16_f16(<vscale x 16 x i1> %0, <vscale x 16 x half> %1, half %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv16f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v13, v0
@@ -855,7 +857,7 @@ entry:
<vscale x 16 x half> %1,
half %2,
<vscale x 16 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 16 x i1> %a
}
@@ -863,9 +865,9 @@ entry:
declare <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f32.f32(
<vscale x 1 x float>,
float,
- i32);
+ iXLen);
-define <vscale x 1 x i1> @intrinsic_vmfle_vf_nxv1f32_f32(<vscale x 1 x float> %0, float %1, i32 %2) nounwind {
+define <vscale x 1 x i1> @intrinsic_vmfle_vf_nxv1f32_f32(<vscale x 1 x float> %0, float %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmfle_vf_nxv1f32_f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
@@ -875,7 +877,7 @@ entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f32.f32(
<vscale x 1 x float> %0,
float %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 1 x i1> %a
}
@@ -885,9 +887,9 @@ declare <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f32.f32(
<vscale x 1 x float>,
float,
<vscale x 1 x i1>,
- i32);
+ iXLen);
-define <vscale x 1 x i1> @intrinsic_vmfle_mask_vf_nxv1f32_f32(<vscale x 1 x i1> %0, <vscale x 1 x float> %1, float %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+define <vscale x 1 x i1> @intrinsic_vmfle_mask_vf_nxv1f32_f32(<vscale x 1 x i1> %0, <vscale x 1 x float> %1, float %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv1f32_f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0
@@ -902,7 +904,7 @@ entry:
<vscale x 1 x float> %1,
float %2,
<vscale x 1 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 1 x i1> %a
}
@@ -910,9 +912,9 @@ entry:
declare <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2f32.f32(
<vscale x 2 x float>,
float,
- i32);
+ iXLen);
-define <vscale x 2 x i1> @intrinsic_vmfle_vf_nxv2f32_f32(<vscale x 2 x float> %0, float %1, i32 %2) nounwind {
+define <vscale x 2 x i1> @intrinsic_vmfle_vf_nxv2f32_f32(<vscale x 2 x float> %0, float %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmfle_vf_nxv2f32_f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
@@ -922,7 +924,7 @@ entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2f32.f32(
<vscale x 2 x float> %0,
float %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 2 x i1> %a
}
@@ -932,9 +934,9 @@ declare <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2f32.f32(
<vscale x 2 x float>,
float,
<vscale x 2 x i1>,
- i32);
+ iXLen);
-define <vscale x 2 x i1> @intrinsic_vmfle_mask_vf_nxv2f32_f32(<vscale x 2 x i1> %0, <vscale x 2 x float> %1, float %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+define <vscale x 2 x i1> @intrinsic_vmfle_mask_vf_nxv2f32_f32(<vscale x 2 x i1> %0, <vscale x 2 x float> %1, float %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv2f32_f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0
@@ -949,7 +951,7 @@ entry:
<vscale x 2 x float> %1,
float %2,
<vscale x 2 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 2 x i1> %a
}
@@ -957,9 +959,9 @@ entry:
declare <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4f32.f32(
<vscale x 4 x float>,
float,
- i32);
+ iXLen);
-define <vscale x 4 x i1> @intrinsic_vmfle_vf_nxv4f32_f32(<vscale x 4 x float> %0, float %1, i32 %2) nounwind {
+define <vscale x 4 x i1> @intrinsic_vmfle_vf_nxv4f32_f32(<vscale x 4 x float> %0, float %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmfle_vf_nxv4f32_f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
@@ -969,7 +971,7 @@ entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4f32.f32(
<vscale x 4 x float> %0,
float %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 4 x i1> %a
}
@@ -979,9 +981,9 @@ declare <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4f32.f32(
<vscale x 4 x float>,
float,
<vscale x 4 x i1>,
- i32);
+ iXLen);
-define <vscale x 4 x i1> @intrinsic_vmfle_mask_vf_nxv4f32_f32(<vscale x 4 x i1> %0, <vscale x 4 x float> %1, float %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+define <vscale x 4 x i1> @intrinsic_vmfle_mask_vf_nxv4f32_f32(<vscale x 4 x i1> %0, <vscale x 4 x float> %1, float %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv4f32_f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v11, v0
@@ -996,7 +998,7 @@ entry:
<vscale x 4 x float> %1,
float %2,
<vscale x 4 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 4 x i1> %a
}
@@ -1004,9 +1006,9 @@ entry:
declare <vscale x 8 x i1> @llvm.riscv.vmfle.nxv8f32.f32(
<vscale x 8 x float>,
float,
- i32);
+ iXLen);
-define <vscale x 8 x i1> @intrinsic_vmfle_vf_nxv8f32_f32(<vscale x 8 x float> %0, float %1, i32 %2) nounwind {
+define <vscale x 8 x i1> @intrinsic_vmfle_vf_nxv8f32_f32(<vscale x 8 x float> %0, float %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmfle_vf_nxv8f32_f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
@@ -1016,7 +1018,7 @@ entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmfle.nxv8f32.f32(
<vscale x 8 x float> %0,
float %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 8 x i1> %a
}
@@ -1026,9 +1028,9 @@ declare <vscale x 8 x i1> @llvm.riscv.vmfle.mask.nxv8f32.f32(
<vscale x 8 x float>,
float,
<vscale x 8 x i1>,
- i32);
+ iXLen);
-define <vscale x 8 x i1> @intrinsic_vmfle_mask_vf_nxv8f32_f32(<vscale x 8 x i1> %0, <vscale x 8 x float> %1, float %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+define <vscale x 8 x i1> @intrinsic_vmfle_mask_vf_nxv8f32_f32(<vscale x 8 x i1> %0, <vscale x 8 x float> %1, float %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv8f32_f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v13, v0
@@ -1043,7 +1045,7 @@ entry:
<vscale x 8 x float> %1,
float %2,
<vscale x 8 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 8 x i1> %a
}
@@ -1051,9 +1053,9 @@ entry:
declare <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f64.f64(
<vscale x 1 x double>,
double,
- i32);
+ iXLen);
-define <vscale x 1 x i1> @intrinsic_vmfle_vf_nxv1f64_f64(<vscale x 1 x double> %0, double %1, i32 %2) nounwind {
+define <vscale x 1 x i1> @intrinsic_vmfle_vf_nxv1f64_f64(<vscale x 1 x double> %0, double %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmfle_vf_nxv1f64_f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
@@ -1063,7 +1065,7 @@ entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f64.f64(
<vscale x 1 x double> %0,
double %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 1 x i1> %a
}
@@ -1073,9 +1075,9 @@ declare <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f64.f64(
<vscale x 1 x double>,
double,
<vscale x 1 x i1>,
- i32);
+ iXLen);
-define <vscale x 1 x i1> @intrinsic_vmfle_mask_vf_nxv1f64_f64(<vscale x 1 x i1> %0, <vscale x 1 x double> %1, double %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+define <vscale x 1 x i1> @intrinsic_vmfle_mask_vf_nxv1f64_f64(<vscale x 1 x i1> %0, <vscale x 1 x double> %1, double %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv1f64_f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0
@@ -1090,7 +1092,7 @@ entry:
<vscale x 1 x double> %1,
double %2,
<vscale x 1 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 1 x i1> %a
}
@@ -1098,9 +1100,9 @@ entry:
declare <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2f64.f64(
<vscale x 2 x double>,
double,
- i32);
+ iXLen);
-define <vscale x 2 x i1> @intrinsic_vmfle_vf_nxv2f64_f64(<vscale x 2 x double> %0, double %1, i32 %2) nounwind {
+define <vscale x 2 x i1> @intrinsic_vmfle_vf_nxv2f64_f64(<vscale x 2 x double> %0, double %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmfle_vf_nxv2f64_f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
@@ -1110,7 +1112,7 @@ entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2f64.f64(
<vscale x 2 x double> %0,
double %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 2 x i1> %a
}
@@ -1120,9 +1122,9 @@ declare <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2f64.f64(
<vscale x 2 x double>,
double,
<vscale x 2 x i1>,
- i32);
+ iXLen);
-define <vscale x 2 x i1> @intrinsic_vmfle_mask_vf_nxv2f64_f64(<vscale x 2 x i1> %0, <vscale x 2 x double> %1, double %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+define <vscale x 2 x i1> @intrinsic_vmfle_mask_vf_nxv2f64_f64(<vscale x 2 x i1> %0, <vscale x 2 x double> %1, double %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv2f64_f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v11, v0
@@ -1137,7 +1139,7 @@ entry:
<vscale x 2 x double> %1,
double %2,
<vscale x 2 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 2 x i1> %a
}
@@ -1145,9 +1147,9 @@ entry:
declare <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4f64.f64(
<vscale x 4 x double>,
double,
- i32);
+ iXLen);
-define <vscale x 4 x i1> @intrinsic_vmfle_vf_nxv4f64_f64(<vscale x 4 x double> %0, double %1, i32 %2) nounwind {
+define <vscale x 4 x i1> @intrinsic_vmfle_vf_nxv4f64_f64(<vscale x 4 x double> %0, double %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmfle_vf_nxv4f64_f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
@@ -1157,7 +1159,7 @@ entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4f64.f64(
<vscale x 4 x double> %0,
double %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 4 x i1> %a
}
@@ -1167,9 +1169,9 @@ declare <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4f64.f64(
<vscale x 4 x double>,
double,
<vscale x 4 x i1>,
- i32);
+ iXLen);
-define <vscale x 4 x i1> @intrinsic_vmfle_mask_vf_nxv4f64_f64(<vscale x 4 x i1> %0, <vscale x 4 x double> %1, double %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+define <vscale x 4 x i1> @intrinsic_vmfle_mask_vf_nxv4f64_f64(<vscale x 4 x i1> %0, <vscale x 4 x double> %1, double %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv4f64_f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v13, v0
@@ -1184,7 +1186,7 @@ entry:
<vscale x 4 x double> %1,
double %2,
<vscale x 4 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 4 x i1> %a
}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmflt-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vmflt-rv64.ll
deleted file mode 100644
index 55bb51365de74..0000000000000
--- a/llvm/test/CodeGen/RISCV/rvv/vmflt-rv64.ll
+++ /dev/null
@@ -1,1190 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv64 -mattr=+v,+d,+zfh -verify-machineinstrs \
-; RUN: -target-abi=lp64d < %s | FileCheck %s
-declare <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1f16(
- <vscale x 1 x half>,
- <vscale x 1 x half>,
- i64);
-
-define <vscale x 1 x i1> @intrinsic_vmflt_vv_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmflt_vv_nxv1f16_nxv1f16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vmflt.vv v0, v8, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1f16(
- <vscale x 1 x half> %0,
- <vscale x 1 x half> %1,
- i64 %2)
-
- ret <vscale x 1 x i1> %a
-}
-
-declare <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1f16(
- <vscale x 1 x i1>,
- <vscale x 1 x half>,
- <vscale x 1 x half>,
- <vscale x 1 x i1>,
- i64);
-
-define <vscale x 1 x i1> @intrinsic_vmflt_mask_vv_nxv1f16_nxv1f16(<vscale x 1 x i1> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x half> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv1f16_nxv1f16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vmflt.vv v8, v8, v9
-; CHECK-NEXT: vmv1r.v v11, v0
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmflt.vv v11, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v11
-; CHECK-NEXT: ret
-entry:
- %mask = call <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1f16(
- <vscale x 1 x half> %1,
- <vscale x 1 x half> %2,
- i64 %4)
- %a = call <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1f16(
- <vscale x 1 x i1> %0,
- <vscale x 1 x half> %2,
- <vscale x 1 x half> %3,
- <vscale x 1 x i1> %mask,
- i64 %4)
-
- ret <vscale x 1 x i1> %a
-}
-
-declare <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2f16(
- <vscale x 2 x half>,
- <vscale x 2 x half>,
- i64);
-
-define <vscale x 2 x i1> @intrinsic_vmflt_vv_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmflt_vv_nxv2f16_nxv2f16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vmflt.vv v0, v8, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2f16(
- <vscale x 2 x half> %0,
- <vscale x 2 x half> %1,
- i64 %2)
-
- ret <vscale x 2 x i1> %a
-}
-
-declare <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2f16(
- <vscale x 2 x i1>,
- <vscale x 2 x half>,
- <vscale x 2 x half>,
- <vscale x 2 x i1>,
- i64);
-
-define <vscale x 2 x i1> @intrinsic_vmflt_mask_vv_nxv2f16_nxv2f16(<vscale x 2 x i1> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, <vscale x 2 x half> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv2f16_nxv2f16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vmflt.vv v8, v8, v9
-; CHECK-NEXT: vmv1r.v v11, v0
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmflt.vv v11, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v11
-; CHECK-NEXT: ret
-entry:
- %mask = call <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2f16(
- <vscale x 2 x half> %1,
- <vscale x 2 x half> %2,
- i64 %4)
- %a = call <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2f16(
- <vscale x 2 x i1> %0,
- <vscale x 2 x half> %2,
- <vscale x 2 x half> %3,
- <vscale x 2 x i1> %mask,
- i64 %4)
-
- ret <vscale x 2 x i1> %a
-}
-
-declare <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4f16(
- <vscale x 4 x half>,
- <vscale x 4 x half>,
- i64);
-
-define <vscale x 4 x i1> @intrinsic_vmflt_vv_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmflt_vv_nxv4f16_nxv4f16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vmflt.vv v0, v8, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4f16(
- <vscale x 4 x half> %0,
- <vscale x 4 x half> %1,
- i64 %2)
-
- ret <vscale x 4 x i1> %a
-}
-
-declare <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4f16(
- <vscale x 4 x i1>,
- <vscale x 4 x half>,
- <vscale x 4 x half>,
- <vscale x 4 x i1>,
- i64);
-
-define <vscale x 4 x i1> @intrinsic_vmflt_mask_vv_nxv4f16_nxv4f16(<vscale x 4 x i1> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x half> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv4f16_nxv4f16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vmflt.vv v8, v8, v9
-; CHECK-NEXT: vmv1r.v v11, v0
-; CHECK-NEXT: vmv.v.v v0, v8
-; CHECK-NEXT: vmflt.vv v11, v9, v10, v0.t
-; CHECK-NEXT: vmv.v.v v0, v11
-; CHECK-NEXT: ret
-entry:
- %mask = call <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4f16(
- <vscale x 4 x half> %1,
- <vscale x 4 x half> %2,
- i64 %4)
- %a = call <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4f16(
- <vscale x 4 x i1> %0,
- <vscale x 4 x half> %2,
- <vscale x 4 x half> %3,
- <vscale x 4 x i1> %mask,
- i64 %4)
-
- ret <vscale x 4 x i1> %a
-}
-
-declare <vscale x 8 x i1> @llvm.riscv.vmflt.nxv8f16(
- <vscale x 8 x half>,
- <vscale x 8 x half>,
- i64);
-
-define <vscale x 8 x i1> @intrinsic_vmflt_vv_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmflt_vv_nxv8f16_nxv8f16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vmflt.vv v0, v8, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i1> @llvm.riscv.vmflt.nxv8f16(
- <vscale x 8 x half> %0,
- <vscale x 8 x half> %1,
- i64 %2)
-
- ret <vscale x 8 x i1> %a
-}
-
-declare <vscale x 8 x i1> @llvm.riscv.vmflt.mask.nxv8f16(
- <vscale x 8 x i1>,
- <vscale x 8 x half>,
- <vscale x 8 x half>,
- <vscale x 8 x i1>,
- i64);
-
-define <vscale x 8 x i1> @intrinsic_vmflt_mask_vv_nxv8f16_nxv8f16(<vscale x 8 x i1> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x half> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv8f16_nxv8f16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vmflt.vv v14, v8, v10
-; CHECK-NEXT: vmv1r.v v8, v0
-; CHECK-NEXT: vmv1r.v v0, v14
-; CHECK-NEXT: vmflt.vv v8, v10, v12, v0.t
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: ret
-entry:
- %mask = call <vscale x 8 x i1> @llvm.riscv.vmflt.nxv8f16(
- <vscale x 8 x half> %1,
- <vscale x 8 x half> %2,
- i64 %4)
- %a = call <vscale x 8 x i1> @llvm.riscv.vmflt.mask.nxv8f16(
- <vscale x 8 x i1> %0,
- <vscale x 8 x half> %2,
- <vscale x 8 x half> %3,
- <vscale x 8 x i1> %mask,
- i64 %4)
-
- ret <vscale x 8 x i1> %a
-}
-
-declare <vscale x 16 x i1> @llvm.riscv.vmflt.nxv16f16(
- <vscale x 16 x half>,
- <vscale x 16 x half>,
- i64);
-
-define <vscale x 16 x i1> @intrinsic_vmflt_vv_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmflt_vv_nxv16f16_nxv16f16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
-; CHECK-NEXT: vmflt.vv v0, v8, v12
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i1> @llvm.riscv.vmflt.nxv16f16(
- <vscale x 16 x half> %0,
- <vscale x 16 x half> %1,
- i64 %2)
-
- ret <vscale x 16 x i1> %a
-}
-
-declare <vscale x 16 x i1> @llvm.riscv.vmflt.mask.nxv16f16(
- <vscale x 16 x i1>,
- <vscale x 16 x half>,
- <vscale x 16 x half>,
- <vscale x 16 x i1>,
- i64);
-
-define <vscale x 16 x i1> @intrinsic_vmflt_mask_vv_nxv16f16_nxv16f16(<vscale x 16 x i1> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, <vscale x 16 x half> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv16f16_nxv16f16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
-; CHECK-NEXT: vmflt.vv v20, v8, v12
-; CHECK-NEXT: vmv1r.v v8, v0
-; CHECK-NEXT: vmv1r.v v0, v20
-; CHECK-NEXT: vmflt.vv v8, v12, v16, v0.t
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: ret
-entry:
- %mask = call <vscale x 16 x i1> @llvm.riscv.vmflt.nxv16f16(
- <vscale x 16 x half> %1,
- <vscale x 16 x half> %2,
- i64 %4)
- %a = call <vscale x 16 x i1> @llvm.riscv.vmflt.mask.nxv16f16(
- <vscale x 16 x i1> %0,
- <vscale x 16 x half> %2,
- <vscale x 16 x half> %3,
- <vscale x 16 x i1> %mask,
- i64 %4)
-
- ret <vscale x 16 x i1> %a
-}
-
-declare <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1f32(
- <vscale x 1 x float>,
- <vscale x 1 x float>,
- i64);
-
-define <vscale x 1 x i1> @intrinsic_vmflt_vv_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmflt_vv_nxv1f32_nxv1f32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vmflt.vv v0, v8, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1f32(
- <vscale x 1 x float> %0,
- <vscale x 1 x float> %1,
- i64 %2)
-
- ret <vscale x 1 x i1> %a
-}
-
-declare <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1f32(
- <vscale x 1 x i1>,
- <vscale x 1 x float>,
- <vscale x 1 x float>,
- <vscale x 1 x i1>,
- i64);
-
-define <vscale x 1 x i1> @intrinsic_vmflt_mask_vv_nxv1f32_nxv1f32(<vscale x 1 x i1> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, <vscale x 1 x float> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv1f32_nxv1f32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vmflt.vv v8, v8, v9
-; CHECK-NEXT: vmv1r.v v11, v0
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmflt.vv v11, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v11
-; CHECK-NEXT: ret
-entry:
- %mask = call <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1f32(
- <vscale x 1 x float> %1,
- <vscale x 1 x float> %2,
- i64 %4)
- %a = call <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1f32(
- <vscale x 1 x i1> %0,
- <vscale x 1 x float> %2,
- <vscale x 1 x float> %3,
- <vscale x 1 x i1> %mask,
- i64 %4)
-
- ret <vscale x 1 x i1> %a
-}
-
-declare <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2f32(
- <vscale x 2 x float>,
- <vscale x 2 x float>,
- i64);
-
-define <vscale x 2 x i1> @intrinsic_vmflt_vv_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmflt_vv_nxv2f32_nxv2f32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vmflt.vv v0, v8, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2f32(
- <vscale x 2 x float> %0,
- <vscale x 2 x float> %1,
- i64 %2)
-
- ret <vscale x 2 x i1> %a
-}
-
-declare <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2f32(
- <vscale x 2 x i1>,
- <vscale x 2 x float>,
- <vscale x 2 x float>,
- <vscale x 2 x i1>,
- i64);
-
-define <vscale x 2 x i1> @intrinsic_vmflt_mask_vv_nxv2f32_nxv2f32(<vscale x 2 x i1> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x float> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv2f32_nxv2f32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vmflt.vv v8, v8, v9
-; CHECK-NEXT: vmv1r.v v11, v0
-; CHECK-NEXT: vmv.v.v v0, v8
-; CHECK-NEXT: vmflt.vv v11, v9, v10, v0.t
-; CHECK-NEXT: vmv.v.v v0, v11
-; CHECK-NEXT: ret
-entry:
- %mask = call <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2f32(
- <vscale x 2 x float> %1,
- <vscale x 2 x float> %2,
- i64 %4)
- %a = call <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2f32(
- <vscale x 2 x i1> %0,
- <vscale x 2 x float> %2,
- <vscale x 2 x float> %3,
- <vscale x 2 x i1> %mask,
- i64 %4)
-
- ret <vscale x 2 x i1> %a
-}
-
-declare <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4f32(
- <vscale x 4 x float>,
- <vscale x 4 x float>,
- i64);
-
-define <vscale x 4 x i1> @intrinsic_vmflt_vv_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmflt_vv_nxv4f32_nxv4f32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vmflt.vv v0, v8, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4f32(
- <vscale x 4 x float> %0,
- <vscale x 4 x float> %1,
- i64 %2)
-
- ret <vscale x 4 x i1> %a
-}
-
-declare <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4f32(
- <vscale x 4 x i1>,
- <vscale x 4 x float>,
- <vscale x 4 x float>,
- <vscale x 4 x i1>,
- i64);
-
-define <vscale x 4 x i1> @intrinsic_vmflt_mask_vv_nxv4f32_nxv4f32(<vscale x 4 x i1> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x float> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv4f32_nxv4f32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vmflt.vv v14, v8, v10
-; CHECK-NEXT: vmv1r.v v8, v0
-; CHECK-NEXT: vmv1r.v v0, v14
-; CHECK-NEXT: vmflt.vv v8, v10, v12, v0.t
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: ret
-entry:
- %mask = call <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4f32(
- <vscale x 4 x float> %1,
- <vscale x 4 x float> %2,
- i64 %4)
- %a = call <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4f32(
- <vscale x 4 x i1> %0,
- <vscale x 4 x float> %2,
- <vscale x 4 x float> %3,
- <vscale x 4 x i1> %mask,
- i64 %4)
-
- ret <vscale x 4 x i1> %a
-}
-
-declare <vscale x 8 x i1> @llvm.riscv.vmflt.nxv8f32(
- <vscale x 8 x float>,
- <vscale x 8 x float>,
- i64);
-
-define <vscale x 8 x i1> @intrinsic_vmflt_vv_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmflt_vv_nxv8f32_nxv8f32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
-; CHECK-NEXT: vmflt.vv v0, v8, v12
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i1> @llvm.riscv.vmflt.nxv8f32(
- <vscale x 8 x float> %0,
- <vscale x 8 x float> %1,
- i64 %2)
-
- ret <vscale x 8 x i1> %a
-}
-
-declare <vscale x 8 x i1> @llvm.riscv.vmflt.mask.nxv8f32(
- <vscale x 8 x i1>,
- <vscale x 8 x float>,
- <vscale x 8 x float>,
- <vscale x 8 x i1>,
- i64);
-
-define <vscale x 8 x i1> @intrinsic_vmflt_mask_vv_nxv8f32_nxv8f32(<vscale x 8 x i1> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, <vscale x 8 x float> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv8f32_nxv8f32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
-; CHECK-NEXT: vmflt.vv v20, v8, v12
-; CHECK-NEXT: vmv1r.v v8, v0
-; CHECK-NEXT: vmv1r.v v0, v20
-; CHECK-NEXT: vmflt.vv v8, v12, v16, v0.t
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: ret
-entry:
- %mask = call <vscale x 8 x i1> @llvm.riscv.vmflt.nxv8f32(
- <vscale x 8 x float> %1,
- <vscale x 8 x float> %2,
- i64 %4)
- %a = call <vscale x 8 x i1> @llvm.riscv.vmflt.mask.nxv8f32(
- <vscale x 8 x i1> %0,
- <vscale x 8 x float> %2,
- <vscale x 8 x float> %3,
- <vscale x 8 x i1> %mask,
- i64 %4)
-
- ret <vscale x 8 x i1> %a
-}
-
-declare <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1f64(
- <vscale x 1 x double>,
- <vscale x 1 x double>,
- i64);
-
-define <vscale x 1 x i1> @intrinsic_vmflt_vv_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmflt_vv_nxv1f64_nxv1f64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
-; CHECK-NEXT: vmflt.vv v0, v8, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1f64(
- <vscale x 1 x double> %0,
- <vscale x 1 x double> %1,
- i64 %2)
-
- ret <vscale x 1 x i1> %a
-}
-
-declare <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1f64(
- <vscale x 1 x i1>,
- <vscale x 1 x double>,
- <vscale x 1 x double>,
- <vscale x 1 x i1>,
- i64);
-
-define <vscale x 1 x i1> @intrinsic_vmflt_mask_vv_nxv1f64_nxv1f64(<vscale x 1 x i1> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, <vscale x 1 x double> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv1f64_nxv1f64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
-; CHECK-NEXT: vmflt.vv v8, v8, v9
-; CHECK-NEXT: vmv1r.v v11, v0
-; CHECK-NEXT: vmv.v.v v0, v8
-; CHECK-NEXT: vmflt.vv v11, v9, v10, v0.t
-; CHECK-NEXT: vmv.v.v v0, v11
-; CHECK-NEXT: ret
-entry:
- %mask = call <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1f64(
- <vscale x 1 x double> %1,
- <vscale x 1 x double> %2,
- i64 %4)
- %a = call <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1f64(
- <vscale x 1 x i1> %0,
- <vscale x 1 x double> %2,
- <vscale x 1 x double> %3,
- <vscale x 1 x i1> %mask,
- i64 %4)
-
- ret <vscale x 1 x i1> %a
-}
-
-declare <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2f64(
- <vscale x 2 x double>,
- <vscale x 2 x double>,
- i64);
-
-define <vscale x 2 x i1> @intrinsic_vmflt_vv_nxv2f64_nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmflt_vv_nxv2f64_nxv2f64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
-; CHECK-NEXT: vmflt.vv v0, v8, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2f64(
- <vscale x 2 x double> %0,
- <vscale x 2 x double> %1,
- i64 %2)
-
- ret <vscale x 2 x i1> %a
-}
-
-declare <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2f64(
- <vscale x 2 x i1>,
- <vscale x 2 x double>,
- <vscale x 2 x double>,
- <vscale x 2 x i1>,
- i64);
-
-define <vscale x 2 x i1> @intrinsic_vmflt_mask_vv_nxv2f64_nxv2f64(<vscale x 2 x i1> %0, <vscale x 2 x double> %1, <vscale x 2 x double> %2, <vscale x 2 x double> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv2f64_nxv2f64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
-; CHECK-NEXT: vmflt.vv v14, v8, v10
-; CHECK-NEXT: vmv1r.v v8, v0
-; CHECK-NEXT: vmv1r.v v0, v14
-; CHECK-NEXT: vmflt.vv v8, v10, v12, v0.t
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: ret
-entry:
- %mask = call <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2f64(
- <vscale x 2 x double> %1,
- <vscale x 2 x double> %2,
- i64 %4)
- %a = call <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2f64(
- <vscale x 2 x i1> %0,
- <vscale x 2 x double> %2,
- <vscale x 2 x double> %3,
- <vscale x 2 x i1> %mask,
- i64 %4)
-
- ret <vscale x 2 x i1> %a
-}
-
-declare <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4f64(
- <vscale x 4 x double>,
- <vscale x 4 x double>,
- i64);
-
-define <vscale x 4 x i1> @intrinsic_vmflt_vv_nxv4f64_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmflt_vv_nxv4f64_nxv4f64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
-; CHECK-NEXT: vmflt.vv v0, v8, v12
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4f64(
- <vscale x 4 x double> %0,
- <vscale x 4 x double> %1,
- i64 %2)
-
- ret <vscale x 4 x i1> %a
-}
-
-declare <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4f64(
- <vscale x 4 x i1>,
- <vscale x 4 x double>,
- <vscale x 4 x double>,
- <vscale x 4 x i1>,
- i64);
-
-define <vscale x 4 x i1> @intrinsic_vmflt_mask_vv_nxv4f64_nxv4f64(<vscale x 4 x i1> %0, <vscale x 4 x double> %1, <vscale x 4 x double> %2, <vscale x 4 x double> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv4f64_nxv4f64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
-; CHECK-NEXT: vmflt.vv v20, v8, v12
-; CHECK-NEXT: vmv1r.v v8, v0
-; CHECK-NEXT: vmv1r.v v0, v20
-; CHECK-NEXT: vmflt.vv v8, v12, v16, v0.t
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: ret
-entry:
- %mask = call <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4f64(
- <vscale x 4 x double> %1,
- <vscale x 4 x double> %2,
- i64 %4)
- %a = call <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4f64(
- <vscale x 4 x i1> %0,
- <vscale x 4 x double> %2,
- <vscale x 4 x double> %3,
- <vscale x 4 x i1> %mask,
- i64 %4)
-
- ret <vscale x 4 x i1> %a
-}
-
-declare <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1f16.f16(
- <vscale x 1 x half>,
- half,
- i64);
-
-define <vscale x 1 x i1> @intrinsic_vmflt_vf_nxv1f16_f16(<vscale x 1 x half> %0, half %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmflt_vf_nxv1f16_f16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vmflt.vf v0, v8, fa0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1f16.f16(
- <vscale x 1 x half> %0,
- half %1,
- i64 %2)
-
- ret <vscale x 1 x i1> %a
-}
-
-declare <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1f16.f16(
- <vscale x 1 x i1>,
- <vscale x 1 x half>,
- half,
- <vscale x 1 x i1>,
- i64);
-
-define <vscale x 1 x i1> @intrinsic_vmflt_mask_vf_nxv1f16_f16(<vscale x 1 x i1> %0, <vscale x 1 x half> %1, half %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv1f16_f16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v10, v0
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmflt.vf v10, v8, fa0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1f16.f16(
- <vscale x 1 x i1> %0,
- <vscale x 1 x half> %1,
- half %2,
- <vscale x 1 x i1> %3,
- i64 %4)
-
- ret <vscale x 1 x i1> %a
-}
-
-declare <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2f16.f16(
- <vscale x 2 x half>,
- half,
- i64);
-
-define <vscale x 2 x i1> @intrinsic_vmflt_vf_nxv2f16_f16(<vscale x 2 x half> %0, half %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmflt_vf_nxv2f16_f16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vmflt.vf v0, v8, fa0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2f16.f16(
- <vscale x 2 x half> %0,
- half %1,
- i64 %2)
-
- ret <vscale x 2 x i1> %a
-}
-
-declare <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2f16.f16(
- <vscale x 2 x i1>,
- <vscale x 2 x half>,
- half,
- <vscale x 2 x i1>,
- i64);
-
-define <vscale x 2 x i1> @intrinsic_vmflt_mask_vf_nxv2f16_f16(<vscale x 2 x i1> %0, <vscale x 2 x half> %1, half %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv2f16_f16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v10, v0
-; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmflt.vf v10, v8, fa0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2f16.f16(
- <vscale x 2 x i1> %0,
- <vscale x 2 x half> %1,
- half %2,
- <vscale x 2 x i1> %3,
- i64 %4)
-
- ret <vscale x 2 x i1> %a
-}
-
-declare <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4f16.f16(
- <vscale x 4 x half>,
- half,
- i64);
-
-define <vscale x 4 x i1> @intrinsic_vmflt_vf_nxv4f16_f16(<vscale x 4 x half> %0, half %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmflt_vf_nxv4f16_f16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vmflt.vf v0, v8, fa0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4f16.f16(
- <vscale x 4 x half> %0,
- half %1,
- i64 %2)
-
- ret <vscale x 4 x i1> %a
-}
-
-declare <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4f16.f16(
- <vscale x 4 x i1>,
- <vscale x 4 x half>,
- half,
- <vscale x 4 x i1>,
- i64);
-
-define <vscale x 4 x i1> @intrinsic_vmflt_mask_vf_nxv4f16_f16(<vscale x 4 x i1> %0, <vscale x 4 x half> %1, half %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv4f16_f16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v10, v0
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmflt.vf v10, v8, fa0, v0.t
-; CHECK-NEXT: vmv.v.v v0, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4f16.f16(
- <vscale x 4 x i1> %0,
- <vscale x 4 x half> %1,
- half %2,
- <vscale x 4 x i1> %3,
- i64 %4)
-
- ret <vscale x 4 x i1> %a
-}
-
-declare <vscale x 8 x i1> @llvm.riscv.vmflt.nxv8f16.f16(
- <vscale x 8 x half>,
- half,
- i64);
-
-define <vscale x 8 x i1> @intrinsic_vmflt_vf_nxv8f16_f16(<vscale x 8 x half> %0, half %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmflt_vf_nxv8f16_f16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vmflt.vf v0, v8, fa0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i1> @llvm.riscv.vmflt.nxv8f16.f16(
- <vscale x 8 x half> %0,
- half %1,
- i64 %2)
-
- ret <vscale x 8 x i1> %a
-}
-
-declare <vscale x 8 x i1> @llvm.riscv.vmflt.mask.nxv8f16.f16(
- <vscale x 8 x i1>,
- <vscale x 8 x half>,
- half,
- <vscale x 8 x i1>,
- i64);
-
-define <vscale x 8 x i1> @intrinsic_vmflt_mask_vf_nxv8f16_f16(<vscale x 8 x i1> %0, <vscale x 8 x half> %1, half %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv8f16_f16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v11, v0
-; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmflt.vf v11, v8, fa0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v11
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i1> @llvm.riscv.vmflt.mask.nxv8f16.f16(
- <vscale x 8 x i1> %0,
- <vscale x 8 x half> %1,
- half %2,
- <vscale x 8 x i1> %3,
- i64 %4)
-
- ret <vscale x 8 x i1> %a
-}
-
-declare <vscale x 16 x i1> @llvm.riscv.vmflt.nxv16f16.f16(
- <vscale x 16 x half>,
- half,
- i64);
-
-define <vscale x 16 x i1> @intrinsic_vmflt_vf_nxv16f16_f16(<vscale x 16 x half> %0, half %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmflt_vf_nxv16f16_f16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
-; CHECK-NEXT: vmflt.vf v0, v8, fa0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i1> @llvm.riscv.vmflt.nxv16f16.f16(
- <vscale x 16 x half> %0,
- half %1,
- i64 %2)
-
- ret <vscale x 16 x i1> %a
-}
-
-declare <vscale x 16 x i1> @llvm.riscv.vmflt.mask.nxv16f16.f16(
- <vscale x 16 x i1>,
- <vscale x 16 x half>,
- half,
- <vscale x 16 x i1>,
- i64);
-
-define <vscale x 16 x i1> @intrinsic_vmflt_mask_vf_nxv16f16_f16(<vscale x 16 x i1> %0, <vscale x 16 x half> %1, half %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv16f16_f16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v13, v0
-; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
-; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmflt.vf v13, v8, fa0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v13
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i1> @llvm.riscv.vmflt.mask.nxv16f16.f16(
- <vscale x 16 x i1> %0,
- <vscale x 16 x half> %1,
- half %2,
- <vscale x 16 x i1> %3,
- i64 %4)
-
- ret <vscale x 16 x i1> %a
-}
-
-declare <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1f32.f32(
- <vscale x 1 x float>,
- float,
- i64);
-
-define <vscale x 1 x i1> @intrinsic_vmflt_vf_nxv1f32_f32(<vscale x 1 x float> %0, float %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmflt_vf_nxv1f32_f32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vmflt.vf v0, v8, fa0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1f32.f32(
- <vscale x 1 x float> %0,
- float %1,
- i64 %2)
-
- ret <vscale x 1 x i1> %a
-}
-
-declare <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1f32.f32(
- <vscale x 1 x i1>,
- <vscale x 1 x float>,
- float,
- <vscale x 1 x i1>,
- i64);
-
-define <vscale x 1 x i1> @intrinsic_vmflt_mask_vf_nxv1f32_f32(<vscale x 1 x i1> %0, <vscale x 1 x float> %1, float %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv1f32_f32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v10, v0
-; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmflt.vf v10, v8, fa0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1f32.f32(
- <vscale x 1 x i1> %0,
- <vscale x 1 x float> %1,
- float %2,
- <vscale x 1 x i1> %3,
- i64 %4)
-
- ret <vscale x 1 x i1> %a
-}
-
-declare <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2f32.f32(
- <vscale x 2 x float>,
- float,
- i64);
-
-define <vscale x 2 x i1> @intrinsic_vmflt_vf_nxv2f32_f32(<vscale x 2 x float> %0, float %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmflt_vf_nxv2f32_f32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vmflt.vf v0, v8, fa0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2f32.f32(
- <vscale x 2 x float> %0,
- float %1,
- i64 %2)
-
- ret <vscale x 2 x i1> %a
-}
-
-declare <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2f32.f32(
- <vscale x 2 x i1>,
- <vscale x 2 x float>,
- float,
- <vscale x 2 x i1>,
- i64);
-
-define <vscale x 2 x i1> @intrinsic_vmflt_mask_vf_nxv2f32_f32(<vscale x 2 x i1> %0, <vscale x 2 x float> %1, float %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv2f32_f32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v10, v0
-; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmflt.vf v10, v8, fa0, v0.t
-; CHECK-NEXT: vmv.v.v v0, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2f32.f32(
- <vscale x 2 x i1> %0,
- <vscale x 2 x float> %1,
- float %2,
- <vscale x 2 x i1> %3,
- i64 %4)
-
- ret <vscale x 2 x i1> %a
-}
-
-declare <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4f32.f32(
- <vscale x 4 x float>,
- float,
- i64);
-
-define <vscale x 4 x i1> @intrinsic_vmflt_vf_nxv4f32_f32(<vscale x 4 x float> %0, float %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmflt_vf_nxv4f32_f32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vmflt.vf v0, v8, fa0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4f32.f32(
- <vscale x 4 x float> %0,
- float %1,
- i64 %2)
-
- ret <vscale x 4 x i1> %a
-}
-
-declare <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4f32.f32(
- <vscale x 4 x i1>,
- <vscale x 4 x float>,
- float,
- <vscale x 4 x i1>,
- i64);
-
-define <vscale x 4 x i1> @intrinsic_vmflt_mask_vf_nxv4f32_f32(<vscale x 4 x i1> %0, <vscale x 4 x float> %1, float %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv4f32_f32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v11, v0
-; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmflt.vf v11, v8, fa0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v11
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4f32.f32(
- <vscale x 4 x i1> %0,
- <vscale x 4 x float> %1,
- float %2,
- <vscale x 4 x i1> %3,
- i64 %4)
-
- ret <vscale x 4 x i1> %a
-}
-
-declare <vscale x 8 x i1> @llvm.riscv.vmflt.nxv8f32.f32(
- <vscale x 8 x float>,
- float,
- i64);
-
-define <vscale x 8 x i1> @intrinsic_vmflt_vf_nxv8f32_f32(<vscale x 8 x float> %0, float %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmflt_vf_nxv8f32_f32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
-; CHECK-NEXT: vmflt.vf v0, v8, fa0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i1> @llvm.riscv.vmflt.nxv8f32.f32(
- <vscale x 8 x float> %0,
- float %1,
- i64 %2)
-
- ret <vscale x 8 x i1> %a
-}
-
-declare <vscale x 8 x i1> @llvm.riscv.vmflt.mask.nxv8f32.f32(
- <vscale x 8 x i1>,
- <vscale x 8 x float>,
- float,
- <vscale x 8 x i1>,
- i64);
-
-define <vscale x 8 x i1> @intrinsic_vmflt_mask_vf_nxv8f32_f32(<vscale x 8 x i1> %0, <vscale x 8 x float> %1, float %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv8f32_f32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v13, v0
-; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
-; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmflt.vf v13, v8, fa0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v13
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i1> @llvm.riscv.vmflt.mask.nxv8f32.f32(
- <vscale x 8 x i1> %0,
- <vscale x 8 x float> %1,
- float %2,
- <vscale x 8 x i1> %3,
- i64 %4)
-
- ret <vscale x 8 x i1> %a
-}
-
-declare <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1f64.f64(
- <vscale x 1 x double>,
- double,
- i64);
-
-define <vscale x 1 x i1> @intrinsic_vmflt_vf_nxv1f64_f64(<vscale x 1 x double> %0, double %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmflt_vf_nxv1f64_f64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
-; CHECK-NEXT: vmflt.vf v0, v8, fa0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1f64.f64(
- <vscale x 1 x double> %0,
- double %1,
- i64 %2)
-
- ret <vscale x 1 x i1> %a
-}
-
-declare <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1f64.f64(
- <vscale x 1 x i1>,
- <vscale x 1 x double>,
- double,
- <vscale x 1 x i1>,
- i64);
-
-define <vscale x 1 x i1> @intrinsic_vmflt_mask_vf_nxv1f64_f64(<vscale x 1 x i1> %0, <vscale x 1 x double> %1, double %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv1f64_f64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v10, v0
-; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
-; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmflt.vf v10, v8, fa0, v0.t
-; CHECK-NEXT: vmv.v.v v0, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1f64.f64(
- <vscale x 1 x i1> %0,
- <vscale x 1 x double> %1,
- double %2,
- <vscale x 1 x i1> %3,
- i64 %4)
-
- ret <vscale x 1 x i1> %a
-}
-
-declare <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2f64.f64(
- <vscale x 2 x double>,
- double,
- i64);
-
-define <vscale x 2 x i1> @intrinsic_vmflt_vf_nxv2f64_f64(<vscale x 2 x double> %0, double %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmflt_vf_nxv2f64_f64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
-; CHECK-NEXT: vmflt.vf v0, v8, fa0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2f64.f64(
- <vscale x 2 x double> %0,
- double %1,
- i64 %2)
-
- ret <vscale x 2 x i1> %a
-}
-
-declare <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2f64.f64(
- <vscale x 2 x i1>,
- <vscale x 2 x double>,
- double,
- <vscale x 2 x i1>,
- i64);
-
-define <vscale x 2 x i1> @intrinsic_vmflt_mask_vf_nxv2f64_f64(<vscale x 2 x i1> %0, <vscale x 2 x double> %1, double %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv2f64_f64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v11, v0
-; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
-; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmflt.vf v11, v8, fa0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v11
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2f64.f64(
- <vscale x 2 x i1> %0,
- <vscale x 2 x double> %1,
- double %2,
- <vscale x 2 x i1> %3,
- i64 %4)
-
- ret <vscale x 2 x i1> %a
-}
-
-declare <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4f64.f64(
- <vscale x 4 x double>,
- double,
- i64);
-
-define <vscale x 4 x i1> @intrinsic_vmflt_vf_nxv4f64_f64(<vscale x 4 x double> %0, double %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmflt_vf_nxv4f64_f64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
-; CHECK-NEXT: vmflt.vf v0, v8, fa0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4f64.f64(
- <vscale x 4 x double> %0,
- double %1,
- i64 %2)
-
- ret <vscale x 4 x i1> %a
-}
-
-declare <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4f64.f64(
- <vscale x 4 x i1>,
- <vscale x 4 x double>,
- double,
- <vscale x 4 x i1>,
- i64);
-
-define <vscale x 4 x i1> @intrinsic_vmflt_mask_vf_nxv4f64_f64(<vscale x 4 x i1> %0, <vscale x 4 x double> %1, double %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv4f64_f64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v13, v0
-; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
-; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmflt.vf v13, v8, fa0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v13
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4f64.f64(
- <vscale x 4 x i1> %0,
- <vscale x 4 x double> %1,
- double %2,
- <vscale x 4 x i1> %3,
- i64 %4)
-
- ret <vscale x 4 x i1> %a
-}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmflt-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmflt.ll
similarity index 88%
rename from llvm/test/CodeGen/RISCV/rvv/vmflt-rv32.ll
rename to llvm/test/CodeGen/RISCV/rvv/vmflt.ll
index 80bb12e6db9f6..f0ef01fae96a8 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vmflt-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vmflt.ll
@@ -1,12 +1,14 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -mattr=+v,+d,+zfh -verify-machineinstrs \
-; RUN: -target-abi=ilp32d < %s | FileCheck %s
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh \
+; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh \
+; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s
declare <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1f16(
<vscale x 1 x half>,
<vscale x 1 x half>,
- i32);
+ iXLen);
-define <vscale x 1 x i1> @intrinsic_vmflt_vv_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i32 %2) nounwind {
+define <vscale x 1 x i1> @intrinsic_vmflt_vv_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmflt_vv_nxv1f16_nxv1f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
@@ -16,7 +18,7 @@ entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1f16(
<vscale x 1 x half> %0,
<vscale x 1 x half> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 1 x i1> %a
}
@@ -26,9 +28,9 @@ declare <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1f16(
<vscale x 1 x half>,
<vscale x 1 x half>,
<vscale x 1 x i1>,
- i32);
+ iXLen);
-define <vscale x 1 x i1> @intrinsic_vmflt_mask_vv_nxv1f16_nxv1f16(<vscale x 1 x i1> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x half> %3, i32 %4) nounwind {
+define <vscale x 1 x i1> @intrinsic_vmflt_mask_vv_nxv1f16_nxv1f16(<vscale x 1 x i1> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x half> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv1f16_nxv1f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
@@ -42,13 +44,13 @@ entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1f16(
<vscale x 1 x half> %1,
<vscale x 1 x half> %2,
- i32 %4)
+ iXLen %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1f16(
<vscale x 1 x i1> %0,
<vscale x 1 x half> %2,
<vscale x 1 x half> %3,
<vscale x 1 x i1> %mask,
- i32 %4)
+ iXLen %4)
ret <vscale x 1 x i1> %a
}
@@ -56,9 +58,9 @@ entry:
declare <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2f16(
<vscale x 2 x half>,
<vscale x 2 x half>,
- i32);
+ iXLen);
-define <vscale x 2 x i1> @intrinsic_vmflt_vv_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i32 %2) nounwind {
+define <vscale x 2 x i1> @intrinsic_vmflt_vv_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmflt_vv_nxv2f16_nxv2f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
@@ -68,7 +70,7 @@ entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2f16(
<vscale x 2 x half> %0,
<vscale x 2 x half> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 2 x i1> %a
}
@@ -78,9 +80,9 @@ declare <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2f16(
<vscale x 2 x half>,
<vscale x 2 x half>,
<vscale x 2 x i1>,
- i32);
+ iXLen);
-define <vscale x 2 x i1> @intrinsic_vmflt_mask_vv_nxv2f16_nxv2f16(<vscale x 2 x i1> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, <vscale x 2 x half> %3, i32 %4) nounwind {
+define <vscale x 2 x i1> @intrinsic_vmflt_mask_vv_nxv2f16_nxv2f16(<vscale x 2 x i1> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, <vscale x 2 x half> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv2f16_nxv2f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
@@ -94,13 +96,13 @@ entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2f16(
<vscale x 2 x half> %1,
<vscale x 2 x half> %2,
- i32 %4)
+ iXLen %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2f16(
<vscale x 2 x i1> %0,
<vscale x 2 x half> %2,
<vscale x 2 x half> %3,
<vscale x 2 x i1> %mask,
- i32 %4)
+ iXLen %4)
ret <vscale x 2 x i1> %a
}
@@ -108,9 +110,9 @@ entry:
declare <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4f16(
<vscale x 4 x half>,
<vscale x 4 x half>,
- i32);
+ iXLen);
-define <vscale x 4 x i1> @intrinsic_vmflt_vv_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i32 %2) nounwind {
+define <vscale x 4 x i1> @intrinsic_vmflt_vv_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmflt_vv_nxv4f16_nxv4f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
@@ -120,7 +122,7 @@ entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4f16(
<vscale x 4 x half> %0,
<vscale x 4 x half> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 4 x i1> %a
}
@@ -130,9 +132,9 @@ declare <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4f16(
<vscale x 4 x half>,
<vscale x 4 x half>,
<vscale x 4 x i1>,
- i32);
+ iXLen);
-define <vscale x 4 x i1> @intrinsic_vmflt_mask_vv_nxv4f16_nxv4f16(<vscale x 4 x i1> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x half> %3, i32 %4) nounwind {
+define <vscale x 4 x i1> @intrinsic_vmflt_mask_vv_nxv4f16_nxv4f16(<vscale x 4 x i1> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x half> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv4f16_nxv4f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
@@ -146,13 +148,13 @@ entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4f16(
<vscale x 4 x half> %1,
<vscale x 4 x half> %2,
- i32 %4)
+ iXLen %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4f16(
<vscale x 4 x i1> %0,
<vscale x 4 x half> %2,
<vscale x 4 x half> %3,
<vscale x 4 x i1> %mask,
- i32 %4)
+ iXLen %4)
ret <vscale x 4 x i1> %a
}
@@ -160,9 +162,9 @@ entry:
declare <vscale x 8 x i1> @llvm.riscv.vmflt.nxv8f16(
<vscale x 8 x half>,
<vscale x 8 x half>,
- i32);
+ iXLen);
-define <vscale x 8 x i1> @intrinsic_vmflt_vv_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i32 %2) nounwind {
+define <vscale x 8 x i1> @intrinsic_vmflt_vv_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmflt_vv_nxv8f16_nxv8f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
@@ -172,7 +174,7 @@ entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmflt.nxv8f16(
<vscale x 8 x half> %0,
<vscale x 8 x half> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 8 x i1> %a
}
@@ -182,9 +184,9 @@ declare <vscale x 8 x i1> @llvm.riscv.vmflt.mask.nxv8f16(
<vscale x 8 x half>,
<vscale x 8 x half>,
<vscale x 8 x i1>,
- i32);
+ iXLen);
-define <vscale x 8 x i1> @intrinsic_vmflt_mask_vv_nxv8f16_nxv8f16(<vscale x 8 x i1> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x half> %3, i32 %4) nounwind {
+define <vscale x 8 x i1> @intrinsic_vmflt_mask_vv_nxv8f16_nxv8f16(<vscale x 8 x i1> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x half> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv8f16_nxv8f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
@@ -198,13 +200,13 @@ entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmflt.nxv8f16(
<vscale x 8 x half> %1,
<vscale x 8 x half> %2,
- i32 %4)
+ iXLen %4)
%a = call <vscale x 8 x i1> @llvm.riscv.vmflt.mask.nxv8f16(
<vscale x 8 x i1> %0,
<vscale x 8 x half> %2,
<vscale x 8 x half> %3,
<vscale x 8 x i1> %mask,
- i32 %4)
+ iXLen %4)
ret <vscale x 8 x i1> %a
}
@@ -212,9 +214,9 @@ entry:
declare <vscale x 16 x i1> @llvm.riscv.vmflt.nxv16f16(
<vscale x 16 x half>,
<vscale x 16 x half>,
- i32);
+ iXLen);
-define <vscale x 16 x i1> @intrinsic_vmflt_vv_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i32 %2) nounwind {
+define <vscale x 16 x i1> @intrinsic_vmflt_vv_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmflt_vv_nxv16f16_nxv16f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
@@ -224,7 +226,7 @@ entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmflt.nxv16f16(
<vscale x 16 x half> %0,
<vscale x 16 x half> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 16 x i1> %a
}
@@ -234,9 +236,9 @@ declare <vscale x 16 x i1> @llvm.riscv.vmflt.mask.nxv16f16(
<vscale x 16 x half>,
<vscale x 16 x half>,
<vscale x 16 x i1>,
- i32);
+ iXLen);
-define <vscale x 16 x i1> @intrinsic_vmflt_mask_vv_nxv16f16_nxv16f16(<vscale x 16 x i1> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, <vscale x 16 x half> %3, i32 %4) nounwind {
+define <vscale x 16 x i1> @intrinsic_vmflt_mask_vv_nxv16f16_nxv16f16(<vscale x 16 x i1> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, <vscale x 16 x half> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv16f16_nxv16f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
@@ -250,13 +252,13 @@ entry:
%mask = call <vscale x 16 x i1> @llvm.riscv.vmflt.nxv16f16(
<vscale x 16 x half> %1,
<vscale x 16 x half> %2,
- i32 %4)
+ iXLen %4)
%a = call <vscale x 16 x i1> @llvm.riscv.vmflt.mask.nxv16f16(
<vscale x 16 x i1> %0,
<vscale x 16 x half> %2,
<vscale x 16 x half> %3,
<vscale x 16 x i1> %mask,
- i32 %4)
+ iXLen %4)
ret <vscale x 16 x i1> %a
}
@@ -264,9 +266,9 @@ entry:
declare <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1f32(
<vscale x 1 x float>,
<vscale x 1 x float>,
- i32);
+ iXLen);
-define <vscale x 1 x i1> @intrinsic_vmflt_vv_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, i32 %2) nounwind {
+define <vscale x 1 x i1> @intrinsic_vmflt_vv_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmflt_vv_nxv1f32_nxv1f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
@@ -276,7 +278,7 @@ entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1f32(
<vscale x 1 x float> %0,
<vscale x 1 x float> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 1 x i1> %a
}
@@ -286,9 +288,9 @@ declare <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1f32(
<vscale x 1 x float>,
<vscale x 1 x float>,
<vscale x 1 x i1>,
- i32);
+ iXLen);
-define <vscale x 1 x i1> @intrinsic_vmflt_mask_vv_nxv1f32_nxv1f32(<vscale x 1 x i1> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, <vscale x 1 x float> %3, i32 %4) nounwind {
+define <vscale x 1 x i1> @intrinsic_vmflt_mask_vv_nxv1f32_nxv1f32(<vscale x 1 x i1> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, <vscale x 1 x float> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv1f32_nxv1f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
@@ -302,13 +304,13 @@ entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1f32(
<vscale x 1 x float> %1,
<vscale x 1 x float> %2,
- i32 %4)
+ iXLen %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1f32(
<vscale x 1 x i1> %0,
<vscale x 1 x float> %2,
<vscale x 1 x float> %3,
<vscale x 1 x i1> %mask,
- i32 %4)
+ iXLen %4)
ret <vscale x 1 x i1> %a
}
@@ -316,9 +318,9 @@ entry:
declare <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2f32(
<vscale x 2 x float>,
<vscale x 2 x float>,
- i32);
+ iXLen);
-define <vscale x 2 x i1> @intrinsic_vmflt_vv_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, i32 %2) nounwind {
+define <vscale x 2 x i1> @intrinsic_vmflt_vv_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmflt_vv_nxv2f32_nxv2f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
@@ -328,7 +330,7 @@ entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2f32(
<vscale x 2 x float> %0,
<vscale x 2 x float> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 2 x i1> %a
}
@@ -338,9 +340,9 @@ declare <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2f32(
<vscale x 2 x float>,
<vscale x 2 x float>,
<vscale x 2 x i1>,
- i32);
+ iXLen);
-define <vscale x 2 x i1> @intrinsic_vmflt_mask_vv_nxv2f32_nxv2f32(<vscale x 2 x i1> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x float> %3, i32 %4) nounwind {
+define <vscale x 2 x i1> @intrinsic_vmflt_mask_vv_nxv2f32_nxv2f32(<vscale x 2 x i1> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x float> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv2f32_nxv2f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
@@ -354,13 +356,13 @@ entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2f32(
<vscale x 2 x float> %1,
<vscale x 2 x float> %2,
- i32 %4)
+ iXLen %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2f32(
<vscale x 2 x i1> %0,
<vscale x 2 x float> %2,
<vscale x 2 x float> %3,
<vscale x 2 x i1> %mask,
- i32 %4)
+ iXLen %4)
ret <vscale x 2 x i1> %a
}
@@ -368,9 +370,9 @@ entry:
declare <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4f32(
<vscale x 4 x float>,
<vscale x 4 x float>,
- i32);
+ iXLen);
-define <vscale x 4 x i1> @intrinsic_vmflt_vv_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, i32 %2) nounwind {
+define <vscale x 4 x i1> @intrinsic_vmflt_vv_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmflt_vv_nxv4f32_nxv4f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
@@ -380,7 +382,7 @@ entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4f32(
<vscale x 4 x float> %0,
<vscale x 4 x float> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 4 x i1> %a
}
@@ -390,9 +392,9 @@ declare <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4f32(
<vscale x 4 x float>,
<vscale x 4 x float>,
<vscale x 4 x i1>,
- i32);
+ iXLen);
-define <vscale x 4 x i1> @intrinsic_vmflt_mask_vv_nxv4f32_nxv4f32(<vscale x 4 x i1> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x float> %3, i32 %4) nounwind {
+define <vscale x 4 x i1> @intrinsic_vmflt_mask_vv_nxv4f32_nxv4f32(<vscale x 4 x i1> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x float> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv4f32_nxv4f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
@@ -406,13 +408,13 @@ entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4f32(
<vscale x 4 x float> %1,
<vscale x 4 x float> %2,
- i32 %4)
+ iXLen %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4f32(
<vscale x 4 x i1> %0,
<vscale x 4 x float> %2,
<vscale x 4 x float> %3,
<vscale x 4 x i1> %mask,
- i32 %4)
+ iXLen %4)
ret <vscale x 4 x i1> %a
}
@@ -420,9 +422,9 @@ entry:
declare <vscale x 8 x i1> @llvm.riscv.vmflt.nxv8f32(
<vscale x 8 x float>,
<vscale x 8 x float>,
- i32);
+ iXLen);
-define <vscale x 8 x i1> @intrinsic_vmflt_vv_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, i32 %2) nounwind {
+define <vscale x 8 x i1> @intrinsic_vmflt_vv_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmflt_vv_nxv8f32_nxv8f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
@@ -432,7 +434,7 @@ entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmflt.nxv8f32(
<vscale x 8 x float> %0,
<vscale x 8 x float> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 8 x i1> %a
}
@@ -442,9 +444,9 @@ declare <vscale x 8 x i1> @llvm.riscv.vmflt.mask.nxv8f32(
<vscale x 8 x float>,
<vscale x 8 x float>,
<vscale x 8 x i1>,
- i32);
+ iXLen);
-define <vscale x 8 x i1> @intrinsic_vmflt_mask_vv_nxv8f32_nxv8f32(<vscale x 8 x i1> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, <vscale x 8 x float> %3, i32 %4) nounwind {
+define <vscale x 8 x i1> @intrinsic_vmflt_mask_vv_nxv8f32_nxv8f32(<vscale x 8 x i1> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, <vscale x 8 x float> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv8f32_nxv8f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
@@ -458,13 +460,13 @@ entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmflt.nxv8f32(
<vscale x 8 x float> %1,
<vscale x 8 x float> %2,
- i32 %4)
+ iXLen %4)
%a = call <vscale x 8 x i1> @llvm.riscv.vmflt.mask.nxv8f32(
<vscale x 8 x i1> %0,
<vscale x 8 x float> %2,
<vscale x 8 x float> %3,
<vscale x 8 x i1> %mask,
- i32 %4)
+ iXLen %4)
ret <vscale x 8 x i1> %a
}
@@ -472,9 +474,9 @@ entry:
declare <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1f64(
<vscale x 1 x double>,
<vscale x 1 x double>,
- i32);
+ iXLen);
-define <vscale x 1 x i1> @intrinsic_vmflt_vv_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, i32 %2) nounwind {
+define <vscale x 1 x i1> @intrinsic_vmflt_vv_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmflt_vv_nxv1f64_nxv1f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
@@ -484,7 +486,7 @@ entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1f64(
<vscale x 1 x double> %0,
<vscale x 1 x double> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 1 x i1> %a
}
@@ -494,9 +496,9 @@ declare <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1f64(
<vscale x 1 x double>,
<vscale x 1 x double>,
<vscale x 1 x i1>,
- i32);
+ iXLen);
-define <vscale x 1 x i1> @intrinsic_vmflt_mask_vv_nxv1f64_nxv1f64(<vscale x 1 x i1> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, <vscale x 1 x double> %3, i32 %4) nounwind {
+define <vscale x 1 x i1> @intrinsic_vmflt_mask_vv_nxv1f64_nxv1f64(<vscale x 1 x i1> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, <vscale x 1 x double> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv1f64_nxv1f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
@@ -510,13 +512,13 @@ entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1f64(
<vscale x 1 x double> %1,
<vscale x 1 x double> %2,
- i32 %4)
+ iXLen %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1f64(
<vscale x 1 x i1> %0,
<vscale x 1 x double> %2,
<vscale x 1 x double> %3,
<vscale x 1 x i1> %mask,
- i32 %4)
+ iXLen %4)
ret <vscale x 1 x i1> %a
}
@@ -524,9 +526,9 @@ entry:
declare <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2f64(
<vscale x 2 x double>,
<vscale x 2 x double>,
- i32);
+ iXLen);
-define <vscale x 2 x i1> @intrinsic_vmflt_vv_nxv2f64_nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, i32 %2) nounwind {
+define <vscale x 2 x i1> @intrinsic_vmflt_vv_nxv2f64_nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmflt_vv_nxv2f64_nxv2f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
@@ -536,7 +538,7 @@ entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2f64(
<vscale x 2 x double> %0,
<vscale x 2 x double> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 2 x i1> %a
}
@@ -546,9 +548,9 @@ declare <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2f64(
<vscale x 2 x double>,
<vscale x 2 x double>,
<vscale x 2 x i1>,
- i32);
+ iXLen);
-define <vscale x 2 x i1> @intrinsic_vmflt_mask_vv_nxv2f64_nxv2f64(<vscale x 2 x i1> %0, <vscale x 2 x double> %1, <vscale x 2 x double> %2, <vscale x 2 x double> %3, i32 %4) nounwind {
+define <vscale x 2 x i1> @intrinsic_vmflt_mask_vv_nxv2f64_nxv2f64(<vscale x 2 x i1> %0, <vscale x 2 x double> %1, <vscale x 2 x double> %2, <vscale x 2 x double> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv2f64_nxv2f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
@@ -562,13 +564,13 @@ entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2f64(
<vscale x 2 x double> %1,
<vscale x 2 x double> %2,
- i32 %4)
+ iXLen %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2f64(
<vscale x 2 x i1> %0,
<vscale x 2 x double> %2,
<vscale x 2 x double> %3,
<vscale x 2 x i1> %mask,
- i32 %4)
+ iXLen %4)
ret <vscale x 2 x i1> %a
}
@@ -576,9 +578,9 @@ entry:
declare <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4f64(
<vscale x 4 x double>,
<vscale x 4 x double>,
- i32);
+ iXLen);
-define <vscale x 4 x i1> @intrinsic_vmflt_vv_nxv4f64_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, i32 %2) nounwind {
+define <vscale x 4 x i1> @intrinsic_vmflt_vv_nxv4f64_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmflt_vv_nxv4f64_nxv4f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
@@ -588,7 +590,7 @@ entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4f64(
<vscale x 4 x double> %0,
<vscale x 4 x double> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 4 x i1> %a
}
@@ -598,9 +600,9 @@ declare <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4f64(
<vscale x 4 x double>,
<vscale x 4 x double>,
<vscale x 4 x i1>,
- i32);
+ iXLen);
-define <vscale x 4 x i1> @intrinsic_vmflt_mask_vv_nxv4f64_nxv4f64(<vscale x 4 x i1> %0, <vscale x 4 x double> %1, <vscale x 4 x double> %2, <vscale x 4 x double> %3, i32 %4) nounwind {
+define <vscale x 4 x i1> @intrinsic_vmflt_mask_vv_nxv4f64_nxv4f64(<vscale x 4 x i1> %0, <vscale x 4 x double> %1, <vscale x 4 x double> %2, <vscale x 4 x double> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv4f64_nxv4f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
@@ -614,13 +616,13 @@ entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4f64(
<vscale x 4 x double> %1,
<vscale x 4 x double> %2,
- i32 %4)
+ iXLen %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4f64(
<vscale x 4 x i1> %0,
<vscale x 4 x double> %2,
<vscale x 4 x double> %3,
<vscale x 4 x i1> %mask,
- i32 %4)
+ iXLen %4)
ret <vscale x 4 x i1> %a
}
@@ -628,9 +630,9 @@ entry:
declare <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1f16.f16(
<vscale x 1 x half>,
half,
- i32);
+ iXLen);
-define <vscale x 1 x i1> @intrinsic_vmflt_vf_nxv1f16_f16(<vscale x 1 x half> %0, half %1, i32 %2) nounwind {
+define <vscale x 1 x i1> @intrinsic_vmflt_vf_nxv1f16_f16(<vscale x 1 x half> %0, half %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmflt_vf_nxv1f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
@@ -640,7 +642,7 @@ entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1f16.f16(
<vscale x 1 x half> %0,
half %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 1 x i1> %a
}
@@ -650,9 +652,9 @@ declare <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1f16.f16(
<vscale x 1 x half>,
half,
<vscale x 1 x i1>,
- i32);
+ iXLen);
-define <vscale x 1 x i1> @intrinsic_vmflt_mask_vf_nxv1f16_f16(<vscale x 1 x i1> %0, <vscale x 1 x half> %1, half %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+define <vscale x 1 x i1> @intrinsic_vmflt_mask_vf_nxv1f16_f16(<vscale x 1 x i1> %0, <vscale x 1 x half> %1, half %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv1f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0
@@ -667,7 +669,7 @@ entry:
<vscale x 1 x half> %1,
half %2,
<vscale x 1 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 1 x i1> %a
}
@@ -675,9 +677,9 @@ entry:
declare <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2f16.f16(
<vscale x 2 x half>,
half,
- i32);
+ iXLen);
-define <vscale x 2 x i1> @intrinsic_vmflt_vf_nxv2f16_f16(<vscale x 2 x half> %0, half %1, i32 %2) nounwind {
+define <vscale x 2 x i1> @intrinsic_vmflt_vf_nxv2f16_f16(<vscale x 2 x half> %0, half %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmflt_vf_nxv2f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
@@ -687,7 +689,7 @@ entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2f16.f16(
<vscale x 2 x half> %0,
half %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 2 x i1> %a
}
@@ -697,9 +699,9 @@ declare <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2f16.f16(
<vscale x 2 x half>,
half,
<vscale x 2 x i1>,
- i32);
+ iXLen);
-define <vscale x 2 x i1> @intrinsic_vmflt_mask_vf_nxv2f16_f16(<vscale x 2 x i1> %0, <vscale x 2 x half> %1, half %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+define <vscale x 2 x i1> @intrinsic_vmflt_mask_vf_nxv2f16_f16(<vscale x 2 x i1> %0, <vscale x 2 x half> %1, half %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv2f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0
@@ -714,7 +716,7 @@ entry:
<vscale x 2 x half> %1,
half %2,
<vscale x 2 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 2 x i1> %a
}
@@ -722,9 +724,9 @@ entry:
declare <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4f16.f16(
<vscale x 4 x half>,
half,
- i32);
+ iXLen);
-define <vscale x 4 x i1> @intrinsic_vmflt_vf_nxv4f16_f16(<vscale x 4 x half> %0, half %1, i32 %2) nounwind {
+define <vscale x 4 x i1> @intrinsic_vmflt_vf_nxv4f16_f16(<vscale x 4 x half> %0, half %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmflt_vf_nxv4f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
@@ -734,7 +736,7 @@ entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4f16.f16(
<vscale x 4 x half> %0,
half %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 4 x i1> %a
}
@@ -744,9 +746,9 @@ declare <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4f16.f16(
<vscale x 4 x half>,
half,
<vscale x 4 x i1>,
- i32);
+ iXLen);
-define <vscale x 4 x i1> @intrinsic_vmflt_mask_vf_nxv4f16_f16(<vscale x 4 x i1> %0, <vscale x 4 x half> %1, half %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+define <vscale x 4 x i1> @intrinsic_vmflt_mask_vf_nxv4f16_f16(<vscale x 4 x i1> %0, <vscale x 4 x half> %1, half %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv4f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0
@@ -761,7 +763,7 @@ entry:
<vscale x 4 x half> %1,
half %2,
<vscale x 4 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 4 x i1> %a
}
@@ -769,9 +771,9 @@ entry:
declare <vscale x 8 x i1> @llvm.riscv.vmflt.nxv8f16.f16(
<vscale x 8 x half>,
half,
- i32);
+ iXLen);
-define <vscale x 8 x i1> @intrinsic_vmflt_vf_nxv8f16_f16(<vscale x 8 x half> %0, half %1, i32 %2) nounwind {
+define <vscale x 8 x i1> @intrinsic_vmflt_vf_nxv8f16_f16(<vscale x 8 x half> %0, half %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmflt_vf_nxv8f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
@@ -781,7 +783,7 @@ entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmflt.nxv8f16.f16(
<vscale x 8 x half> %0,
half %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 8 x i1> %a
}
@@ -791,9 +793,9 @@ declare <vscale x 8 x i1> @llvm.riscv.vmflt.mask.nxv8f16.f16(
<vscale x 8 x half>,
half,
<vscale x 8 x i1>,
- i32);
+ iXLen);
-define <vscale x 8 x i1> @intrinsic_vmflt_mask_vf_nxv8f16_f16(<vscale x 8 x i1> %0, <vscale x 8 x half> %1, half %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+define <vscale x 8 x i1> @intrinsic_vmflt_mask_vf_nxv8f16_f16(<vscale x 8 x i1> %0, <vscale x 8 x half> %1, half %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv8f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v11, v0
@@ -808,7 +810,7 @@ entry:
<vscale x 8 x half> %1,
half %2,
<vscale x 8 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 8 x i1> %a
}
@@ -816,9 +818,9 @@ entry:
declare <vscale x 16 x i1> @llvm.riscv.vmflt.nxv16f16.f16(
<vscale x 16 x half>,
half,
- i32);
+ iXLen);
-define <vscale x 16 x i1> @intrinsic_vmflt_vf_nxv16f16_f16(<vscale x 16 x half> %0, half %1, i32 %2) nounwind {
+define <vscale x 16 x i1> @intrinsic_vmflt_vf_nxv16f16_f16(<vscale x 16 x half> %0, half %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmflt_vf_nxv16f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
@@ -828,7 +830,7 @@ entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmflt.nxv16f16.f16(
<vscale x 16 x half> %0,
half %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 16 x i1> %a
}
@@ -838,9 +840,9 @@ declare <vscale x 16 x i1> @llvm.riscv.vmflt.mask.nxv16f16.f16(
<vscale x 16 x half>,
half,
<vscale x 16 x i1>,
- i32);
+ iXLen);
-define <vscale x 16 x i1> @intrinsic_vmflt_mask_vf_nxv16f16_f16(<vscale x 16 x i1> %0, <vscale x 16 x half> %1, half %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+define <vscale x 16 x i1> @intrinsic_vmflt_mask_vf_nxv16f16_f16(<vscale x 16 x i1> %0, <vscale x 16 x half> %1, half %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv16f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v13, v0
@@ -855,7 +857,7 @@ entry:
<vscale x 16 x half> %1,
half %2,
<vscale x 16 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 16 x i1> %a
}
@@ -863,9 +865,9 @@ entry:
declare <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1f32.f32(
<vscale x 1 x float>,
float,
- i32);
+ iXLen);
-define <vscale x 1 x i1> @intrinsic_vmflt_vf_nxv1f32_f32(<vscale x 1 x float> %0, float %1, i32 %2) nounwind {
+define <vscale x 1 x i1> @intrinsic_vmflt_vf_nxv1f32_f32(<vscale x 1 x float> %0, float %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmflt_vf_nxv1f32_f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
@@ -875,7 +877,7 @@ entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1f32.f32(
<vscale x 1 x float> %0,
float %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 1 x i1> %a
}
@@ -885,9 +887,9 @@ declare <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1f32.f32(
<vscale x 1 x float>,
float,
<vscale x 1 x i1>,
- i32);
+ iXLen);
-define <vscale x 1 x i1> @intrinsic_vmflt_mask_vf_nxv1f32_f32(<vscale x 1 x i1> %0, <vscale x 1 x float> %1, float %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+define <vscale x 1 x i1> @intrinsic_vmflt_mask_vf_nxv1f32_f32(<vscale x 1 x i1> %0, <vscale x 1 x float> %1, float %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv1f32_f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0
@@ -902,7 +904,7 @@ entry:
<vscale x 1 x float> %1,
float %2,
<vscale x 1 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 1 x i1> %a
}
@@ -910,9 +912,9 @@ entry:
declare <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2f32.f32(
<vscale x 2 x float>,
float,
- i32);
+ iXLen);
-define <vscale x 2 x i1> @intrinsic_vmflt_vf_nxv2f32_f32(<vscale x 2 x float> %0, float %1, i32 %2) nounwind {
+define <vscale x 2 x i1> @intrinsic_vmflt_vf_nxv2f32_f32(<vscale x 2 x float> %0, float %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmflt_vf_nxv2f32_f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
@@ -922,7 +924,7 @@ entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2f32.f32(
<vscale x 2 x float> %0,
float %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 2 x i1> %a
}
@@ -932,9 +934,9 @@ declare <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2f32.f32(
<vscale x 2 x float>,
float,
<vscale x 2 x i1>,
- i32);
+ iXLen);
-define <vscale x 2 x i1> @intrinsic_vmflt_mask_vf_nxv2f32_f32(<vscale x 2 x i1> %0, <vscale x 2 x float> %1, float %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+define <vscale x 2 x i1> @intrinsic_vmflt_mask_vf_nxv2f32_f32(<vscale x 2 x i1> %0, <vscale x 2 x float> %1, float %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv2f32_f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0
@@ -949,7 +951,7 @@ entry:
<vscale x 2 x float> %1,
float %2,
<vscale x 2 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 2 x i1> %a
}
@@ -957,9 +959,9 @@ entry:
declare <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4f32.f32(
<vscale x 4 x float>,
float,
- i32);
+ iXLen);
-define <vscale x 4 x i1> @intrinsic_vmflt_vf_nxv4f32_f32(<vscale x 4 x float> %0, float %1, i32 %2) nounwind {
+define <vscale x 4 x i1> @intrinsic_vmflt_vf_nxv4f32_f32(<vscale x 4 x float> %0, float %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmflt_vf_nxv4f32_f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
@@ -969,7 +971,7 @@ entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4f32.f32(
<vscale x 4 x float> %0,
float %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 4 x i1> %a
}
@@ -979,9 +981,9 @@ declare <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4f32.f32(
<vscale x 4 x float>,
float,
<vscale x 4 x i1>,
- i32);
+ iXLen);
-define <vscale x 4 x i1> @intrinsic_vmflt_mask_vf_nxv4f32_f32(<vscale x 4 x i1> %0, <vscale x 4 x float> %1, float %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+define <vscale x 4 x i1> @intrinsic_vmflt_mask_vf_nxv4f32_f32(<vscale x 4 x i1> %0, <vscale x 4 x float> %1, float %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv4f32_f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v11, v0
@@ -996,7 +998,7 @@ entry:
<vscale x 4 x float> %1,
float %2,
<vscale x 4 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 4 x i1> %a
}
@@ -1004,9 +1006,9 @@ entry:
declare <vscale x 8 x i1> @llvm.riscv.vmflt.nxv8f32.f32(
<vscale x 8 x float>,
float,
- i32);
+ iXLen);
-define <vscale x 8 x i1> @intrinsic_vmflt_vf_nxv8f32_f32(<vscale x 8 x float> %0, float %1, i32 %2) nounwind {
+define <vscale x 8 x i1> @intrinsic_vmflt_vf_nxv8f32_f32(<vscale x 8 x float> %0, float %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmflt_vf_nxv8f32_f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
@@ -1016,7 +1018,7 @@ entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmflt.nxv8f32.f32(
<vscale x 8 x float> %0,
float %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 8 x i1> %a
}
@@ -1026,9 +1028,9 @@ declare <vscale x 8 x i1> @llvm.riscv.vmflt.mask.nxv8f32.f32(
<vscale x 8 x float>,
float,
<vscale x 8 x i1>,
- i32);
+ iXLen);
-define <vscale x 8 x i1> @intrinsic_vmflt_mask_vf_nxv8f32_f32(<vscale x 8 x i1> %0, <vscale x 8 x float> %1, float %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+define <vscale x 8 x i1> @intrinsic_vmflt_mask_vf_nxv8f32_f32(<vscale x 8 x i1> %0, <vscale x 8 x float> %1, float %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv8f32_f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v13, v0
@@ -1043,7 +1045,7 @@ entry:
<vscale x 8 x float> %1,
float %2,
<vscale x 8 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 8 x i1> %a
}
@@ -1051,9 +1053,9 @@ entry:
declare <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1f64.f64(
<vscale x 1 x double>,
double,
- i32);
+ iXLen);
-define <vscale x 1 x i1> @intrinsic_vmflt_vf_nxv1f64_f64(<vscale x 1 x double> %0, double %1, i32 %2) nounwind {
+define <vscale x 1 x i1> @intrinsic_vmflt_vf_nxv1f64_f64(<vscale x 1 x double> %0, double %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmflt_vf_nxv1f64_f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
@@ -1063,7 +1065,7 @@ entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1f64.f64(
<vscale x 1 x double> %0,
double %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 1 x i1> %a
}
@@ -1073,9 +1075,9 @@ declare <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1f64.f64(
<vscale x 1 x double>,
double,
<vscale x 1 x i1>,
- i32);
+ iXLen);
-define <vscale x 1 x i1> @intrinsic_vmflt_mask_vf_nxv1f64_f64(<vscale x 1 x i1> %0, <vscale x 1 x double> %1, double %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+define <vscale x 1 x i1> @intrinsic_vmflt_mask_vf_nxv1f64_f64(<vscale x 1 x i1> %0, <vscale x 1 x double> %1, double %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv1f64_f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0
@@ -1090,7 +1092,7 @@ entry:
<vscale x 1 x double> %1,
double %2,
<vscale x 1 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 1 x i1> %a
}
@@ -1098,9 +1100,9 @@ entry:
declare <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2f64.f64(
<vscale x 2 x double>,
double,
- i32);
+ iXLen);
-define <vscale x 2 x i1> @intrinsic_vmflt_vf_nxv2f64_f64(<vscale x 2 x double> %0, double %1, i32 %2) nounwind {
+define <vscale x 2 x i1> @intrinsic_vmflt_vf_nxv2f64_f64(<vscale x 2 x double> %0, double %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmflt_vf_nxv2f64_f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
@@ -1110,7 +1112,7 @@ entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2f64.f64(
<vscale x 2 x double> %0,
double %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 2 x i1> %a
}
@@ -1120,9 +1122,9 @@ declare <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2f64.f64(
<vscale x 2 x double>,
double,
<vscale x 2 x i1>,
- i32);
+ iXLen);
-define <vscale x 2 x i1> @intrinsic_vmflt_mask_vf_nxv2f64_f64(<vscale x 2 x i1> %0, <vscale x 2 x double> %1, double %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+define <vscale x 2 x i1> @intrinsic_vmflt_mask_vf_nxv2f64_f64(<vscale x 2 x i1> %0, <vscale x 2 x double> %1, double %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv2f64_f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v11, v0
@@ -1137,7 +1139,7 @@ entry:
<vscale x 2 x double> %1,
double %2,
<vscale x 2 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 2 x i1> %a
}
@@ -1145,9 +1147,9 @@ entry:
declare <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4f64.f64(
<vscale x 4 x double>,
double,
- i32);
+ iXLen);
-define <vscale x 4 x i1> @intrinsic_vmflt_vf_nxv4f64_f64(<vscale x 4 x double> %0, double %1, i32 %2) nounwind {
+define <vscale x 4 x i1> @intrinsic_vmflt_vf_nxv4f64_f64(<vscale x 4 x double> %0, double %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmflt_vf_nxv4f64_f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
@@ -1157,7 +1159,7 @@ entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4f64.f64(
<vscale x 4 x double> %0,
double %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 4 x i1> %a
}
@@ -1167,9 +1169,9 @@ declare <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4f64.f64(
<vscale x 4 x double>,
double,
<vscale x 4 x i1>,
- i32);
+ iXLen);
-define <vscale x 4 x i1> @intrinsic_vmflt_mask_vf_nxv4f64_f64(<vscale x 4 x i1> %0, <vscale x 4 x double> %1, double %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+define <vscale x 4 x i1> @intrinsic_vmflt_mask_vf_nxv4f64_f64(<vscale x 4 x i1> %0, <vscale x 4 x double> %1, double %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv4f64_f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v13, v0
@@ -1184,7 +1186,7 @@ entry:
<vscale x 4 x double> %1,
double %2,
<vscale x 4 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 4 x i1> %a
}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmfne-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vmfne-rv64.ll
deleted file mode 100644
index 26e2a5fcdc1dd..0000000000000
--- a/llvm/test/CodeGen/RISCV/rvv/vmfne-rv64.ll
+++ /dev/null
@@ -1,1190 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv64 -mattr=+v,+d,+zfh -verify-machineinstrs \
-; RUN: -target-abi=lp64d < %s | FileCheck %s
-declare <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1f16(
- <vscale x 1 x half>,
- <vscale x 1 x half>,
- i64);
-
-define <vscale x 1 x i1> @intrinsic_vmfne_vv_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmfne_vv_nxv1f16_nxv1f16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vmfne.vv v0, v8, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1f16(
- <vscale x 1 x half> %0,
- <vscale x 1 x half> %1,
- i64 %2)
-
- ret <vscale x 1 x i1> %a
-}
-
-declare <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1f16(
- <vscale x 1 x i1>,
- <vscale x 1 x half>,
- <vscale x 1 x half>,
- <vscale x 1 x i1>,
- i64);
-
-define <vscale x 1 x i1> @intrinsic_vmfne_mask_vv_nxv1f16_nxv1f16(<vscale x 1 x i1> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x half> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv1f16_nxv1f16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vmfne.vv v8, v8, v9
-; CHECK-NEXT: vmv1r.v v11, v0
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmfne.vv v11, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v11
-; CHECK-NEXT: ret
-entry:
- %mask = call <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1f16(
- <vscale x 1 x half> %1,
- <vscale x 1 x half> %2,
- i64 %4)
- %a = call <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1f16(
- <vscale x 1 x i1> %0,
- <vscale x 1 x half> %2,
- <vscale x 1 x half> %3,
- <vscale x 1 x i1> %mask,
- i64 %4)
-
- ret <vscale x 1 x i1> %a
-}
-
-declare <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2f16(
- <vscale x 2 x half>,
- <vscale x 2 x half>,
- i64);
-
-define <vscale x 2 x i1> @intrinsic_vmfne_vv_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmfne_vv_nxv2f16_nxv2f16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vmfne.vv v0, v8, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2f16(
- <vscale x 2 x half> %0,
- <vscale x 2 x half> %1,
- i64 %2)
-
- ret <vscale x 2 x i1> %a
-}
-
-declare <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2f16(
- <vscale x 2 x i1>,
- <vscale x 2 x half>,
- <vscale x 2 x half>,
- <vscale x 2 x i1>,
- i64);
-
-define <vscale x 2 x i1> @intrinsic_vmfne_mask_vv_nxv2f16_nxv2f16(<vscale x 2 x i1> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, <vscale x 2 x half> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv2f16_nxv2f16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vmfne.vv v8, v8, v9
-; CHECK-NEXT: vmv1r.v v11, v0
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmfne.vv v11, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v11
-; CHECK-NEXT: ret
-entry:
- %mask = call <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2f16(
- <vscale x 2 x half> %1,
- <vscale x 2 x half> %2,
- i64 %4)
- %a = call <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2f16(
- <vscale x 2 x i1> %0,
- <vscale x 2 x half> %2,
- <vscale x 2 x half> %3,
- <vscale x 2 x i1> %mask,
- i64 %4)
-
- ret <vscale x 2 x i1> %a
-}
-
-declare <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4f16(
- <vscale x 4 x half>,
- <vscale x 4 x half>,
- i64);
-
-define <vscale x 4 x i1> @intrinsic_vmfne_vv_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmfne_vv_nxv4f16_nxv4f16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vmfne.vv v0, v8, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4f16(
- <vscale x 4 x half> %0,
- <vscale x 4 x half> %1,
- i64 %2)
-
- ret <vscale x 4 x i1> %a
-}
-
-declare <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4f16(
- <vscale x 4 x i1>,
- <vscale x 4 x half>,
- <vscale x 4 x half>,
- <vscale x 4 x i1>,
- i64);
-
-define <vscale x 4 x i1> @intrinsic_vmfne_mask_vv_nxv4f16_nxv4f16(<vscale x 4 x i1> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x half> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv4f16_nxv4f16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vmfne.vv v8, v8, v9
-; CHECK-NEXT: vmv1r.v v11, v0
-; CHECK-NEXT: vmv.v.v v0, v8
-; CHECK-NEXT: vmfne.vv v11, v9, v10, v0.t
-; CHECK-NEXT: vmv.v.v v0, v11
-; CHECK-NEXT: ret
-entry:
- %mask = call <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4f16(
- <vscale x 4 x half> %1,
- <vscale x 4 x half> %2,
- i64 %4)
- %a = call <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4f16(
- <vscale x 4 x i1> %0,
- <vscale x 4 x half> %2,
- <vscale x 4 x half> %3,
- <vscale x 4 x i1> %mask,
- i64 %4)
-
- ret <vscale x 4 x i1> %a
-}
-
-declare <vscale x 8 x i1> @llvm.riscv.vmfne.nxv8f16(
- <vscale x 8 x half>,
- <vscale x 8 x half>,
- i64);
-
-define <vscale x 8 x i1> @intrinsic_vmfne_vv_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmfne_vv_nxv8f16_nxv8f16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vmfne.vv v0, v8, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i1> @llvm.riscv.vmfne.nxv8f16(
- <vscale x 8 x half> %0,
- <vscale x 8 x half> %1,
- i64 %2)
-
- ret <vscale x 8 x i1> %a
-}
-
-declare <vscale x 8 x i1> @llvm.riscv.vmfne.mask.nxv8f16(
- <vscale x 8 x i1>,
- <vscale x 8 x half>,
- <vscale x 8 x half>,
- <vscale x 8 x i1>,
- i64);
-
-define <vscale x 8 x i1> @intrinsic_vmfne_mask_vv_nxv8f16_nxv8f16(<vscale x 8 x i1> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x half> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv8f16_nxv8f16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vmfne.vv v14, v8, v10
-; CHECK-NEXT: vmv1r.v v8, v0
-; CHECK-NEXT: vmv1r.v v0, v14
-; CHECK-NEXT: vmfne.vv v8, v10, v12, v0.t
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: ret
-entry:
- %mask = call <vscale x 8 x i1> @llvm.riscv.vmfne.nxv8f16(
- <vscale x 8 x half> %1,
- <vscale x 8 x half> %2,
- i64 %4)
- %a = call <vscale x 8 x i1> @llvm.riscv.vmfne.mask.nxv8f16(
- <vscale x 8 x i1> %0,
- <vscale x 8 x half> %2,
- <vscale x 8 x half> %3,
- <vscale x 8 x i1> %mask,
- i64 %4)
-
- ret <vscale x 8 x i1> %a
-}
-
-declare <vscale x 16 x i1> @llvm.riscv.vmfne.nxv16f16(
- <vscale x 16 x half>,
- <vscale x 16 x half>,
- i64);
-
-define <vscale x 16 x i1> @intrinsic_vmfne_vv_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmfne_vv_nxv16f16_nxv16f16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
-; CHECK-NEXT: vmfne.vv v0, v8, v12
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i1> @llvm.riscv.vmfne.nxv16f16(
- <vscale x 16 x half> %0,
- <vscale x 16 x half> %1,
- i64 %2)
-
- ret <vscale x 16 x i1> %a
-}
-
-declare <vscale x 16 x i1> @llvm.riscv.vmfne.mask.nxv16f16(
- <vscale x 16 x i1>,
- <vscale x 16 x half>,
- <vscale x 16 x half>,
- <vscale x 16 x i1>,
- i64);
-
-define <vscale x 16 x i1> @intrinsic_vmfne_mask_vv_nxv16f16_nxv16f16(<vscale x 16 x i1> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, <vscale x 16 x half> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv16f16_nxv16f16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
-; CHECK-NEXT: vmfne.vv v20, v8, v12
-; CHECK-NEXT: vmv1r.v v8, v0
-; CHECK-NEXT: vmv1r.v v0, v20
-; CHECK-NEXT: vmfne.vv v8, v12, v16, v0.t
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: ret
-entry:
- %mask = call <vscale x 16 x i1> @llvm.riscv.vmfne.nxv16f16(
- <vscale x 16 x half> %1,
- <vscale x 16 x half> %2,
- i64 %4)
- %a = call <vscale x 16 x i1> @llvm.riscv.vmfne.mask.nxv16f16(
- <vscale x 16 x i1> %0,
- <vscale x 16 x half> %2,
- <vscale x 16 x half> %3,
- <vscale x 16 x i1> %mask,
- i64 %4)
-
- ret <vscale x 16 x i1> %a
-}
-
-declare <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1f32(
- <vscale x 1 x float>,
- <vscale x 1 x float>,
- i64);
-
-define <vscale x 1 x i1> @intrinsic_vmfne_vv_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmfne_vv_nxv1f32_nxv1f32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vmfne.vv v0, v8, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1f32(
- <vscale x 1 x float> %0,
- <vscale x 1 x float> %1,
- i64 %2)
-
- ret <vscale x 1 x i1> %a
-}
-
-declare <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1f32(
- <vscale x 1 x i1>,
- <vscale x 1 x float>,
- <vscale x 1 x float>,
- <vscale x 1 x i1>,
- i64);
-
-define <vscale x 1 x i1> @intrinsic_vmfne_mask_vv_nxv1f32_nxv1f32(<vscale x 1 x i1> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, <vscale x 1 x float> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv1f32_nxv1f32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vmfne.vv v8, v8, v9
-; CHECK-NEXT: vmv1r.v v11, v0
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmfne.vv v11, v9, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v11
-; CHECK-NEXT: ret
-entry:
- %mask = call <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1f32(
- <vscale x 1 x float> %1,
- <vscale x 1 x float> %2,
- i64 %4)
- %a = call <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1f32(
- <vscale x 1 x i1> %0,
- <vscale x 1 x float> %2,
- <vscale x 1 x float> %3,
- <vscale x 1 x i1> %mask,
- i64 %4)
-
- ret <vscale x 1 x i1> %a
-}
-
-declare <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2f32(
- <vscale x 2 x float>,
- <vscale x 2 x float>,
- i64);
-
-define <vscale x 2 x i1> @intrinsic_vmfne_vv_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmfne_vv_nxv2f32_nxv2f32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vmfne.vv v0, v8, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2f32(
- <vscale x 2 x float> %0,
- <vscale x 2 x float> %1,
- i64 %2)
-
- ret <vscale x 2 x i1> %a
-}
-
-declare <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2f32(
- <vscale x 2 x i1>,
- <vscale x 2 x float>,
- <vscale x 2 x float>,
- <vscale x 2 x i1>,
- i64);
-
-define <vscale x 2 x i1> @intrinsic_vmfne_mask_vv_nxv2f32_nxv2f32(<vscale x 2 x i1> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x float> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv2f32_nxv2f32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vmfne.vv v8, v8, v9
-; CHECK-NEXT: vmv1r.v v11, v0
-; CHECK-NEXT: vmv.v.v v0, v8
-; CHECK-NEXT: vmfne.vv v11, v9, v10, v0.t
-; CHECK-NEXT: vmv.v.v v0, v11
-; CHECK-NEXT: ret
-entry:
- %mask = call <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2f32(
- <vscale x 2 x float> %1,
- <vscale x 2 x float> %2,
- i64 %4)
- %a = call <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2f32(
- <vscale x 2 x i1> %0,
- <vscale x 2 x float> %2,
- <vscale x 2 x float> %3,
- <vscale x 2 x i1> %mask,
- i64 %4)
-
- ret <vscale x 2 x i1> %a
-}
-
-declare <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4f32(
- <vscale x 4 x float>,
- <vscale x 4 x float>,
- i64);
-
-define <vscale x 4 x i1> @intrinsic_vmfne_vv_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmfne_vv_nxv4f32_nxv4f32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vmfne.vv v0, v8, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4f32(
- <vscale x 4 x float> %0,
- <vscale x 4 x float> %1,
- i64 %2)
-
- ret <vscale x 4 x i1> %a
-}
-
-declare <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4f32(
- <vscale x 4 x i1>,
- <vscale x 4 x float>,
- <vscale x 4 x float>,
- <vscale x 4 x i1>,
- i64);
-
-define <vscale x 4 x i1> @intrinsic_vmfne_mask_vv_nxv4f32_nxv4f32(<vscale x 4 x i1> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x float> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv4f32_nxv4f32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vmfne.vv v14, v8, v10
-; CHECK-NEXT: vmv1r.v v8, v0
-; CHECK-NEXT: vmv1r.v v0, v14
-; CHECK-NEXT: vmfne.vv v8, v10, v12, v0.t
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: ret
-entry:
- %mask = call <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4f32(
- <vscale x 4 x float> %1,
- <vscale x 4 x float> %2,
- i64 %4)
- %a = call <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4f32(
- <vscale x 4 x i1> %0,
- <vscale x 4 x float> %2,
- <vscale x 4 x float> %3,
- <vscale x 4 x i1> %mask,
- i64 %4)
-
- ret <vscale x 4 x i1> %a
-}
-
-declare <vscale x 8 x i1> @llvm.riscv.vmfne.nxv8f32(
- <vscale x 8 x float>,
- <vscale x 8 x float>,
- i64);
-
-define <vscale x 8 x i1> @intrinsic_vmfne_vv_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmfne_vv_nxv8f32_nxv8f32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
-; CHECK-NEXT: vmfne.vv v0, v8, v12
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i1> @llvm.riscv.vmfne.nxv8f32(
- <vscale x 8 x float> %0,
- <vscale x 8 x float> %1,
- i64 %2)
-
- ret <vscale x 8 x i1> %a
-}
-
-declare <vscale x 8 x i1> @llvm.riscv.vmfne.mask.nxv8f32(
- <vscale x 8 x i1>,
- <vscale x 8 x float>,
- <vscale x 8 x float>,
- <vscale x 8 x i1>,
- i64);
-
-define <vscale x 8 x i1> @intrinsic_vmfne_mask_vv_nxv8f32_nxv8f32(<vscale x 8 x i1> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, <vscale x 8 x float> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv8f32_nxv8f32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
-; CHECK-NEXT: vmfne.vv v20, v8, v12
-; CHECK-NEXT: vmv1r.v v8, v0
-; CHECK-NEXT: vmv1r.v v0, v20
-; CHECK-NEXT: vmfne.vv v8, v12, v16, v0.t
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: ret
-entry:
- %mask = call <vscale x 8 x i1> @llvm.riscv.vmfne.nxv8f32(
- <vscale x 8 x float> %1,
- <vscale x 8 x float> %2,
- i64 %4)
- %a = call <vscale x 8 x i1> @llvm.riscv.vmfne.mask.nxv8f32(
- <vscale x 8 x i1> %0,
- <vscale x 8 x float> %2,
- <vscale x 8 x float> %3,
- <vscale x 8 x i1> %mask,
- i64 %4)
-
- ret <vscale x 8 x i1> %a
-}
-
-declare <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1f64(
- <vscale x 1 x double>,
- <vscale x 1 x double>,
- i64);
-
-define <vscale x 1 x i1> @intrinsic_vmfne_vv_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmfne_vv_nxv1f64_nxv1f64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
-; CHECK-NEXT: vmfne.vv v0, v8, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1f64(
- <vscale x 1 x double> %0,
- <vscale x 1 x double> %1,
- i64 %2)
-
- ret <vscale x 1 x i1> %a
-}
-
-declare <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1f64(
- <vscale x 1 x i1>,
- <vscale x 1 x double>,
- <vscale x 1 x double>,
- <vscale x 1 x i1>,
- i64);
-
-define <vscale x 1 x i1> @intrinsic_vmfne_mask_vv_nxv1f64_nxv1f64(<vscale x 1 x i1> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, <vscale x 1 x double> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv1f64_nxv1f64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
-; CHECK-NEXT: vmfne.vv v8, v8, v9
-; CHECK-NEXT: vmv1r.v v11, v0
-; CHECK-NEXT: vmv.v.v v0, v8
-; CHECK-NEXT: vmfne.vv v11, v9, v10, v0.t
-; CHECK-NEXT: vmv.v.v v0, v11
-; CHECK-NEXT: ret
-entry:
- %mask = call <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1f64(
- <vscale x 1 x double> %1,
- <vscale x 1 x double> %2,
- i64 %4)
- %a = call <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1f64(
- <vscale x 1 x i1> %0,
- <vscale x 1 x double> %2,
- <vscale x 1 x double> %3,
- <vscale x 1 x i1> %mask,
- i64 %4)
-
- ret <vscale x 1 x i1> %a
-}
-
-declare <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2f64(
- <vscale x 2 x double>,
- <vscale x 2 x double>,
- i64);
-
-define <vscale x 2 x i1> @intrinsic_vmfne_vv_nxv2f64_nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmfne_vv_nxv2f64_nxv2f64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
-; CHECK-NEXT: vmfne.vv v0, v8, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2f64(
- <vscale x 2 x double> %0,
- <vscale x 2 x double> %1,
- i64 %2)
-
- ret <vscale x 2 x i1> %a
-}
-
-declare <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2f64(
- <vscale x 2 x i1>,
- <vscale x 2 x double>,
- <vscale x 2 x double>,
- <vscale x 2 x i1>,
- i64);
-
-define <vscale x 2 x i1> @intrinsic_vmfne_mask_vv_nxv2f64_nxv2f64(<vscale x 2 x i1> %0, <vscale x 2 x double> %1, <vscale x 2 x double> %2, <vscale x 2 x double> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv2f64_nxv2f64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
-; CHECK-NEXT: vmfne.vv v14, v8, v10
-; CHECK-NEXT: vmv1r.v v8, v0
-; CHECK-NEXT: vmv1r.v v0, v14
-; CHECK-NEXT: vmfne.vv v8, v10, v12, v0.t
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: ret
-entry:
- %mask = call <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2f64(
- <vscale x 2 x double> %1,
- <vscale x 2 x double> %2,
- i64 %4)
- %a = call <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2f64(
- <vscale x 2 x i1> %0,
- <vscale x 2 x double> %2,
- <vscale x 2 x double> %3,
- <vscale x 2 x i1> %mask,
- i64 %4)
-
- ret <vscale x 2 x i1> %a
-}
-
-declare <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4f64(
- <vscale x 4 x double>,
- <vscale x 4 x double>,
- i64);
-
-define <vscale x 4 x i1> @intrinsic_vmfne_vv_nxv4f64_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmfne_vv_nxv4f64_nxv4f64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
-; CHECK-NEXT: vmfne.vv v0, v8, v12
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4f64(
- <vscale x 4 x double> %0,
- <vscale x 4 x double> %1,
- i64 %2)
-
- ret <vscale x 4 x i1> %a
-}
-
-declare <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4f64(
- <vscale x 4 x i1>,
- <vscale x 4 x double>,
- <vscale x 4 x double>,
- <vscale x 4 x i1>,
- i64);
-
-define <vscale x 4 x i1> @intrinsic_vmfne_mask_vv_nxv4f64_nxv4f64(<vscale x 4 x i1> %0, <vscale x 4 x double> %1, <vscale x 4 x double> %2, <vscale x 4 x double> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv4f64_nxv4f64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
-; CHECK-NEXT: vmfne.vv v20, v8, v12
-; CHECK-NEXT: vmv1r.v v8, v0
-; CHECK-NEXT: vmv1r.v v0, v20
-; CHECK-NEXT: vmfne.vv v8, v12, v16, v0.t
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: ret
-entry:
- %mask = call <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4f64(
- <vscale x 4 x double> %1,
- <vscale x 4 x double> %2,
- i64 %4)
- %a = call <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4f64(
- <vscale x 4 x i1> %0,
- <vscale x 4 x double> %2,
- <vscale x 4 x double> %3,
- <vscale x 4 x i1> %mask,
- i64 %4)
-
- ret <vscale x 4 x i1> %a
-}
-
-declare <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1f16.f16(
- <vscale x 1 x half>,
- half,
- i64);
-
-define <vscale x 1 x i1> @intrinsic_vmfne_vf_nxv1f16_f16(<vscale x 1 x half> %0, half %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmfne_vf_nxv1f16_f16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vmfne.vf v0, v8, fa0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1f16.f16(
- <vscale x 1 x half> %0,
- half %1,
- i64 %2)
-
- ret <vscale x 1 x i1> %a
-}
-
-declare <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1f16.f16(
- <vscale x 1 x i1>,
- <vscale x 1 x half>,
- half,
- <vscale x 1 x i1>,
- i64);
-
-define <vscale x 1 x i1> @intrinsic_vmfne_mask_vf_nxv1f16_f16(<vscale x 1 x i1> %0, <vscale x 1 x half> %1, half %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv1f16_f16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v10, v0
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmfne.vf v10, v8, fa0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1f16.f16(
- <vscale x 1 x i1> %0,
- <vscale x 1 x half> %1,
- half %2,
- <vscale x 1 x i1> %3,
- i64 %4)
-
- ret <vscale x 1 x i1> %a
-}
-
-declare <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2f16.f16(
- <vscale x 2 x half>,
- half,
- i64);
-
-define <vscale x 2 x i1> @intrinsic_vmfne_vf_nxv2f16_f16(<vscale x 2 x half> %0, half %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmfne_vf_nxv2f16_f16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vmfne.vf v0, v8, fa0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2f16.f16(
- <vscale x 2 x half> %0,
- half %1,
- i64 %2)
-
- ret <vscale x 2 x i1> %a
-}
-
-declare <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2f16.f16(
- <vscale x 2 x i1>,
- <vscale x 2 x half>,
- half,
- <vscale x 2 x i1>,
- i64);
-
-define <vscale x 2 x i1> @intrinsic_vmfne_mask_vf_nxv2f16_f16(<vscale x 2 x i1> %0, <vscale x 2 x half> %1, half %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv2f16_f16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v10, v0
-; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmfne.vf v10, v8, fa0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2f16.f16(
- <vscale x 2 x i1> %0,
- <vscale x 2 x half> %1,
- half %2,
- <vscale x 2 x i1> %3,
- i64 %4)
-
- ret <vscale x 2 x i1> %a
-}
-
-declare <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4f16.f16(
- <vscale x 4 x half>,
- half,
- i64);
-
-define <vscale x 4 x i1> @intrinsic_vmfne_vf_nxv4f16_f16(<vscale x 4 x half> %0, half %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmfne_vf_nxv4f16_f16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vmfne.vf v0, v8, fa0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4f16.f16(
- <vscale x 4 x half> %0,
- half %1,
- i64 %2)
-
- ret <vscale x 4 x i1> %a
-}
-
-declare <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4f16.f16(
- <vscale x 4 x i1>,
- <vscale x 4 x half>,
- half,
- <vscale x 4 x i1>,
- i64);
-
-define <vscale x 4 x i1> @intrinsic_vmfne_mask_vf_nxv4f16_f16(<vscale x 4 x i1> %0, <vscale x 4 x half> %1, half %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv4f16_f16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v10, v0
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmfne.vf v10, v8, fa0, v0.t
-; CHECK-NEXT: vmv.v.v v0, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4f16.f16(
- <vscale x 4 x i1> %0,
- <vscale x 4 x half> %1,
- half %2,
- <vscale x 4 x i1> %3,
- i64 %4)
-
- ret <vscale x 4 x i1> %a
-}
-
-declare <vscale x 8 x i1> @llvm.riscv.vmfne.nxv8f16.f16(
- <vscale x 8 x half>,
- half,
- i64);
-
-define <vscale x 8 x i1> @intrinsic_vmfne_vf_nxv8f16_f16(<vscale x 8 x half> %0, half %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmfne_vf_nxv8f16_f16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vmfne.vf v0, v8, fa0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i1> @llvm.riscv.vmfne.nxv8f16.f16(
- <vscale x 8 x half> %0,
- half %1,
- i64 %2)
-
- ret <vscale x 8 x i1> %a
-}
-
-declare <vscale x 8 x i1> @llvm.riscv.vmfne.mask.nxv8f16.f16(
- <vscale x 8 x i1>,
- <vscale x 8 x half>,
- half,
- <vscale x 8 x i1>,
- i64);
-
-define <vscale x 8 x i1> @intrinsic_vmfne_mask_vf_nxv8f16_f16(<vscale x 8 x i1> %0, <vscale x 8 x half> %1, half %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv8f16_f16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v11, v0
-; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmfne.vf v11, v8, fa0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v11
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i1> @llvm.riscv.vmfne.mask.nxv8f16.f16(
- <vscale x 8 x i1> %0,
- <vscale x 8 x half> %1,
- half %2,
- <vscale x 8 x i1> %3,
- i64 %4)
-
- ret <vscale x 8 x i1> %a
-}
-
-declare <vscale x 16 x i1> @llvm.riscv.vmfne.nxv16f16.f16(
- <vscale x 16 x half>,
- half,
- i64);
-
-define <vscale x 16 x i1> @intrinsic_vmfne_vf_nxv16f16_f16(<vscale x 16 x half> %0, half %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmfne_vf_nxv16f16_f16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
-; CHECK-NEXT: vmfne.vf v0, v8, fa0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i1> @llvm.riscv.vmfne.nxv16f16.f16(
- <vscale x 16 x half> %0,
- half %1,
- i64 %2)
-
- ret <vscale x 16 x i1> %a
-}
-
-declare <vscale x 16 x i1> @llvm.riscv.vmfne.mask.nxv16f16.f16(
- <vscale x 16 x i1>,
- <vscale x 16 x half>,
- half,
- <vscale x 16 x i1>,
- i64);
-
-define <vscale x 16 x i1> @intrinsic_vmfne_mask_vf_nxv16f16_f16(<vscale x 16 x i1> %0, <vscale x 16 x half> %1, half %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv16f16_f16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v13, v0
-; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
-; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmfne.vf v13, v8, fa0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v13
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i1> @llvm.riscv.vmfne.mask.nxv16f16.f16(
- <vscale x 16 x i1> %0,
- <vscale x 16 x half> %1,
- half %2,
- <vscale x 16 x i1> %3,
- i64 %4)
-
- ret <vscale x 16 x i1> %a
-}
-
-declare <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1f32.f32(
- <vscale x 1 x float>,
- float,
- i64);
-
-define <vscale x 1 x i1> @intrinsic_vmfne_vf_nxv1f32_f32(<vscale x 1 x float> %0, float %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmfne_vf_nxv1f32_f32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vmfne.vf v0, v8, fa0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1f32.f32(
- <vscale x 1 x float> %0,
- float %1,
- i64 %2)
-
- ret <vscale x 1 x i1> %a
-}
-
-declare <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1f32.f32(
- <vscale x 1 x i1>,
- <vscale x 1 x float>,
- float,
- <vscale x 1 x i1>,
- i64);
-
-define <vscale x 1 x i1> @intrinsic_vmfne_mask_vf_nxv1f32_f32(<vscale x 1 x i1> %0, <vscale x 1 x float> %1, float %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv1f32_f32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v10, v0
-; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmfne.vf v10, v8, fa0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1f32.f32(
- <vscale x 1 x i1> %0,
- <vscale x 1 x float> %1,
- float %2,
- <vscale x 1 x i1> %3,
- i64 %4)
-
- ret <vscale x 1 x i1> %a
-}
-
-declare <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2f32.f32(
- <vscale x 2 x float>,
- float,
- i64);
-
-define <vscale x 2 x i1> @intrinsic_vmfne_vf_nxv2f32_f32(<vscale x 2 x float> %0, float %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmfne_vf_nxv2f32_f32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vmfne.vf v0, v8, fa0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2f32.f32(
- <vscale x 2 x float> %0,
- float %1,
- i64 %2)
-
- ret <vscale x 2 x i1> %a
-}
-
-declare <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2f32.f32(
- <vscale x 2 x i1>,
- <vscale x 2 x float>,
- float,
- <vscale x 2 x i1>,
- i64);
-
-define <vscale x 2 x i1> @intrinsic_vmfne_mask_vf_nxv2f32_f32(<vscale x 2 x i1> %0, <vscale x 2 x float> %1, float %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv2f32_f32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v10, v0
-; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmfne.vf v10, v8, fa0, v0.t
-; CHECK-NEXT: vmv.v.v v0, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2f32.f32(
- <vscale x 2 x i1> %0,
- <vscale x 2 x float> %1,
- float %2,
- <vscale x 2 x i1> %3,
- i64 %4)
-
- ret <vscale x 2 x i1> %a
-}
-
-declare <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4f32.f32(
- <vscale x 4 x float>,
- float,
- i64);
-
-define <vscale x 4 x i1> @intrinsic_vmfne_vf_nxv4f32_f32(<vscale x 4 x float> %0, float %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmfne_vf_nxv4f32_f32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vmfne.vf v0, v8, fa0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4f32.f32(
- <vscale x 4 x float> %0,
- float %1,
- i64 %2)
-
- ret <vscale x 4 x i1> %a
-}
-
-declare <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4f32.f32(
- <vscale x 4 x i1>,
- <vscale x 4 x float>,
- float,
- <vscale x 4 x i1>,
- i64);
-
-define <vscale x 4 x i1> @intrinsic_vmfne_mask_vf_nxv4f32_f32(<vscale x 4 x i1> %0, <vscale x 4 x float> %1, float %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv4f32_f32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v11, v0
-; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmfne.vf v11, v8, fa0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v11
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4f32.f32(
- <vscale x 4 x i1> %0,
- <vscale x 4 x float> %1,
- float %2,
- <vscale x 4 x i1> %3,
- i64 %4)
-
- ret <vscale x 4 x i1> %a
-}
-
-declare <vscale x 8 x i1> @llvm.riscv.vmfne.nxv8f32.f32(
- <vscale x 8 x float>,
- float,
- i64);
-
-define <vscale x 8 x i1> @intrinsic_vmfne_vf_nxv8f32_f32(<vscale x 8 x float> %0, float %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmfne_vf_nxv8f32_f32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
-; CHECK-NEXT: vmfne.vf v0, v8, fa0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i1> @llvm.riscv.vmfne.nxv8f32.f32(
- <vscale x 8 x float> %0,
- float %1,
- i64 %2)
-
- ret <vscale x 8 x i1> %a
-}
-
-declare <vscale x 8 x i1> @llvm.riscv.vmfne.mask.nxv8f32.f32(
- <vscale x 8 x i1>,
- <vscale x 8 x float>,
- float,
- <vscale x 8 x i1>,
- i64);
-
-define <vscale x 8 x i1> @intrinsic_vmfne_mask_vf_nxv8f32_f32(<vscale x 8 x i1> %0, <vscale x 8 x float> %1, float %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv8f32_f32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v13, v0
-; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
-; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmfne.vf v13, v8, fa0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v13
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i1> @llvm.riscv.vmfne.mask.nxv8f32.f32(
- <vscale x 8 x i1> %0,
- <vscale x 8 x float> %1,
- float %2,
- <vscale x 8 x i1> %3,
- i64 %4)
-
- ret <vscale x 8 x i1> %a
-}
-
-declare <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1f64.f64(
- <vscale x 1 x double>,
- double,
- i64);
-
-define <vscale x 1 x i1> @intrinsic_vmfne_vf_nxv1f64_f64(<vscale x 1 x double> %0, double %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmfne_vf_nxv1f64_f64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
-; CHECK-NEXT: vmfne.vf v0, v8, fa0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1f64.f64(
- <vscale x 1 x double> %0,
- double %1,
- i64 %2)
-
- ret <vscale x 1 x i1> %a
-}
-
-declare <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1f64.f64(
- <vscale x 1 x i1>,
- <vscale x 1 x double>,
- double,
- <vscale x 1 x i1>,
- i64);
-
-define <vscale x 1 x i1> @intrinsic_vmfne_mask_vf_nxv1f64_f64(<vscale x 1 x i1> %0, <vscale x 1 x double> %1, double %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv1f64_f64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v10, v0
-; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
-; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmfne.vf v10, v8, fa0, v0.t
-; CHECK-NEXT: vmv.v.v v0, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1f64.f64(
- <vscale x 1 x i1> %0,
- <vscale x 1 x double> %1,
- double %2,
- <vscale x 1 x i1> %3,
- i64 %4)
-
- ret <vscale x 1 x i1> %a
-}
-
-declare <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2f64.f64(
- <vscale x 2 x double>,
- double,
- i64);
-
-define <vscale x 2 x i1> @intrinsic_vmfne_vf_nxv2f64_f64(<vscale x 2 x double> %0, double %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmfne_vf_nxv2f64_f64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
-; CHECK-NEXT: vmfne.vf v0, v8, fa0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2f64.f64(
- <vscale x 2 x double> %0,
- double %1,
- i64 %2)
-
- ret <vscale x 2 x i1> %a
-}
-
-declare <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2f64.f64(
- <vscale x 2 x i1>,
- <vscale x 2 x double>,
- double,
- <vscale x 2 x i1>,
- i64);
-
-define <vscale x 2 x i1> @intrinsic_vmfne_mask_vf_nxv2f64_f64(<vscale x 2 x i1> %0, <vscale x 2 x double> %1, double %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv2f64_f64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v11, v0
-; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
-; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmfne.vf v11, v8, fa0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v11
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2f64.f64(
- <vscale x 2 x i1> %0,
- <vscale x 2 x double> %1,
- double %2,
- <vscale x 2 x i1> %3,
- i64 %4)
-
- ret <vscale x 2 x i1> %a
-}
-
-declare <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4f64.f64(
- <vscale x 4 x double>,
- double,
- i64);
-
-define <vscale x 4 x i1> @intrinsic_vmfne_vf_nxv4f64_f64(<vscale x 4 x double> %0, double %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmfne_vf_nxv4f64_f64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
-; CHECK-NEXT: vmfne.vf v0, v8, fa0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4f64.f64(
- <vscale x 4 x double> %0,
- double %1,
- i64 %2)
-
- ret <vscale x 4 x i1> %a
-}
-
-declare <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4f64.f64(
- <vscale x 4 x i1>,
- <vscale x 4 x double>,
- double,
- <vscale x 4 x i1>,
- i64);
-
-define <vscale x 4 x i1> @intrinsic_vmfne_mask_vf_nxv4f64_f64(<vscale x 4 x i1> %0, <vscale x 4 x double> %1, double %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv4f64_f64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v13, v0
-; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
-; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmfne.vf v13, v8, fa0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v13
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4f64.f64(
- <vscale x 4 x i1> %0,
- <vscale x 4 x double> %1,
- double %2,
- <vscale x 4 x i1> %3,
- i64 %4)
-
- ret <vscale x 4 x i1> %a
-}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmfne-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmfne.ll
similarity index 88%
rename from llvm/test/CodeGen/RISCV/rvv/vmfne-rv32.ll
rename to llvm/test/CodeGen/RISCV/rvv/vmfne.ll
index ac45efea41597..bcd3e50fc4e59 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vmfne-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vmfne.ll
@@ -1,12 +1,14 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -mattr=+v,+d,+zfh -verify-machineinstrs \
-; RUN: -target-abi=ilp32d < %s | FileCheck %s
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh \
+; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh \
+; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s
declare <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1f16(
<vscale x 1 x half>,
<vscale x 1 x half>,
- i32);
+ iXLen);
-define <vscale x 1 x i1> @intrinsic_vmfne_vv_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i32 %2) nounwind {
+define <vscale x 1 x i1> @intrinsic_vmfne_vv_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmfne_vv_nxv1f16_nxv1f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
@@ -16,7 +18,7 @@ entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1f16(
<vscale x 1 x half> %0,
<vscale x 1 x half> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 1 x i1> %a
}
@@ -26,9 +28,9 @@ declare <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1f16(
<vscale x 1 x half>,
<vscale x 1 x half>,
<vscale x 1 x i1>,
- i32);
+ iXLen);
-define <vscale x 1 x i1> @intrinsic_vmfne_mask_vv_nxv1f16_nxv1f16(<vscale x 1 x i1> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x half> %3, i32 %4) nounwind {
+define <vscale x 1 x i1> @intrinsic_vmfne_mask_vv_nxv1f16_nxv1f16(<vscale x 1 x i1> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x half> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv1f16_nxv1f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
@@ -42,13 +44,13 @@ entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1f16(
<vscale x 1 x half> %1,
<vscale x 1 x half> %2,
- i32 %4)
+ iXLen %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1f16(
<vscale x 1 x i1> %0,
<vscale x 1 x half> %2,
<vscale x 1 x half> %3,
<vscale x 1 x i1> %mask,
- i32 %4)
+ iXLen %4)
ret <vscale x 1 x i1> %a
}
@@ -56,9 +58,9 @@ entry:
declare <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2f16(
<vscale x 2 x half>,
<vscale x 2 x half>,
- i32);
+ iXLen);
-define <vscale x 2 x i1> @intrinsic_vmfne_vv_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i32 %2) nounwind {
+define <vscale x 2 x i1> @intrinsic_vmfne_vv_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmfne_vv_nxv2f16_nxv2f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
@@ -68,7 +70,7 @@ entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2f16(
<vscale x 2 x half> %0,
<vscale x 2 x half> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 2 x i1> %a
}
@@ -78,9 +80,9 @@ declare <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2f16(
<vscale x 2 x half>,
<vscale x 2 x half>,
<vscale x 2 x i1>,
- i32);
+ iXLen);
-define <vscale x 2 x i1> @intrinsic_vmfne_mask_vv_nxv2f16_nxv2f16(<vscale x 2 x i1> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, <vscale x 2 x half> %3, i32 %4) nounwind {
+define <vscale x 2 x i1> @intrinsic_vmfne_mask_vv_nxv2f16_nxv2f16(<vscale x 2 x i1> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, <vscale x 2 x half> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv2f16_nxv2f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
@@ -94,13 +96,13 @@ entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2f16(
<vscale x 2 x half> %1,
<vscale x 2 x half> %2,
- i32 %4)
+ iXLen %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2f16(
<vscale x 2 x i1> %0,
<vscale x 2 x half> %2,
<vscale x 2 x half> %3,
<vscale x 2 x i1> %mask,
- i32 %4)
+ iXLen %4)
ret <vscale x 2 x i1> %a
}
@@ -108,9 +110,9 @@ entry:
declare <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4f16(
<vscale x 4 x half>,
<vscale x 4 x half>,
- i32);
+ iXLen);
-define <vscale x 4 x i1> @intrinsic_vmfne_vv_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i32 %2) nounwind {
+define <vscale x 4 x i1> @intrinsic_vmfne_vv_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmfne_vv_nxv4f16_nxv4f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
@@ -120,7 +122,7 @@ entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4f16(
<vscale x 4 x half> %0,
<vscale x 4 x half> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 4 x i1> %a
}
@@ -130,9 +132,9 @@ declare <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4f16(
<vscale x 4 x half>,
<vscale x 4 x half>,
<vscale x 4 x i1>,
- i32);
+ iXLen);
-define <vscale x 4 x i1> @intrinsic_vmfne_mask_vv_nxv4f16_nxv4f16(<vscale x 4 x i1> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x half> %3, i32 %4) nounwind {
+define <vscale x 4 x i1> @intrinsic_vmfne_mask_vv_nxv4f16_nxv4f16(<vscale x 4 x i1> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x half> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv4f16_nxv4f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
@@ -146,13 +148,13 @@ entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4f16(
<vscale x 4 x half> %1,
<vscale x 4 x half> %2,
- i32 %4)
+ iXLen %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4f16(
<vscale x 4 x i1> %0,
<vscale x 4 x half> %2,
<vscale x 4 x half> %3,
<vscale x 4 x i1> %mask,
- i32 %4)
+ iXLen %4)
ret <vscale x 4 x i1> %a
}
@@ -160,9 +162,9 @@ entry:
declare <vscale x 8 x i1> @llvm.riscv.vmfne.nxv8f16(
<vscale x 8 x half>,
<vscale x 8 x half>,
- i32);
+ iXLen);
-define <vscale x 8 x i1> @intrinsic_vmfne_vv_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i32 %2) nounwind {
+define <vscale x 8 x i1> @intrinsic_vmfne_vv_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmfne_vv_nxv8f16_nxv8f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
@@ -172,7 +174,7 @@ entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmfne.nxv8f16(
<vscale x 8 x half> %0,
<vscale x 8 x half> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 8 x i1> %a
}
@@ -182,9 +184,9 @@ declare <vscale x 8 x i1> @llvm.riscv.vmfne.mask.nxv8f16(
<vscale x 8 x half>,
<vscale x 8 x half>,
<vscale x 8 x i1>,
- i32);
+ iXLen);
-define <vscale x 8 x i1> @intrinsic_vmfne_mask_vv_nxv8f16_nxv8f16(<vscale x 8 x i1> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x half> %3, i32 %4) nounwind {
+define <vscale x 8 x i1> @intrinsic_vmfne_mask_vv_nxv8f16_nxv8f16(<vscale x 8 x i1> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x half> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv8f16_nxv8f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
@@ -198,13 +200,13 @@ entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmfne.nxv8f16(
<vscale x 8 x half> %1,
<vscale x 8 x half> %2,
- i32 %4)
+ iXLen %4)
%a = call <vscale x 8 x i1> @llvm.riscv.vmfne.mask.nxv8f16(
<vscale x 8 x i1> %0,
<vscale x 8 x half> %2,
<vscale x 8 x half> %3,
<vscale x 8 x i1> %mask,
- i32 %4)
+ iXLen %4)
ret <vscale x 8 x i1> %a
}
@@ -212,9 +214,9 @@ entry:
declare <vscale x 16 x i1> @llvm.riscv.vmfne.nxv16f16(
<vscale x 16 x half>,
<vscale x 16 x half>,
- i32);
+ iXLen);
-define <vscale x 16 x i1> @intrinsic_vmfne_vv_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i32 %2) nounwind {
+define <vscale x 16 x i1> @intrinsic_vmfne_vv_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmfne_vv_nxv16f16_nxv16f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
@@ -224,7 +226,7 @@ entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmfne.nxv16f16(
<vscale x 16 x half> %0,
<vscale x 16 x half> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 16 x i1> %a
}
@@ -234,9 +236,9 @@ declare <vscale x 16 x i1> @llvm.riscv.vmfne.mask.nxv16f16(
<vscale x 16 x half>,
<vscale x 16 x half>,
<vscale x 16 x i1>,
- i32);
+ iXLen);
-define <vscale x 16 x i1> @intrinsic_vmfne_mask_vv_nxv16f16_nxv16f16(<vscale x 16 x i1> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, <vscale x 16 x half> %3, i32 %4) nounwind {
+define <vscale x 16 x i1> @intrinsic_vmfne_mask_vv_nxv16f16_nxv16f16(<vscale x 16 x i1> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, <vscale x 16 x half> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv16f16_nxv16f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
@@ -250,13 +252,13 @@ entry:
%mask = call <vscale x 16 x i1> @llvm.riscv.vmfne.nxv16f16(
<vscale x 16 x half> %1,
<vscale x 16 x half> %2,
- i32 %4)
+ iXLen %4)
%a = call <vscale x 16 x i1> @llvm.riscv.vmfne.mask.nxv16f16(
<vscale x 16 x i1> %0,
<vscale x 16 x half> %2,
<vscale x 16 x half> %3,
<vscale x 16 x i1> %mask,
- i32 %4)
+ iXLen %4)
ret <vscale x 16 x i1> %a
}
@@ -264,9 +266,9 @@ entry:
declare <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1f32(
<vscale x 1 x float>,
<vscale x 1 x float>,
- i32);
+ iXLen);
-define <vscale x 1 x i1> @intrinsic_vmfne_vv_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, i32 %2) nounwind {
+define <vscale x 1 x i1> @intrinsic_vmfne_vv_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmfne_vv_nxv1f32_nxv1f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
@@ -276,7 +278,7 @@ entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1f32(
<vscale x 1 x float> %0,
<vscale x 1 x float> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 1 x i1> %a
}
@@ -286,9 +288,9 @@ declare <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1f32(
<vscale x 1 x float>,
<vscale x 1 x float>,
<vscale x 1 x i1>,
- i32);
+ iXLen);
-define <vscale x 1 x i1> @intrinsic_vmfne_mask_vv_nxv1f32_nxv1f32(<vscale x 1 x i1> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, <vscale x 1 x float> %3, i32 %4) nounwind {
+define <vscale x 1 x i1> @intrinsic_vmfne_mask_vv_nxv1f32_nxv1f32(<vscale x 1 x i1> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, <vscale x 1 x float> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv1f32_nxv1f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
@@ -302,13 +304,13 @@ entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1f32(
<vscale x 1 x float> %1,
<vscale x 1 x float> %2,
- i32 %4)
+ iXLen %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1f32(
<vscale x 1 x i1> %0,
<vscale x 1 x float> %2,
<vscale x 1 x float> %3,
<vscale x 1 x i1> %mask,
- i32 %4)
+ iXLen %4)
ret <vscale x 1 x i1> %a
}
@@ -316,9 +318,9 @@ entry:
declare <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2f32(
<vscale x 2 x float>,
<vscale x 2 x float>,
- i32);
+ iXLen);
-define <vscale x 2 x i1> @intrinsic_vmfne_vv_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, i32 %2) nounwind {
+define <vscale x 2 x i1> @intrinsic_vmfne_vv_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmfne_vv_nxv2f32_nxv2f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
@@ -328,7 +330,7 @@ entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2f32(
<vscale x 2 x float> %0,
<vscale x 2 x float> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 2 x i1> %a
}
@@ -338,9 +340,9 @@ declare <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2f32(
<vscale x 2 x float>,
<vscale x 2 x float>,
<vscale x 2 x i1>,
- i32);
+ iXLen);
-define <vscale x 2 x i1> @intrinsic_vmfne_mask_vv_nxv2f32_nxv2f32(<vscale x 2 x i1> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x float> %3, i32 %4) nounwind {
+define <vscale x 2 x i1> @intrinsic_vmfne_mask_vv_nxv2f32_nxv2f32(<vscale x 2 x i1> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x float> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv2f32_nxv2f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
@@ -354,13 +356,13 @@ entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2f32(
<vscale x 2 x float> %1,
<vscale x 2 x float> %2,
- i32 %4)
+ iXLen %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2f32(
<vscale x 2 x i1> %0,
<vscale x 2 x float> %2,
<vscale x 2 x float> %3,
<vscale x 2 x i1> %mask,
- i32 %4)
+ iXLen %4)
ret <vscale x 2 x i1> %a
}
@@ -368,9 +370,9 @@ entry:
declare <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4f32(
<vscale x 4 x float>,
<vscale x 4 x float>,
- i32);
+ iXLen);
-define <vscale x 4 x i1> @intrinsic_vmfne_vv_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, i32 %2) nounwind {
+define <vscale x 4 x i1> @intrinsic_vmfne_vv_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmfne_vv_nxv4f32_nxv4f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
@@ -380,7 +382,7 @@ entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4f32(
<vscale x 4 x float> %0,
<vscale x 4 x float> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 4 x i1> %a
}
@@ -390,9 +392,9 @@ declare <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4f32(
<vscale x 4 x float>,
<vscale x 4 x float>,
<vscale x 4 x i1>,
- i32);
+ iXLen);
-define <vscale x 4 x i1> @intrinsic_vmfne_mask_vv_nxv4f32_nxv4f32(<vscale x 4 x i1> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x float> %3, i32 %4) nounwind {
+define <vscale x 4 x i1> @intrinsic_vmfne_mask_vv_nxv4f32_nxv4f32(<vscale x 4 x i1> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x float> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv4f32_nxv4f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
@@ -406,13 +408,13 @@ entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4f32(
<vscale x 4 x float> %1,
<vscale x 4 x float> %2,
- i32 %4)
+ iXLen %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4f32(
<vscale x 4 x i1> %0,
<vscale x 4 x float> %2,
<vscale x 4 x float> %3,
<vscale x 4 x i1> %mask,
- i32 %4)
+ iXLen %4)
ret <vscale x 4 x i1> %a
}
@@ -420,9 +422,9 @@ entry:
declare <vscale x 8 x i1> @llvm.riscv.vmfne.nxv8f32(
<vscale x 8 x float>,
<vscale x 8 x float>,
- i32);
+ iXLen);
-define <vscale x 8 x i1> @intrinsic_vmfne_vv_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, i32 %2) nounwind {
+define <vscale x 8 x i1> @intrinsic_vmfne_vv_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmfne_vv_nxv8f32_nxv8f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
@@ -432,7 +434,7 @@ entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmfne.nxv8f32(
<vscale x 8 x float> %0,
<vscale x 8 x float> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 8 x i1> %a
}
@@ -442,9 +444,9 @@ declare <vscale x 8 x i1> @llvm.riscv.vmfne.mask.nxv8f32(
<vscale x 8 x float>,
<vscale x 8 x float>,
<vscale x 8 x i1>,
- i32);
+ iXLen);
-define <vscale x 8 x i1> @intrinsic_vmfne_mask_vv_nxv8f32_nxv8f32(<vscale x 8 x i1> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, <vscale x 8 x float> %3, i32 %4) nounwind {
+define <vscale x 8 x i1> @intrinsic_vmfne_mask_vv_nxv8f32_nxv8f32(<vscale x 8 x i1> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, <vscale x 8 x float> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv8f32_nxv8f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
@@ -458,13 +460,13 @@ entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmfne.nxv8f32(
<vscale x 8 x float> %1,
<vscale x 8 x float> %2,
- i32 %4)
+ iXLen %4)
%a = call <vscale x 8 x i1> @llvm.riscv.vmfne.mask.nxv8f32(
<vscale x 8 x i1> %0,
<vscale x 8 x float> %2,
<vscale x 8 x float> %3,
<vscale x 8 x i1> %mask,
- i32 %4)
+ iXLen %4)
ret <vscale x 8 x i1> %a
}
@@ -472,9 +474,9 @@ entry:
declare <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1f64(
<vscale x 1 x double>,
<vscale x 1 x double>,
- i32);
+ iXLen);
-define <vscale x 1 x i1> @intrinsic_vmfne_vv_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, i32 %2) nounwind {
+define <vscale x 1 x i1> @intrinsic_vmfne_vv_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmfne_vv_nxv1f64_nxv1f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
@@ -484,7 +486,7 @@ entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1f64(
<vscale x 1 x double> %0,
<vscale x 1 x double> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 1 x i1> %a
}
@@ -494,9 +496,9 @@ declare <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1f64(
<vscale x 1 x double>,
<vscale x 1 x double>,
<vscale x 1 x i1>,
- i32);
+ iXLen);
-define <vscale x 1 x i1> @intrinsic_vmfne_mask_vv_nxv1f64_nxv1f64(<vscale x 1 x i1> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, <vscale x 1 x double> %3, i32 %4) nounwind {
+define <vscale x 1 x i1> @intrinsic_vmfne_mask_vv_nxv1f64_nxv1f64(<vscale x 1 x i1> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, <vscale x 1 x double> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv1f64_nxv1f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
@@ -510,13 +512,13 @@ entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1f64(
<vscale x 1 x double> %1,
<vscale x 1 x double> %2,
- i32 %4)
+ iXLen %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1f64(
<vscale x 1 x i1> %0,
<vscale x 1 x double> %2,
<vscale x 1 x double> %3,
<vscale x 1 x i1> %mask,
- i32 %4)
+ iXLen %4)
ret <vscale x 1 x i1> %a
}
@@ -524,9 +526,9 @@ entry:
declare <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2f64(
<vscale x 2 x double>,
<vscale x 2 x double>,
- i32);
+ iXLen);
-define <vscale x 2 x i1> @intrinsic_vmfne_vv_nxv2f64_nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, i32 %2) nounwind {
+define <vscale x 2 x i1> @intrinsic_vmfne_vv_nxv2f64_nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmfne_vv_nxv2f64_nxv2f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
@@ -536,7 +538,7 @@ entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2f64(
<vscale x 2 x double> %0,
<vscale x 2 x double> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 2 x i1> %a
}
@@ -546,9 +548,9 @@ declare <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2f64(
<vscale x 2 x double>,
<vscale x 2 x double>,
<vscale x 2 x i1>,
- i32);
+ iXLen);
-define <vscale x 2 x i1> @intrinsic_vmfne_mask_vv_nxv2f64_nxv2f64(<vscale x 2 x i1> %0, <vscale x 2 x double> %1, <vscale x 2 x double> %2, <vscale x 2 x double> %3, i32 %4) nounwind {
+define <vscale x 2 x i1> @intrinsic_vmfne_mask_vv_nxv2f64_nxv2f64(<vscale x 2 x i1> %0, <vscale x 2 x double> %1, <vscale x 2 x double> %2, <vscale x 2 x double> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv2f64_nxv2f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
@@ -562,13 +564,13 @@ entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2f64(
<vscale x 2 x double> %1,
<vscale x 2 x double> %2,
- i32 %4)
+ iXLen %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2f64(
<vscale x 2 x i1> %0,
<vscale x 2 x double> %2,
<vscale x 2 x double> %3,
<vscale x 2 x i1> %mask,
- i32 %4)
+ iXLen %4)
ret <vscale x 2 x i1> %a
}
@@ -576,9 +578,9 @@ entry:
declare <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4f64(
<vscale x 4 x double>,
<vscale x 4 x double>,
- i32);
+ iXLen);
-define <vscale x 4 x i1> @intrinsic_vmfne_vv_nxv4f64_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, i32 %2) nounwind {
+define <vscale x 4 x i1> @intrinsic_vmfne_vv_nxv4f64_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmfne_vv_nxv4f64_nxv4f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
@@ -588,7 +590,7 @@ entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4f64(
<vscale x 4 x double> %0,
<vscale x 4 x double> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 4 x i1> %a
}
@@ -598,9 +600,9 @@ declare <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4f64(
<vscale x 4 x double>,
<vscale x 4 x double>,
<vscale x 4 x i1>,
- i32);
+ iXLen);
-define <vscale x 4 x i1> @intrinsic_vmfne_mask_vv_nxv4f64_nxv4f64(<vscale x 4 x i1> %0, <vscale x 4 x double> %1, <vscale x 4 x double> %2, <vscale x 4 x double> %3, i32 %4) nounwind {
+define <vscale x 4 x i1> @intrinsic_vmfne_mask_vv_nxv4f64_nxv4f64(<vscale x 4 x i1> %0, <vscale x 4 x double> %1, <vscale x 4 x double> %2, <vscale x 4 x double> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv4f64_nxv4f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
@@ -614,13 +616,13 @@ entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4f64(
<vscale x 4 x double> %1,
<vscale x 4 x double> %2,
- i32 %4)
+ iXLen %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4f64(
<vscale x 4 x i1> %0,
<vscale x 4 x double> %2,
<vscale x 4 x double> %3,
<vscale x 4 x i1> %mask,
- i32 %4)
+ iXLen %4)
ret <vscale x 4 x i1> %a
}
@@ -628,9 +630,9 @@ entry:
declare <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1f16.f16(
<vscale x 1 x half>,
half,
- i32);
+ iXLen);
-define <vscale x 1 x i1> @intrinsic_vmfne_vf_nxv1f16_f16(<vscale x 1 x half> %0, half %1, i32 %2) nounwind {
+define <vscale x 1 x i1> @intrinsic_vmfne_vf_nxv1f16_f16(<vscale x 1 x half> %0, half %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmfne_vf_nxv1f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
@@ -640,7 +642,7 @@ entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1f16.f16(
<vscale x 1 x half> %0,
half %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 1 x i1> %a
}
@@ -650,9 +652,9 @@ declare <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1f16.f16(
<vscale x 1 x half>,
half,
<vscale x 1 x i1>,
- i32);
+ iXLen);
-define <vscale x 1 x i1> @intrinsic_vmfne_mask_vf_nxv1f16_f16(<vscale x 1 x i1> %0, <vscale x 1 x half> %1, half %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+define <vscale x 1 x i1> @intrinsic_vmfne_mask_vf_nxv1f16_f16(<vscale x 1 x i1> %0, <vscale x 1 x half> %1, half %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv1f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0
@@ -667,7 +669,7 @@ entry:
<vscale x 1 x half> %1,
half %2,
<vscale x 1 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 1 x i1> %a
}
@@ -675,9 +677,9 @@ entry:
declare <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2f16.f16(
<vscale x 2 x half>,
half,
- i32);
+ iXLen);
-define <vscale x 2 x i1> @intrinsic_vmfne_vf_nxv2f16_f16(<vscale x 2 x half> %0, half %1, i32 %2) nounwind {
+define <vscale x 2 x i1> @intrinsic_vmfne_vf_nxv2f16_f16(<vscale x 2 x half> %0, half %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmfne_vf_nxv2f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
@@ -687,7 +689,7 @@ entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2f16.f16(
<vscale x 2 x half> %0,
half %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 2 x i1> %a
}
@@ -697,9 +699,9 @@ declare <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2f16.f16(
<vscale x 2 x half>,
half,
<vscale x 2 x i1>,
- i32);
+ iXLen);
-define <vscale x 2 x i1> @intrinsic_vmfne_mask_vf_nxv2f16_f16(<vscale x 2 x i1> %0, <vscale x 2 x half> %1, half %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+define <vscale x 2 x i1> @intrinsic_vmfne_mask_vf_nxv2f16_f16(<vscale x 2 x i1> %0, <vscale x 2 x half> %1, half %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv2f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0
@@ -714,7 +716,7 @@ entry:
<vscale x 2 x half> %1,
half %2,
<vscale x 2 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 2 x i1> %a
}
@@ -722,9 +724,9 @@ entry:
declare <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4f16.f16(
<vscale x 4 x half>,
half,
- i32);
+ iXLen);
-define <vscale x 4 x i1> @intrinsic_vmfne_vf_nxv4f16_f16(<vscale x 4 x half> %0, half %1, i32 %2) nounwind {
+define <vscale x 4 x i1> @intrinsic_vmfne_vf_nxv4f16_f16(<vscale x 4 x half> %0, half %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmfne_vf_nxv4f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
@@ -734,7 +736,7 @@ entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4f16.f16(
<vscale x 4 x half> %0,
half %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 4 x i1> %a
}
@@ -744,9 +746,9 @@ declare <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4f16.f16(
<vscale x 4 x half>,
half,
<vscale x 4 x i1>,
- i32);
+ iXLen);
-define <vscale x 4 x i1> @intrinsic_vmfne_mask_vf_nxv4f16_f16(<vscale x 4 x i1> %0, <vscale x 4 x half> %1, half %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+define <vscale x 4 x i1> @intrinsic_vmfne_mask_vf_nxv4f16_f16(<vscale x 4 x i1> %0, <vscale x 4 x half> %1, half %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv4f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0
@@ -761,7 +763,7 @@ entry:
<vscale x 4 x half> %1,
half %2,
<vscale x 4 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 4 x i1> %a
}
@@ -769,9 +771,9 @@ entry:
declare <vscale x 8 x i1> @llvm.riscv.vmfne.nxv8f16.f16(
<vscale x 8 x half>,
half,
- i32);
+ iXLen);
-define <vscale x 8 x i1> @intrinsic_vmfne_vf_nxv8f16_f16(<vscale x 8 x half> %0, half %1, i32 %2) nounwind {
+define <vscale x 8 x i1> @intrinsic_vmfne_vf_nxv8f16_f16(<vscale x 8 x half> %0, half %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmfne_vf_nxv8f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
@@ -781,7 +783,7 @@ entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmfne.nxv8f16.f16(
<vscale x 8 x half> %0,
half %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 8 x i1> %a
}
@@ -791,9 +793,9 @@ declare <vscale x 8 x i1> @llvm.riscv.vmfne.mask.nxv8f16.f16(
<vscale x 8 x half>,
half,
<vscale x 8 x i1>,
- i32);
+ iXLen);
-define <vscale x 8 x i1> @intrinsic_vmfne_mask_vf_nxv8f16_f16(<vscale x 8 x i1> %0, <vscale x 8 x half> %1, half %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+define <vscale x 8 x i1> @intrinsic_vmfne_mask_vf_nxv8f16_f16(<vscale x 8 x i1> %0, <vscale x 8 x half> %1, half %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv8f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v11, v0
@@ -808,7 +810,7 @@ entry:
<vscale x 8 x half> %1,
half %2,
<vscale x 8 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 8 x i1> %a
}
@@ -816,9 +818,9 @@ entry:
declare <vscale x 16 x i1> @llvm.riscv.vmfne.nxv16f16.f16(
<vscale x 16 x half>,
half,
- i32);
+ iXLen);
-define <vscale x 16 x i1> @intrinsic_vmfne_vf_nxv16f16_f16(<vscale x 16 x half> %0, half %1, i32 %2) nounwind {
+define <vscale x 16 x i1> @intrinsic_vmfne_vf_nxv16f16_f16(<vscale x 16 x half> %0, half %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmfne_vf_nxv16f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
@@ -828,7 +830,7 @@ entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmfne.nxv16f16.f16(
<vscale x 16 x half> %0,
half %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 16 x i1> %a
}
@@ -838,9 +840,9 @@ declare <vscale x 16 x i1> @llvm.riscv.vmfne.mask.nxv16f16.f16(
<vscale x 16 x half>,
half,
<vscale x 16 x i1>,
- i32);
+ iXLen);
-define <vscale x 16 x i1> @intrinsic_vmfne_mask_vf_nxv16f16_f16(<vscale x 16 x i1> %0, <vscale x 16 x half> %1, half %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+define <vscale x 16 x i1> @intrinsic_vmfne_mask_vf_nxv16f16_f16(<vscale x 16 x i1> %0, <vscale x 16 x half> %1, half %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv16f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v13, v0
@@ -855,7 +857,7 @@ entry:
<vscale x 16 x half> %1,
half %2,
<vscale x 16 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 16 x i1> %a
}
@@ -863,9 +865,9 @@ entry:
declare <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1f32.f32(
<vscale x 1 x float>,
float,
- i32);
+ iXLen);
-define <vscale x 1 x i1> @intrinsic_vmfne_vf_nxv1f32_f32(<vscale x 1 x float> %0, float %1, i32 %2) nounwind {
+define <vscale x 1 x i1> @intrinsic_vmfne_vf_nxv1f32_f32(<vscale x 1 x float> %0, float %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmfne_vf_nxv1f32_f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
@@ -875,7 +877,7 @@ entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1f32.f32(
<vscale x 1 x float> %0,
float %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 1 x i1> %a
}
@@ -885,9 +887,9 @@ declare <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1f32.f32(
<vscale x 1 x float>,
float,
<vscale x 1 x i1>,
- i32);
+ iXLen);
-define <vscale x 1 x i1> @intrinsic_vmfne_mask_vf_nxv1f32_f32(<vscale x 1 x i1> %0, <vscale x 1 x float> %1, float %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+define <vscale x 1 x i1> @intrinsic_vmfne_mask_vf_nxv1f32_f32(<vscale x 1 x i1> %0, <vscale x 1 x float> %1, float %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv1f32_f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0
@@ -902,7 +904,7 @@ entry:
<vscale x 1 x float> %1,
float %2,
<vscale x 1 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 1 x i1> %a
}
@@ -910,9 +912,9 @@ entry:
declare <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2f32.f32(
<vscale x 2 x float>,
float,
- i32);
+ iXLen);
-define <vscale x 2 x i1> @intrinsic_vmfne_vf_nxv2f32_f32(<vscale x 2 x float> %0, float %1, i32 %2) nounwind {
+define <vscale x 2 x i1> @intrinsic_vmfne_vf_nxv2f32_f32(<vscale x 2 x float> %0, float %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmfne_vf_nxv2f32_f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
@@ -922,7 +924,7 @@ entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2f32.f32(
<vscale x 2 x float> %0,
float %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 2 x i1> %a
}
@@ -932,9 +934,9 @@ declare <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2f32.f32(
<vscale x 2 x float>,
float,
<vscale x 2 x i1>,
- i32);
+ iXLen);
-define <vscale x 2 x i1> @intrinsic_vmfne_mask_vf_nxv2f32_f32(<vscale x 2 x i1> %0, <vscale x 2 x float> %1, float %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+define <vscale x 2 x i1> @intrinsic_vmfne_mask_vf_nxv2f32_f32(<vscale x 2 x i1> %0, <vscale x 2 x float> %1, float %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv2f32_f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0
@@ -949,7 +951,7 @@ entry:
<vscale x 2 x float> %1,
float %2,
<vscale x 2 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 2 x i1> %a
}
@@ -957,9 +959,9 @@ entry:
declare <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4f32.f32(
<vscale x 4 x float>,
float,
- i32);
+ iXLen);
-define <vscale x 4 x i1> @intrinsic_vmfne_vf_nxv4f32_f32(<vscale x 4 x float> %0, float %1, i32 %2) nounwind {
+define <vscale x 4 x i1> @intrinsic_vmfne_vf_nxv4f32_f32(<vscale x 4 x float> %0, float %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmfne_vf_nxv4f32_f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
@@ -969,7 +971,7 @@ entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4f32.f32(
<vscale x 4 x float> %0,
float %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 4 x i1> %a
}
@@ -979,9 +981,9 @@ declare <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4f32.f32(
<vscale x 4 x float>,
float,
<vscale x 4 x i1>,
- i32);
+ iXLen);
-define <vscale x 4 x i1> @intrinsic_vmfne_mask_vf_nxv4f32_f32(<vscale x 4 x i1> %0, <vscale x 4 x float> %1, float %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+define <vscale x 4 x i1> @intrinsic_vmfne_mask_vf_nxv4f32_f32(<vscale x 4 x i1> %0, <vscale x 4 x float> %1, float %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv4f32_f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v11, v0
@@ -996,7 +998,7 @@ entry:
<vscale x 4 x float> %1,
float %2,
<vscale x 4 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 4 x i1> %a
}
@@ -1004,9 +1006,9 @@ entry:
declare <vscale x 8 x i1> @llvm.riscv.vmfne.nxv8f32.f32(
<vscale x 8 x float>,
float,
- i32);
+ iXLen);
-define <vscale x 8 x i1> @intrinsic_vmfne_vf_nxv8f32_f32(<vscale x 8 x float> %0, float %1, i32 %2) nounwind {
+define <vscale x 8 x i1> @intrinsic_vmfne_vf_nxv8f32_f32(<vscale x 8 x float> %0, float %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmfne_vf_nxv8f32_f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
@@ -1016,7 +1018,7 @@ entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmfne.nxv8f32.f32(
<vscale x 8 x float> %0,
float %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 8 x i1> %a
}
@@ -1026,9 +1028,9 @@ declare <vscale x 8 x i1> @llvm.riscv.vmfne.mask.nxv8f32.f32(
<vscale x 8 x float>,
float,
<vscale x 8 x i1>,
- i32);
+ iXLen);
-define <vscale x 8 x i1> @intrinsic_vmfne_mask_vf_nxv8f32_f32(<vscale x 8 x i1> %0, <vscale x 8 x float> %1, float %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+define <vscale x 8 x i1> @intrinsic_vmfne_mask_vf_nxv8f32_f32(<vscale x 8 x i1> %0, <vscale x 8 x float> %1, float %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv8f32_f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v13, v0
@@ -1043,7 +1045,7 @@ entry:
<vscale x 8 x float> %1,
float %2,
<vscale x 8 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 8 x i1> %a
}
@@ -1051,9 +1053,9 @@ entry:
declare <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1f64.f64(
<vscale x 1 x double>,
double,
- i32);
+ iXLen);
-define <vscale x 1 x i1> @intrinsic_vmfne_vf_nxv1f64_f64(<vscale x 1 x double> %0, double %1, i32 %2) nounwind {
+define <vscale x 1 x i1> @intrinsic_vmfne_vf_nxv1f64_f64(<vscale x 1 x double> %0, double %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmfne_vf_nxv1f64_f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
@@ -1063,7 +1065,7 @@ entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1f64.f64(
<vscale x 1 x double> %0,
double %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 1 x i1> %a
}
@@ -1073,9 +1075,9 @@ declare <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1f64.f64(
<vscale x 1 x double>,
double,
<vscale x 1 x i1>,
- i32);
+ iXLen);
-define <vscale x 1 x i1> @intrinsic_vmfne_mask_vf_nxv1f64_f64(<vscale x 1 x i1> %0, <vscale x 1 x double> %1, double %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+define <vscale x 1 x i1> @intrinsic_vmfne_mask_vf_nxv1f64_f64(<vscale x 1 x i1> %0, <vscale x 1 x double> %1, double %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv1f64_f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0
@@ -1090,7 +1092,7 @@ entry:
<vscale x 1 x double> %1,
double %2,
<vscale x 1 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 1 x i1> %a
}
@@ -1098,9 +1100,9 @@ entry:
declare <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2f64.f64(
<vscale x 2 x double>,
double,
- i32);
+ iXLen);
-define <vscale x 2 x i1> @intrinsic_vmfne_vf_nxv2f64_f64(<vscale x 2 x double> %0, double %1, i32 %2) nounwind {
+define <vscale x 2 x i1> @intrinsic_vmfne_vf_nxv2f64_f64(<vscale x 2 x double> %0, double %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmfne_vf_nxv2f64_f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
@@ -1110,7 +1112,7 @@ entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2f64.f64(
<vscale x 2 x double> %0,
double %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 2 x i1> %a
}
@@ -1120,9 +1122,9 @@ declare <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2f64.f64(
<vscale x 2 x double>,
double,
<vscale x 2 x i1>,
- i32);
+ iXLen);
-define <vscale x 2 x i1> @intrinsic_vmfne_mask_vf_nxv2f64_f64(<vscale x 2 x i1> %0, <vscale x 2 x double> %1, double %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+define <vscale x 2 x i1> @intrinsic_vmfne_mask_vf_nxv2f64_f64(<vscale x 2 x i1> %0, <vscale x 2 x double> %1, double %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv2f64_f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v11, v0
@@ -1137,7 +1139,7 @@ entry:
<vscale x 2 x double> %1,
double %2,
<vscale x 2 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 2 x i1> %a
}
@@ -1145,9 +1147,9 @@ entry:
declare <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4f64.f64(
<vscale x 4 x double>,
double,
- i32);
+ iXLen);
-define <vscale x 4 x i1> @intrinsic_vmfne_vf_nxv4f64_f64(<vscale x 4 x double> %0, double %1, i32 %2) nounwind {
+define <vscale x 4 x i1> @intrinsic_vmfne_vf_nxv4f64_f64(<vscale x 4 x double> %0, double %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmfne_vf_nxv4f64_f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
@@ -1157,7 +1159,7 @@ entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4f64.f64(
<vscale x 4 x double> %0,
double %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 4 x i1> %a
}
@@ -1167,9 +1169,9 @@ declare <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4f64.f64(
<vscale x 4 x double>,
double,
<vscale x 4 x i1>,
- i32);
+ iXLen);
-define <vscale x 4 x i1> @intrinsic_vmfne_mask_vf_nxv4f64_f64(<vscale x 4 x i1> %0, <vscale x 4 x double> %1, double %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+define <vscale x 4 x i1> @intrinsic_vmfne_mask_vf_nxv4f64_f64(<vscale x 4 x i1> %0, <vscale x 4 x double> %1, double %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv4f64_f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v13, v0
@@ -1184,7 +1186,7 @@ entry:
<vscale x 4 x double> %1,
double %2,
<vscale x 4 x i1> %3,
- i32 %4)
+ iXLen %4)
ret <vscale x 4 x i1> %a
}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmsbf-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vmsbf-rv64.ll
deleted file mode 100644
index bf773b7c45502..0000000000000
--- a/llvm/test/CodeGen/RISCV/rvv/vmsbf-rv64.ll
+++ /dev/null
@@ -1,296 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs \
-; RUN: < %s | FileCheck %s
-declare <vscale x 1 x i1> @llvm.riscv.vmsbf.nxv1i1(
- <vscale x 1 x i1>,
- i64);
-
-define <vscale x 1 x i1> @intrinsic_vmsbf_m_nxv1i1(<vscale x 1 x i1> %0, i64 %1) nounwind {
-; CHECK-LABEL: intrinsic_vmsbf_m_nxv1i1:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
-; CHECK-NEXT: vmsbf.m v8, v0
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i1> @llvm.riscv.vmsbf.nxv1i1(
- <vscale x 1 x i1> %0,
- i64 %1)
- ret <vscale x 1 x i1> %a
-}
-
-declare <vscale x 1 x i1> @llvm.riscv.vmsbf.mask.nxv1i1(
- <vscale x 1 x i1>,
- <vscale x 1 x i1>,
- <vscale x 1 x i1>,
- i64);
-
-define <vscale x 1 x i1> @intrinsic_vmsbf_mask_m_nxv1i1_nxv1i1(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vmsbf_mask_m_nxv1i1_nxv1i1:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v10, v0
-; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, mu
-; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsbf.m v10, v8, v0.t
-; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i1> @llvm.riscv.vmsbf.mask.nxv1i1(
- <vscale x 1 x i1> %0,
- <vscale x 1 x i1> %1,
- <vscale x 1 x i1> %2,
- i64 %3)
- ret <vscale x 1 x i1> %a
-}
-
-declare <vscale x 2 x i1> @llvm.riscv.vmsbf.nxv2i1(
- <vscale x 2 x i1>,
- i64);
-
-define <vscale x 2 x i1> @intrinsic_vmsbf_m_nxv2i1(<vscale x 2 x i1> %0, i64 %1) nounwind {
-; CHECK-LABEL: intrinsic_vmsbf_m_nxv2i1:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
-; CHECK-NEXT: vmsbf.m v8, v0
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i1> @llvm.riscv.vmsbf.nxv2i1(
- <vscale x 2 x i1> %0,
- i64 %1)
- ret <vscale x 2 x i1> %a
-}
-
-declare <vscale x 2 x i1> @llvm.riscv.vmsbf.mask.nxv2i1(
- <vscale x 2 x i1>,
- <vscale x 2 x i1>,
- <vscale x 2 x i1>,
- i64);
-
-define <vscale x 2 x i1> @intrinsic_vmsbf_mask_m_nxv2i1_nxv2i1(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vmsbf_mask_m_nxv2i1_nxv2i1:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v10, v0
-; CHECK-NEXT: vsetvli zero, a0, e8, mf4, tu, mu
-; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsbf.m v10, v8, v0.t
-; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i1> @llvm.riscv.vmsbf.mask.nxv2i1(
- <vscale x 2 x i1> %0,
- <vscale x 2 x i1> %1,
- <vscale x 2 x i1> %2,
- i64 %3)
- ret <vscale x 2 x i1> %a
-}
-
-declare <vscale x 4 x i1> @llvm.riscv.vmsbf.nxv4i1(
- <vscale x 4 x i1>,
- i64);
-
-define <vscale x 4 x i1> @intrinsic_vmsbf_m_nxv4i1(<vscale x 4 x i1> %0, i64 %1) nounwind {
-; CHECK-LABEL: intrinsic_vmsbf_m_nxv4i1:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
-; CHECK-NEXT: vmsbf.m v8, v0
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i1> @llvm.riscv.vmsbf.nxv4i1(
- <vscale x 4 x i1> %0,
- i64 %1)
- ret <vscale x 4 x i1> %a
-}
-
-declare <vscale x 4 x i1> @llvm.riscv.vmsbf.mask.nxv4i1(
- <vscale x 4 x i1>,
- <vscale x 4 x i1>,
- <vscale x 4 x i1>,
- i64);
-
-define <vscale x 4 x i1> @intrinsic_vmsbf_mask_m_nxv4i1_nxv4i1(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vmsbf_mask_m_nxv4i1_nxv4i1:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v10, v0
-; CHECK-NEXT: vsetvli zero, a0, e8, mf2, tu, mu
-; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsbf.m v10, v8, v0.t
-; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i1> @llvm.riscv.vmsbf.mask.nxv4i1(
- <vscale x 4 x i1> %0,
- <vscale x 4 x i1> %1,
- <vscale x 4 x i1> %2,
- i64 %3)
- ret <vscale x 4 x i1> %a
-}
-
-declare <vscale x 8 x i1> @llvm.riscv.vmsbf.nxv8i1(
- <vscale x 8 x i1>,
- i64);
-
-define <vscale x 8 x i1> @intrinsic_vmsbf_m_nxv8i1(<vscale x 8 x i1> %0, i64 %1) nounwind {
-; CHECK-LABEL: intrinsic_vmsbf_m_nxv8i1:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
-; CHECK-NEXT: vmsbf.m v8, v0
-; CHECK-NEXT: vmv.v.v v0, v8
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i1> @llvm.riscv.vmsbf.nxv8i1(
- <vscale x 8 x i1> %0,
- i64 %1)
- ret <vscale x 8 x i1> %a
-}
-
-declare <vscale x 8 x i1> @llvm.riscv.vmsbf.mask.nxv8i1(
- <vscale x 8 x i1>,
- <vscale x 8 x i1>,
- <vscale x 8 x i1>,
- i64);
-
-define <vscale x 8 x i1> @intrinsic_vmsbf_mask_m_nxv8i1_nxv8i1(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vmsbf_mask_m_nxv8i1_nxv8i1:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v10, v0
-; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, mu
-; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsbf.m v10, v8, v0.t
-; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i1> @llvm.riscv.vmsbf.mask.nxv8i1(
- <vscale x 8 x i1> %0,
- <vscale x 8 x i1> %1,
- <vscale x 8 x i1> %2,
- i64 %3)
- ret <vscale x 8 x i1> %a
-}
-
-declare <vscale x 16 x i1> @llvm.riscv.vmsbf.nxv16i1(
- <vscale x 16 x i1>,
- i64);
-
-define <vscale x 16 x i1> @intrinsic_vmsbf_m_nxv16i1(<vscale x 16 x i1> %0, i64 %1) nounwind {
-; CHECK-LABEL: intrinsic_vmsbf_m_nxv16i1:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
-; CHECK-NEXT: vmsbf.m v8, v0
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i1> @llvm.riscv.vmsbf.nxv16i1(
- <vscale x 16 x i1> %0,
- i64 %1)
- ret <vscale x 16 x i1> %a
-}
-
-declare <vscale x 16 x i1> @llvm.riscv.vmsbf.mask.nxv16i1(
- <vscale x 16 x i1>,
- <vscale x 16 x i1>,
- <vscale x 16 x i1>,
- i64);
-
-define <vscale x 16 x i1> @intrinsic_vmsbf_mask_m_nxv16i1_nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, <vscale x 16 x i1> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vmsbf_mask_m_nxv16i1_nxv16i1:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v10, v0
-; CHECK-NEXT: vsetvli zero, a0, e8, m2, tu, mu
-; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsbf.m v10, v8, v0.t
-; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i1> @llvm.riscv.vmsbf.mask.nxv16i1(
- <vscale x 16 x i1> %0,
- <vscale x 16 x i1> %1,
- <vscale x 16 x i1> %2,
- i64 %3)
- ret <vscale x 16 x i1> %a
-}
-
-declare <vscale x 32 x i1> @llvm.riscv.vmsbf.nxv32i1(
- <vscale x 32 x i1>,
- i64);
-
-define <vscale x 32 x i1> @intrinsic_vmsbf_m_nxv32i1(<vscale x 32 x i1> %0, i64 %1) nounwind {
-; CHECK-LABEL: intrinsic_vmsbf_m_nxv32i1:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
-; CHECK-NEXT: vmsbf.m v8, v0
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 32 x i1> @llvm.riscv.vmsbf.nxv32i1(
- <vscale x 32 x i1> %0,
- i64 %1)
- ret <vscale x 32 x i1> %a
-}
-
-declare <vscale x 32 x i1> @llvm.riscv.vmsbf.mask.nxv32i1(
- <vscale x 32 x i1>,
- <vscale x 32 x i1>,
- <vscale x 32 x i1>,
- i64);
-
-define <vscale x 32 x i1> @intrinsic_vmsbf_mask_m_nxv32i1_nxv32i1(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, <vscale x 32 x i1> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vmsbf_mask_m_nxv32i1_nxv32i1:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v10, v0
-; CHECK-NEXT: vsetvli zero, a0, e8, m4, tu, mu
-; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsbf.m v10, v8, v0.t
-; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 32 x i1> @llvm.riscv.vmsbf.mask.nxv32i1(
- <vscale x 32 x i1> %0,
- <vscale x 32 x i1> %1,
- <vscale x 32 x i1> %2,
- i64 %3)
- ret <vscale x 32 x i1> %a
-}
-
-declare <vscale x 64 x i1> @llvm.riscv.vmsbf.nxv64i1(
- <vscale x 64 x i1>,
- i64);
-
-define <vscale x 64 x i1> @intrinsic_vmsbf_m_nxv64i1(<vscale x 64 x i1> %0, i64 %1) nounwind {
-; CHECK-LABEL: intrinsic_vmsbf_m_nxv64i1:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, mu
-; CHECK-NEXT: vmsbf.m v8, v0
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 64 x i1> @llvm.riscv.vmsbf.nxv64i1(
- <vscale x 64 x i1> %0,
- i64 %1)
- ret <vscale x 64 x i1> %a
-}
-
-declare <vscale x 64 x i1> @llvm.riscv.vmsbf.mask.nxv64i1(
- <vscale x 64 x i1>,
- <vscale x 64 x i1>,
- <vscale x 64 x i1>,
- i64);
-
-define <vscale x 64 x i1> @intrinsic_vmsbf_mask_m_nxv64i1_nxv64i1(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, <vscale x 64 x i1> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vmsbf_mask_m_nxv64i1_nxv64i1:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vmv1r.v v10, v0
-; CHECK-NEXT: vsetvli zero, a0, e8, m8, tu, mu
-; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmsbf.m v10, v8, v0.t
-; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 64 x i1> @llvm.riscv.vmsbf.mask.nxv64i1(
- <vscale x 64 x i1> %0,
- <vscale x 64 x i1> %1,
- <vscale x 64 x i1> %2,
- i64 %3)
- ret <vscale x 64 x i1> %a
-}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmsbf-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmsbf.ll
similarity index 89%
rename from llvm/test/CodeGen/RISCV/rvv/vmsbf-rv32.ll
rename to llvm/test/CodeGen/RISCV/rvv/vmsbf.ll
index b8f27529534da..8011b56633017 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vmsbf-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vmsbf.ll
@@ -1,11 +1,13 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs \
-; RUN: < %s | FileCheck %s
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v \
+; RUN: -verify-machineinstrs | FileCheck %s
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v \
+; RUN: -verify-machineinstrs | FileCheck %s
declare <vscale x 1 x i1> @llvm.riscv.vmsbf.nxv1i1(
<vscale x 1 x i1>,
- i32);
+ iXLen);
-define <vscale x 1 x i1> @intrinsic_vmsbf_m_nxv1i1(<vscale x 1 x i1> %0, i32 %1) nounwind {
+define <vscale x 1 x i1> @intrinsic_vmsbf_m_nxv1i1(<vscale x 1 x i1> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vmsbf_m_nxv1i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
@@ -15,7 +17,7 @@ define <vscale x 1 x i1> @intrinsic_vmsbf_m_nxv1i1(<vscale x 1 x i1> %0, i32 %1)
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsbf.nxv1i1(
<vscale x 1 x i1> %0,
- i32 %1)
+ iXLen %1)
ret <vscale x 1 x i1> %a
}
@@ -23,9 +25,9 @@ declare <vscale x 1 x i1> @llvm.riscv.vmsbf.mask.nxv1i1(
<vscale x 1 x i1>,
<vscale x 1 x i1>,
<vscale x 1 x i1>,
- i32);
+ iXLen);
-define <vscale x 1 x i1> @intrinsic_vmsbf_mask_m_nxv1i1_nxv1i1(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
+define <vscale x 1 x i1> @intrinsic_vmsbf_mask_m_nxv1i1_nxv1i1(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vmsbf_mask_m_nxv1i1_nxv1i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0
@@ -39,15 +41,15 @@ entry:
<vscale x 1 x i1> %0,
<vscale x 1 x i1> %1,
<vscale x 1 x i1> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 1 x i1> %a
}
declare <vscale x 2 x i1> @llvm.riscv.vmsbf.nxv2i1(
<vscale x 2 x i1>,
- i32);
+ iXLen);
-define <vscale x 2 x i1> @intrinsic_vmsbf_m_nxv2i1(<vscale x 2 x i1> %0, i32 %1) nounwind {
+define <vscale x 2 x i1> @intrinsic_vmsbf_m_nxv2i1(<vscale x 2 x i1> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vmsbf_m_nxv2i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
@@ -57,7 +59,7 @@ define <vscale x 2 x i1> @intrinsic_vmsbf_m_nxv2i1(<vscale x 2 x i1> %0, i32 %1)
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsbf.nxv2i1(
<vscale x 2 x i1> %0,
- i32 %1)
+ iXLen %1)
ret <vscale x 2 x i1> %a
}
@@ -65,9 +67,9 @@ declare <vscale x 2 x i1> @llvm.riscv.vmsbf.mask.nxv2i1(
<vscale x 2 x i1>,
<vscale x 2 x i1>,
<vscale x 2 x i1>,
- i32);
+ iXLen);
-define <vscale x 2 x i1> @intrinsic_vmsbf_mask_m_nxv2i1_nxv2i1(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
+define <vscale x 2 x i1> @intrinsic_vmsbf_mask_m_nxv2i1_nxv2i1(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vmsbf_mask_m_nxv2i1_nxv2i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0
@@ -81,15 +83,15 @@ entry:
<vscale x 2 x i1> %0,
<vscale x 2 x i1> %1,
<vscale x 2 x i1> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 2 x i1> %a
}
declare <vscale x 4 x i1> @llvm.riscv.vmsbf.nxv4i1(
<vscale x 4 x i1>,
- i32);
+ iXLen);
-define <vscale x 4 x i1> @intrinsic_vmsbf_m_nxv4i1(<vscale x 4 x i1> %0, i32 %1) nounwind {
+define <vscale x 4 x i1> @intrinsic_vmsbf_m_nxv4i1(<vscale x 4 x i1> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vmsbf_m_nxv4i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
@@ -99,7 +101,7 @@ define <vscale x 4 x i1> @intrinsic_vmsbf_m_nxv4i1(<vscale x 4 x i1> %0, i32 %1)
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsbf.nxv4i1(
<vscale x 4 x i1> %0,
- i32 %1)
+ iXLen %1)
ret <vscale x 4 x i1> %a
}
@@ -107,9 +109,9 @@ declare <vscale x 4 x i1> @llvm.riscv.vmsbf.mask.nxv4i1(
<vscale x 4 x i1>,
<vscale x 4 x i1>,
<vscale x 4 x i1>,
- i32);
+ iXLen);
-define <vscale x 4 x i1> @intrinsic_vmsbf_mask_m_nxv4i1_nxv4i1(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
+define <vscale x 4 x i1> @intrinsic_vmsbf_mask_m_nxv4i1_nxv4i1(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vmsbf_mask_m_nxv4i1_nxv4i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0
@@ -123,15 +125,15 @@ entry:
<vscale x 4 x i1> %0,
<vscale x 4 x i1> %1,
<vscale x 4 x i1> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 4 x i1> %a
}
declare <vscale x 8 x i1> @llvm.riscv.vmsbf.nxv8i1(
<vscale x 8 x i1>,
- i32);
+ iXLen);
-define <vscale x 8 x i1> @intrinsic_vmsbf_m_nxv8i1(<vscale x 8 x i1> %0, i32 %1) nounwind {
+define <vscale x 8 x i1> @intrinsic_vmsbf_m_nxv8i1(<vscale x 8 x i1> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vmsbf_m_nxv8i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
@@ -141,7 +143,7 @@ define <vscale x 8 x i1> @intrinsic_vmsbf_m_nxv8i1(<vscale x 8 x i1> %0, i32 %1)
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsbf.nxv8i1(
<vscale x 8 x i1> %0,
- i32 %1)
+ iXLen %1)
ret <vscale x 8 x i1> %a
}
@@ -149,9 +151,9 @@ declare <vscale x 8 x i1> @llvm.riscv.vmsbf.mask.nxv8i1(
<vscale x 8 x i1>,
<vscale x 8 x i1>,
<vscale x 8 x i1>,
- i32);
+ iXLen);
-define <vscale x 8 x i1> @intrinsic_vmsbf_mask_m_nxv8i1_nxv8i1(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
+define <vscale x 8 x i1> @intrinsic_vmsbf_mask_m_nxv8i1_nxv8i1(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vmsbf_mask_m_nxv8i1_nxv8i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0
@@ -165,15 +167,15 @@ entry:
<vscale x 8 x i1> %0,
<vscale x 8 x i1> %1,
<vscale x 8 x i1> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 8 x i1> %a
}
declare <vscale x 16 x i1> @llvm.riscv.vmsbf.nxv16i1(
<vscale x 16 x i1>,
- i32);
+ iXLen);
-define <vscale x 16 x i1> @intrinsic_vmsbf_m_nxv16i1(<vscale x 16 x i1> %0, i32 %1) nounwind {
+define <vscale x 16 x i1> @intrinsic_vmsbf_m_nxv16i1(<vscale x 16 x i1> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vmsbf_m_nxv16i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
@@ -183,7 +185,7 @@ define <vscale x 16 x i1> @intrinsic_vmsbf_m_nxv16i1(<vscale x 16 x i1> %0, i32
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsbf.nxv16i1(
<vscale x 16 x i1> %0,
- i32 %1)
+ iXLen %1)
ret <vscale x 16 x i1> %a
}
@@ -191,9 +193,9 @@ declare <vscale x 16 x i1> @llvm.riscv.vmsbf.mask.nxv16i1(
<vscale x 16 x i1>,
<vscale x 16 x i1>,
<vscale x 16 x i1>,
- i32);
+ iXLen);
-define <vscale x 16 x i1> @intrinsic_vmsbf_mask_m_nxv16i1_nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, <vscale x 16 x i1> %2, i32 %3) nounwind {
+define <vscale x 16 x i1> @intrinsic_vmsbf_mask_m_nxv16i1_nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, <vscale x 16 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vmsbf_mask_m_nxv16i1_nxv16i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0
@@ -207,15 +209,15 @@ entry:
<vscale x 16 x i1> %0,
<vscale x 16 x i1> %1,
<vscale x 16 x i1> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 16 x i1> %a
}
declare <vscale x 32 x i1> @llvm.riscv.vmsbf.nxv32i1(
<vscale x 32 x i1>,
- i32);
+ iXLen);
-define <vscale x 32 x i1> @intrinsic_vmsbf_m_nxv32i1(<vscale x 32 x i1> %0, i32 %1) nounwind {
+define <vscale x 32 x i1> @intrinsic_vmsbf_m_nxv32i1(<vscale x 32 x i1> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vmsbf_m_nxv32i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
@@ -225,7 +227,7 @@ define <vscale x 32 x i1> @intrinsic_vmsbf_m_nxv32i1(<vscale x 32 x i1> %0, i32
entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmsbf.nxv32i1(
<vscale x 32 x i1> %0,
- i32 %1)
+ iXLen %1)
ret <vscale x 32 x i1> %a
}
@@ -233,9 +235,9 @@ declare <vscale x 32 x i1> @llvm.riscv.vmsbf.mask.nxv32i1(
<vscale x 32 x i1>,
<vscale x 32 x i1>,
<vscale x 32 x i1>,
- i32);
+ iXLen);
-define <vscale x 32 x i1> @intrinsic_vmsbf_mask_m_nxv32i1_nxv32i1(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, <vscale x 32 x i1> %2, i32 %3) nounwind {
+define <vscale x 32 x i1> @intrinsic_vmsbf_mask_m_nxv32i1_nxv32i1(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, <vscale x 32 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vmsbf_mask_m_nxv32i1_nxv32i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0
@@ -249,15 +251,15 @@ entry:
<vscale x 32 x i1> %0,
<vscale x 32 x i1> %1,
<vscale x 32 x i1> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 32 x i1> %a
}
declare <vscale x 64 x i1> @llvm.riscv.vmsbf.nxv64i1(
<vscale x 64 x i1>,
- i32);
+ iXLen);
-define <vscale x 64 x i1> @intrinsic_vmsbf_m_nxv64i1(<vscale x 64 x i1> %0, i32 %1) nounwind {
+define <vscale x 64 x i1> @intrinsic_vmsbf_m_nxv64i1(<vscale x 64 x i1> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vmsbf_m_nxv64i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, mu
@@ -267,7 +269,7 @@ define <vscale x 64 x i1> @intrinsic_vmsbf_m_nxv64i1(<vscale x 64 x i1> %0, i32
entry:
%a = call <vscale x 64 x i1> @llvm.riscv.vmsbf.nxv64i1(
<vscale x 64 x i1> %0,
- i32 %1)
+ iXLen %1)
ret <vscale x 64 x i1> %a
}
@@ -275,9 +277,9 @@ declare <vscale x 64 x i1> @llvm.riscv.vmsbf.mask.nxv64i1(
<vscale x 64 x i1>,
<vscale x 64 x i1>,
<vscale x 64 x i1>,
- i32);
+ iXLen);
-define <vscale x 64 x i1> @intrinsic_vmsbf_mask_m_nxv64i1_nxv64i1(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, <vscale x 64 x i1> %2, i32 %3) nounwind {
+define <vscale x 64 x i1> @intrinsic_vmsbf_mask_m_nxv64i1_nxv64i1(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, <vscale x 64 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vmsbf_mask_m_nxv64i1_nxv64i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0
@@ -291,6 +293,6 @@ entry:
<vscale x 64 x i1> %0,
<vscale x 64 x i1> %1,
<vscale x 64 x i1> %2,
- i32 %3)
+ iXLen %3)
ret <vscale x 64 x i1> %a
}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmul-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vmul-rv64.ll
deleted file mode 100644
index 28c2d775e1bc7..0000000000000
--- a/llvm/test/CodeGen/RISCV/rvv/vmul-rv64.ll
+++ /dev/null
@@ -1,2074 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs \
-; RUN: < %s | FileCheck %s
-declare <vscale x 1 x i8> @llvm.riscv.vmul.nxv1i8.nxv1i8(
- <vscale x 1 x i8>,
- <vscale x 1 x i8>,
- <vscale x 1 x i8>,
- i64);
-
-define <vscale x 1 x i8> @intrinsic_vmul_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmul_vv_nxv1i8_nxv1i8_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
-; CHECK-NEXT: vmul.vv v8, v8, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i8> @llvm.riscv.vmul.nxv1i8.nxv1i8(
- <vscale x 1 x i8> undef,
- <vscale x 1 x i8> %0,
- <vscale x 1 x i8> %1,
- i64 %2)
-
- ret <vscale x 1 x i8> %a
-}
-
-declare <vscale x 1 x i8> @llvm.riscv.vmul.mask.nxv1i8.nxv1i8(
- <vscale x 1 x i8>,
- <vscale x 1 x i8>,
- <vscale x 1 x i8>,
- <vscale x 1 x i1>,
- i64,
- i64);
-
-define <vscale x 1 x i8> @intrinsic_vmul_mask_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv1i8_nxv1i8_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
-; CHECK-NEXT: vmul.vv v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i8> @llvm.riscv.vmul.mask.nxv1i8.nxv1i8(
- <vscale x 1 x i8> %0,
- <vscale x 1 x i8> %1,
- <vscale x 1 x i8> %2,
- <vscale x 1 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 1 x i8> %a
-}
-
-declare <vscale x 2 x i8> @llvm.riscv.vmul.nxv2i8.nxv2i8(
- <vscale x 2 x i8>,
- <vscale x 2 x i8>,
- <vscale x 2 x i8>,
- i64);
-
-define <vscale x 2 x i8> @intrinsic_vmul_vv_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmul_vv_nxv2i8_nxv2i8_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
-; CHECK-NEXT: vmul.vv v8, v8, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i8> @llvm.riscv.vmul.nxv2i8.nxv2i8(
- <vscale x 2 x i8> undef,
- <vscale x 2 x i8> %0,
- <vscale x 2 x i8> %1,
- i64 %2)
-
- ret <vscale x 2 x i8> %a
-}
-
-declare <vscale x 2 x i8> @llvm.riscv.vmul.mask.nxv2i8.nxv2i8(
- <vscale x 2 x i8>,
- <vscale x 2 x i8>,
- <vscale x 2 x i8>,
- <vscale x 2 x i1>,
- i64,
- i64);
-
-define <vscale x 2 x i8> @intrinsic_vmul_mask_vv_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv2i8_nxv2i8_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
-; CHECK-NEXT: vmul.vv v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i8> @llvm.riscv.vmul.mask.nxv2i8.nxv2i8(
- <vscale x 2 x i8> %0,
- <vscale x 2 x i8> %1,
- <vscale x 2 x i8> %2,
- <vscale x 2 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 2 x i8> %a
-}
-
-declare <vscale x 4 x i8> @llvm.riscv.vmul.nxv4i8.nxv4i8(
- <vscale x 4 x i8>,
- <vscale x 4 x i8>,
- <vscale x 4 x i8>,
- i64);
-
-define <vscale x 4 x i8> @intrinsic_vmul_vv_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmul_vv_nxv4i8_nxv4i8_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
-; CHECK-NEXT: vmul.vv v8, v8, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i8> @llvm.riscv.vmul.nxv4i8.nxv4i8(
- <vscale x 4 x i8> undef,
- <vscale x 4 x i8> %0,
- <vscale x 4 x i8> %1,
- i64 %2)
-
- ret <vscale x 4 x i8> %a
-}
-
-declare <vscale x 4 x i8> @llvm.riscv.vmul.mask.nxv4i8.nxv4i8(
- <vscale x 4 x i8>,
- <vscale x 4 x i8>,
- <vscale x 4 x i8>,
- <vscale x 4 x i1>,
- i64,
- i64);
-
-define <vscale x 4 x i8> @intrinsic_vmul_mask_vv_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv4i8_nxv4i8_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
-; CHECK-NEXT: vmul.vv v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i8> @llvm.riscv.vmul.mask.nxv4i8.nxv4i8(
- <vscale x 4 x i8> %0,
- <vscale x 4 x i8> %1,
- <vscale x 4 x i8> %2,
- <vscale x 4 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 4 x i8> %a
-}
-
-declare <vscale x 8 x i8> @llvm.riscv.vmul.nxv8i8.nxv8i8(
- <vscale x 8 x i8>,
- <vscale x 8 x i8>,
- <vscale x 8 x i8>,
- i64);
-
-define <vscale x 8 x i8> @intrinsic_vmul_vv_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmul_vv_nxv8i8_nxv8i8_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
-; CHECK-NEXT: vmul.vv v8, v8, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i8> @llvm.riscv.vmul.nxv8i8.nxv8i8(
- <vscale x 8 x i8> undef,
- <vscale x 8 x i8> %0,
- <vscale x 8 x i8> %1,
- i64 %2)
-
- ret <vscale x 8 x i8> %a
-}
-
-declare <vscale x 8 x i8> @llvm.riscv.vmul.mask.nxv8i8.nxv8i8(
- <vscale x 8 x i8>,
- <vscale x 8 x i8>,
- <vscale x 8 x i8>,
- <vscale x 8 x i1>,
- i64,
- i64);
-
-define <vscale x 8 x i8> @intrinsic_vmul_mask_vv_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv8i8_nxv8i8_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
-; CHECK-NEXT: vmul.vv v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i8> @llvm.riscv.vmul.mask.nxv8i8.nxv8i8(
- <vscale x 8 x i8> %0,
- <vscale x 8 x i8> %1,
- <vscale x 8 x i8> %2,
- <vscale x 8 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 8 x i8> %a
-}
-
-declare <vscale x 16 x i8> @llvm.riscv.vmul.nxv16i8.nxv16i8(
- <vscale x 16 x i8>,
- <vscale x 16 x i8>,
- <vscale x 16 x i8>,
- i64);
-
-define <vscale x 16 x i8> @intrinsic_vmul_vv_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmul_vv_nxv16i8_nxv16i8_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
-; CHECK-NEXT: vmul.vv v8, v8, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i8> @llvm.riscv.vmul.nxv16i8.nxv16i8(
- <vscale x 16 x i8> undef,
- <vscale x 16 x i8> %0,
- <vscale x 16 x i8> %1,
- i64 %2)
-
- ret <vscale x 16 x i8> %a
-}
-
-declare <vscale x 16 x i8> @llvm.riscv.vmul.mask.nxv16i8.nxv16i8(
- <vscale x 16 x i8>,
- <vscale x 16 x i8>,
- <vscale x 16 x i8>,
- <vscale x 16 x i1>,
- i64,
- i64);
-
-define <vscale x 16 x i8> @intrinsic_vmul_mask_vv_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv16i8_nxv16i8_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
-; CHECK-NEXT: vmul.vv v8, v10, v12, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i8> @llvm.riscv.vmul.mask.nxv16i8.nxv16i8(
- <vscale x 16 x i8> %0,
- <vscale x 16 x i8> %1,
- <vscale x 16 x i8> %2,
- <vscale x 16 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 16 x i8> %a
-}
-
-declare <vscale x 32 x i8> @llvm.riscv.vmul.nxv32i8.nxv32i8(
- <vscale x 32 x i8>,
- <vscale x 32 x i8>,
- <vscale x 32 x i8>,
- i64);
-
-define <vscale x 32 x i8> @intrinsic_vmul_vv_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmul_vv_nxv32i8_nxv32i8_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
-; CHECK-NEXT: vmul.vv v8, v8, v12
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 32 x i8> @llvm.riscv.vmul.nxv32i8.nxv32i8(
- <vscale x 32 x i8> undef,
- <vscale x 32 x i8> %0,
- <vscale x 32 x i8> %1,
- i64 %2)
-
- ret <vscale x 32 x i8> %a
-}
-
-declare <vscale x 32 x i8> @llvm.riscv.vmul.mask.nxv32i8.nxv32i8(
- <vscale x 32 x i8>,
- <vscale x 32 x i8>,
- <vscale x 32 x i8>,
- <vscale x 32 x i1>,
- i64,
- i64);
-
-define <vscale x 32 x i8> @intrinsic_vmul_mask_vv_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv32i8_nxv32i8_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
-; CHECK-NEXT: vmul.vv v8, v12, v16, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 32 x i8> @llvm.riscv.vmul.mask.nxv32i8.nxv32i8(
- <vscale x 32 x i8> %0,
- <vscale x 32 x i8> %1,
- <vscale x 32 x i8> %2,
- <vscale x 32 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 32 x i8> %a
-}
-
-declare <vscale x 64 x i8> @llvm.riscv.vmul.nxv64i8.nxv64i8(
- <vscale x 64 x i8>,
- <vscale x 64 x i8>,
- <vscale x 64 x i8>,
- i64);
-
-define <vscale x 64 x i8> @intrinsic_vmul_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmul_vv_nxv64i8_nxv64i8_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, mu
-; CHECK-NEXT: vmul.vv v8, v8, v16
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 64 x i8> @llvm.riscv.vmul.nxv64i8.nxv64i8(
- <vscale x 64 x i8> undef,
- <vscale x 64 x i8> %0,
- <vscale x 64 x i8> %1,
- i64 %2)
-
- ret <vscale x 64 x i8> %a
-}
-
-declare <vscale x 64 x i8> @llvm.riscv.vmul.mask.nxv64i8.nxv64i8(
- <vscale x 64 x i8>,
- <vscale x 64 x i8>,
- <vscale x 64 x i8>,
- <vscale x 64 x i1>,
- i64,
- i64);
-
-define <vscale x 64 x i8> @intrinsic_vmul_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv64i8_nxv64i8_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vl8r.v v24, (a0)
-; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu
-; CHECK-NEXT: vmul.vv v8, v16, v24, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 64 x i8> @llvm.riscv.vmul.mask.nxv64i8.nxv64i8(
- <vscale x 64 x i8> %0,
- <vscale x 64 x i8> %1,
- <vscale x 64 x i8> %2,
- <vscale x 64 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 64 x i8> %a
-}
-
-declare <vscale x 1 x i16> @llvm.riscv.vmul.nxv1i16.nxv1i16(
- <vscale x 1 x i16>,
- <vscale x 1 x i16>,
- <vscale x 1 x i16>,
- i64);
-
-define <vscale x 1 x i16> @intrinsic_vmul_vv_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmul_vv_nxv1i16_nxv1i16_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vmul.vv v8, v8, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i16> @llvm.riscv.vmul.nxv1i16.nxv1i16(
- <vscale x 1 x i16> undef,
- <vscale x 1 x i16> %0,
- <vscale x 1 x i16> %1,
- i64 %2)
-
- ret <vscale x 1 x i16> %a
-}
-
-declare <vscale x 1 x i16> @llvm.riscv.vmul.mask.nxv1i16.nxv1i16(
- <vscale x 1 x i16>,
- <vscale x 1 x i16>,
- <vscale x 1 x i16>,
- <vscale x 1 x i1>,
- i64,
- i64);
-
-define <vscale x 1 x i16> @intrinsic_vmul_mask_vv_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv1i16_nxv1i16_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vmul.vv v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i16> @llvm.riscv.vmul.mask.nxv1i16.nxv1i16(
- <vscale x 1 x i16> %0,
- <vscale x 1 x i16> %1,
- <vscale x 1 x i16> %2,
- <vscale x 1 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 1 x i16> %a
-}
-
-declare <vscale x 2 x i16> @llvm.riscv.vmul.nxv2i16.nxv2i16(
- <vscale x 2 x i16>,
- <vscale x 2 x i16>,
- <vscale x 2 x i16>,
- i64);
-
-define <vscale x 2 x i16> @intrinsic_vmul_vv_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmul_vv_nxv2i16_nxv2i16_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vmul.vv v8, v8, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i16> @llvm.riscv.vmul.nxv2i16.nxv2i16(
- <vscale x 2 x i16> undef,
- <vscale x 2 x i16> %0,
- <vscale x 2 x i16> %1,
- i64 %2)
-
- ret <vscale x 2 x i16> %a
-}
-
-declare <vscale x 2 x i16> @llvm.riscv.vmul.mask.nxv2i16.nxv2i16(
- <vscale x 2 x i16>,
- <vscale x 2 x i16>,
- <vscale x 2 x i16>,
- <vscale x 2 x i1>,
- i64,
- i64);
-
-define <vscale x 2 x i16> @intrinsic_vmul_mask_vv_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv2i16_nxv2i16_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vmul.vv v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i16> @llvm.riscv.vmul.mask.nxv2i16.nxv2i16(
- <vscale x 2 x i16> %0,
- <vscale x 2 x i16> %1,
- <vscale x 2 x i16> %2,
- <vscale x 2 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 2 x i16> %a
-}
-
-declare <vscale x 4 x i16> @llvm.riscv.vmul.nxv4i16.nxv4i16(
- <vscale x 4 x i16>,
- <vscale x 4 x i16>,
- <vscale x 4 x i16>,
- i64);
-
-define <vscale x 4 x i16> @intrinsic_vmul_vv_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmul_vv_nxv4i16_nxv4i16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vmul.vv v8, v8, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i16> @llvm.riscv.vmul.nxv4i16.nxv4i16(
- <vscale x 4 x i16> undef,
- <vscale x 4 x i16> %0,
- <vscale x 4 x i16> %1,
- i64 %2)
-
- ret <vscale x 4 x i16> %a
-}
-
-declare <vscale x 4 x i16> @llvm.riscv.vmul.mask.nxv4i16.nxv4i16(
- <vscale x 4 x i16>,
- <vscale x 4 x i16>,
- <vscale x 4 x i16>,
- <vscale x 4 x i1>,
- i64,
- i64);
-
-define <vscale x 4 x i16> @intrinsic_vmul_mask_vv_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv4i16_nxv4i16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vmul.vv v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i16> @llvm.riscv.vmul.mask.nxv4i16.nxv4i16(
- <vscale x 4 x i16> %0,
- <vscale x 4 x i16> %1,
- <vscale x 4 x i16> %2,
- <vscale x 4 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 4 x i16> %a
-}
-
-declare <vscale x 8 x i16> @llvm.riscv.vmul.nxv8i16.nxv8i16(
- <vscale x 8 x i16>,
- <vscale x 8 x i16>,
- <vscale x 8 x i16>,
- i64);
-
-define <vscale x 8 x i16> @intrinsic_vmul_vv_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmul_vv_nxv8i16_nxv8i16_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vmul.vv v8, v8, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i16> @llvm.riscv.vmul.nxv8i16.nxv8i16(
- <vscale x 8 x i16> undef,
- <vscale x 8 x i16> %0,
- <vscale x 8 x i16> %1,
- i64 %2)
-
- ret <vscale x 8 x i16> %a
-}
-
-declare <vscale x 8 x i16> @llvm.riscv.vmul.mask.nxv8i16.nxv8i16(
- <vscale x 8 x i16>,
- <vscale x 8 x i16>,
- <vscale x 8 x i16>,
- <vscale x 8 x i1>,
- i64,
- i64);
-
-define <vscale x 8 x i16> @intrinsic_vmul_mask_vv_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv8i16_nxv8i16_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vmul.vv v8, v10, v12, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i16> @llvm.riscv.vmul.mask.nxv8i16.nxv8i16(
- <vscale x 8 x i16> %0,
- <vscale x 8 x i16> %1,
- <vscale x 8 x i16> %2,
- <vscale x 8 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 8 x i16> %a
-}
-
-declare <vscale x 16 x i16> @llvm.riscv.vmul.nxv16i16.nxv16i16(
- <vscale x 16 x i16>,
- <vscale x 16 x i16>,
- <vscale x 16 x i16>,
- i64);
-
-define <vscale x 16 x i16> @intrinsic_vmul_vv_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmul_vv_nxv16i16_nxv16i16_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
-; CHECK-NEXT: vmul.vv v8, v8, v12
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i16> @llvm.riscv.vmul.nxv16i16.nxv16i16(
- <vscale x 16 x i16> undef,
- <vscale x 16 x i16> %0,
- <vscale x 16 x i16> %1,
- i64 %2)
-
- ret <vscale x 16 x i16> %a
-}
-
-declare <vscale x 16 x i16> @llvm.riscv.vmul.mask.nxv16i16.nxv16i16(
- <vscale x 16 x i16>,
- <vscale x 16 x i16>,
- <vscale x 16 x i16>,
- <vscale x 16 x i1>,
- i64,
- i64);
-
-define <vscale x 16 x i16> @intrinsic_vmul_mask_vv_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv16i16_nxv16i16_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
-; CHECK-NEXT: vmul.vv v8, v12, v16, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i16> @llvm.riscv.vmul.mask.nxv16i16.nxv16i16(
- <vscale x 16 x i16> %0,
- <vscale x 16 x i16> %1,
- <vscale x 16 x i16> %2,
- <vscale x 16 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 16 x i16> %a
-}
-
-declare <vscale x 32 x i16> @llvm.riscv.vmul.nxv32i16.nxv32i16(
- <vscale x 32 x i16>,
- <vscale x 32 x i16>,
- <vscale x 32 x i16>,
- i64);
-
-define <vscale x 32 x i16> @intrinsic_vmul_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmul_vv_nxv32i16_nxv32i16_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, mu
-; CHECK-NEXT: vmul.vv v8, v8, v16
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 32 x i16> @llvm.riscv.vmul.nxv32i16.nxv32i16(
- <vscale x 32 x i16> undef,
- <vscale x 32 x i16> %0,
- <vscale x 32 x i16> %1,
- i64 %2)
-
- ret <vscale x 32 x i16> %a
-}
-
-declare <vscale x 32 x i16> @llvm.riscv.vmul.mask.nxv32i16.nxv32i16(
- <vscale x 32 x i16>,
- <vscale x 32 x i16>,
- <vscale x 32 x i16>,
- <vscale x 32 x i1>,
- i64,
- i64);
-
-define <vscale x 32 x i16> @intrinsic_vmul_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv32i16_nxv32i16_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vl8re16.v v24, (a0)
-; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu
-; CHECK-NEXT: vmul.vv v8, v16, v24, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 32 x i16> @llvm.riscv.vmul.mask.nxv32i16.nxv32i16(
- <vscale x 32 x i16> %0,
- <vscale x 32 x i16> %1,
- <vscale x 32 x i16> %2,
- <vscale x 32 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 32 x i16> %a
-}
-
-declare <vscale x 1 x i32> @llvm.riscv.vmul.nxv1i32.nxv1i32(
- <vscale x 1 x i32>,
- <vscale x 1 x i32>,
- <vscale x 1 x i32>,
- i64);
-
-define <vscale x 1 x i32> @intrinsic_vmul_vv_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmul_vv_nxv1i32_nxv1i32_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vmul.vv v8, v8, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i32> @llvm.riscv.vmul.nxv1i32.nxv1i32(
- <vscale x 1 x i32> undef,
- <vscale x 1 x i32> %0,
- <vscale x 1 x i32> %1,
- i64 %2)
-
- ret <vscale x 1 x i32> %a
-}
-
-declare <vscale x 1 x i32> @llvm.riscv.vmul.mask.nxv1i32.nxv1i32(
- <vscale x 1 x i32>,
- <vscale x 1 x i32>,
- <vscale x 1 x i32>,
- <vscale x 1 x i1>,
- i64,
- i64);
-
-define <vscale x 1 x i32> @intrinsic_vmul_mask_vv_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv1i32_nxv1i32_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vmul.vv v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i32> @llvm.riscv.vmul.mask.nxv1i32.nxv1i32(
- <vscale x 1 x i32> %0,
- <vscale x 1 x i32> %1,
- <vscale x 1 x i32> %2,
- <vscale x 1 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 1 x i32> %a
-}
-
-declare <vscale x 2 x i32> @llvm.riscv.vmul.nxv2i32.nxv2i32(
- <vscale x 2 x i32>,
- <vscale x 2 x i32>,
- <vscale x 2 x i32>,
- i64);
-
-define <vscale x 2 x i32> @intrinsic_vmul_vv_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmul_vv_nxv2i32_nxv2i32_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vmul.vv v8, v8, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i32> @llvm.riscv.vmul.nxv2i32.nxv2i32(
- <vscale x 2 x i32> undef,
- <vscale x 2 x i32> %0,
- <vscale x 2 x i32> %1,
- i64 %2)
-
- ret <vscale x 2 x i32> %a
-}
-
-declare <vscale x 2 x i32> @llvm.riscv.vmul.mask.nxv2i32.nxv2i32(
- <vscale x 2 x i32>,
- <vscale x 2 x i32>,
- <vscale x 2 x i32>,
- <vscale x 2 x i1>,
- i64,
- i64);
-
-define <vscale x 2 x i32> @intrinsic_vmul_mask_vv_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv2i32_nxv2i32_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vmul.vv v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i32> @llvm.riscv.vmul.mask.nxv2i32.nxv2i32(
- <vscale x 2 x i32> %0,
- <vscale x 2 x i32> %1,
- <vscale x 2 x i32> %2,
- <vscale x 2 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 2 x i32> %a
-}
-
-declare <vscale x 4 x i32> @llvm.riscv.vmul.nxv4i32.nxv4i32(
- <vscale x 4 x i32>,
- <vscale x 4 x i32>,
- <vscale x 4 x i32>,
- i64);
-
-define <vscale x 4 x i32> @intrinsic_vmul_vv_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmul_vv_nxv4i32_nxv4i32_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vmul.vv v8, v8, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i32> @llvm.riscv.vmul.nxv4i32.nxv4i32(
- <vscale x 4 x i32> undef,
- <vscale x 4 x i32> %0,
- <vscale x 4 x i32> %1,
- i64 %2)
-
- ret <vscale x 4 x i32> %a
-}
-
-declare <vscale x 4 x i32> @llvm.riscv.vmul.mask.nxv4i32.nxv4i32(
- <vscale x 4 x i32>,
- <vscale x 4 x i32>,
- <vscale x 4 x i32>,
- <vscale x 4 x i1>,
- i64,
- i64);
-
-define <vscale x 4 x i32> @intrinsic_vmul_mask_vv_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv4i32_nxv4i32_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vmul.vv v8, v10, v12, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i32> @llvm.riscv.vmul.mask.nxv4i32.nxv4i32(
- <vscale x 4 x i32> %0,
- <vscale x 4 x i32> %1,
- <vscale x 4 x i32> %2,
- <vscale x 4 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 4 x i32> %a
-}
-
-declare <vscale x 8 x i32> @llvm.riscv.vmul.nxv8i32.nxv8i32(
- <vscale x 8 x i32>,
- <vscale x 8 x i32>,
- <vscale x 8 x i32>,
- i64);
-
-define <vscale x 8 x i32> @intrinsic_vmul_vv_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmul_vv_nxv8i32_nxv8i32_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
-; CHECK-NEXT: vmul.vv v8, v8, v12
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i32> @llvm.riscv.vmul.nxv8i32.nxv8i32(
- <vscale x 8 x i32> undef,
- <vscale x 8 x i32> %0,
- <vscale x 8 x i32> %1,
- i64 %2)
-
- ret <vscale x 8 x i32> %a
-}
-
-declare <vscale x 8 x i32> @llvm.riscv.vmul.mask.nxv8i32.nxv8i32(
- <vscale x 8 x i32>,
- <vscale x 8 x i32>,
- <vscale x 8 x i32>,
- <vscale x 8 x i1>,
- i64,
- i64);
-
-define <vscale x 8 x i32> @intrinsic_vmul_mask_vv_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv8i32_nxv8i32_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
-; CHECK-NEXT: vmul.vv v8, v12, v16, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i32> @llvm.riscv.vmul.mask.nxv8i32.nxv8i32(
- <vscale x 8 x i32> %0,
- <vscale x 8 x i32> %1,
- <vscale x 8 x i32> %2,
- <vscale x 8 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 8 x i32> %a
-}
-
-declare <vscale x 16 x i32> @llvm.riscv.vmul.nxv16i32.nxv16i32(
- <vscale x 16 x i32>,
- <vscale x 16 x i32>,
- <vscale x 16 x i32>,
- i64);
-
-define <vscale x 16 x i32> @intrinsic_vmul_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmul_vv_nxv16i32_nxv16i32_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu
-; CHECK-NEXT: vmul.vv v8, v8, v16
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i32> @llvm.riscv.vmul.nxv16i32.nxv16i32(
- <vscale x 16 x i32> undef,
- <vscale x 16 x i32> %0,
- <vscale x 16 x i32> %1,
- i64 %2)
-
- ret <vscale x 16 x i32> %a
-}
-
-declare <vscale x 16 x i32> @llvm.riscv.vmul.mask.nxv16i32.nxv16i32(
- <vscale x 16 x i32>,
- <vscale x 16 x i32>,
- <vscale x 16 x i32>,
- <vscale x 16 x i1>,
- i64,
- i64);
-
-define <vscale x 16 x i32> @intrinsic_vmul_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv16i32_nxv16i32_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vl8re32.v v24, (a0)
-; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu
-; CHECK-NEXT: vmul.vv v8, v16, v24, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i32> @llvm.riscv.vmul.mask.nxv16i32.nxv16i32(
- <vscale x 16 x i32> %0,
- <vscale x 16 x i32> %1,
- <vscale x 16 x i32> %2,
- <vscale x 16 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 16 x i32> %a
-}
-
-declare <vscale x 1 x i64> @llvm.riscv.vmul.nxv1i64.nxv1i64(
- <vscale x 1 x i64>,
- <vscale x 1 x i64>,
- <vscale x 1 x i64>,
- i64);
-
-define <vscale x 1 x i64> @intrinsic_vmul_vv_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmul_vv_nxv1i64_nxv1i64_nxv1i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
-; CHECK-NEXT: vmul.vv v8, v8, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i64> @llvm.riscv.vmul.nxv1i64.nxv1i64(
- <vscale x 1 x i64> undef,
- <vscale x 1 x i64> %0,
- <vscale x 1 x i64> %1,
- i64 %2)
-
- ret <vscale x 1 x i64> %a
-}
-
-declare <vscale x 1 x i64> @llvm.riscv.vmul.mask.nxv1i64.nxv1i64(
- <vscale x 1 x i64>,
- <vscale x 1 x i64>,
- <vscale x 1 x i64>,
- <vscale x 1 x i1>,
- i64,
- i64);
-
-define <vscale x 1 x i64> @intrinsic_vmul_mask_vv_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv1i64_nxv1i64_nxv1i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
-; CHECK-NEXT: vmul.vv v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i64> @llvm.riscv.vmul.mask.nxv1i64.nxv1i64(
- <vscale x 1 x i64> %0,
- <vscale x 1 x i64> %1,
- <vscale x 1 x i64> %2,
- <vscale x 1 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 1 x i64> %a
-}
-
-declare <vscale x 2 x i64> @llvm.riscv.vmul.nxv2i64.nxv2i64(
- <vscale x 2 x i64>,
- <vscale x 2 x i64>,
- <vscale x 2 x i64>,
- i64);
-
-define <vscale x 2 x i64> @intrinsic_vmul_vv_nxv2i64_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmul_vv_nxv2i64_nxv2i64_nxv2i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
-; CHECK-NEXT: vmul.vv v8, v8, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i64> @llvm.riscv.vmul.nxv2i64.nxv2i64(
- <vscale x 2 x i64> undef,
- <vscale x 2 x i64> %0,
- <vscale x 2 x i64> %1,
- i64 %2)
-
- ret <vscale x 2 x i64> %a
-}
-
-declare <vscale x 2 x i64> @llvm.riscv.vmul.mask.nxv2i64.nxv2i64(
- <vscale x 2 x i64>,
- <vscale x 2 x i64>,
- <vscale x 2 x i64>,
- <vscale x 2 x i1>,
- i64,
- i64);
-
-define <vscale x 2 x i64> @intrinsic_vmul_mask_vv_nxv2i64_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv2i64_nxv2i64_nxv2i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
-; CHECK-NEXT: vmul.vv v8, v10, v12, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i64> @llvm.riscv.vmul.mask.nxv2i64.nxv2i64(
- <vscale x 2 x i64> %0,
- <vscale x 2 x i64> %1,
- <vscale x 2 x i64> %2,
- <vscale x 2 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 2 x i64> %a
-}
-
-declare <vscale x 4 x i64> @llvm.riscv.vmul.nxv4i64.nxv4i64(
- <vscale x 4 x i64>,
- <vscale x 4 x i64>,
- <vscale x 4 x i64>,
- i64);
-
-define <vscale x 4 x i64> @intrinsic_vmul_vv_nxv4i64_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmul_vv_nxv4i64_nxv4i64_nxv4i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
-; CHECK-NEXT: vmul.vv v8, v8, v12
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i64> @llvm.riscv.vmul.nxv4i64.nxv4i64(
- <vscale x 4 x i64> undef,
- <vscale x 4 x i64> %0,
- <vscale x 4 x i64> %1,
- i64 %2)
-
- ret <vscale x 4 x i64> %a
-}
-
-declare <vscale x 4 x i64> @llvm.riscv.vmul.mask.nxv4i64.nxv4i64(
- <vscale x 4 x i64>,
- <vscale x 4 x i64>,
- <vscale x 4 x i64>,
- <vscale x 4 x i1>,
- i64,
- i64);
-
-define <vscale x 4 x i64> @intrinsic_vmul_mask_vv_nxv4i64_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv4i64_nxv4i64_nxv4i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
-; CHECK-NEXT: vmul.vv v8, v12, v16, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i64> @llvm.riscv.vmul.mask.nxv4i64.nxv4i64(
- <vscale x 4 x i64> %0,
- <vscale x 4 x i64> %1,
- <vscale x 4 x i64> %2,
- <vscale x 4 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 4 x i64> %a
-}
-
-declare <vscale x 8 x i64> @llvm.riscv.vmul.nxv8i64.nxv8i64(
- <vscale x 8 x i64>,
- <vscale x 8 x i64>,
- <vscale x 8 x i64>,
- i64);
-
-define <vscale x 8 x i64> @intrinsic_vmul_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmul_vv_nxv8i64_nxv8i64_nxv8i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu
-; CHECK-NEXT: vmul.vv v8, v8, v16
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i64> @llvm.riscv.vmul.nxv8i64.nxv8i64(
- <vscale x 8 x i64> undef,
- <vscale x 8 x i64> %0,
- <vscale x 8 x i64> %1,
- i64 %2)
-
- ret <vscale x 8 x i64> %a
-}
-
-declare <vscale x 8 x i64> @llvm.riscv.vmul.mask.nxv8i64.nxv8i64(
- <vscale x 8 x i64>,
- <vscale x 8 x i64>,
- <vscale x 8 x i64>,
- <vscale x 8 x i1>,
- i64,
- i64);
-
-define <vscale x 8 x i64> @intrinsic_vmul_mask_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv8i64_nxv8i64_nxv8i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vl8re64.v v24, (a0)
-; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu
-; CHECK-NEXT: vmul.vv v8, v16, v24, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i64> @llvm.riscv.vmul.mask.nxv8i64.nxv8i64(
- <vscale x 8 x i64> %0,
- <vscale x 8 x i64> %1,
- <vscale x 8 x i64> %2,
- <vscale x 8 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 8 x i64> %a
-}
-
-declare <vscale x 1 x i8> @llvm.riscv.vmul.nxv1i8.i8(
- <vscale x 1 x i8>,
- <vscale x 1 x i8>,
- i8,
- i64);
-
-define <vscale x 1 x i8> @intrinsic_vmul_vx_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, i8 %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmul_vx_nxv1i8_nxv1i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
-; CHECK-NEXT: vmul.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i8> @llvm.riscv.vmul.nxv1i8.i8(
- <vscale x 1 x i8> undef,
- <vscale x 1 x i8> %0,
- i8 %1,
- i64 %2)
-
- ret <vscale x 1 x i8> %a
-}
-
-declare <vscale x 1 x i8> @llvm.riscv.vmul.mask.nxv1i8.i8(
- <vscale x 1 x i8>,
- <vscale x 1 x i8>,
- i8,
- <vscale x 1 x i1>,
- i64,
- i64);
-
-define <vscale x 1 x i8> @intrinsic_vmul_mask_vx_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmul_mask_vx_nxv1i8_nxv1i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
-; CHECK-NEXT: vmul.vx v8, v9, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i8> @llvm.riscv.vmul.mask.nxv1i8.i8(
- <vscale x 1 x i8> %0,
- <vscale x 1 x i8> %1,
- i8 %2,
- <vscale x 1 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 1 x i8> %a
-}
-
-declare <vscale x 2 x i8> @llvm.riscv.vmul.nxv2i8.i8(
- <vscale x 2 x i8>,
- <vscale x 2 x i8>,
- i8,
- i64);
-
-define <vscale x 2 x i8> @intrinsic_vmul_vx_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, i8 %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmul_vx_nxv2i8_nxv2i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
-; CHECK-NEXT: vmul.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i8> @llvm.riscv.vmul.nxv2i8.i8(
- <vscale x 2 x i8> undef,
- <vscale x 2 x i8> %0,
- i8 %1,
- i64 %2)
-
- ret <vscale x 2 x i8> %a
-}
-
-declare <vscale x 2 x i8> @llvm.riscv.vmul.mask.nxv2i8.i8(
- <vscale x 2 x i8>,
- <vscale x 2 x i8>,
- i8,
- <vscale x 2 x i1>,
- i64,
- i64);
-
-define <vscale x 2 x i8> @intrinsic_vmul_mask_vx_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmul_mask_vx_nxv2i8_nxv2i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
-; CHECK-NEXT: vmul.vx v8, v9, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i8> @llvm.riscv.vmul.mask.nxv2i8.i8(
- <vscale x 2 x i8> %0,
- <vscale x 2 x i8> %1,
- i8 %2,
- <vscale x 2 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 2 x i8> %a
-}
-
-declare <vscale x 4 x i8> @llvm.riscv.vmul.nxv4i8.i8(
- <vscale x 4 x i8>,
- <vscale x 4 x i8>,
- i8,
- i64);
-
-define <vscale x 4 x i8> @intrinsic_vmul_vx_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, i8 %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmul_vx_nxv4i8_nxv4i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
-; CHECK-NEXT: vmul.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i8> @llvm.riscv.vmul.nxv4i8.i8(
- <vscale x 4 x i8> undef,
- <vscale x 4 x i8> %0,
- i8 %1,
- i64 %2)
-
- ret <vscale x 4 x i8> %a
-}
-
-declare <vscale x 4 x i8> @llvm.riscv.vmul.mask.nxv4i8.i8(
- <vscale x 4 x i8>,
- <vscale x 4 x i8>,
- i8,
- <vscale x 4 x i1>,
- i64,
- i64);
-
-define <vscale x 4 x i8> @intrinsic_vmul_mask_vx_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmul_mask_vx_nxv4i8_nxv4i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
-; CHECK-NEXT: vmul.vx v8, v9, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i8> @llvm.riscv.vmul.mask.nxv4i8.i8(
- <vscale x 4 x i8> %0,
- <vscale x 4 x i8> %1,
- i8 %2,
- <vscale x 4 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 4 x i8> %a
-}
-
-declare <vscale x 8 x i8> @llvm.riscv.vmul.nxv8i8.i8(
- <vscale x 8 x i8>,
- <vscale x 8 x i8>,
- i8,
- i64);
-
-define <vscale x 8 x i8> @intrinsic_vmul_vx_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, i8 %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmul_vx_nxv8i8_nxv8i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
-; CHECK-NEXT: vmul.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i8> @llvm.riscv.vmul.nxv8i8.i8(
- <vscale x 8 x i8> undef,
- <vscale x 8 x i8> %0,
- i8 %1,
- i64 %2)
-
- ret <vscale x 8 x i8> %a
-}
-
-declare <vscale x 8 x i8> @llvm.riscv.vmul.mask.nxv8i8.i8(
- <vscale x 8 x i8>,
- <vscale x 8 x i8>,
- i8,
- <vscale x 8 x i1>,
- i64,
- i64);
-
-define <vscale x 8 x i8> @intrinsic_vmul_mask_vx_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmul_mask_vx_nxv8i8_nxv8i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
-; CHECK-NEXT: vmul.vx v8, v9, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i8> @llvm.riscv.vmul.mask.nxv8i8.i8(
- <vscale x 8 x i8> %0,
- <vscale x 8 x i8> %1,
- i8 %2,
- <vscale x 8 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 8 x i8> %a
-}
-
-declare <vscale x 16 x i8> @llvm.riscv.vmul.nxv16i8.i8(
- <vscale x 16 x i8>,
- <vscale x 16 x i8>,
- i8,
- i64);
-
-define <vscale x 16 x i8> @intrinsic_vmul_vx_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, i8 %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmul_vx_nxv16i8_nxv16i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
-; CHECK-NEXT: vmul.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i8> @llvm.riscv.vmul.nxv16i8.i8(
- <vscale x 16 x i8> undef,
- <vscale x 16 x i8> %0,
- i8 %1,
- i64 %2)
-
- ret <vscale x 16 x i8> %a
-}
-
-declare <vscale x 16 x i8> @llvm.riscv.vmul.mask.nxv16i8.i8(
- <vscale x 16 x i8>,
- <vscale x 16 x i8>,
- i8,
- <vscale x 16 x i1>,
- i64,
- i64);
-
-define <vscale x 16 x i8> @intrinsic_vmul_mask_vx_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmul_mask_vx_nxv16i8_nxv16i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
-; CHECK-NEXT: vmul.vx v8, v10, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i8> @llvm.riscv.vmul.mask.nxv16i8.i8(
- <vscale x 16 x i8> %0,
- <vscale x 16 x i8> %1,
- i8 %2,
- <vscale x 16 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 16 x i8> %a
-}
-
-declare <vscale x 32 x i8> @llvm.riscv.vmul.nxv32i8.i8(
- <vscale x 32 x i8>,
- <vscale x 32 x i8>,
- i8,
- i64);
-
-define <vscale x 32 x i8> @intrinsic_vmul_vx_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, i8 %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmul_vx_nxv32i8_nxv32i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
-; CHECK-NEXT: vmul.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 32 x i8> @llvm.riscv.vmul.nxv32i8.i8(
- <vscale x 32 x i8> undef,
- <vscale x 32 x i8> %0,
- i8 %1,
- i64 %2)
-
- ret <vscale x 32 x i8> %a
-}
-
-declare <vscale x 32 x i8> @llvm.riscv.vmul.mask.nxv32i8.i8(
- <vscale x 32 x i8>,
- <vscale x 32 x i8>,
- i8,
- <vscale x 32 x i1>,
- i64,
- i64);
-
-define <vscale x 32 x i8> @intrinsic_vmul_mask_vx_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmul_mask_vx_nxv32i8_nxv32i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
-; CHECK-NEXT: vmul.vx v8, v12, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 32 x i8> @llvm.riscv.vmul.mask.nxv32i8.i8(
- <vscale x 32 x i8> %0,
- <vscale x 32 x i8> %1,
- i8 %2,
- <vscale x 32 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 32 x i8> %a
-}
-
-declare <vscale x 64 x i8> @llvm.riscv.vmul.nxv64i8.i8(
- <vscale x 64 x i8>,
- <vscale x 64 x i8>,
- i8,
- i64);
-
-define <vscale x 64 x i8> @intrinsic_vmul_vx_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, i8 %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmul_vx_nxv64i8_nxv64i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu
-; CHECK-NEXT: vmul.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 64 x i8> @llvm.riscv.vmul.nxv64i8.i8(
- <vscale x 64 x i8> undef,
- <vscale x 64 x i8> %0,
- i8 %1,
- i64 %2)
-
- ret <vscale x 64 x i8> %a
-}
-
-declare <vscale x 64 x i8> @llvm.riscv.vmul.mask.nxv64i8.i8(
- <vscale x 64 x i8>,
- <vscale x 64 x i8>,
- i8,
- <vscale x 64 x i1>,
- i64,
- i64);
-
-define <vscale x 64 x i8> @intrinsic_vmul_mask_vx_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i8 %2, <vscale x 64 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmul_mask_vx_nxv64i8_nxv64i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu
-; CHECK-NEXT: vmul.vx v8, v16, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 64 x i8> @llvm.riscv.vmul.mask.nxv64i8.i8(
- <vscale x 64 x i8> %0,
- <vscale x 64 x i8> %1,
- i8 %2,
- <vscale x 64 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 64 x i8> %a
-}
-
-declare <vscale x 1 x i16> @llvm.riscv.vmul.nxv1i16.i16(
- <vscale x 1 x i16>,
- <vscale x 1 x i16>,
- i16,
- i64);
-
-define <vscale x 1 x i16> @intrinsic_vmul_vx_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, i16 %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmul_vx_nxv1i16_nxv1i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
-; CHECK-NEXT: vmul.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i16> @llvm.riscv.vmul.nxv1i16.i16(
- <vscale x 1 x i16> undef,
- <vscale x 1 x i16> %0,
- i16 %1,
- i64 %2)
-
- ret <vscale x 1 x i16> %a
-}
-
-declare <vscale x 1 x i16> @llvm.riscv.vmul.mask.nxv1i16.i16(
- <vscale x 1 x i16>,
- <vscale x 1 x i16>,
- i16,
- <vscale x 1 x i1>,
- i64,
- i64);
-
-define <vscale x 1 x i16> @intrinsic_vmul_mask_vx_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmul_mask_vx_nxv1i16_nxv1i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
-; CHECK-NEXT: vmul.vx v8, v9, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i16> @llvm.riscv.vmul.mask.nxv1i16.i16(
- <vscale x 1 x i16> %0,
- <vscale x 1 x i16> %1,
- i16 %2,
- <vscale x 1 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 1 x i16> %a
-}
-
-declare <vscale x 2 x i16> @llvm.riscv.vmul.nxv2i16.i16(
- <vscale x 2 x i16>,
- <vscale x 2 x i16>,
- i16,
- i64);
-
-define <vscale x 2 x i16> @intrinsic_vmul_vx_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, i16 %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmul_vx_nxv2i16_nxv2i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
-; CHECK-NEXT: vmul.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i16> @llvm.riscv.vmul.nxv2i16.i16(
- <vscale x 2 x i16> undef,
- <vscale x 2 x i16> %0,
- i16 %1,
- i64 %2)
-
- ret <vscale x 2 x i16> %a
-}
-
-declare <vscale x 2 x i16> @llvm.riscv.vmul.mask.nxv2i16.i16(
- <vscale x 2 x i16>,
- <vscale x 2 x i16>,
- i16,
- <vscale x 2 x i1>,
- i64,
- i64);
-
-define <vscale x 2 x i16> @intrinsic_vmul_mask_vx_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmul_mask_vx_nxv2i16_nxv2i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
-; CHECK-NEXT: vmul.vx v8, v9, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i16> @llvm.riscv.vmul.mask.nxv2i16.i16(
- <vscale x 2 x i16> %0,
- <vscale x 2 x i16> %1,
- i16 %2,
- <vscale x 2 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 2 x i16> %a
-}
-
-declare <vscale x 4 x i16> @llvm.riscv.vmul.nxv4i16.i16(
- <vscale x 4 x i16>,
- <vscale x 4 x i16>,
- i16,
- i64);
-
-define <vscale x 4 x i16> @intrinsic_vmul_vx_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, i16 %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmul_vx_nxv4i16_nxv4i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
-; CHECK-NEXT: vmul.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i16> @llvm.riscv.vmul.nxv4i16.i16(
- <vscale x 4 x i16> undef,
- <vscale x 4 x i16> %0,
- i16 %1,
- i64 %2)
-
- ret <vscale x 4 x i16> %a
-}
-
-declare <vscale x 4 x i16> @llvm.riscv.vmul.mask.nxv4i16.i16(
- <vscale x 4 x i16>,
- <vscale x 4 x i16>,
- i16,
- <vscale x 4 x i1>,
- i64,
- i64);
-
-define <vscale x 4 x i16> @intrinsic_vmul_mask_vx_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmul_mask_vx_nxv4i16_nxv4i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
-; CHECK-NEXT: vmul.vx v8, v9, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i16> @llvm.riscv.vmul.mask.nxv4i16.i16(
- <vscale x 4 x i16> %0,
- <vscale x 4 x i16> %1,
- i16 %2,
- <vscale x 4 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 4 x i16> %a
-}
-
-declare <vscale x 8 x i16> @llvm.riscv.vmul.nxv8i16.i16(
- <vscale x 8 x i16>,
- <vscale x 8 x i16>,
- i16,
- i64);
-
-define <vscale x 8 x i16> @intrinsic_vmul_vx_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, i16 %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmul_vx_nxv8i16_nxv8i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
-; CHECK-NEXT: vmul.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i16> @llvm.riscv.vmul.nxv8i16.i16(
- <vscale x 8 x i16> undef,
- <vscale x 8 x i16> %0,
- i16 %1,
- i64 %2)
-
- ret <vscale x 8 x i16> %a
-}
-
-declare <vscale x 8 x i16> @llvm.riscv.vmul.mask.nxv8i16.i16(
- <vscale x 8 x i16>,
- <vscale x 8 x i16>,
- i16,
- <vscale x 8 x i1>,
- i64,
- i64);
-
-define <vscale x 8 x i16> @intrinsic_vmul_mask_vx_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmul_mask_vx_nxv8i16_nxv8i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
-; CHECK-NEXT: vmul.vx v8, v10, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i16> @llvm.riscv.vmul.mask.nxv8i16.i16(
- <vscale x 8 x i16> %0,
- <vscale x 8 x i16> %1,
- i16 %2,
- <vscale x 8 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 8 x i16> %a
-}
-
-declare <vscale x 16 x i16> @llvm.riscv.vmul.nxv16i16.i16(
- <vscale x 16 x i16>,
- <vscale x 16 x i16>,
- i16,
- i64);
-
-define <vscale x 16 x i16> @intrinsic_vmul_vx_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, i16 %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmul_vx_nxv16i16_nxv16i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
-; CHECK-NEXT: vmul.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i16> @llvm.riscv.vmul.nxv16i16.i16(
- <vscale x 16 x i16> undef,
- <vscale x 16 x i16> %0,
- i16 %1,
- i64 %2)
-
- ret <vscale x 16 x i16> %a
-}
-
-declare <vscale x 16 x i16> @llvm.riscv.vmul.mask.nxv16i16.i16(
- <vscale x 16 x i16>,
- <vscale x 16 x i16>,
- i16,
- <vscale x 16 x i1>,
- i64,
- i64);
-
-define <vscale x 16 x i16> @intrinsic_vmul_mask_vx_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmul_mask_vx_nxv16i16_nxv16i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
-; CHECK-NEXT: vmul.vx v8, v12, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i16> @llvm.riscv.vmul.mask.nxv16i16.i16(
- <vscale x 16 x i16> %0,
- <vscale x 16 x i16> %1,
- i16 %2,
- <vscale x 16 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 16 x i16> %a
-}
-
-declare <vscale x 32 x i16> @llvm.riscv.vmul.nxv32i16.i16(
- <vscale x 32 x i16>,
- <vscale x 32 x i16>,
- i16,
- i64);
-
-define <vscale x 32 x i16> @intrinsic_vmul_vx_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, i16 %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmul_vx_nxv32i16_nxv32i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu
-; CHECK-NEXT: vmul.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 32 x i16> @llvm.riscv.vmul.nxv32i16.i16(
- <vscale x 32 x i16> undef,
- <vscale x 32 x i16> %0,
- i16 %1,
- i64 %2)
-
- ret <vscale x 32 x i16> %a
-}
-
-declare <vscale x 32 x i16> @llvm.riscv.vmul.mask.nxv32i16.i16(
- <vscale x 32 x i16>,
- <vscale x 32 x i16>,
- i16,
- <vscale x 32 x i1>,
- i64,
- i64);
-
-define <vscale x 32 x i16> @intrinsic_vmul_mask_vx_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, i16 %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmul_mask_vx_nxv32i16_nxv32i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu
-; CHECK-NEXT: vmul.vx v8, v16, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 32 x i16> @llvm.riscv.vmul.mask.nxv32i16.i16(
- <vscale x 32 x i16> %0,
- <vscale x 32 x i16> %1,
- i16 %2,
- <vscale x 32 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 32 x i16> %a
-}
-
-declare <vscale x 1 x i32> @llvm.riscv.vmul.nxv1i32.i32(
- <vscale x 1 x i32>,
- <vscale x 1 x i32>,
- i32,
- i64);
-
-define <vscale x 1 x i32> @intrinsic_vmul_vx_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, i32 %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmul_vx_nxv1i32_nxv1i32_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
-; CHECK-NEXT: vmul.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i32> @llvm.riscv.vmul.nxv1i32.i32(
- <vscale x 1 x i32> undef,
- <vscale x 1 x i32> %0,
- i32 %1,
- i64 %2)
-
- ret <vscale x 1 x i32> %a
-}
-
-declare <vscale x 1 x i32> @llvm.riscv.vmul.mask.nxv1i32.i32(
- <vscale x 1 x i32>,
- <vscale x 1 x i32>,
- i32,
- <vscale x 1 x i1>,
- i64,
- i64);
-
-define <vscale x 1 x i32> @intrinsic_vmul_mask_vx_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmul_mask_vx_nxv1i32_nxv1i32_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
-; CHECK-NEXT: vmul.vx v8, v9, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i32> @llvm.riscv.vmul.mask.nxv1i32.i32(
- <vscale x 1 x i32> %0,
- <vscale x 1 x i32> %1,
- i32 %2,
- <vscale x 1 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 1 x i32> %a
-}
-
-declare <vscale x 2 x i32> @llvm.riscv.vmul.nxv2i32.i32(
- <vscale x 2 x i32>,
- <vscale x 2 x i32>,
- i32,
- i64);
-
-define <vscale x 2 x i32> @intrinsic_vmul_vx_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, i32 %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmul_vx_nxv2i32_nxv2i32_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
-; CHECK-NEXT: vmul.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i32> @llvm.riscv.vmul.nxv2i32.i32(
- <vscale x 2 x i32> undef,
- <vscale x 2 x i32> %0,
- i32 %1,
- i64 %2)
-
- ret <vscale x 2 x i32> %a
-}
-
-declare <vscale x 2 x i32> @llvm.riscv.vmul.mask.nxv2i32.i32(
- <vscale x 2 x i32>,
- <vscale x 2 x i32>,
- i32,
- <vscale x 2 x i1>,
- i64,
- i64);
-
-define <vscale x 2 x i32> @intrinsic_vmul_mask_vx_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmul_mask_vx_nxv2i32_nxv2i32_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
-; CHECK-NEXT: vmul.vx v8, v9, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i32> @llvm.riscv.vmul.mask.nxv2i32.i32(
- <vscale x 2 x i32> %0,
- <vscale x 2 x i32> %1,
- i32 %2,
- <vscale x 2 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 2 x i32> %a
-}
-
-declare <vscale x 4 x i32> @llvm.riscv.vmul.nxv4i32.i32(
- <vscale x 4 x i32>,
- <vscale x 4 x i32>,
- i32,
- i64);
-
-define <vscale x 4 x i32> @intrinsic_vmul_vx_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, i32 %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmul_vx_nxv4i32_nxv4i32_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; CHECK-NEXT: vmul.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i32> @llvm.riscv.vmul.nxv4i32.i32(
- <vscale x 4 x i32> undef,
- <vscale x 4 x i32> %0,
- i32 %1,
- i64 %2)
-
- ret <vscale x 4 x i32> %a
-}
-
-declare <vscale x 4 x i32> @llvm.riscv.vmul.mask.nxv4i32.i32(
- <vscale x 4 x i32>,
- <vscale x 4 x i32>,
- i32,
- <vscale x 4 x i1>,
- i64,
- i64);
-
-define <vscale x 4 x i32> @intrinsic_vmul_mask_vx_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmul_mask_vx_nxv4i32_nxv4i32_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; CHECK-NEXT: vmul.vx v8, v10, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i32> @llvm.riscv.vmul.mask.nxv4i32.i32(
- <vscale x 4 x i32> %0,
- <vscale x 4 x i32> %1,
- i32 %2,
- <vscale x 4 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 4 x i32> %a
-}
-
-declare <vscale x 8 x i32> @llvm.riscv.vmul.nxv8i32.i32(
- <vscale x 8 x i32>,
- <vscale x 8 x i32>,
- i32,
- i64);
-
-define <vscale x 8 x i32> @intrinsic_vmul_vx_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, i32 %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmul_vx_nxv8i32_nxv8i32_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
-; CHECK-NEXT: vmul.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i32> @llvm.riscv.vmul.nxv8i32.i32(
- <vscale x 8 x i32> undef,
- <vscale x 8 x i32> %0,
- i32 %1,
- i64 %2)
-
- ret <vscale x 8 x i32> %a
-}
-
-declare <vscale x 8 x i32> @llvm.riscv.vmul.mask.nxv8i32.i32(
- <vscale x 8 x i32>,
- <vscale x 8 x i32>,
- i32,
- <vscale x 8 x i1>,
- i64,
- i64);
-
-define <vscale x 8 x i32> @intrinsic_vmul_mask_vx_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmul_mask_vx_nxv8i32_nxv8i32_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
-; CHECK-NEXT: vmul.vx v8, v12, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i32> @llvm.riscv.vmul.mask.nxv8i32.i32(
- <vscale x 8 x i32> %0,
- <vscale x 8 x i32> %1,
- i32 %2,
- <vscale x 8 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 8 x i32> %a
-}
-
-declare <vscale x 16 x i32> @llvm.riscv.vmul.nxv16i32.i32(
- <vscale x 16 x i32>,
- <vscale x 16 x i32>,
- i32,
- i64);
-
-define <vscale x 16 x i32> @intrinsic_vmul_vx_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, i32 %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmul_vx_nxv16i32_nxv16i32_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu
-; CHECK-NEXT: vmul.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i32> @llvm.riscv.vmul.nxv16i32.i32(
- <vscale x 16 x i32> undef,
- <vscale x 16 x i32> %0,
- i32 %1,
- i64 %2)
-
- ret <vscale x 16 x i32> %a
-}
-
-declare <vscale x 16 x i32> @llvm.riscv.vmul.mask.nxv16i32.i32(
- <vscale x 16 x i32>,
- <vscale x 16 x i32>,
- i32,
- <vscale x 16 x i1>,
- i64,
- i64);
-
-define <vscale x 16 x i32> @intrinsic_vmul_mask_vx_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmul_mask_vx_nxv16i32_nxv16i32_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu
-; CHECK-NEXT: vmul.vx v8, v16, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i32> @llvm.riscv.vmul.mask.nxv16i32.i32(
- <vscale x 16 x i32> %0,
- <vscale x 16 x i32> %1,
- i32 %2,
- <vscale x 16 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 16 x i32> %a
-}
-
-declare <vscale x 1 x i64> @llvm.riscv.vmul.nxv1i64.i64(
- <vscale x 1 x i64>,
- <vscale x 1 x i64>,
- i64,
- i64);
-
-define <vscale x 1 x i64> @intrinsic_vmul_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmul_vx_nxv1i64_nxv1i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
-; CHECK-NEXT: vmul.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i64> @llvm.riscv.vmul.nxv1i64.i64(
- <vscale x 1 x i64> undef,
- <vscale x 1 x i64> %0,
- i64 %1,
- i64 %2)
-
- ret <vscale x 1 x i64> %a
-}
-
-declare <vscale x 1 x i64> @llvm.riscv.vmul.mask.nxv1i64.i64(
- <vscale x 1 x i64>,
- <vscale x 1 x i64>,
- i64,
- <vscale x 1 x i1>,
- i64,
- i64);
-
-define <vscale x 1 x i64> @intrinsic_vmul_mask_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmul_mask_vx_nxv1i64_nxv1i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
-; CHECK-NEXT: vmul.vx v8, v9, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i64> @llvm.riscv.vmul.mask.nxv1i64.i64(
- <vscale x 1 x i64> %0,
- <vscale x 1 x i64> %1,
- i64 %2,
- <vscale x 1 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 1 x i64> %a
-}
-
-declare <vscale x 2 x i64> @llvm.riscv.vmul.nxv2i64.i64(
- <vscale x 2 x i64>,
- <vscale x 2 x i64>,
- i64,
- i64);
-
-define <vscale x 2 x i64> @intrinsic_vmul_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmul_vx_nxv2i64_nxv2i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
-; CHECK-NEXT: vmul.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i64> @llvm.riscv.vmul.nxv2i64.i64(
- <vscale x 2 x i64> undef,
- <vscale x 2 x i64> %0,
- i64 %1,
- i64 %2)
-
- ret <vscale x 2 x i64> %a
-}
-
-declare <vscale x 2 x i64> @llvm.riscv.vmul.mask.nxv2i64.i64(
- <vscale x 2 x i64>,
- <vscale x 2 x i64>,
- i64,
- <vscale x 2 x i1>,
- i64,
- i64);
-
-define <vscale x 2 x i64> @intrinsic_vmul_mask_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmul_mask_vx_nxv2i64_nxv2i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
-; CHECK-NEXT: vmul.vx v8, v10, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i64> @llvm.riscv.vmul.mask.nxv2i64.i64(
- <vscale x 2 x i64> %0,
- <vscale x 2 x i64> %1,
- i64 %2,
- <vscale x 2 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 2 x i64> %a
-}
-
-declare <vscale x 4 x i64> @llvm.riscv.vmul.nxv4i64.i64(
- <vscale x 4 x i64>,
- <vscale x 4 x i64>,
- i64,
- i64);
-
-define <vscale x 4 x i64> @intrinsic_vmul_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmul_vx_nxv4i64_nxv4i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
-; CHECK-NEXT: vmul.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i64> @llvm.riscv.vmul.nxv4i64.i64(
- <vscale x 4 x i64> undef,
- <vscale x 4 x i64> %0,
- i64 %1,
- i64 %2)
-
- ret <vscale x 4 x i64> %a
-}
-
-declare <vscale x 4 x i64> @llvm.riscv.vmul.mask.nxv4i64.i64(
- <vscale x 4 x i64>,
- <vscale x 4 x i64>,
- i64,
- <vscale x 4 x i1>,
- i64,
- i64);
-
-define <vscale x 4 x i64> @intrinsic_vmul_mask_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmul_mask_vx_nxv4i64_nxv4i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
-; CHECK-NEXT: vmul.vx v8, v12, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i64> @llvm.riscv.vmul.mask.nxv4i64.i64(
- <vscale x 4 x i64> %0,
- <vscale x 4 x i64> %1,
- i64 %2,
- <vscale x 4 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 4 x i64> %a
-}
-
-declare <vscale x 8 x i64> @llvm.riscv.vmul.nxv8i64.i64(
- <vscale x 8 x i64>,
- <vscale x 8 x i64>,
- i64,
- i64);
-
-define <vscale x 8 x i64> @intrinsic_vmul_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, i64 %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmul_vx_nxv8i64_nxv8i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu
-; CHECK-NEXT: vmul.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i64> @llvm.riscv.vmul.nxv8i64.i64(
- <vscale x 8 x i64> undef,
- <vscale x 8 x i64> %0,
- i64 %1,
- i64 %2)
-
- ret <vscale x 8 x i64> %a
-}
-
-declare <vscale x 8 x i64> @llvm.riscv.vmul.mask.nxv8i64.i64(
- <vscale x 8 x i64>,
- <vscale x 8 x i64>,
- i64,
- <vscale x 8 x i1>,
- i64,
- i64);
-
-define <vscale x 8 x i64> @intrinsic_vmul_mask_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmul_mask_vx_nxv8i64_nxv8i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu
-; CHECK-NEXT: vmul.vx v8, v16, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i64> @llvm.riscv.vmul.mask.nxv8i64.i64(
- <vscale x 8 x i64> %0,
- <vscale x 8 x i64> %1,
- i64 %2,
- <vscale x 8 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 8 x i64> %a
-}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmul-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmul.ll
similarity index 80%
rename from llvm/test/CodeGen/RISCV/rvv/vmul-rv32.ll
rename to llvm/test/CodeGen/RISCV/rvv/vmul.ll
index 6727bb585e2a7..36a51068e119b 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vmul-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vmul.ll
@@ -1,13 +1,15 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs \
-; RUN: < %s | FileCheck %s
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v \
+; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,RV32
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v \
+; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,RV64
declare <vscale x 1 x i8> @llvm.riscv.vmul.nxv1i8.nxv1i8(
<vscale x 1 x i8>,
<vscale x 1 x i8>,
<vscale x 1 x i8>,
- i32);
+ iXLen);
-define <vscale x 1 x i8> @intrinsic_vmul_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i32 %2) nounwind {
+define <vscale x 1 x i8> @intrinsic_vmul_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmul_vv_nxv1i8_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
@@ -18,7 +20,7 @@ entry:
<vscale x 1 x i8> undef,
<vscale x 1 x i8> %0,
<vscale x 1 x i8> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 1 x i8> %a
}
@@ -28,10 +30,9 @@ declare <vscale x 1 x i8> @llvm.riscv.vmul.mask.nxv1i8.nxv1i8(
<vscale x 1 x i8>,
<vscale x 1 x i8>,
<vscale x 1 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 1 x i8> @intrinsic_vmul_mask_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+define <vscale x 1 x i8> @intrinsic_vmul_mask_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv1i8_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
@@ -43,7 +44,7 @@ entry:
<vscale x 1 x i8> %1,
<vscale x 1 x i8> %2,
<vscale x 1 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 1 x i8> %a
}
@@ -52,9 +53,9 @@ declare <vscale x 2 x i8> @llvm.riscv.vmul.nxv2i8.nxv2i8(
<vscale x 2 x i8>,
<vscale x 2 x i8>,
<vscale x 2 x i8>,
- i32);
+ iXLen);
-define <vscale x 2 x i8> @intrinsic_vmul_vv_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i32 %2) nounwind {
+define <vscale x 2 x i8> @intrinsic_vmul_vv_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmul_vv_nxv2i8_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
@@ -65,7 +66,7 @@ entry:
<vscale x 2 x i8> undef,
<vscale x 2 x i8> %0,
<vscale x 2 x i8> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 2 x i8> %a
}
@@ -75,10 +76,9 @@ declare <vscale x 2 x i8> @llvm.riscv.vmul.mask.nxv2i8.nxv2i8(
<vscale x 2 x i8>,
<vscale x 2 x i8>,
<vscale x 2 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 2 x i8> @intrinsic_vmul_mask_vv_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+define <vscale x 2 x i8> @intrinsic_vmul_mask_vv_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv2i8_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
@@ -90,7 +90,7 @@ entry:
<vscale x 2 x i8> %1,
<vscale x 2 x i8> %2,
<vscale x 2 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 2 x i8> %a
}
@@ -99,9 +99,9 @@ declare <vscale x 4 x i8> @llvm.riscv.vmul.nxv4i8.nxv4i8(
<vscale x 4 x i8>,
<vscale x 4 x i8>,
<vscale x 4 x i8>,
- i32);
+ iXLen);
-define <vscale x 4 x i8> @intrinsic_vmul_vv_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i32 %2) nounwind {
+define <vscale x 4 x i8> @intrinsic_vmul_vv_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmul_vv_nxv4i8_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
@@ -112,7 +112,7 @@ entry:
<vscale x 4 x i8> undef,
<vscale x 4 x i8> %0,
<vscale x 4 x i8> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 4 x i8> %a
}
@@ -122,10 +122,9 @@ declare <vscale x 4 x i8> @llvm.riscv.vmul.mask.nxv4i8.nxv4i8(
<vscale x 4 x i8>,
<vscale x 4 x i8>,
<vscale x 4 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 4 x i8> @intrinsic_vmul_mask_vv_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+define <vscale x 4 x i8> @intrinsic_vmul_mask_vv_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv4i8_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
@@ -137,7 +136,7 @@ entry:
<vscale x 4 x i8> %1,
<vscale x 4 x i8> %2,
<vscale x 4 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 4 x i8> %a
}
@@ -146,9 +145,9 @@ declare <vscale x 8 x i8> @llvm.riscv.vmul.nxv8i8.nxv8i8(
<vscale x 8 x i8>,
<vscale x 8 x i8>,
<vscale x 8 x i8>,
- i32);
+ iXLen);
-define <vscale x 8 x i8> @intrinsic_vmul_vv_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i32 %2) nounwind {
+define <vscale x 8 x i8> @intrinsic_vmul_vv_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmul_vv_nxv8i8_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
@@ -159,7 +158,7 @@ entry:
<vscale x 8 x i8> undef,
<vscale x 8 x i8> %0,
<vscale x 8 x i8> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 8 x i8> %a
}
@@ -169,10 +168,9 @@ declare <vscale x 8 x i8> @llvm.riscv.vmul.mask.nxv8i8.nxv8i8(
<vscale x 8 x i8>,
<vscale x 8 x i8>,
<vscale x 8 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 8 x i8> @intrinsic_vmul_mask_vv_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+define <vscale x 8 x i8> @intrinsic_vmul_mask_vv_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv8i8_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
@@ -184,7 +182,7 @@ entry:
<vscale x 8 x i8> %1,
<vscale x 8 x i8> %2,
<vscale x 8 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 8 x i8> %a
}
@@ -193,9 +191,9 @@ declare <vscale x 16 x i8> @llvm.riscv.vmul.nxv16i8.nxv16i8(
<vscale x 16 x i8>,
<vscale x 16 x i8>,
<vscale x 16 x i8>,
- i32);
+ iXLen);
-define <vscale x 16 x i8> @intrinsic_vmul_vv_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i32 %2) nounwind {
+define <vscale x 16 x i8> @intrinsic_vmul_vv_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmul_vv_nxv16i8_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
@@ -206,7 +204,7 @@ entry:
<vscale x 16 x i8> undef,
<vscale x 16 x i8> %0,
<vscale x 16 x i8> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 16 x i8> %a
}
@@ -216,10 +214,9 @@ declare <vscale x 16 x i8> @llvm.riscv.vmul.mask.nxv16i8.nxv16i8(
<vscale x 16 x i8>,
<vscale x 16 x i8>,
<vscale x 16 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 16 x i8> @intrinsic_vmul_mask_vv_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+define <vscale x 16 x i8> @intrinsic_vmul_mask_vv_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv16i8_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
@@ -231,7 +228,7 @@ entry:
<vscale x 16 x i8> %1,
<vscale x 16 x i8> %2,
<vscale x 16 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 16 x i8> %a
}
@@ -240,9 +237,9 @@ declare <vscale x 32 x i8> @llvm.riscv.vmul.nxv32i8.nxv32i8(
<vscale x 32 x i8>,
<vscale x 32 x i8>,
<vscale x 32 x i8>,
- i32);
+ iXLen);
-define <vscale x 32 x i8> @intrinsic_vmul_vv_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i32 %2) nounwind {
+define <vscale x 32 x i8> @intrinsic_vmul_vv_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmul_vv_nxv32i8_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
@@ -253,7 +250,7 @@ entry:
<vscale x 32 x i8> undef,
<vscale x 32 x i8> %0,
<vscale x 32 x i8> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 32 x i8> %a
}
@@ -263,10 +260,9 @@ declare <vscale x 32 x i8> @llvm.riscv.vmul.mask.nxv32i8.nxv32i8(
<vscale x 32 x i8>,
<vscale x 32 x i8>,
<vscale x 32 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 32 x i8> @intrinsic_vmul_mask_vv_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
+define <vscale x 32 x i8> @intrinsic_vmul_mask_vv_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv32i8_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
@@ -278,7 +274,7 @@ entry:
<vscale x 32 x i8> %1,
<vscale x 32 x i8> %2,
<vscale x 32 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 32 x i8> %a
}
@@ -287,9 +283,9 @@ declare <vscale x 64 x i8> @llvm.riscv.vmul.nxv64i8.nxv64i8(
<vscale x 64 x i8>,
<vscale x 64 x i8>,
<vscale x 64 x i8>,
- i32);
+ iXLen);
-define <vscale x 64 x i8> @intrinsic_vmul_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i32 %2) nounwind {
+define <vscale x 64 x i8> @intrinsic_vmul_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmul_vv_nxv64i8_nxv64i8_nxv64i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, mu
@@ -300,7 +296,7 @@ entry:
<vscale x 64 x i8> undef,
<vscale x 64 x i8> %0,
<vscale x 64 x i8> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 64 x i8> %a
}
@@ -310,10 +306,9 @@ declare <vscale x 64 x i8> @llvm.riscv.vmul.mask.nxv64i8.nxv64i8(
<vscale x 64 x i8>,
<vscale x 64 x i8>,
<vscale x 64 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 64 x i8> @intrinsic_vmul_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, i32 %4) nounwind {
+define <vscale x 64 x i8> @intrinsic_vmul_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv64i8_nxv64i8_nxv64i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vl8r.v v24, (a0)
@@ -326,7 +321,7 @@ entry:
<vscale x 64 x i8> %1,
<vscale x 64 x i8> %2,
<vscale x 64 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 64 x i8> %a
}
@@ -335,9 +330,9 @@ declare <vscale x 1 x i16> @llvm.riscv.vmul.nxv1i16.nxv1i16(
<vscale x 1 x i16>,
<vscale x 1 x i16>,
<vscale x 1 x i16>,
- i32);
+ iXLen);
-define <vscale x 1 x i16> @intrinsic_vmul_vv_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i32 %2) nounwind {
+define <vscale x 1 x i16> @intrinsic_vmul_vv_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmul_vv_nxv1i16_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
@@ -348,7 +343,7 @@ entry:
<vscale x 1 x i16> undef,
<vscale x 1 x i16> %0,
<vscale x 1 x i16> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 1 x i16> %a
}
@@ -358,10 +353,9 @@ declare <vscale x 1 x i16> @llvm.riscv.vmul.mask.nxv1i16.nxv1i16(
<vscale x 1 x i16>,
<vscale x 1 x i16>,
<vscale x 1 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 1 x i16> @intrinsic_vmul_mask_vv_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+define <vscale x 1 x i16> @intrinsic_vmul_mask_vv_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv1i16_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
@@ -373,7 +367,7 @@ entry:
<vscale x 1 x i16> %1,
<vscale x 1 x i16> %2,
<vscale x 1 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 1 x i16> %a
}
@@ -382,9 +376,9 @@ declare <vscale x 2 x i16> @llvm.riscv.vmul.nxv2i16.nxv2i16(
<vscale x 2 x i16>,
<vscale x 2 x i16>,
<vscale x 2 x i16>,
- i32);
+ iXLen);
-define <vscale x 2 x i16> @intrinsic_vmul_vv_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i32 %2) nounwind {
+define <vscale x 2 x i16> @intrinsic_vmul_vv_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmul_vv_nxv2i16_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
@@ -395,7 +389,7 @@ entry:
<vscale x 2 x i16> undef,
<vscale x 2 x i16> %0,
<vscale x 2 x i16> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 2 x i16> %a
}
@@ -405,10 +399,9 @@ declare <vscale x 2 x i16> @llvm.riscv.vmul.mask.nxv2i16.nxv2i16(
<vscale x 2 x i16>,
<vscale x 2 x i16>,
<vscale x 2 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 2 x i16> @intrinsic_vmul_mask_vv_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+define <vscale x 2 x i16> @intrinsic_vmul_mask_vv_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv2i16_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
@@ -420,7 +413,7 @@ entry:
<vscale x 2 x i16> %1,
<vscale x 2 x i16> %2,
<vscale x 2 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 2 x i16> %a
}
@@ -429,9 +422,9 @@ declare <vscale x 4 x i16> @llvm.riscv.vmul.nxv4i16.nxv4i16(
<vscale x 4 x i16>,
<vscale x 4 x i16>,
<vscale x 4 x i16>,
- i32);
+ iXLen);
-define <vscale x 4 x i16> @intrinsic_vmul_vv_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i32 %2) nounwind {
+define <vscale x 4 x i16> @intrinsic_vmul_vv_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmul_vv_nxv4i16_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
@@ -442,7 +435,7 @@ entry:
<vscale x 4 x i16> undef,
<vscale x 4 x i16> %0,
<vscale x 4 x i16> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 4 x i16> %a
}
@@ -452,10 +445,9 @@ declare <vscale x 4 x i16> @llvm.riscv.vmul.mask.nxv4i16.nxv4i16(
<vscale x 4 x i16>,
<vscale x 4 x i16>,
<vscale x 4 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 4 x i16> @intrinsic_vmul_mask_vv_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+define <vscale x 4 x i16> @intrinsic_vmul_mask_vv_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv4i16_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
@@ -467,7 +459,7 @@ entry:
<vscale x 4 x i16> %1,
<vscale x 4 x i16> %2,
<vscale x 4 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 4 x i16> %a
}
@@ -476,9 +468,9 @@ declare <vscale x 8 x i16> @llvm.riscv.vmul.nxv8i16.nxv8i16(
<vscale x 8 x i16>,
<vscale x 8 x i16>,
<vscale x 8 x i16>,
- i32);
+ iXLen);
-define <vscale x 8 x i16> @intrinsic_vmul_vv_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i32 %2) nounwind {
+define <vscale x 8 x i16> @intrinsic_vmul_vv_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmul_vv_nxv8i16_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
@@ -489,7 +481,7 @@ entry:
<vscale x 8 x i16> undef,
<vscale x 8 x i16> %0,
<vscale x 8 x i16> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 8 x i16> %a
}
@@ -499,10 +491,9 @@ declare <vscale x 8 x i16> @llvm.riscv.vmul.mask.nxv8i16.nxv8i16(
<vscale x 8 x i16>,
<vscale x 8 x i16>,
<vscale x 8 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 8 x i16> @intrinsic_vmul_mask_vv_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+define <vscale x 8 x i16> @intrinsic_vmul_mask_vv_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv8i16_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
@@ -514,7 +505,7 @@ entry:
<vscale x 8 x i16> %1,
<vscale x 8 x i16> %2,
<vscale x 8 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 8 x i16> %a
}
@@ -523,9 +514,9 @@ declare <vscale x 16 x i16> @llvm.riscv.vmul.nxv16i16.nxv16i16(
<vscale x 16 x i16>,
<vscale x 16 x i16>,
<vscale x 16 x i16>,
- i32);
+ iXLen);
-define <vscale x 16 x i16> @intrinsic_vmul_vv_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i32 %2) nounwind {
+define <vscale x 16 x i16> @intrinsic_vmul_vv_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmul_vv_nxv16i16_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
@@ -536,7 +527,7 @@ entry:
<vscale x 16 x i16> undef,
<vscale x 16 x i16> %0,
<vscale x 16 x i16> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 16 x i16> %a
}
@@ -546,10 +537,9 @@ declare <vscale x 16 x i16> @llvm.riscv.vmul.mask.nxv16i16.nxv16i16(
<vscale x 16 x i16>,
<vscale x 16 x i16>,
<vscale x 16 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 16 x i16> @intrinsic_vmul_mask_vv_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+define <vscale x 16 x i16> @intrinsic_vmul_mask_vv_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv16i16_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
@@ -561,7 +551,7 @@ entry:
<vscale x 16 x i16> %1,
<vscale x 16 x i16> %2,
<vscale x 16 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 16 x i16> %a
}
@@ -570,9 +560,9 @@ declare <vscale x 32 x i16> @llvm.riscv.vmul.nxv32i16.nxv32i16(
<vscale x 32 x i16>,
<vscale x 32 x i16>,
<vscale x 32 x i16>,
- i32);
+ iXLen);
-define <vscale x 32 x i16> @intrinsic_vmul_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, i32 %2) nounwind {
+define <vscale x 32 x i16> @intrinsic_vmul_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmul_vv_nxv32i16_nxv32i16_nxv32i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, mu
@@ -583,7 +573,7 @@ entry:
<vscale x 32 x i16> undef,
<vscale x 32 x i16> %0,
<vscale x 32 x i16> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 32 x i16> %a
}
@@ -593,10 +583,9 @@ declare <vscale x 32 x i16> @llvm.riscv.vmul.mask.nxv32i16.nxv32i16(
<vscale x 32 x i16>,
<vscale x 32 x i16>,
<vscale x 32 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 32 x i16> @intrinsic_vmul_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
+define <vscale x 32 x i16> @intrinsic_vmul_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv32i16_nxv32i16_nxv32i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vl8re16.v v24, (a0)
@@ -609,7 +598,7 @@ entry:
<vscale x 32 x i16> %1,
<vscale x 32 x i16> %2,
<vscale x 32 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 32 x i16> %a
}
@@ -618,9 +607,9 @@ declare <vscale x 1 x i32> @llvm.riscv.vmul.nxv1i32.nxv1i32(
<vscale x 1 x i32>,
<vscale x 1 x i32>,
<vscale x 1 x i32>,
- i32);
+ iXLen);
-define <vscale x 1 x i32> @intrinsic_vmul_vv_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2) nounwind {
+define <vscale x 1 x i32> @intrinsic_vmul_vv_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmul_vv_nxv1i32_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
@@ -631,7 +620,7 @@ entry:
<vscale x 1 x i32> undef,
<vscale x 1 x i32> %0,
<vscale x 1 x i32> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 1 x i32> %a
}
@@ -641,10 +630,9 @@ declare <vscale x 1 x i32> @llvm.riscv.vmul.mask.nxv1i32.nxv1i32(
<vscale x 1 x i32>,
<vscale x 1 x i32>,
<vscale x 1 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 1 x i32> @intrinsic_vmul_mask_vv_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+define <vscale x 1 x i32> @intrinsic_vmul_mask_vv_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv1i32_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
@@ -656,7 +644,7 @@ entry:
<vscale x 1 x i32> %1,
<vscale x 1 x i32> %2,
<vscale x 1 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 1 x i32> %a
}
@@ -665,9 +653,9 @@ declare <vscale x 2 x i32> @llvm.riscv.vmul.nxv2i32.nxv2i32(
<vscale x 2 x i32>,
<vscale x 2 x i32>,
<vscale x 2 x i32>,
- i32);
+ iXLen);
-define <vscale x 2 x i32> @intrinsic_vmul_vv_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2) nounwind {
+define <vscale x 2 x i32> @intrinsic_vmul_vv_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmul_vv_nxv2i32_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
@@ -678,7 +666,7 @@ entry:
<vscale x 2 x i32> undef,
<vscale x 2 x i32> %0,
<vscale x 2 x i32> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 2 x i32> %a
}
@@ -688,10 +676,9 @@ declare <vscale x 2 x i32> @llvm.riscv.vmul.mask.nxv2i32.nxv2i32(
<vscale x 2 x i32>,
<vscale x 2 x i32>,
<vscale x 2 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 2 x i32> @intrinsic_vmul_mask_vv_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+define <vscale x 2 x i32> @intrinsic_vmul_mask_vv_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv2i32_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
@@ -703,7 +690,7 @@ entry:
<vscale x 2 x i32> %1,
<vscale x 2 x i32> %2,
<vscale x 2 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 2 x i32> %a
}
@@ -712,9 +699,9 @@ declare <vscale x 4 x i32> @llvm.riscv.vmul.nxv4i32.nxv4i32(
<vscale x 4 x i32>,
<vscale x 4 x i32>,
<vscale x 4 x i32>,
- i32);
+ iXLen);
-define <vscale x 4 x i32> @intrinsic_vmul_vv_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2) nounwind {
+define <vscale x 4 x i32> @intrinsic_vmul_vv_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmul_vv_nxv4i32_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
@@ -725,7 +712,7 @@ entry:
<vscale x 4 x i32> undef,
<vscale x 4 x i32> %0,
<vscale x 4 x i32> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 4 x i32> %a
}
@@ -735,10 +722,9 @@ declare <vscale x 4 x i32> @llvm.riscv.vmul.mask.nxv4i32.nxv4i32(
<vscale x 4 x i32>,
<vscale x 4 x i32>,
<vscale x 4 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 4 x i32> @intrinsic_vmul_mask_vv_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+define <vscale x 4 x i32> @intrinsic_vmul_mask_vv_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv4i32_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
@@ -750,7 +736,7 @@ entry:
<vscale x 4 x i32> %1,
<vscale x 4 x i32> %2,
<vscale x 4 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 4 x i32> %a
}
@@ -759,9 +745,9 @@ declare <vscale x 8 x i32> @llvm.riscv.vmul.nxv8i32.nxv8i32(
<vscale x 8 x i32>,
<vscale x 8 x i32>,
<vscale x 8 x i32>,
- i32);
+ iXLen);
-define <vscale x 8 x i32> @intrinsic_vmul_vv_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2) nounwind {
+define <vscale x 8 x i32> @intrinsic_vmul_vv_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmul_vv_nxv8i32_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
@@ -772,7 +758,7 @@ entry:
<vscale x 8 x i32> undef,
<vscale x 8 x i32> %0,
<vscale x 8 x i32> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 8 x i32> %a
}
@@ -782,10 +768,9 @@ declare <vscale x 8 x i32> @llvm.riscv.vmul.mask.nxv8i32.nxv8i32(
<vscale x 8 x i32>,
<vscale x 8 x i32>,
<vscale x 8 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 8 x i32> @intrinsic_vmul_mask_vv_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+define <vscale x 8 x i32> @intrinsic_vmul_mask_vv_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv8i32_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
@@ -797,7 +782,7 @@ entry:
<vscale x 8 x i32> %1,
<vscale x 8 x i32> %2,
<vscale x 8 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 8 x i32> %a
}
@@ -806,9 +791,9 @@ declare <vscale x 16 x i32> @llvm.riscv.vmul.nxv16i32.nxv16i32(
<vscale x 16 x i32>,
<vscale x 16 x i32>,
<vscale x 16 x i32>,
- i32);
+ iXLen);
-define <vscale x 16 x i32> @intrinsic_vmul_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2) nounwind {
+define <vscale x 16 x i32> @intrinsic_vmul_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmul_vv_nxv16i32_nxv16i32_nxv16i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu
@@ -819,7 +804,7 @@ entry:
<vscale x 16 x i32> undef,
<vscale x 16 x i32> %0,
<vscale x 16 x i32> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 16 x i32> %a
}
@@ -829,10 +814,9 @@ declare <vscale x 16 x i32> @llvm.riscv.vmul.mask.nxv16i32.nxv16i32(
<vscale x 16 x i32>,
<vscale x 16 x i32>,
<vscale x 16 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 16 x i32> @intrinsic_vmul_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+define <vscale x 16 x i32> @intrinsic_vmul_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv16i32_nxv16i32_nxv16i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vl8re32.v v24, (a0)
@@ -845,7 +829,7 @@ entry:
<vscale x 16 x i32> %1,
<vscale x 16 x i32> %2,
<vscale x 16 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 16 x i32> %a
}
@@ -854,9 +838,9 @@ declare <vscale x 1 x i64> @llvm.riscv.vmul.nxv1i64.nxv1i64(
<vscale x 1 x i64>,
<vscale x 1 x i64>,
<vscale x 1 x i64>,
- i32);
+ iXLen);
-define <vscale x 1 x i64> @intrinsic_vmul_vv_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i32 %2) nounwind {
+define <vscale x 1 x i64> @intrinsic_vmul_vv_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmul_vv_nxv1i64_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
@@ -867,7 +851,7 @@ entry:
<vscale x 1 x i64> undef,
<vscale x 1 x i64> %0,
<vscale x 1 x i64> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 1 x i64> %a
}
@@ -877,10 +861,9 @@ declare <vscale x 1 x i64> @llvm.riscv.vmul.mask.nxv1i64.nxv1i64(
<vscale x 1 x i64>,
<vscale x 1 x i64>,
<vscale x 1 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 1 x i64> @intrinsic_vmul_mask_vv_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+define <vscale x 1 x i64> @intrinsic_vmul_mask_vv_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv1i64_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
@@ -892,7 +875,7 @@ entry:
<vscale x 1 x i64> %1,
<vscale x 1 x i64> %2,
<vscale x 1 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 1 x i64> %a
}
@@ -901,9 +884,9 @@ declare <vscale x 2 x i64> @llvm.riscv.vmul.nxv2i64.nxv2i64(
<vscale x 2 x i64>,
<vscale x 2 x i64>,
<vscale x 2 x i64>,
- i32);
+ iXLen);
-define <vscale x 2 x i64> @intrinsic_vmul_vv_nxv2i64_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i32 %2) nounwind {
+define <vscale x 2 x i64> @intrinsic_vmul_vv_nxv2i64_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmul_vv_nxv2i64_nxv2i64_nxv2i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
@@ -914,7 +897,7 @@ entry:
<vscale x 2 x i64> undef,
<vscale x 2 x i64> %0,
<vscale x 2 x i64> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 2 x i64> %a
}
@@ -924,10 +907,9 @@ declare <vscale x 2 x i64> @llvm.riscv.vmul.mask.nxv2i64.nxv2i64(
<vscale x 2 x i64>,
<vscale x 2 x i64>,
<vscale x 2 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 2 x i64> @intrinsic_vmul_mask_vv_nxv2i64_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+define <vscale x 2 x i64> @intrinsic_vmul_mask_vv_nxv2i64_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv2i64_nxv2i64_nxv2i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
@@ -939,7 +921,7 @@ entry:
<vscale x 2 x i64> %1,
<vscale x 2 x i64> %2,
<vscale x 2 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 2 x i64> %a
}
@@ -948,9 +930,9 @@ declare <vscale x 4 x i64> @llvm.riscv.vmul.nxv4i64.nxv4i64(
<vscale x 4 x i64>,
<vscale x 4 x i64>,
<vscale x 4 x i64>,
- i32);
+ iXLen);
-define <vscale x 4 x i64> @intrinsic_vmul_vv_nxv4i64_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i32 %2) nounwind {
+define <vscale x 4 x i64> @intrinsic_vmul_vv_nxv4i64_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmul_vv_nxv4i64_nxv4i64_nxv4i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
@@ -961,7 +943,7 @@ entry:
<vscale x 4 x i64> undef,
<vscale x 4 x i64> %0,
<vscale x 4 x i64> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 4 x i64> %a
}
@@ -971,10 +953,9 @@ declare <vscale x 4 x i64> @llvm.riscv.vmul.mask.nxv4i64.nxv4i64(
<vscale x 4 x i64>,
<vscale x 4 x i64>,
<vscale x 4 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 4 x i64> @intrinsic_vmul_mask_vv_nxv4i64_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+define <vscale x 4 x i64> @intrinsic_vmul_mask_vv_nxv4i64_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv4i64_nxv4i64_nxv4i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
@@ -986,7 +967,7 @@ entry:
<vscale x 4 x i64> %1,
<vscale x 4 x i64> %2,
<vscale x 4 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 4 x i64> %a
}
@@ -995,9 +976,9 @@ declare <vscale x 8 x i64> @llvm.riscv.vmul.nxv8i64.nxv8i64(
<vscale x 8 x i64>,
<vscale x 8 x i64>,
<vscale x 8 x i64>,
- i32);
+ iXLen);
-define <vscale x 8 x i64> @intrinsic_vmul_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i32 %2) nounwind {
+define <vscale x 8 x i64> @intrinsic_vmul_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmul_vv_nxv8i64_nxv8i64_nxv8i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu
@@ -1008,7 +989,7 @@ entry:
<vscale x 8 x i64> undef,
<vscale x 8 x i64> %0,
<vscale x 8 x i64> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 8 x i64> %a
}
@@ -1018,10 +999,9 @@ declare <vscale x 8 x i64> @llvm.riscv.vmul.mask.nxv8i64.nxv8i64(
<vscale x 8 x i64>,
<vscale x 8 x i64>,
<vscale x 8 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 8 x i64> @intrinsic_vmul_mask_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+define <vscale x 8 x i64> @intrinsic_vmul_mask_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv8i64_nxv8i64_nxv8i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vl8re64.v v24, (a0)
@@ -1034,7 +1014,7 @@ entry:
<vscale x 8 x i64> %1,
<vscale x 8 x i64> %2,
<vscale x 8 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 8 x i64> %a
}
@@ -1043,9 +1023,9 @@ declare <vscale x 1 x i8> @llvm.riscv.vmul.nxv1i8.i8(
<vscale x 1 x i8>,
<vscale x 1 x i8>,
i8,
- i32);
+ iXLen);
-define <vscale x 1 x i8> @intrinsic_vmul_vx_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, i8 %1, i32 %2) nounwind {
+define <vscale x 1 x i8> @intrinsic_vmul_vx_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, i8 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmul_vx_nxv1i8_nxv1i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
@@ -1056,7 +1036,7 @@ entry:
<vscale x 1 x i8> undef,
<vscale x 1 x i8> %0,
i8 %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 1 x i8> %a
}
@@ -1066,10 +1046,9 @@ declare <vscale x 1 x i8> @llvm.riscv.vmul.mask.nxv1i8.i8(
<vscale x 1 x i8>,
i8,
<vscale x 1 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 1 x i8> @intrinsic_vmul_mask_vx_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+define <vscale x 1 x i8> @intrinsic_vmul_mask_vx_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmul_mask_vx_nxv1i8_nxv1i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
@@ -1081,7 +1060,7 @@ entry:
<vscale x 1 x i8> %1,
i8 %2,
<vscale x 1 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 1 x i8> %a
}
@@ -1090,9 +1069,9 @@ declare <vscale x 2 x i8> @llvm.riscv.vmul.nxv2i8.i8(
<vscale x 2 x i8>,
<vscale x 2 x i8>,
i8,
- i32);
+ iXLen);
-define <vscale x 2 x i8> @intrinsic_vmul_vx_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, i8 %1, i32 %2) nounwind {
+define <vscale x 2 x i8> @intrinsic_vmul_vx_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, i8 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmul_vx_nxv2i8_nxv2i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
@@ -1103,7 +1082,7 @@ entry:
<vscale x 2 x i8> undef,
<vscale x 2 x i8> %0,
i8 %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 2 x i8> %a
}
@@ -1113,10 +1092,9 @@ declare <vscale x 2 x i8> @llvm.riscv.vmul.mask.nxv2i8.i8(
<vscale x 2 x i8>,
i8,
<vscale x 2 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 2 x i8> @intrinsic_vmul_mask_vx_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+define <vscale x 2 x i8> @intrinsic_vmul_mask_vx_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmul_mask_vx_nxv2i8_nxv2i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
@@ -1128,7 +1106,7 @@ entry:
<vscale x 2 x i8> %1,
i8 %2,
<vscale x 2 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 2 x i8> %a
}
@@ -1137,9 +1115,9 @@ declare <vscale x 4 x i8> @llvm.riscv.vmul.nxv4i8.i8(
<vscale x 4 x i8>,
<vscale x 4 x i8>,
i8,
- i32);
+ iXLen);
-define <vscale x 4 x i8> @intrinsic_vmul_vx_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, i8 %1, i32 %2) nounwind {
+define <vscale x 4 x i8> @intrinsic_vmul_vx_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, i8 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmul_vx_nxv4i8_nxv4i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
@@ -1150,7 +1128,7 @@ entry:
<vscale x 4 x i8> undef,
<vscale x 4 x i8> %0,
i8 %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 4 x i8> %a
}
@@ -1160,10 +1138,9 @@ declare <vscale x 4 x i8> @llvm.riscv.vmul.mask.nxv4i8.i8(
<vscale x 4 x i8>,
i8,
<vscale x 4 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 4 x i8> @intrinsic_vmul_mask_vx_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+define <vscale x 4 x i8> @intrinsic_vmul_mask_vx_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmul_mask_vx_nxv4i8_nxv4i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
@@ -1175,7 +1152,7 @@ entry:
<vscale x 4 x i8> %1,
i8 %2,
<vscale x 4 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 4 x i8> %a
}
@@ -1184,9 +1161,9 @@ declare <vscale x 8 x i8> @llvm.riscv.vmul.nxv8i8.i8(
<vscale x 8 x i8>,
<vscale x 8 x i8>,
i8,
- i32);
+ iXLen);
-define <vscale x 8 x i8> @intrinsic_vmul_vx_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, i8 %1, i32 %2) nounwind {
+define <vscale x 8 x i8> @intrinsic_vmul_vx_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, i8 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmul_vx_nxv8i8_nxv8i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
@@ -1197,7 +1174,7 @@ entry:
<vscale x 8 x i8> undef,
<vscale x 8 x i8> %0,
i8 %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 8 x i8> %a
}
@@ -1207,10 +1184,9 @@ declare <vscale x 8 x i8> @llvm.riscv.vmul.mask.nxv8i8.i8(
<vscale x 8 x i8>,
i8,
<vscale x 8 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 8 x i8> @intrinsic_vmul_mask_vx_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+define <vscale x 8 x i8> @intrinsic_vmul_mask_vx_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmul_mask_vx_nxv8i8_nxv8i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
@@ -1222,7 +1198,7 @@ entry:
<vscale x 8 x i8> %1,
i8 %2,
<vscale x 8 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 8 x i8> %a
}
@@ -1231,9 +1207,9 @@ declare <vscale x 16 x i8> @llvm.riscv.vmul.nxv16i8.i8(
<vscale x 16 x i8>,
<vscale x 16 x i8>,
i8,
- i32);
+ iXLen);
-define <vscale x 16 x i8> @intrinsic_vmul_vx_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, i8 %1, i32 %2) nounwind {
+define <vscale x 16 x i8> @intrinsic_vmul_vx_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, i8 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmul_vx_nxv16i8_nxv16i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
@@ -1244,7 +1220,7 @@ entry:
<vscale x 16 x i8> undef,
<vscale x 16 x i8> %0,
i8 %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 16 x i8> %a
}
@@ -1254,10 +1230,9 @@ declare <vscale x 16 x i8> @llvm.riscv.vmul.mask.nxv16i8.i8(
<vscale x 16 x i8>,
i8,
<vscale x 16 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 16 x i8> @intrinsic_vmul_mask_vx_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+define <vscale x 16 x i8> @intrinsic_vmul_mask_vx_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmul_mask_vx_nxv16i8_nxv16i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
@@ -1269,7 +1244,7 @@ entry:
<vscale x 16 x i8> %1,
i8 %2,
<vscale x 16 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 16 x i8> %a
}
@@ -1278,9 +1253,9 @@ declare <vscale x 32 x i8> @llvm.riscv.vmul.nxv32i8.i8(
<vscale x 32 x i8>,
<vscale x 32 x i8>,
i8,
- i32);
+ iXLen);
-define <vscale x 32 x i8> @intrinsic_vmul_vx_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, i8 %1, i32 %2) nounwind {
+define <vscale x 32 x i8> @intrinsic_vmul_vx_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, i8 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmul_vx_nxv32i8_nxv32i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
@@ -1291,7 +1266,7 @@ entry:
<vscale x 32 x i8> undef,
<vscale x 32 x i8> %0,
i8 %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 32 x i8> %a
}
@@ -1301,10 +1276,9 @@ declare <vscale x 32 x i8> @llvm.riscv.vmul.mask.nxv32i8.i8(
<vscale x 32 x i8>,
i8,
<vscale x 32 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 32 x i8> @intrinsic_vmul_mask_vx_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
+define <vscale x 32 x i8> @intrinsic_vmul_mask_vx_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmul_mask_vx_nxv32i8_nxv32i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
@@ -1316,7 +1290,7 @@ entry:
<vscale x 32 x i8> %1,
i8 %2,
<vscale x 32 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 32 x i8> %a
}
@@ -1325,9 +1299,9 @@ declare <vscale x 64 x i8> @llvm.riscv.vmul.nxv64i8.i8(
<vscale x 64 x i8>,
<vscale x 64 x i8>,
i8,
- i32);
+ iXLen);
-define <vscale x 64 x i8> @intrinsic_vmul_vx_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, i8 %1, i32 %2) nounwind {
+define <vscale x 64 x i8> @intrinsic_vmul_vx_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, i8 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmul_vx_nxv64i8_nxv64i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu
@@ -1338,7 +1312,7 @@ entry:
<vscale x 64 x i8> undef,
<vscale x 64 x i8> %0,
i8 %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 64 x i8> %a
}
@@ -1348,10 +1322,9 @@ declare <vscale x 64 x i8> @llvm.riscv.vmul.mask.nxv64i8.i8(
<vscale x 64 x i8>,
i8,
<vscale x 64 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 64 x i8> @intrinsic_vmul_mask_vx_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i8 %2, <vscale x 64 x i1> %3, i32 %4) nounwind {
+define <vscale x 64 x i8> @intrinsic_vmul_mask_vx_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i8 %2, <vscale x 64 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmul_mask_vx_nxv64i8_nxv64i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu
@@ -1363,7 +1336,7 @@ entry:
<vscale x 64 x i8> %1,
i8 %2,
<vscale x 64 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 64 x i8> %a
}
@@ -1372,9 +1345,9 @@ declare <vscale x 1 x i16> @llvm.riscv.vmul.nxv1i16.i16(
<vscale x 1 x i16>,
<vscale x 1 x i16>,
i16,
- i32);
+ iXLen);
-define <vscale x 1 x i16> @intrinsic_vmul_vx_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, i16 %1, i32 %2) nounwind {
+define <vscale x 1 x i16> @intrinsic_vmul_vx_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, i16 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmul_vx_nxv1i16_nxv1i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
@@ -1385,7 +1358,7 @@ entry:
<vscale x 1 x i16> undef,
<vscale x 1 x i16> %0,
i16 %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 1 x i16> %a
}
@@ -1395,10 +1368,9 @@ declare <vscale x 1 x i16> @llvm.riscv.vmul.mask.nxv1i16.i16(
<vscale x 1 x i16>,
i16,
<vscale x 1 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 1 x i16> @intrinsic_vmul_mask_vx_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+define <vscale x 1 x i16> @intrinsic_vmul_mask_vx_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmul_mask_vx_nxv1i16_nxv1i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
@@ -1410,7 +1382,7 @@ entry:
<vscale x 1 x i16> %1,
i16 %2,
<vscale x 1 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 1 x i16> %a
}
@@ -1419,9 +1391,9 @@ declare <vscale x 2 x i16> @llvm.riscv.vmul.nxv2i16.i16(
<vscale x 2 x i16>,
<vscale x 2 x i16>,
i16,
- i32);
+ iXLen);
-define <vscale x 2 x i16> @intrinsic_vmul_vx_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, i16 %1, i32 %2) nounwind {
+define <vscale x 2 x i16> @intrinsic_vmul_vx_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, i16 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmul_vx_nxv2i16_nxv2i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
@@ -1432,7 +1404,7 @@ entry:
<vscale x 2 x i16> undef,
<vscale x 2 x i16> %0,
i16 %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 2 x i16> %a
}
@@ -1442,10 +1414,9 @@ declare <vscale x 2 x i16> @llvm.riscv.vmul.mask.nxv2i16.i16(
<vscale x 2 x i16>,
i16,
<vscale x 2 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 2 x i16> @intrinsic_vmul_mask_vx_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+define <vscale x 2 x i16> @intrinsic_vmul_mask_vx_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmul_mask_vx_nxv2i16_nxv2i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
@@ -1457,7 +1428,7 @@ entry:
<vscale x 2 x i16> %1,
i16 %2,
<vscale x 2 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 2 x i16> %a
}
@@ -1466,9 +1437,9 @@ declare <vscale x 4 x i16> @llvm.riscv.vmul.nxv4i16.i16(
<vscale x 4 x i16>,
<vscale x 4 x i16>,
i16,
- i32);
+ iXLen);
-define <vscale x 4 x i16> @intrinsic_vmul_vx_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, i16 %1, i32 %2) nounwind {
+define <vscale x 4 x i16> @intrinsic_vmul_vx_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, i16 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmul_vx_nxv4i16_nxv4i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
@@ -1479,7 +1450,7 @@ entry:
<vscale x 4 x i16> undef,
<vscale x 4 x i16> %0,
i16 %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 4 x i16> %a
}
@@ -1489,10 +1460,9 @@ declare <vscale x 4 x i16> @llvm.riscv.vmul.mask.nxv4i16.i16(
<vscale x 4 x i16>,
i16,
<vscale x 4 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 4 x i16> @intrinsic_vmul_mask_vx_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+define <vscale x 4 x i16> @intrinsic_vmul_mask_vx_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmul_mask_vx_nxv4i16_nxv4i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
@@ -1504,7 +1474,7 @@ entry:
<vscale x 4 x i16> %1,
i16 %2,
<vscale x 4 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 4 x i16> %a
}
@@ -1513,9 +1483,9 @@ declare <vscale x 8 x i16> @llvm.riscv.vmul.nxv8i16.i16(
<vscale x 8 x i16>,
<vscale x 8 x i16>,
i16,
- i32);
+ iXLen);
-define <vscale x 8 x i16> @intrinsic_vmul_vx_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, i16 %1, i32 %2) nounwind {
+define <vscale x 8 x i16> @intrinsic_vmul_vx_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, i16 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmul_vx_nxv8i16_nxv8i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
@@ -1526,7 +1496,7 @@ entry:
<vscale x 8 x i16> undef,
<vscale x 8 x i16> %0,
i16 %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 8 x i16> %a
}
@@ -1536,10 +1506,9 @@ declare <vscale x 8 x i16> @llvm.riscv.vmul.mask.nxv8i16.i16(
<vscale x 8 x i16>,
i16,
<vscale x 8 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 8 x i16> @intrinsic_vmul_mask_vx_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+define <vscale x 8 x i16> @intrinsic_vmul_mask_vx_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmul_mask_vx_nxv8i16_nxv8i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
@@ -1551,7 +1520,7 @@ entry:
<vscale x 8 x i16> %1,
i16 %2,
<vscale x 8 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 8 x i16> %a
}
@@ -1560,9 +1529,9 @@ declare <vscale x 16 x i16> @llvm.riscv.vmul.nxv16i16.i16(
<vscale x 16 x i16>,
<vscale x 16 x i16>,
i16,
- i32);
+ iXLen);
-define <vscale x 16 x i16> @intrinsic_vmul_vx_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, i16 %1, i32 %2) nounwind {
+define <vscale x 16 x i16> @intrinsic_vmul_vx_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, i16 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmul_vx_nxv16i16_nxv16i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
@@ -1573,7 +1542,7 @@ entry:
<vscale x 16 x i16> undef,
<vscale x 16 x i16> %0,
i16 %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 16 x i16> %a
}
@@ -1583,10 +1552,9 @@ declare <vscale x 16 x i16> @llvm.riscv.vmul.mask.nxv16i16.i16(
<vscale x 16 x i16>,
i16,
<vscale x 16 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 16 x i16> @intrinsic_vmul_mask_vx_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+define <vscale x 16 x i16> @intrinsic_vmul_mask_vx_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmul_mask_vx_nxv16i16_nxv16i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
@@ -1598,7 +1566,7 @@ entry:
<vscale x 16 x i16> %1,
i16 %2,
<vscale x 16 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 16 x i16> %a
}
@@ -1607,9 +1575,9 @@ declare <vscale x 32 x i16> @llvm.riscv.vmul.nxv32i16.i16(
<vscale x 32 x i16>,
<vscale x 32 x i16>,
i16,
- i32);
+ iXLen);
-define <vscale x 32 x i16> @intrinsic_vmul_vx_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, i16 %1, i32 %2) nounwind {
+define <vscale x 32 x i16> @intrinsic_vmul_vx_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, i16 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmul_vx_nxv32i16_nxv32i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu
@@ -1620,7 +1588,7 @@ entry:
<vscale x 32 x i16> undef,
<vscale x 32 x i16> %0,
i16 %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 32 x i16> %a
}
@@ -1630,10 +1598,9 @@ declare <vscale x 32 x i16> @llvm.riscv.vmul.mask.nxv32i16.i16(
<vscale x 32 x i16>,
i16,
<vscale x 32 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 32 x i16> @intrinsic_vmul_mask_vx_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, i16 %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
+define <vscale x 32 x i16> @intrinsic_vmul_mask_vx_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, i16 %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmul_mask_vx_nxv32i16_nxv32i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu
@@ -1645,7 +1612,7 @@ entry:
<vscale x 32 x i16> %1,
i16 %2,
<vscale x 32 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 32 x i16> %a
}
@@ -1654,9 +1621,9 @@ declare <vscale x 1 x i32> @llvm.riscv.vmul.nxv1i32.i32(
<vscale x 1 x i32>,
<vscale x 1 x i32>,
i32,
- i32);
+ iXLen);
-define <vscale x 1 x i32> @intrinsic_vmul_vx_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, i32 %1, i32 %2) nounwind {
+define <vscale x 1 x i32> @intrinsic_vmul_vx_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, i32 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmul_vx_nxv1i32_nxv1i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
@@ -1667,7 +1634,7 @@ entry:
<vscale x 1 x i32> undef,
<vscale x 1 x i32> %0,
i32 %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 1 x i32> %a
}
@@ -1677,10 +1644,9 @@ declare <vscale x 1 x i32> @llvm.riscv.vmul.mask.nxv1i32.i32(
<vscale x 1 x i32>,
i32,
<vscale x 1 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 1 x i32> @intrinsic_vmul_mask_vx_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+define <vscale x 1 x i32> @intrinsic_vmul_mask_vx_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmul_mask_vx_nxv1i32_nxv1i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
@@ -1692,7 +1658,7 @@ entry:
<vscale x 1 x i32> %1,
i32 %2,
<vscale x 1 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 1 x i32> %a
}
@@ -1701,9 +1667,9 @@ declare <vscale x 2 x i32> @llvm.riscv.vmul.nxv2i32.i32(
<vscale x 2 x i32>,
<vscale x 2 x i32>,
i32,
- i32);
+ iXLen);
-define <vscale x 2 x i32> @intrinsic_vmul_vx_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, i32 %1, i32 %2) nounwind {
+define <vscale x 2 x i32> @intrinsic_vmul_vx_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, i32 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmul_vx_nxv2i32_nxv2i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
@@ -1714,7 +1680,7 @@ entry:
<vscale x 2 x i32> undef,
<vscale x 2 x i32> %0,
i32 %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 2 x i32> %a
}
@@ -1724,10 +1690,9 @@ declare <vscale x 2 x i32> @llvm.riscv.vmul.mask.nxv2i32.i32(
<vscale x 2 x i32>,
i32,
<vscale x 2 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 2 x i32> @intrinsic_vmul_mask_vx_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+define <vscale x 2 x i32> @intrinsic_vmul_mask_vx_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmul_mask_vx_nxv2i32_nxv2i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
@@ -1739,7 +1704,7 @@ entry:
<vscale x 2 x i32> %1,
i32 %2,
<vscale x 2 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 2 x i32> %a
}
@@ -1748,9 +1713,9 @@ declare <vscale x 4 x i32> @llvm.riscv.vmul.nxv4i32.i32(
<vscale x 4 x i32>,
<vscale x 4 x i32>,
i32,
- i32);
+ iXLen);
-define <vscale x 4 x i32> @intrinsic_vmul_vx_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, i32 %1, i32 %2) nounwind {
+define <vscale x 4 x i32> @intrinsic_vmul_vx_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, i32 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmul_vx_nxv4i32_nxv4i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
@@ -1761,7 +1726,7 @@ entry:
<vscale x 4 x i32> undef,
<vscale x 4 x i32> %0,
i32 %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 4 x i32> %a
}
@@ -1771,10 +1736,9 @@ declare <vscale x 4 x i32> @llvm.riscv.vmul.mask.nxv4i32.i32(
<vscale x 4 x i32>,
i32,
<vscale x 4 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 4 x i32> @intrinsic_vmul_mask_vx_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+define <vscale x 4 x i32> @intrinsic_vmul_mask_vx_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmul_mask_vx_nxv4i32_nxv4i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
@@ -1786,7 +1750,7 @@ entry:
<vscale x 4 x i32> %1,
i32 %2,
<vscale x 4 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 4 x i32> %a
}
@@ -1795,9 +1759,9 @@ declare <vscale x 8 x i32> @llvm.riscv.vmul.nxv8i32.i32(
<vscale x 8 x i32>,
<vscale x 8 x i32>,
i32,
- i32);
+ iXLen);
-define <vscale x 8 x i32> @intrinsic_vmul_vx_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, i32 %1, i32 %2) nounwind {
+define <vscale x 8 x i32> @intrinsic_vmul_vx_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, i32 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmul_vx_nxv8i32_nxv8i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
@@ -1808,7 +1772,7 @@ entry:
<vscale x 8 x i32> undef,
<vscale x 8 x i32> %0,
i32 %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 8 x i32> %a
}
@@ -1818,10 +1782,9 @@ declare <vscale x 8 x i32> @llvm.riscv.vmul.mask.nxv8i32.i32(
<vscale x 8 x i32>,
i32,
<vscale x 8 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 8 x i32> @intrinsic_vmul_mask_vx_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+define <vscale x 8 x i32> @intrinsic_vmul_mask_vx_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmul_mask_vx_nxv8i32_nxv8i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
@@ -1833,7 +1796,7 @@ entry:
<vscale x 8 x i32> %1,
i32 %2,
<vscale x 8 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 8 x i32> %a
}
@@ -1842,9 +1805,9 @@ declare <vscale x 16 x i32> @llvm.riscv.vmul.nxv16i32.i32(
<vscale x 16 x i32>,
<vscale x 16 x i32>,
i32,
- i32);
+ iXLen);
-define <vscale x 16 x i32> @intrinsic_vmul_vx_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, i32 %1, i32 %2) nounwind {
+define <vscale x 16 x i32> @intrinsic_vmul_vx_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, i32 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmul_vx_nxv16i32_nxv16i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu
@@ -1855,7 +1818,7 @@ entry:
<vscale x 16 x i32> undef,
<vscale x 16 x i32> %0,
i32 %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 16 x i32> %a
}
@@ -1865,10 +1828,9 @@ declare <vscale x 16 x i32> @llvm.riscv.vmul.mask.nxv16i32.i32(
<vscale x 16 x i32>,
i32,
<vscale x 16 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 16 x i32> @intrinsic_vmul_mask_vx_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+define <vscale x 16 x i32> @intrinsic_vmul_mask_vx_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmul_mask_vx_nxv16i32_nxv16i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu
@@ -1880,7 +1842,7 @@ entry:
<vscale x 16 x i32> %1,
i32 %2,
<vscale x 16 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 16 x i32> %a
}
@@ -1889,26 +1851,32 @@ declare <vscale x 1 x i64> @llvm.riscv.vmul.nxv1i64.i64(
<vscale x 1 x i64>,
<vscale x 1 x i64>,
i64,
- i32);
-
-define <vscale x 1 x i64> @intrinsic_vmul_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmul_vx_nxv1i64_nxv1i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addi sp, sp, -16
-; CHECK-NEXT: sw a1, 12(sp)
-; CHECK-NEXT: sw a0, 8(sp)
-; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
-; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v9, (a0), zero
-; CHECK-NEXT: vmul.vv v8, v8, v9
-; CHECK-NEXT: addi sp, sp, 16
-; CHECK-NEXT: ret
+ iXLen);
+
+define <vscale x 1 x i64> @intrinsic_vmul_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, iXLen %2) nounwind {
+; RV32-LABEL: intrinsic_vmul_vx_nxv1i64_nxv1i64_i64:
+; RV32: # %bb.0: # %entry
+; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: sw a1, 12(sp)
+; RV32-NEXT: sw a0, 8(sp)
+; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
+; RV32-NEXT: addi a0, sp, 8
+; RV32-NEXT: vlse64.v v9, (a0), zero
+; RV32-NEXT: vmul.vv v8, v8, v9
+; RV32-NEXT: addi sp, sp, 16
+; RV32-NEXT: ret
+;
+; RV64-LABEL: intrinsic_vmul_vx_nxv1i64_nxv1i64_i64:
+; RV64: # %bb.0: # %entry
+; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, mu
+; RV64-NEXT: vmul.vx v8, v8, a0
+; RV64-NEXT: ret
entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vmul.nxv1i64.i64(
<vscale x 1 x i64> undef,
<vscale x 1 x i64> %0,
i64 %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 1 x i64> %a
}
@@ -1918,28 +1886,33 @@ declare <vscale x 1 x i64> @llvm.riscv.vmul.mask.nxv1i64.i64(
<vscale x 1 x i64>,
i64,
<vscale x 1 x i1>,
- i32,
- i32);
-
-define <vscale x 1 x i64> @intrinsic_vmul_mask_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmul_mask_vx_nxv1i64_nxv1i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addi sp, sp, -16
-; CHECK-NEXT: sw a1, 12(sp)
-; CHECK-NEXT: sw a0, 8(sp)
-; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
-; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v10, (a0), zero
-; CHECK-NEXT: vmul.vv v8, v9, v10, v0.t
-; CHECK-NEXT: addi sp, sp, 16
-; CHECK-NEXT: ret
+ iXLen, iXLen);
+
+define <vscale x 1 x i64> @intrinsic_vmul_mask_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
+; RV32-LABEL: intrinsic_vmul_mask_vx_nxv1i64_nxv1i64_i64:
+; RV32: # %bb.0: # %entry
+; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: sw a1, 12(sp)
+; RV32-NEXT: sw a0, 8(sp)
+; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
+; RV32-NEXT: addi a0, sp, 8
+; RV32-NEXT: vlse64.v v10, (a0), zero
+; RV32-NEXT: vmul.vv v8, v9, v10, v0.t
+; RV32-NEXT: addi sp, sp, 16
+; RV32-NEXT: ret
+;
+; RV64-LABEL: intrinsic_vmul_mask_vx_nxv1i64_nxv1i64_i64:
+; RV64: # %bb.0: # %entry
+; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, mu
+; RV64-NEXT: vmul.vx v8, v9, a0, v0.t
+; RV64-NEXT: ret
entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vmul.mask.nxv1i64.i64(
<vscale x 1 x i64> %0,
<vscale x 1 x i64> %1,
i64 %2,
<vscale x 1 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 1 x i64> %a
}
@@ -1948,26 +1921,32 @@ declare <vscale x 2 x i64> @llvm.riscv.vmul.nxv2i64.i64(
<vscale x 2 x i64>,
<vscale x 2 x i64>,
i64,
- i32);
-
-define <vscale x 2 x i64> @intrinsic_vmul_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmul_vx_nxv2i64_nxv2i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addi sp, sp, -16
-; CHECK-NEXT: sw a1, 12(sp)
-; CHECK-NEXT: sw a0, 8(sp)
-; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
-; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v10, (a0), zero
-; CHECK-NEXT: vmul.vv v8, v8, v10
-; CHECK-NEXT: addi sp, sp, 16
-; CHECK-NEXT: ret
+ iXLen);
+
+define <vscale x 2 x i64> @intrinsic_vmul_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, iXLen %2) nounwind {
+; RV32-LABEL: intrinsic_vmul_vx_nxv2i64_nxv2i64_i64:
+; RV32: # %bb.0: # %entry
+; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: sw a1, 12(sp)
+; RV32-NEXT: sw a0, 8(sp)
+; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
+; RV32-NEXT: addi a0, sp, 8
+; RV32-NEXT: vlse64.v v10, (a0), zero
+; RV32-NEXT: vmul.vv v8, v8, v10
+; RV32-NEXT: addi sp, sp, 16
+; RV32-NEXT: ret
+;
+; RV64-LABEL: intrinsic_vmul_vx_nxv2i64_nxv2i64_i64:
+; RV64: # %bb.0: # %entry
+; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, mu
+; RV64-NEXT: vmul.vx v8, v8, a0
+; RV64-NEXT: ret
entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vmul.nxv2i64.i64(
<vscale x 2 x i64> undef,
<vscale x 2 x i64> %0,
i64 %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 2 x i64> %a
}
@@ -1977,28 +1956,33 @@ declare <vscale x 2 x i64> @llvm.riscv.vmul.mask.nxv2i64.i64(
<vscale x 2 x i64>,
i64,
<vscale x 2 x i1>,
- i32,
- i32);
-
-define <vscale x 2 x i64> @intrinsic_vmul_mask_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmul_mask_vx_nxv2i64_nxv2i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addi sp, sp, -16
-; CHECK-NEXT: sw a1, 12(sp)
-; CHECK-NEXT: sw a0, 8(sp)
-; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
-; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v12, (a0), zero
-; CHECK-NEXT: vmul.vv v8, v10, v12, v0.t
-; CHECK-NEXT: addi sp, sp, 16
-; CHECK-NEXT: ret
+ iXLen, iXLen);
+
+define <vscale x 2 x i64> @intrinsic_vmul_mask_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
+; RV32-LABEL: intrinsic_vmul_mask_vx_nxv2i64_nxv2i64_i64:
+; RV32: # %bb.0: # %entry
+; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: sw a1, 12(sp)
+; RV32-NEXT: sw a0, 8(sp)
+; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
+; RV32-NEXT: addi a0, sp, 8
+; RV32-NEXT: vlse64.v v12, (a0), zero
+; RV32-NEXT: vmul.vv v8, v10, v12, v0.t
+; RV32-NEXT: addi sp, sp, 16
+; RV32-NEXT: ret
+;
+; RV64-LABEL: intrinsic_vmul_mask_vx_nxv2i64_nxv2i64_i64:
+; RV64: # %bb.0: # %entry
+; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, mu
+; RV64-NEXT: vmul.vx v8, v10, a0, v0.t
+; RV64-NEXT: ret
entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vmul.mask.nxv2i64.i64(
<vscale x 2 x i64> %0,
<vscale x 2 x i64> %1,
i64 %2,
<vscale x 2 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 2 x i64> %a
}
@@ -2007,26 +1991,32 @@ declare <vscale x 4 x i64> @llvm.riscv.vmul.nxv4i64.i64(
<vscale x 4 x i64>,
<vscale x 4 x i64>,
i64,
- i32);
-
-define <vscale x 4 x i64> @intrinsic_vmul_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmul_vx_nxv4i64_nxv4i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addi sp, sp, -16
-; CHECK-NEXT: sw a1, 12(sp)
-; CHECK-NEXT: sw a0, 8(sp)
-; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
-; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v12, (a0), zero
-; CHECK-NEXT: vmul.vv v8, v8, v12
-; CHECK-NEXT: addi sp, sp, 16
-; CHECK-NEXT: ret
+ iXLen);
+
+define <vscale x 4 x i64> @intrinsic_vmul_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, iXLen %2) nounwind {
+; RV32-LABEL: intrinsic_vmul_vx_nxv4i64_nxv4i64_i64:
+; RV32: # %bb.0: # %entry
+; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: sw a1, 12(sp)
+; RV32-NEXT: sw a0, 8(sp)
+; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
+; RV32-NEXT: addi a0, sp, 8
+; RV32-NEXT: vlse64.v v12, (a0), zero
+; RV32-NEXT: vmul.vv v8, v8, v12
+; RV32-NEXT: addi sp, sp, 16
+; RV32-NEXT: ret
+;
+; RV64-LABEL: intrinsic_vmul_vx_nxv4i64_nxv4i64_i64:
+; RV64: # %bb.0: # %entry
+; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu
+; RV64-NEXT: vmul.vx v8, v8, a0
+; RV64-NEXT: ret
entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vmul.nxv4i64.i64(
<vscale x 4 x i64> undef,
<vscale x 4 x i64> %0,
i64 %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 4 x i64> %a
}
@@ -2036,28 +2026,33 @@ declare <vscale x 4 x i64> @llvm.riscv.vmul.mask.nxv4i64.i64(
<vscale x 4 x i64>,
i64,
<vscale x 4 x i1>,
- i32,
- i32);
-
-define <vscale x 4 x i64> @intrinsic_vmul_mask_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmul_mask_vx_nxv4i64_nxv4i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addi sp, sp, -16
-; CHECK-NEXT: sw a1, 12(sp)
-; CHECK-NEXT: sw a0, 8(sp)
-; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
-; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v16, (a0), zero
-; CHECK-NEXT: vmul.vv v8, v12, v16, v0.t
-; CHECK-NEXT: addi sp, sp, 16
-; CHECK-NEXT: ret
+ iXLen, iXLen);
+
+define <vscale x 4 x i64> @intrinsic_vmul_mask_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
+; RV32-LABEL: intrinsic_vmul_mask_vx_nxv4i64_nxv4i64_i64:
+; RV32: # %bb.0: # %entry
+; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: sw a1, 12(sp)
+; RV32-NEXT: sw a0, 8(sp)
+; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
+; RV32-NEXT: addi a0, sp, 8
+; RV32-NEXT: vlse64.v v16, (a0), zero
+; RV32-NEXT: vmul.vv v8, v12, v16, v0.t
+; RV32-NEXT: addi sp, sp, 16
+; RV32-NEXT: ret
+;
+; RV64-LABEL: intrinsic_vmul_mask_vx_nxv4i64_nxv4i64_i64:
+; RV64: # %bb.0: # %entry
+; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu
+; RV64-NEXT: vmul.vx v8, v12, a0, v0.t
+; RV64-NEXT: ret
entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vmul.mask.nxv4i64.i64(
<vscale x 4 x i64> %0,
<vscale x 4 x i64> %1,
i64 %2,
<vscale x 4 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 4 x i64> %a
}
@@ -2066,26 +2061,32 @@ declare <vscale x 8 x i64> @llvm.riscv.vmul.nxv8i64.i64(
<vscale x 8 x i64>,
<vscale x 8 x i64>,
i64,
- i32);
-
-define <vscale x 8 x i64> @intrinsic_vmul_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, i64 %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmul_vx_nxv8i64_nxv8i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addi sp, sp, -16
-; CHECK-NEXT: sw a1, 12(sp)
-; CHECK-NEXT: sw a0, 8(sp)
-; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, mu
-; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v16, (a0), zero
-; CHECK-NEXT: vmul.vv v8, v8, v16
-; CHECK-NEXT: addi sp, sp, 16
-; CHECK-NEXT: ret
+ iXLen);
+
+define <vscale x 8 x i64> @intrinsic_vmul_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, i64 %1, iXLen %2) nounwind {
+; RV32-LABEL: intrinsic_vmul_vx_nxv8i64_nxv8i64_i64:
+; RV32: # %bb.0: # %entry
+; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: sw a1, 12(sp)
+; RV32-NEXT: sw a0, 8(sp)
+; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu
+; RV32-NEXT: addi a0, sp, 8
+; RV32-NEXT: vlse64.v v16, (a0), zero
+; RV32-NEXT: vmul.vv v8, v8, v16
+; RV32-NEXT: addi sp, sp, 16
+; RV32-NEXT: ret
+;
+; RV64-LABEL: intrinsic_vmul_vx_nxv8i64_nxv8i64_i64:
+; RV64: # %bb.0: # %entry
+; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, mu
+; RV64-NEXT: vmul.vx v8, v8, a0
+; RV64-NEXT: ret
entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vmul.nxv8i64.i64(
<vscale x 8 x i64> undef,
<vscale x 8 x i64> %0,
i64 %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 8 x i64> %a
}
@@ -2095,28 +2096,33 @@ declare <vscale x 8 x i64> @llvm.riscv.vmul.mask.nxv8i64.i64(
<vscale x 8 x i64>,
i64,
<vscale x 8 x i1>,
- i32,
- i32);
-
-define <vscale x 8 x i64> @intrinsic_vmul_mask_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmul_mask_vx_nxv8i64_nxv8i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addi sp, sp, -16
-; CHECK-NEXT: sw a1, 12(sp)
-; CHECK-NEXT: sw a0, 8(sp)
-; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, mu
-; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v24, (a0), zero
-; CHECK-NEXT: vmul.vv v8, v16, v24, v0.t
-; CHECK-NEXT: addi sp, sp, 16
-; CHECK-NEXT: ret
+ iXLen, iXLen);
+
+define <vscale x 8 x i64> @intrinsic_vmul_mask_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
+; RV32-LABEL: intrinsic_vmul_mask_vx_nxv8i64_nxv8i64_i64:
+; RV32: # %bb.0: # %entry
+; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: sw a1, 12(sp)
+; RV32-NEXT: sw a0, 8(sp)
+; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu
+; RV32-NEXT: addi a0, sp, 8
+; RV32-NEXT: vlse64.v v24, (a0), zero
+; RV32-NEXT: vmul.vv v8, v16, v24, v0.t
+; RV32-NEXT: addi sp, sp, 16
+; RV32-NEXT: ret
+;
+; RV64-LABEL: intrinsic_vmul_mask_vx_nxv8i64_nxv8i64_i64:
+; RV64: # %bb.0: # %entry
+; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, mu
+; RV64-NEXT: vmul.vx v8, v16, a0, v0.t
+; RV64-NEXT: ret
entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vmul.mask.nxv8i64.i64(
<vscale x 8 x i64> %0,
<vscale x 8 x i64> %1,
i64 %2,
<vscale x 8 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 8 x i64> %a
}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmulh-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vmulh-rv64.ll
deleted file mode 100644
index 2fd93845e4be2..0000000000000
--- a/llvm/test/CodeGen/RISCV/rvv/vmulh-rv64.ll
+++ /dev/null
@@ -1,2074 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs \
-; RUN: < %s | FileCheck %s
-declare <vscale x 1 x i8> @llvm.riscv.vmulh.nxv1i8.nxv1i8(
- <vscale x 1 x i8>,
- <vscale x 1 x i8>,
- <vscale x 1 x i8>,
- i64);
-
-define <vscale x 1 x i8> @intrinsic_vmulh_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmulh_vv_nxv1i8_nxv1i8_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
-; CHECK-NEXT: vmulh.vv v8, v8, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i8> @llvm.riscv.vmulh.nxv1i8.nxv1i8(
- <vscale x 1 x i8> undef,
- <vscale x 1 x i8> %0,
- <vscale x 1 x i8> %1,
- i64 %2)
-
- ret <vscale x 1 x i8> %a
-}
-
-declare <vscale x 1 x i8> @llvm.riscv.vmulh.mask.nxv1i8.nxv1i8(
- <vscale x 1 x i8>,
- <vscale x 1 x i8>,
- <vscale x 1 x i8>,
- <vscale x 1 x i1>,
- i64,
- i64);
-
-define <vscale x 1 x i8> @intrinsic_vmulh_mask_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmulh_mask_vv_nxv1i8_nxv1i8_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
-; CHECK-NEXT: vmulh.vv v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i8> @llvm.riscv.vmulh.mask.nxv1i8.nxv1i8(
- <vscale x 1 x i8> %0,
- <vscale x 1 x i8> %1,
- <vscale x 1 x i8> %2,
- <vscale x 1 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 1 x i8> %a
-}
-
-declare <vscale x 2 x i8> @llvm.riscv.vmulh.nxv2i8.nxv2i8(
- <vscale x 2 x i8>,
- <vscale x 2 x i8>,
- <vscale x 2 x i8>,
- i64);
-
-define <vscale x 2 x i8> @intrinsic_vmulh_vv_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmulh_vv_nxv2i8_nxv2i8_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
-; CHECK-NEXT: vmulh.vv v8, v8, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i8> @llvm.riscv.vmulh.nxv2i8.nxv2i8(
- <vscale x 2 x i8> undef,
- <vscale x 2 x i8> %0,
- <vscale x 2 x i8> %1,
- i64 %2)
-
- ret <vscale x 2 x i8> %a
-}
-
-declare <vscale x 2 x i8> @llvm.riscv.vmulh.mask.nxv2i8.nxv2i8(
- <vscale x 2 x i8>,
- <vscale x 2 x i8>,
- <vscale x 2 x i8>,
- <vscale x 2 x i1>,
- i64,
- i64);
-
-define <vscale x 2 x i8> @intrinsic_vmulh_mask_vv_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmulh_mask_vv_nxv2i8_nxv2i8_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
-; CHECK-NEXT: vmulh.vv v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i8> @llvm.riscv.vmulh.mask.nxv2i8.nxv2i8(
- <vscale x 2 x i8> %0,
- <vscale x 2 x i8> %1,
- <vscale x 2 x i8> %2,
- <vscale x 2 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 2 x i8> %a
-}
-
-declare <vscale x 4 x i8> @llvm.riscv.vmulh.nxv4i8.nxv4i8(
- <vscale x 4 x i8>,
- <vscale x 4 x i8>,
- <vscale x 4 x i8>,
- i64);
-
-define <vscale x 4 x i8> @intrinsic_vmulh_vv_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmulh_vv_nxv4i8_nxv4i8_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
-; CHECK-NEXT: vmulh.vv v8, v8, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i8> @llvm.riscv.vmulh.nxv4i8.nxv4i8(
- <vscale x 4 x i8> undef,
- <vscale x 4 x i8> %0,
- <vscale x 4 x i8> %1,
- i64 %2)
-
- ret <vscale x 4 x i8> %a
-}
-
-declare <vscale x 4 x i8> @llvm.riscv.vmulh.mask.nxv4i8.nxv4i8(
- <vscale x 4 x i8>,
- <vscale x 4 x i8>,
- <vscale x 4 x i8>,
- <vscale x 4 x i1>,
- i64,
- i64);
-
-define <vscale x 4 x i8> @intrinsic_vmulh_mask_vv_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmulh_mask_vv_nxv4i8_nxv4i8_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
-; CHECK-NEXT: vmulh.vv v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i8> @llvm.riscv.vmulh.mask.nxv4i8.nxv4i8(
- <vscale x 4 x i8> %0,
- <vscale x 4 x i8> %1,
- <vscale x 4 x i8> %2,
- <vscale x 4 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 4 x i8> %a
-}
-
-declare <vscale x 8 x i8> @llvm.riscv.vmulh.nxv8i8.nxv8i8(
- <vscale x 8 x i8>,
- <vscale x 8 x i8>,
- <vscale x 8 x i8>,
- i64);
-
-define <vscale x 8 x i8> @intrinsic_vmulh_vv_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmulh_vv_nxv8i8_nxv8i8_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
-; CHECK-NEXT: vmulh.vv v8, v8, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i8> @llvm.riscv.vmulh.nxv8i8.nxv8i8(
- <vscale x 8 x i8> undef,
- <vscale x 8 x i8> %0,
- <vscale x 8 x i8> %1,
- i64 %2)
-
- ret <vscale x 8 x i8> %a
-}
-
-declare <vscale x 8 x i8> @llvm.riscv.vmulh.mask.nxv8i8.nxv8i8(
- <vscale x 8 x i8>,
- <vscale x 8 x i8>,
- <vscale x 8 x i8>,
- <vscale x 8 x i1>,
- i64,
- i64);
-
-define <vscale x 8 x i8> @intrinsic_vmulh_mask_vv_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmulh_mask_vv_nxv8i8_nxv8i8_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
-; CHECK-NEXT: vmulh.vv v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i8> @llvm.riscv.vmulh.mask.nxv8i8.nxv8i8(
- <vscale x 8 x i8> %0,
- <vscale x 8 x i8> %1,
- <vscale x 8 x i8> %2,
- <vscale x 8 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 8 x i8> %a
-}
-
-declare <vscale x 16 x i8> @llvm.riscv.vmulh.nxv16i8.nxv16i8(
- <vscale x 16 x i8>,
- <vscale x 16 x i8>,
- <vscale x 16 x i8>,
- i64);
-
-define <vscale x 16 x i8> @intrinsic_vmulh_vv_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmulh_vv_nxv16i8_nxv16i8_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
-; CHECK-NEXT: vmulh.vv v8, v8, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i8> @llvm.riscv.vmulh.nxv16i8.nxv16i8(
- <vscale x 16 x i8> undef,
- <vscale x 16 x i8> %0,
- <vscale x 16 x i8> %1,
- i64 %2)
-
- ret <vscale x 16 x i8> %a
-}
-
-declare <vscale x 16 x i8> @llvm.riscv.vmulh.mask.nxv16i8.nxv16i8(
- <vscale x 16 x i8>,
- <vscale x 16 x i8>,
- <vscale x 16 x i8>,
- <vscale x 16 x i1>,
- i64,
- i64);
-
-define <vscale x 16 x i8> @intrinsic_vmulh_mask_vv_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmulh_mask_vv_nxv16i8_nxv16i8_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
-; CHECK-NEXT: vmulh.vv v8, v10, v12, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i8> @llvm.riscv.vmulh.mask.nxv16i8.nxv16i8(
- <vscale x 16 x i8> %0,
- <vscale x 16 x i8> %1,
- <vscale x 16 x i8> %2,
- <vscale x 16 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 16 x i8> %a
-}
-
-declare <vscale x 32 x i8> @llvm.riscv.vmulh.nxv32i8.nxv32i8(
- <vscale x 32 x i8>,
- <vscale x 32 x i8>,
- <vscale x 32 x i8>,
- i64);
-
-define <vscale x 32 x i8> @intrinsic_vmulh_vv_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmulh_vv_nxv32i8_nxv32i8_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
-; CHECK-NEXT: vmulh.vv v8, v8, v12
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 32 x i8> @llvm.riscv.vmulh.nxv32i8.nxv32i8(
- <vscale x 32 x i8> undef,
- <vscale x 32 x i8> %0,
- <vscale x 32 x i8> %1,
- i64 %2)
-
- ret <vscale x 32 x i8> %a
-}
-
-declare <vscale x 32 x i8> @llvm.riscv.vmulh.mask.nxv32i8.nxv32i8(
- <vscale x 32 x i8>,
- <vscale x 32 x i8>,
- <vscale x 32 x i8>,
- <vscale x 32 x i1>,
- i64,
- i64);
-
-define <vscale x 32 x i8> @intrinsic_vmulh_mask_vv_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmulh_mask_vv_nxv32i8_nxv32i8_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
-; CHECK-NEXT: vmulh.vv v8, v12, v16, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 32 x i8> @llvm.riscv.vmulh.mask.nxv32i8.nxv32i8(
- <vscale x 32 x i8> %0,
- <vscale x 32 x i8> %1,
- <vscale x 32 x i8> %2,
- <vscale x 32 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 32 x i8> %a
-}
-
-declare <vscale x 64 x i8> @llvm.riscv.vmulh.nxv64i8.nxv64i8(
- <vscale x 64 x i8>,
- <vscale x 64 x i8>,
- <vscale x 64 x i8>,
- i64);
-
-define <vscale x 64 x i8> @intrinsic_vmulh_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmulh_vv_nxv64i8_nxv64i8_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, mu
-; CHECK-NEXT: vmulh.vv v8, v8, v16
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 64 x i8> @llvm.riscv.vmulh.nxv64i8.nxv64i8(
- <vscale x 64 x i8> undef,
- <vscale x 64 x i8> %0,
- <vscale x 64 x i8> %1,
- i64 %2)
-
- ret <vscale x 64 x i8> %a
-}
-
-declare <vscale x 64 x i8> @llvm.riscv.vmulh.mask.nxv64i8.nxv64i8(
- <vscale x 64 x i8>,
- <vscale x 64 x i8>,
- <vscale x 64 x i8>,
- <vscale x 64 x i1>,
- i64,
- i64);
-
-define <vscale x 64 x i8> @intrinsic_vmulh_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmulh_mask_vv_nxv64i8_nxv64i8_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vl8r.v v24, (a0)
-; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu
-; CHECK-NEXT: vmulh.vv v8, v16, v24, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 64 x i8> @llvm.riscv.vmulh.mask.nxv64i8.nxv64i8(
- <vscale x 64 x i8> %0,
- <vscale x 64 x i8> %1,
- <vscale x 64 x i8> %2,
- <vscale x 64 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 64 x i8> %a
-}
-
-declare <vscale x 1 x i16> @llvm.riscv.vmulh.nxv1i16.nxv1i16(
- <vscale x 1 x i16>,
- <vscale x 1 x i16>,
- <vscale x 1 x i16>,
- i64);
-
-define <vscale x 1 x i16> @intrinsic_vmulh_vv_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmulh_vv_nxv1i16_nxv1i16_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vmulh.vv v8, v8, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i16> @llvm.riscv.vmulh.nxv1i16.nxv1i16(
- <vscale x 1 x i16> undef,
- <vscale x 1 x i16> %0,
- <vscale x 1 x i16> %1,
- i64 %2)
-
- ret <vscale x 1 x i16> %a
-}
-
-declare <vscale x 1 x i16> @llvm.riscv.vmulh.mask.nxv1i16.nxv1i16(
- <vscale x 1 x i16>,
- <vscale x 1 x i16>,
- <vscale x 1 x i16>,
- <vscale x 1 x i1>,
- i64,
- i64);
-
-define <vscale x 1 x i16> @intrinsic_vmulh_mask_vv_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmulh_mask_vv_nxv1i16_nxv1i16_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vmulh.vv v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i16> @llvm.riscv.vmulh.mask.nxv1i16.nxv1i16(
- <vscale x 1 x i16> %0,
- <vscale x 1 x i16> %1,
- <vscale x 1 x i16> %2,
- <vscale x 1 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 1 x i16> %a
-}
-
-declare <vscale x 2 x i16> @llvm.riscv.vmulh.nxv2i16.nxv2i16(
- <vscale x 2 x i16>,
- <vscale x 2 x i16>,
- <vscale x 2 x i16>,
- i64);
-
-define <vscale x 2 x i16> @intrinsic_vmulh_vv_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmulh_vv_nxv2i16_nxv2i16_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vmulh.vv v8, v8, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i16> @llvm.riscv.vmulh.nxv2i16.nxv2i16(
- <vscale x 2 x i16> undef,
- <vscale x 2 x i16> %0,
- <vscale x 2 x i16> %1,
- i64 %2)
-
- ret <vscale x 2 x i16> %a
-}
-
-declare <vscale x 2 x i16> @llvm.riscv.vmulh.mask.nxv2i16.nxv2i16(
- <vscale x 2 x i16>,
- <vscale x 2 x i16>,
- <vscale x 2 x i16>,
- <vscale x 2 x i1>,
- i64,
- i64);
-
-define <vscale x 2 x i16> @intrinsic_vmulh_mask_vv_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmulh_mask_vv_nxv2i16_nxv2i16_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vmulh.vv v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i16> @llvm.riscv.vmulh.mask.nxv2i16.nxv2i16(
- <vscale x 2 x i16> %0,
- <vscale x 2 x i16> %1,
- <vscale x 2 x i16> %2,
- <vscale x 2 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 2 x i16> %a
-}
-
-declare <vscale x 4 x i16> @llvm.riscv.vmulh.nxv4i16.nxv4i16(
- <vscale x 4 x i16>,
- <vscale x 4 x i16>,
- <vscale x 4 x i16>,
- i64);
-
-define <vscale x 4 x i16> @intrinsic_vmulh_vv_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmulh_vv_nxv4i16_nxv4i16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vmulh.vv v8, v8, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i16> @llvm.riscv.vmulh.nxv4i16.nxv4i16(
- <vscale x 4 x i16> undef,
- <vscale x 4 x i16> %0,
- <vscale x 4 x i16> %1,
- i64 %2)
-
- ret <vscale x 4 x i16> %a
-}
-
-declare <vscale x 4 x i16> @llvm.riscv.vmulh.mask.nxv4i16.nxv4i16(
- <vscale x 4 x i16>,
- <vscale x 4 x i16>,
- <vscale x 4 x i16>,
- <vscale x 4 x i1>,
- i64,
- i64);
-
-define <vscale x 4 x i16> @intrinsic_vmulh_mask_vv_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmulh_mask_vv_nxv4i16_nxv4i16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vmulh.vv v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i16> @llvm.riscv.vmulh.mask.nxv4i16.nxv4i16(
- <vscale x 4 x i16> %0,
- <vscale x 4 x i16> %1,
- <vscale x 4 x i16> %2,
- <vscale x 4 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 4 x i16> %a
-}
-
-declare <vscale x 8 x i16> @llvm.riscv.vmulh.nxv8i16.nxv8i16(
- <vscale x 8 x i16>,
- <vscale x 8 x i16>,
- <vscale x 8 x i16>,
- i64);
-
-define <vscale x 8 x i16> @intrinsic_vmulh_vv_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmulh_vv_nxv8i16_nxv8i16_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vmulh.vv v8, v8, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i16> @llvm.riscv.vmulh.nxv8i16.nxv8i16(
- <vscale x 8 x i16> undef,
- <vscale x 8 x i16> %0,
- <vscale x 8 x i16> %1,
- i64 %2)
-
- ret <vscale x 8 x i16> %a
-}
-
-declare <vscale x 8 x i16> @llvm.riscv.vmulh.mask.nxv8i16.nxv8i16(
- <vscale x 8 x i16>,
- <vscale x 8 x i16>,
- <vscale x 8 x i16>,
- <vscale x 8 x i1>,
- i64,
- i64);
-
-define <vscale x 8 x i16> @intrinsic_vmulh_mask_vv_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmulh_mask_vv_nxv8i16_nxv8i16_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vmulh.vv v8, v10, v12, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i16> @llvm.riscv.vmulh.mask.nxv8i16.nxv8i16(
- <vscale x 8 x i16> %0,
- <vscale x 8 x i16> %1,
- <vscale x 8 x i16> %2,
- <vscale x 8 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 8 x i16> %a
-}
-
-declare <vscale x 16 x i16> @llvm.riscv.vmulh.nxv16i16.nxv16i16(
- <vscale x 16 x i16>,
- <vscale x 16 x i16>,
- <vscale x 16 x i16>,
- i64);
-
-define <vscale x 16 x i16> @intrinsic_vmulh_vv_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmulh_vv_nxv16i16_nxv16i16_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
-; CHECK-NEXT: vmulh.vv v8, v8, v12
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i16> @llvm.riscv.vmulh.nxv16i16.nxv16i16(
- <vscale x 16 x i16> undef,
- <vscale x 16 x i16> %0,
- <vscale x 16 x i16> %1,
- i64 %2)
-
- ret <vscale x 16 x i16> %a
-}
-
-declare <vscale x 16 x i16> @llvm.riscv.vmulh.mask.nxv16i16.nxv16i16(
- <vscale x 16 x i16>,
- <vscale x 16 x i16>,
- <vscale x 16 x i16>,
- <vscale x 16 x i1>,
- i64,
- i64);
-
-define <vscale x 16 x i16> @intrinsic_vmulh_mask_vv_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmulh_mask_vv_nxv16i16_nxv16i16_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
-; CHECK-NEXT: vmulh.vv v8, v12, v16, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i16> @llvm.riscv.vmulh.mask.nxv16i16.nxv16i16(
- <vscale x 16 x i16> %0,
- <vscale x 16 x i16> %1,
- <vscale x 16 x i16> %2,
- <vscale x 16 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 16 x i16> %a
-}
-
-declare <vscale x 32 x i16> @llvm.riscv.vmulh.nxv32i16.nxv32i16(
- <vscale x 32 x i16>,
- <vscale x 32 x i16>,
- <vscale x 32 x i16>,
- i64);
-
-define <vscale x 32 x i16> @intrinsic_vmulh_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmulh_vv_nxv32i16_nxv32i16_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, mu
-; CHECK-NEXT: vmulh.vv v8, v8, v16
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 32 x i16> @llvm.riscv.vmulh.nxv32i16.nxv32i16(
- <vscale x 32 x i16> undef,
- <vscale x 32 x i16> %0,
- <vscale x 32 x i16> %1,
- i64 %2)
-
- ret <vscale x 32 x i16> %a
-}
-
-declare <vscale x 32 x i16> @llvm.riscv.vmulh.mask.nxv32i16.nxv32i16(
- <vscale x 32 x i16>,
- <vscale x 32 x i16>,
- <vscale x 32 x i16>,
- <vscale x 32 x i1>,
- i64,
- i64);
-
-define <vscale x 32 x i16> @intrinsic_vmulh_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmulh_mask_vv_nxv32i16_nxv32i16_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vl8re16.v v24, (a0)
-; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu
-; CHECK-NEXT: vmulh.vv v8, v16, v24, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 32 x i16> @llvm.riscv.vmulh.mask.nxv32i16.nxv32i16(
- <vscale x 32 x i16> %0,
- <vscale x 32 x i16> %1,
- <vscale x 32 x i16> %2,
- <vscale x 32 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 32 x i16> %a
-}
-
-declare <vscale x 1 x i32> @llvm.riscv.vmulh.nxv1i32.nxv1i32(
- <vscale x 1 x i32>,
- <vscale x 1 x i32>,
- <vscale x 1 x i32>,
- i64);
-
-define <vscale x 1 x i32> @intrinsic_vmulh_vv_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmulh_vv_nxv1i32_nxv1i32_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vmulh.vv v8, v8, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i32> @llvm.riscv.vmulh.nxv1i32.nxv1i32(
- <vscale x 1 x i32> undef,
- <vscale x 1 x i32> %0,
- <vscale x 1 x i32> %1,
- i64 %2)
-
- ret <vscale x 1 x i32> %a
-}
-
-declare <vscale x 1 x i32> @llvm.riscv.vmulh.mask.nxv1i32.nxv1i32(
- <vscale x 1 x i32>,
- <vscale x 1 x i32>,
- <vscale x 1 x i32>,
- <vscale x 1 x i1>,
- i64,
- i64);
-
-define <vscale x 1 x i32> @intrinsic_vmulh_mask_vv_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmulh_mask_vv_nxv1i32_nxv1i32_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vmulh.vv v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i32> @llvm.riscv.vmulh.mask.nxv1i32.nxv1i32(
- <vscale x 1 x i32> %0,
- <vscale x 1 x i32> %1,
- <vscale x 1 x i32> %2,
- <vscale x 1 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 1 x i32> %a
-}
-
-declare <vscale x 2 x i32> @llvm.riscv.vmulh.nxv2i32.nxv2i32(
- <vscale x 2 x i32>,
- <vscale x 2 x i32>,
- <vscale x 2 x i32>,
- i64);
-
-define <vscale x 2 x i32> @intrinsic_vmulh_vv_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmulh_vv_nxv2i32_nxv2i32_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vmulh.vv v8, v8, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i32> @llvm.riscv.vmulh.nxv2i32.nxv2i32(
- <vscale x 2 x i32> undef,
- <vscale x 2 x i32> %0,
- <vscale x 2 x i32> %1,
- i64 %2)
-
- ret <vscale x 2 x i32> %a
-}
-
-declare <vscale x 2 x i32> @llvm.riscv.vmulh.mask.nxv2i32.nxv2i32(
- <vscale x 2 x i32>,
- <vscale x 2 x i32>,
- <vscale x 2 x i32>,
- <vscale x 2 x i1>,
- i64,
- i64);
-
-define <vscale x 2 x i32> @intrinsic_vmulh_mask_vv_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmulh_mask_vv_nxv2i32_nxv2i32_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vmulh.vv v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i32> @llvm.riscv.vmulh.mask.nxv2i32.nxv2i32(
- <vscale x 2 x i32> %0,
- <vscale x 2 x i32> %1,
- <vscale x 2 x i32> %2,
- <vscale x 2 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 2 x i32> %a
-}
-
-declare <vscale x 4 x i32> @llvm.riscv.vmulh.nxv4i32.nxv4i32(
- <vscale x 4 x i32>,
- <vscale x 4 x i32>,
- <vscale x 4 x i32>,
- i64);
-
-define <vscale x 4 x i32> @intrinsic_vmulh_vv_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmulh_vv_nxv4i32_nxv4i32_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vmulh.vv v8, v8, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i32> @llvm.riscv.vmulh.nxv4i32.nxv4i32(
- <vscale x 4 x i32> undef,
- <vscale x 4 x i32> %0,
- <vscale x 4 x i32> %1,
- i64 %2)
-
- ret <vscale x 4 x i32> %a
-}
-
-declare <vscale x 4 x i32> @llvm.riscv.vmulh.mask.nxv4i32.nxv4i32(
- <vscale x 4 x i32>,
- <vscale x 4 x i32>,
- <vscale x 4 x i32>,
- <vscale x 4 x i1>,
- i64,
- i64);
-
-define <vscale x 4 x i32> @intrinsic_vmulh_mask_vv_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmulh_mask_vv_nxv4i32_nxv4i32_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vmulh.vv v8, v10, v12, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i32> @llvm.riscv.vmulh.mask.nxv4i32.nxv4i32(
- <vscale x 4 x i32> %0,
- <vscale x 4 x i32> %1,
- <vscale x 4 x i32> %2,
- <vscale x 4 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 4 x i32> %a
-}
-
-declare <vscale x 8 x i32> @llvm.riscv.vmulh.nxv8i32.nxv8i32(
- <vscale x 8 x i32>,
- <vscale x 8 x i32>,
- <vscale x 8 x i32>,
- i64);
-
-define <vscale x 8 x i32> @intrinsic_vmulh_vv_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmulh_vv_nxv8i32_nxv8i32_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
-; CHECK-NEXT: vmulh.vv v8, v8, v12
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i32> @llvm.riscv.vmulh.nxv8i32.nxv8i32(
- <vscale x 8 x i32> undef,
- <vscale x 8 x i32> %0,
- <vscale x 8 x i32> %1,
- i64 %2)
-
- ret <vscale x 8 x i32> %a
-}
-
-declare <vscale x 8 x i32> @llvm.riscv.vmulh.mask.nxv8i32.nxv8i32(
- <vscale x 8 x i32>,
- <vscale x 8 x i32>,
- <vscale x 8 x i32>,
- <vscale x 8 x i1>,
- i64,
- i64);
-
-define <vscale x 8 x i32> @intrinsic_vmulh_mask_vv_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmulh_mask_vv_nxv8i32_nxv8i32_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
-; CHECK-NEXT: vmulh.vv v8, v12, v16, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i32> @llvm.riscv.vmulh.mask.nxv8i32.nxv8i32(
- <vscale x 8 x i32> %0,
- <vscale x 8 x i32> %1,
- <vscale x 8 x i32> %2,
- <vscale x 8 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 8 x i32> %a
-}
-
-declare <vscale x 16 x i32> @llvm.riscv.vmulh.nxv16i32.nxv16i32(
- <vscale x 16 x i32>,
- <vscale x 16 x i32>,
- <vscale x 16 x i32>,
- i64);
-
-define <vscale x 16 x i32> @intrinsic_vmulh_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmulh_vv_nxv16i32_nxv16i32_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu
-; CHECK-NEXT: vmulh.vv v8, v8, v16
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i32> @llvm.riscv.vmulh.nxv16i32.nxv16i32(
- <vscale x 16 x i32> undef,
- <vscale x 16 x i32> %0,
- <vscale x 16 x i32> %1,
- i64 %2)
-
- ret <vscale x 16 x i32> %a
-}
-
-declare <vscale x 16 x i32> @llvm.riscv.vmulh.mask.nxv16i32.nxv16i32(
- <vscale x 16 x i32>,
- <vscale x 16 x i32>,
- <vscale x 16 x i32>,
- <vscale x 16 x i1>,
- i64,
- i64);
-
-define <vscale x 16 x i32> @intrinsic_vmulh_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmulh_mask_vv_nxv16i32_nxv16i32_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vl8re32.v v24, (a0)
-; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu
-; CHECK-NEXT: vmulh.vv v8, v16, v24, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i32> @llvm.riscv.vmulh.mask.nxv16i32.nxv16i32(
- <vscale x 16 x i32> %0,
- <vscale x 16 x i32> %1,
- <vscale x 16 x i32> %2,
- <vscale x 16 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 16 x i32> %a
-}
-
-declare <vscale x 1 x i64> @llvm.riscv.vmulh.nxv1i64.nxv1i64(
- <vscale x 1 x i64>,
- <vscale x 1 x i64>,
- <vscale x 1 x i64>,
- i64);
-
-define <vscale x 1 x i64> @intrinsic_vmulh_vv_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmulh_vv_nxv1i64_nxv1i64_nxv1i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
-; CHECK-NEXT: vmulh.vv v8, v8, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i64> @llvm.riscv.vmulh.nxv1i64.nxv1i64(
- <vscale x 1 x i64> undef,
- <vscale x 1 x i64> %0,
- <vscale x 1 x i64> %1,
- i64 %2)
-
- ret <vscale x 1 x i64> %a
-}
-
-declare <vscale x 1 x i64> @llvm.riscv.vmulh.mask.nxv1i64.nxv1i64(
- <vscale x 1 x i64>,
- <vscale x 1 x i64>,
- <vscale x 1 x i64>,
- <vscale x 1 x i1>,
- i64,
- i64);
-
-define <vscale x 1 x i64> @intrinsic_vmulh_mask_vv_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmulh_mask_vv_nxv1i64_nxv1i64_nxv1i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
-; CHECK-NEXT: vmulh.vv v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i64> @llvm.riscv.vmulh.mask.nxv1i64.nxv1i64(
- <vscale x 1 x i64> %0,
- <vscale x 1 x i64> %1,
- <vscale x 1 x i64> %2,
- <vscale x 1 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 1 x i64> %a
-}
-
-declare <vscale x 2 x i64> @llvm.riscv.vmulh.nxv2i64.nxv2i64(
- <vscale x 2 x i64>,
- <vscale x 2 x i64>,
- <vscale x 2 x i64>,
- i64);
-
-define <vscale x 2 x i64> @intrinsic_vmulh_vv_nxv2i64_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmulh_vv_nxv2i64_nxv2i64_nxv2i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
-; CHECK-NEXT: vmulh.vv v8, v8, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i64> @llvm.riscv.vmulh.nxv2i64.nxv2i64(
- <vscale x 2 x i64> undef,
- <vscale x 2 x i64> %0,
- <vscale x 2 x i64> %1,
- i64 %2)
-
- ret <vscale x 2 x i64> %a
-}
-
-declare <vscale x 2 x i64> @llvm.riscv.vmulh.mask.nxv2i64.nxv2i64(
- <vscale x 2 x i64>,
- <vscale x 2 x i64>,
- <vscale x 2 x i64>,
- <vscale x 2 x i1>,
- i64,
- i64);
-
-define <vscale x 2 x i64> @intrinsic_vmulh_mask_vv_nxv2i64_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmulh_mask_vv_nxv2i64_nxv2i64_nxv2i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
-; CHECK-NEXT: vmulh.vv v8, v10, v12, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i64> @llvm.riscv.vmulh.mask.nxv2i64.nxv2i64(
- <vscale x 2 x i64> %0,
- <vscale x 2 x i64> %1,
- <vscale x 2 x i64> %2,
- <vscale x 2 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 2 x i64> %a
-}
-
-declare <vscale x 4 x i64> @llvm.riscv.vmulh.nxv4i64.nxv4i64(
- <vscale x 4 x i64>,
- <vscale x 4 x i64>,
- <vscale x 4 x i64>,
- i64);
-
-define <vscale x 4 x i64> @intrinsic_vmulh_vv_nxv4i64_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmulh_vv_nxv4i64_nxv4i64_nxv4i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
-; CHECK-NEXT: vmulh.vv v8, v8, v12
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i64> @llvm.riscv.vmulh.nxv4i64.nxv4i64(
- <vscale x 4 x i64> undef,
- <vscale x 4 x i64> %0,
- <vscale x 4 x i64> %1,
- i64 %2)
-
- ret <vscale x 4 x i64> %a
-}
-
-declare <vscale x 4 x i64> @llvm.riscv.vmulh.mask.nxv4i64.nxv4i64(
- <vscale x 4 x i64>,
- <vscale x 4 x i64>,
- <vscale x 4 x i64>,
- <vscale x 4 x i1>,
- i64,
- i64);
-
-define <vscale x 4 x i64> @intrinsic_vmulh_mask_vv_nxv4i64_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmulh_mask_vv_nxv4i64_nxv4i64_nxv4i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
-; CHECK-NEXT: vmulh.vv v8, v12, v16, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i64> @llvm.riscv.vmulh.mask.nxv4i64.nxv4i64(
- <vscale x 4 x i64> %0,
- <vscale x 4 x i64> %1,
- <vscale x 4 x i64> %2,
- <vscale x 4 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 4 x i64> %a
-}
-
-declare <vscale x 8 x i64> @llvm.riscv.vmulh.nxv8i64.nxv8i64(
- <vscale x 8 x i64>,
- <vscale x 8 x i64>,
- <vscale x 8 x i64>,
- i64);
-
-define <vscale x 8 x i64> @intrinsic_vmulh_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmulh_vv_nxv8i64_nxv8i64_nxv8i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu
-; CHECK-NEXT: vmulh.vv v8, v8, v16
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i64> @llvm.riscv.vmulh.nxv8i64.nxv8i64(
- <vscale x 8 x i64> undef,
- <vscale x 8 x i64> %0,
- <vscale x 8 x i64> %1,
- i64 %2)
-
- ret <vscale x 8 x i64> %a
-}
-
-declare <vscale x 8 x i64> @llvm.riscv.vmulh.mask.nxv8i64.nxv8i64(
- <vscale x 8 x i64>,
- <vscale x 8 x i64>,
- <vscale x 8 x i64>,
- <vscale x 8 x i1>,
- i64,
- i64);
-
-define <vscale x 8 x i64> @intrinsic_vmulh_mask_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmulh_mask_vv_nxv8i64_nxv8i64_nxv8i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vl8re64.v v24, (a0)
-; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu
-; CHECK-NEXT: vmulh.vv v8, v16, v24, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i64> @llvm.riscv.vmulh.mask.nxv8i64.nxv8i64(
- <vscale x 8 x i64> %0,
- <vscale x 8 x i64> %1,
- <vscale x 8 x i64> %2,
- <vscale x 8 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 8 x i64> %a
-}
-
-declare <vscale x 1 x i8> @llvm.riscv.vmulh.nxv1i8.i8(
- <vscale x 1 x i8>,
- <vscale x 1 x i8>,
- i8,
- i64);
-
-define <vscale x 1 x i8> @intrinsic_vmulh_vx_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, i8 %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmulh_vx_nxv1i8_nxv1i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
-; CHECK-NEXT: vmulh.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i8> @llvm.riscv.vmulh.nxv1i8.i8(
- <vscale x 1 x i8> undef,
- <vscale x 1 x i8> %0,
- i8 %1,
- i64 %2)
-
- ret <vscale x 1 x i8> %a
-}
-
-declare <vscale x 1 x i8> @llvm.riscv.vmulh.mask.nxv1i8.i8(
- <vscale x 1 x i8>,
- <vscale x 1 x i8>,
- i8,
- <vscale x 1 x i1>,
- i64,
- i64);
-
-define <vscale x 1 x i8> @intrinsic_vmulh_mask_vx_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmulh_mask_vx_nxv1i8_nxv1i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
-; CHECK-NEXT: vmulh.vx v8, v9, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i8> @llvm.riscv.vmulh.mask.nxv1i8.i8(
- <vscale x 1 x i8> %0,
- <vscale x 1 x i8> %1,
- i8 %2,
- <vscale x 1 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 1 x i8> %a
-}
-
-declare <vscale x 2 x i8> @llvm.riscv.vmulh.nxv2i8.i8(
- <vscale x 2 x i8>,
- <vscale x 2 x i8>,
- i8,
- i64);
-
-define <vscale x 2 x i8> @intrinsic_vmulh_vx_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, i8 %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmulh_vx_nxv2i8_nxv2i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
-; CHECK-NEXT: vmulh.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i8> @llvm.riscv.vmulh.nxv2i8.i8(
- <vscale x 2 x i8> undef,
- <vscale x 2 x i8> %0,
- i8 %1,
- i64 %2)
-
- ret <vscale x 2 x i8> %a
-}
-
-declare <vscale x 2 x i8> @llvm.riscv.vmulh.mask.nxv2i8.i8(
- <vscale x 2 x i8>,
- <vscale x 2 x i8>,
- i8,
- <vscale x 2 x i1>,
- i64,
- i64);
-
-define <vscale x 2 x i8> @intrinsic_vmulh_mask_vx_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmulh_mask_vx_nxv2i8_nxv2i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
-; CHECK-NEXT: vmulh.vx v8, v9, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i8> @llvm.riscv.vmulh.mask.nxv2i8.i8(
- <vscale x 2 x i8> %0,
- <vscale x 2 x i8> %1,
- i8 %2,
- <vscale x 2 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 2 x i8> %a
-}
-
-declare <vscale x 4 x i8> @llvm.riscv.vmulh.nxv4i8.i8(
- <vscale x 4 x i8>,
- <vscale x 4 x i8>,
- i8,
- i64);
-
-define <vscale x 4 x i8> @intrinsic_vmulh_vx_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, i8 %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmulh_vx_nxv4i8_nxv4i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
-; CHECK-NEXT: vmulh.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i8> @llvm.riscv.vmulh.nxv4i8.i8(
- <vscale x 4 x i8> undef,
- <vscale x 4 x i8> %0,
- i8 %1,
- i64 %2)
-
- ret <vscale x 4 x i8> %a
-}
-
-declare <vscale x 4 x i8> @llvm.riscv.vmulh.mask.nxv4i8.i8(
- <vscale x 4 x i8>,
- <vscale x 4 x i8>,
- i8,
- <vscale x 4 x i1>,
- i64,
- i64);
-
-define <vscale x 4 x i8> @intrinsic_vmulh_mask_vx_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmulh_mask_vx_nxv4i8_nxv4i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
-; CHECK-NEXT: vmulh.vx v8, v9, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i8> @llvm.riscv.vmulh.mask.nxv4i8.i8(
- <vscale x 4 x i8> %0,
- <vscale x 4 x i8> %1,
- i8 %2,
- <vscale x 4 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 4 x i8> %a
-}
-
-declare <vscale x 8 x i8> @llvm.riscv.vmulh.nxv8i8.i8(
- <vscale x 8 x i8>,
- <vscale x 8 x i8>,
- i8,
- i64);
-
-define <vscale x 8 x i8> @intrinsic_vmulh_vx_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, i8 %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmulh_vx_nxv8i8_nxv8i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
-; CHECK-NEXT: vmulh.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i8> @llvm.riscv.vmulh.nxv8i8.i8(
- <vscale x 8 x i8> undef,
- <vscale x 8 x i8> %0,
- i8 %1,
- i64 %2)
-
- ret <vscale x 8 x i8> %a
-}
-
-declare <vscale x 8 x i8> @llvm.riscv.vmulh.mask.nxv8i8.i8(
- <vscale x 8 x i8>,
- <vscale x 8 x i8>,
- i8,
- <vscale x 8 x i1>,
- i64,
- i64);
-
-define <vscale x 8 x i8> @intrinsic_vmulh_mask_vx_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmulh_mask_vx_nxv8i8_nxv8i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
-; CHECK-NEXT: vmulh.vx v8, v9, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i8> @llvm.riscv.vmulh.mask.nxv8i8.i8(
- <vscale x 8 x i8> %0,
- <vscale x 8 x i8> %1,
- i8 %2,
- <vscale x 8 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 8 x i8> %a
-}
-
-declare <vscale x 16 x i8> @llvm.riscv.vmulh.nxv16i8.i8(
- <vscale x 16 x i8>,
- <vscale x 16 x i8>,
- i8,
- i64);
-
-define <vscale x 16 x i8> @intrinsic_vmulh_vx_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, i8 %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmulh_vx_nxv16i8_nxv16i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
-; CHECK-NEXT: vmulh.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i8> @llvm.riscv.vmulh.nxv16i8.i8(
- <vscale x 16 x i8> undef,
- <vscale x 16 x i8> %0,
- i8 %1,
- i64 %2)
-
- ret <vscale x 16 x i8> %a
-}
-
-declare <vscale x 16 x i8> @llvm.riscv.vmulh.mask.nxv16i8.i8(
- <vscale x 16 x i8>,
- <vscale x 16 x i8>,
- i8,
- <vscale x 16 x i1>,
- i64,
- i64);
-
-define <vscale x 16 x i8> @intrinsic_vmulh_mask_vx_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmulh_mask_vx_nxv16i8_nxv16i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
-; CHECK-NEXT: vmulh.vx v8, v10, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i8> @llvm.riscv.vmulh.mask.nxv16i8.i8(
- <vscale x 16 x i8> %0,
- <vscale x 16 x i8> %1,
- i8 %2,
- <vscale x 16 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 16 x i8> %a
-}
-
-declare <vscale x 32 x i8> @llvm.riscv.vmulh.nxv32i8.i8(
- <vscale x 32 x i8>,
- <vscale x 32 x i8>,
- i8,
- i64);
-
-define <vscale x 32 x i8> @intrinsic_vmulh_vx_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, i8 %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmulh_vx_nxv32i8_nxv32i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
-; CHECK-NEXT: vmulh.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 32 x i8> @llvm.riscv.vmulh.nxv32i8.i8(
- <vscale x 32 x i8> undef,
- <vscale x 32 x i8> %0,
- i8 %1,
- i64 %2)
-
- ret <vscale x 32 x i8> %a
-}
-
-declare <vscale x 32 x i8> @llvm.riscv.vmulh.mask.nxv32i8.i8(
- <vscale x 32 x i8>,
- <vscale x 32 x i8>,
- i8,
- <vscale x 32 x i1>,
- i64,
- i64);
-
-define <vscale x 32 x i8> @intrinsic_vmulh_mask_vx_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmulh_mask_vx_nxv32i8_nxv32i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
-; CHECK-NEXT: vmulh.vx v8, v12, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 32 x i8> @llvm.riscv.vmulh.mask.nxv32i8.i8(
- <vscale x 32 x i8> %0,
- <vscale x 32 x i8> %1,
- i8 %2,
- <vscale x 32 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 32 x i8> %a
-}
-
-declare <vscale x 64 x i8> @llvm.riscv.vmulh.nxv64i8.i8(
- <vscale x 64 x i8>,
- <vscale x 64 x i8>,
- i8,
- i64);
-
-define <vscale x 64 x i8> @intrinsic_vmulh_vx_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, i8 %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmulh_vx_nxv64i8_nxv64i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu
-; CHECK-NEXT: vmulh.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 64 x i8> @llvm.riscv.vmulh.nxv64i8.i8(
- <vscale x 64 x i8> undef,
- <vscale x 64 x i8> %0,
- i8 %1,
- i64 %2)
-
- ret <vscale x 64 x i8> %a
-}
-
-declare <vscale x 64 x i8> @llvm.riscv.vmulh.mask.nxv64i8.i8(
- <vscale x 64 x i8>,
- <vscale x 64 x i8>,
- i8,
- <vscale x 64 x i1>,
- i64,
- i64);
-
-define <vscale x 64 x i8> @intrinsic_vmulh_mask_vx_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i8 %2, <vscale x 64 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmulh_mask_vx_nxv64i8_nxv64i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu
-; CHECK-NEXT: vmulh.vx v8, v16, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 64 x i8> @llvm.riscv.vmulh.mask.nxv64i8.i8(
- <vscale x 64 x i8> %0,
- <vscale x 64 x i8> %1,
- i8 %2,
- <vscale x 64 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 64 x i8> %a
-}
-
-declare <vscale x 1 x i16> @llvm.riscv.vmulh.nxv1i16.i16(
- <vscale x 1 x i16>,
- <vscale x 1 x i16>,
- i16,
- i64);
-
-define <vscale x 1 x i16> @intrinsic_vmulh_vx_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, i16 %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmulh_vx_nxv1i16_nxv1i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
-; CHECK-NEXT: vmulh.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i16> @llvm.riscv.vmulh.nxv1i16.i16(
- <vscale x 1 x i16> undef,
- <vscale x 1 x i16> %0,
- i16 %1,
- i64 %2)
-
- ret <vscale x 1 x i16> %a
-}
-
-declare <vscale x 1 x i16> @llvm.riscv.vmulh.mask.nxv1i16.i16(
- <vscale x 1 x i16>,
- <vscale x 1 x i16>,
- i16,
- <vscale x 1 x i1>,
- i64,
- i64);
-
-define <vscale x 1 x i16> @intrinsic_vmulh_mask_vx_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmulh_mask_vx_nxv1i16_nxv1i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
-; CHECK-NEXT: vmulh.vx v8, v9, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i16> @llvm.riscv.vmulh.mask.nxv1i16.i16(
- <vscale x 1 x i16> %0,
- <vscale x 1 x i16> %1,
- i16 %2,
- <vscale x 1 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 1 x i16> %a
-}
-
-declare <vscale x 2 x i16> @llvm.riscv.vmulh.nxv2i16.i16(
- <vscale x 2 x i16>,
- <vscale x 2 x i16>,
- i16,
- i64);
-
-define <vscale x 2 x i16> @intrinsic_vmulh_vx_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, i16 %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmulh_vx_nxv2i16_nxv2i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
-; CHECK-NEXT: vmulh.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i16> @llvm.riscv.vmulh.nxv2i16.i16(
- <vscale x 2 x i16> undef,
- <vscale x 2 x i16> %0,
- i16 %1,
- i64 %2)
-
- ret <vscale x 2 x i16> %a
-}
-
-declare <vscale x 2 x i16> @llvm.riscv.vmulh.mask.nxv2i16.i16(
- <vscale x 2 x i16>,
- <vscale x 2 x i16>,
- i16,
- <vscale x 2 x i1>,
- i64,
- i64);
-
-define <vscale x 2 x i16> @intrinsic_vmulh_mask_vx_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmulh_mask_vx_nxv2i16_nxv2i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
-; CHECK-NEXT: vmulh.vx v8, v9, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i16> @llvm.riscv.vmulh.mask.nxv2i16.i16(
- <vscale x 2 x i16> %0,
- <vscale x 2 x i16> %1,
- i16 %2,
- <vscale x 2 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 2 x i16> %a
-}
-
-declare <vscale x 4 x i16> @llvm.riscv.vmulh.nxv4i16.i16(
- <vscale x 4 x i16>,
- <vscale x 4 x i16>,
- i16,
- i64);
-
-define <vscale x 4 x i16> @intrinsic_vmulh_vx_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, i16 %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmulh_vx_nxv4i16_nxv4i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
-; CHECK-NEXT: vmulh.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i16> @llvm.riscv.vmulh.nxv4i16.i16(
- <vscale x 4 x i16> undef,
- <vscale x 4 x i16> %0,
- i16 %1,
- i64 %2)
-
- ret <vscale x 4 x i16> %a
-}
-
-declare <vscale x 4 x i16> @llvm.riscv.vmulh.mask.nxv4i16.i16(
- <vscale x 4 x i16>,
- <vscale x 4 x i16>,
- i16,
- <vscale x 4 x i1>,
- i64,
- i64);
-
-define <vscale x 4 x i16> @intrinsic_vmulh_mask_vx_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmulh_mask_vx_nxv4i16_nxv4i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
-; CHECK-NEXT: vmulh.vx v8, v9, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i16> @llvm.riscv.vmulh.mask.nxv4i16.i16(
- <vscale x 4 x i16> %0,
- <vscale x 4 x i16> %1,
- i16 %2,
- <vscale x 4 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 4 x i16> %a
-}
-
-declare <vscale x 8 x i16> @llvm.riscv.vmulh.nxv8i16.i16(
- <vscale x 8 x i16>,
- <vscale x 8 x i16>,
- i16,
- i64);
-
-define <vscale x 8 x i16> @intrinsic_vmulh_vx_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, i16 %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmulh_vx_nxv8i16_nxv8i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
-; CHECK-NEXT: vmulh.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i16> @llvm.riscv.vmulh.nxv8i16.i16(
- <vscale x 8 x i16> undef,
- <vscale x 8 x i16> %0,
- i16 %1,
- i64 %2)
-
- ret <vscale x 8 x i16> %a
-}
-
-declare <vscale x 8 x i16> @llvm.riscv.vmulh.mask.nxv8i16.i16(
- <vscale x 8 x i16>,
- <vscale x 8 x i16>,
- i16,
- <vscale x 8 x i1>,
- i64,
- i64);
-
-define <vscale x 8 x i16> @intrinsic_vmulh_mask_vx_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmulh_mask_vx_nxv8i16_nxv8i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
-; CHECK-NEXT: vmulh.vx v8, v10, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i16> @llvm.riscv.vmulh.mask.nxv8i16.i16(
- <vscale x 8 x i16> %0,
- <vscale x 8 x i16> %1,
- i16 %2,
- <vscale x 8 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 8 x i16> %a
-}
-
-declare <vscale x 16 x i16> @llvm.riscv.vmulh.nxv16i16.i16(
- <vscale x 16 x i16>,
- <vscale x 16 x i16>,
- i16,
- i64);
-
-define <vscale x 16 x i16> @intrinsic_vmulh_vx_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, i16 %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmulh_vx_nxv16i16_nxv16i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
-; CHECK-NEXT: vmulh.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i16> @llvm.riscv.vmulh.nxv16i16.i16(
- <vscale x 16 x i16> undef,
- <vscale x 16 x i16> %0,
- i16 %1,
- i64 %2)
-
- ret <vscale x 16 x i16> %a
-}
-
-declare <vscale x 16 x i16> @llvm.riscv.vmulh.mask.nxv16i16.i16(
- <vscale x 16 x i16>,
- <vscale x 16 x i16>,
- i16,
- <vscale x 16 x i1>,
- i64,
- i64);
-
-define <vscale x 16 x i16> @intrinsic_vmulh_mask_vx_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmulh_mask_vx_nxv16i16_nxv16i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
-; CHECK-NEXT: vmulh.vx v8, v12, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i16> @llvm.riscv.vmulh.mask.nxv16i16.i16(
- <vscale x 16 x i16> %0,
- <vscale x 16 x i16> %1,
- i16 %2,
- <vscale x 16 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 16 x i16> %a
-}
-
-declare <vscale x 32 x i16> @llvm.riscv.vmulh.nxv32i16.i16(
- <vscale x 32 x i16>,
- <vscale x 32 x i16>,
- i16,
- i64);
-
-define <vscale x 32 x i16> @intrinsic_vmulh_vx_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, i16 %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmulh_vx_nxv32i16_nxv32i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu
-; CHECK-NEXT: vmulh.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 32 x i16> @llvm.riscv.vmulh.nxv32i16.i16(
- <vscale x 32 x i16> undef,
- <vscale x 32 x i16> %0,
- i16 %1,
- i64 %2)
-
- ret <vscale x 32 x i16> %a
-}
-
-declare <vscale x 32 x i16> @llvm.riscv.vmulh.mask.nxv32i16.i16(
- <vscale x 32 x i16>,
- <vscale x 32 x i16>,
- i16,
- <vscale x 32 x i1>,
- i64,
- i64);
-
-define <vscale x 32 x i16> @intrinsic_vmulh_mask_vx_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, i16 %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmulh_mask_vx_nxv32i16_nxv32i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu
-; CHECK-NEXT: vmulh.vx v8, v16, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 32 x i16> @llvm.riscv.vmulh.mask.nxv32i16.i16(
- <vscale x 32 x i16> %0,
- <vscale x 32 x i16> %1,
- i16 %2,
- <vscale x 32 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 32 x i16> %a
-}
-
-declare <vscale x 1 x i32> @llvm.riscv.vmulh.nxv1i32.i32(
- <vscale x 1 x i32>,
- <vscale x 1 x i32>,
- i32,
- i64);
-
-define <vscale x 1 x i32> @intrinsic_vmulh_vx_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, i32 %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmulh_vx_nxv1i32_nxv1i32_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
-; CHECK-NEXT: vmulh.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i32> @llvm.riscv.vmulh.nxv1i32.i32(
- <vscale x 1 x i32> undef,
- <vscale x 1 x i32> %0,
- i32 %1,
- i64 %2)
-
- ret <vscale x 1 x i32> %a
-}
-
-declare <vscale x 1 x i32> @llvm.riscv.vmulh.mask.nxv1i32.i32(
- <vscale x 1 x i32>,
- <vscale x 1 x i32>,
- i32,
- <vscale x 1 x i1>,
- i64,
- i64);
-
-define <vscale x 1 x i32> @intrinsic_vmulh_mask_vx_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmulh_mask_vx_nxv1i32_nxv1i32_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
-; CHECK-NEXT: vmulh.vx v8, v9, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i32> @llvm.riscv.vmulh.mask.nxv1i32.i32(
- <vscale x 1 x i32> %0,
- <vscale x 1 x i32> %1,
- i32 %2,
- <vscale x 1 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 1 x i32> %a
-}
-
-declare <vscale x 2 x i32> @llvm.riscv.vmulh.nxv2i32.i32(
- <vscale x 2 x i32>,
- <vscale x 2 x i32>,
- i32,
- i64);
-
-define <vscale x 2 x i32> @intrinsic_vmulh_vx_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, i32 %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmulh_vx_nxv2i32_nxv2i32_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
-; CHECK-NEXT: vmulh.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i32> @llvm.riscv.vmulh.nxv2i32.i32(
- <vscale x 2 x i32> undef,
- <vscale x 2 x i32> %0,
- i32 %1,
- i64 %2)
-
- ret <vscale x 2 x i32> %a
-}
-
-declare <vscale x 2 x i32> @llvm.riscv.vmulh.mask.nxv2i32.i32(
- <vscale x 2 x i32>,
- <vscale x 2 x i32>,
- i32,
- <vscale x 2 x i1>,
- i64,
- i64);
-
-define <vscale x 2 x i32> @intrinsic_vmulh_mask_vx_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmulh_mask_vx_nxv2i32_nxv2i32_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
-; CHECK-NEXT: vmulh.vx v8, v9, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i32> @llvm.riscv.vmulh.mask.nxv2i32.i32(
- <vscale x 2 x i32> %0,
- <vscale x 2 x i32> %1,
- i32 %2,
- <vscale x 2 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 2 x i32> %a
-}
-
-declare <vscale x 4 x i32> @llvm.riscv.vmulh.nxv4i32.i32(
- <vscale x 4 x i32>,
- <vscale x 4 x i32>,
- i32,
- i64);
-
-define <vscale x 4 x i32> @intrinsic_vmulh_vx_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, i32 %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmulh_vx_nxv4i32_nxv4i32_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; CHECK-NEXT: vmulh.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i32> @llvm.riscv.vmulh.nxv4i32.i32(
- <vscale x 4 x i32> undef,
- <vscale x 4 x i32> %0,
- i32 %1,
- i64 %2)
-
- ret <vscale x 4 x i32> %a
-}
-
-declare <vscale x 4 x i32> @llvm.riscv.vmulh.mask.nxv4i32.i32(
- <vscale x 4 x i32>,
- <vscale x 4 x i32>,
- i32,
- <vscale x 4 x i1>,
- i64,
- i64);
-
-define <vscale x 4 x i32> @intrinsic_vmulh_mask_vx_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmulh_mask_vx_nxv4i32_nxv4i32_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; CHECK-NEXT: vmulh.vx v8, v10, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i32> @llvm.riscv.vmulh.mask.nxv4i32.i32(
- <vscale x 4 x i32> %0,
- <vscale x 4 x i32> %1,
- i32 %2,
- <vscale x 4 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 4 x i32> %a
-}
-
-declare <vscale x 8 x i32> @llvm.riscv.vmulh.nxv8i32.i32(
- <vscale x 8 x i32>,
- <vscale x 8 x i32>,
- i32,
- i64);
-
-define <vscale x 8 x i32> @intrinsic_vmulh_vx_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, i32 %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmulh_vx_nxv8i32_nxv8i32_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
-; CHECK-NEXT: vmulh.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i32> @llvm.riscv.vmulh.nxv8i32.i32(
- <vscale x 8 x i32> undef,
- <vscale x 8 x i32> %0,
- i32 %1,
- i64 %2)
-
- ret <vscale x 8 x i32> %a
-}
-
-declare <vscale x 8 x i32> @llvm.riscv.vmulh.mask.nxv8i32.i32(
- <vscale x 8 x i32>,
- <vscale x 8 x i32>,
- i32,
- <vscale x 8 x i1>,
- i64,
- i64);
-
-define <vscale x 8 x i32> @intrinsic_vmulh_mask_vx_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmulh_mask_vx_nxv8i32_nxv8i32_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
-; CHECK-NEXT: vmulh.vx v8, v12, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i32> @llvm.riscv.vmulh.mask.nxv8i32.i32(
- <vscale x 8 x i32> %0,
- <vscale x 8 x i32> %1,
- i32 %2,
- <vscale x 8 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 8 x i32> %a
-}
-
-declare <vscale x 16 x i32> @llvm.riscv.vmulh.nxv16i32.i32(
- <vscale x 16 x i32>,
- <vscale x 16 x i32>,
- i32,
- i64);
-
-define <vscale x 16 x i32> @intrinsic_vmulh_vx_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, i32 %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmulh_vx_nxv16i32_nxv16i32_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu
-; CHECK-NEXT: vmulh.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i32> @llvm.riscv.vmulh.nxv16i32.i32(
- <vscale x 16 x i32> undef,
- <vscale x 16 x i32> %0,
- i32 %1,
- i64 %2)
-
- ret <vscale x 16 x i32> %a
-}
-
-declare <vscale x 16 x i32> @llvm.riscv.vmulh.mask.nxv16i32.i32(
- <vscale x 16 x i32>,
- <vscale x 16 x i32>,
- i32,
- <vscale x 16 x i1>,
- i64,
- i64);
-
-define <vscale x 16 x i32> @intrinsic_vmulh_mask_vx_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmulh_mask_vx_nxv16i32_nxv16i32_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu
-; CHECK-NEXT: vmulh.vx v8, v16, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i32> @llvm.riscv.vmulh.mask.nxv16i32.i32(
- <vscale x 16 x i32> %0,
- <vscale x 16 x i32> %1,
- i32 %2,
- <vscale x 16 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 16 x i32> %a
-}
-
-declare <vscale x 1 x i64> @llvm.riscv.vmulh.nxv1i64.i64(
- <vscale x 1 x i64>,
- <vscale x 1 x i64>,
- i64,
- i64);
-
-define <vscale x 1 x i64> @intrinsic_vmulh_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmulh_vx_nxv1i64_nxv1i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
-; CHECK-NEXT: vmulh.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i64> @llvm.riscv.vmulh.nxv1i64.i64(
- <vscale x 1 x i64> undef,
- <vscale x 1 x i64> %0,
- i64 %1,
- i64 %2)
-
- ret <vscale x 1 x i64> %a
-}
-
-declare <vscale x 1 x i64> @llvm.riscv.vmulh.mask.nxv1i64.i64(
- <vscale x 1 x i64>,
- <vscale x 1 x i64>,
- i64,
- <vscale x 1 x i1>,
- i64,
- i64);
-
-define <vscale x 1 x i64> @intrinsic_vmulh_mask_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmulh_mask_vx_nxv1i64_nxv1i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
-; CHECK-NEXT: vmulh.vx v8, v9, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i64> @llvm.riscv.vmulh.mask.nxv1i64.i64(
- <vscale x 1 x i64> %0,
- <vscale x 1 x i64> %1,
- i64 %2,
- <vscale x 1 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 1 x i64> %a
-}
-
-declare <vscale x 2 x i64> @llvm.riscv.vmulh.nxv2i64.i64(
- <vscale x 2 x i64>,
- <vscale x 2 x i64>,
- i64,
- i64);
-
-define <vscale x 2 x i64> @intrinsic_vmulh_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmulh_vx_nxv2i64_nxv2i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
-; CHECK-NEXT: vmulh.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i64> @llvm.riscv.vmulh.nxv2i64.i64(
- <vscale x 2 x i64> undef,
- <vscale x 2 x i64> %0,
- i64 %1,
- i64 %2)
-
- ret <vscale x 2 x i64> %a
-}
-
-declare <vscale x 2 x i64> @llvm.riscv.vmulh.mask.nxv2i64.i64(
- <vscale x 2 x i64>,
- <vscale x 2 x i64>,
- i64,
- <vscale x 2 x i1>,
- i64,
- i64);
-
-define <vscale x 2 x i64> @intrinsic_vmulh_mask_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmulh_mask_vx_nxv2i64_nxv2i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
-; CHECK-NEXT: vmulh.vx v8, v10, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i64> @llvm.riscv.vmulh.mask.nxv2i64.i64(
- <vscale x 2 x i64> %0,
- <vscale x 2 x i64> %1,
- i64 %2,
- <vscale x 2 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 2 x i64> %a
-}
-
-declare <vscale x 4 x i64> @llvm.riscv.vmulh.nxv4i64.i64(
- <vscale x 4 x i64>,
- <vscale x 4 x i64>,
- i64,
- i64);
-
-define <vscale x 4 x i64> @intrinsic_vmulh_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmulh_vx_nxv4i64_nxv4i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
-; CHECK-NEXT: vmulh.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i64> @llvm.riscv.vmulh.nxv4i64.i64(
- <vscale x 4 x i64> undef,
- <vscale x 4 x i64> %0,
- i64 %1,
- i64 %2)
-
- ret <vscale x 4 x i64> %a
-}
-
-declare <vscale x 4 x i64> @llvm.riscv.vmulh.mask.nxv4i64.i64(
- <vscale x 4 x i64>,
- <vscale x 4 x i64>,
- i64,
- <vscale x 4 x i1>,
- i64,
- i64);
-
-define <vscale x 4 x i64> @intrinsic_vmulh_mask_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmulh_mask_vx_nxv4i64_nxv4i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
-; CHECK-NEXT: vmulh.vx v8, v12, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i64> @llvm.riscv.vmulh.mask.nxv4i64.i64(
- <vscale x 4 x i64> %0,
- <vscale x 4 x i64> %1,
- i64 %2,
- <vscale x 4 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 4 x i64> %a
-}
-
-declare <vscale x 8 x i64> @llvm.riscv.vmulh.nxv8i64.i64(
- <vscale x 8 x i64>,
- <vscale x 8 x i64>,
- i64,
- i64);
-
-define <vscale x 8 x i64> @intrinsic_vmulh_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, i64 %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmulh_vx_nxv8i64_nxv8i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu
-; CHECK-NEXT: vmulh.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i64> @llvm.riscv.vmulh.nxv8i64.i64(
- <vscale x 8 x i64> undef,
- <vscale x 8 x i64> %0,
- i64 %1,
- i64 %2)
-
- ret <vscale x 8 x i64> %a
-}
-
-declare <vscale x 8 x i64> @llvm.riscv.vmulh.mask.nxv8i64.i64(
- <vscale x 8 x i64>,
- <vscale x 8 x i64>,
- i64,
- <vscale x 8 x i1>,
- i64,
- i64);
-
-define <vscale x 8 x i64> @intrinsic_vmulh_mask_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmulh_mask_vx_nxv8i64_nxv8i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu
-; CHECK-NEXT: vmulh.vx v8, v16, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i64> @llvm.riscv.vmulh.mask.nxv8i64.i64(
- <vscale x 8 x i64> %0,
- <vscale x 8 x i64> %1,
- i64 %2,
- <vscale x 8 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 8 x i64> %a
-}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmulh-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmulh.ll
similarity index 80%
rename from llvm/test/CodeGen/RISCV/rvv/vmulh-rv32.ll
rename to llvm/test/CodeGen/RISCV/rvv/vmulh.ll
index 4bd0f83699203..3ee681411b0d5 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vmulh-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vmulh.ll
@@ -1,13 +1,15 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs \
-; RUN: < %s | FileCheck %s
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v \
+; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,RV32
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v \
+; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,RV64
declare <vscale x 1 x i8> @llvm.riscv.vmulh.nxv1i8.nxv1i8(
<vscale x 1 x i8>,
<vscale x 1 x i8>,
<vscale x 1 x i8>,
- i32);
+ iXLen);
-define <vscale x 1 x i8> @intrinsic_vmulh_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i32 %2) nounwind {
+define <vscale x 1 x i8> @intrinsic_vmulh_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmulh_vv_nxv1i8_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
@@ -18,7 +20,7 @@ entry:
<vscale x 1 x i8> undef,
<vscale x 1 x i8> %0,
<vscale x 1 x i8> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 1 x i8> %a
}
@@ -28,10 +30,9 @@ declare <vscale x 1 x i8> @llvm.riscv.vmulh.mask.nxv1i8.nxv1i8(
<vscale x 1 x i8>,
<vscale x 1 x i8>,
<vscale x 1 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 1 x i8> @intrinsic_vmulh_mask_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+define <vscale x 1 x i8> @intrinsic_vmulh_mask_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmulh_mask_vv_nxv1i8_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
@@ -43,7 +44,7 @@ entry:
<vscale x 1 x i8> %1,
<vscale x 1 x i8> %2,
<vscale x 1 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 1 x i8> %a
}
@@ -52,9 +53,9 @@ declare <vscale x 2 x i8> @llvm.riscv.vmulh.nxv2i8.nxv2i8(
<vscale x 2 x i8>,
<vscale x 2 x i8>,
<vscale x 2 x i8>,
- i32);
+ iXLen);
-define <vscale x 2 x i8> @intrinsic_vmulh_vv_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i32 %2) nounwind {
+define <vscale x 2 x i8> @intrinsic_vmulh_vv_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmulh_vv_nxv2i8_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
@@ -65,7 +66,7 @@ entry:
<vscale x 2 x i8> undef,
<vscale x 2 x i8> %0,
<vscale x 2 x i8> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 2 x i8> %a
}
@@ -75,10 +76,9 @@ declare <vscale x 2 x i8> @llvm.riscv.vmulh.mask.nxv2i8.nxv2i8(
<vscale x 2 x i8>,
<vscale x 2 x i8>,
<vscale x 2 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 2 x i8> @intrinsic_vmulh_mask_vv_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+define <vscale x 2 x i8> @intrinsic_vmulh_mask_vv_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmulh_mask_vv_nxv2i8_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
@@ -90,7 +90,7 @@ entry:
<vscale x 2 x i8> %1,
<vscale x 2 x i8> %2,
<vscale x 2 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 2 x i8> %a
}
@@ -99,9 +99,9 @@ declare <vscale x 4 x i8> @llvm.riscv.vmulh.nxv4i8.nxv4i8(
<vscale x 4 x i8>,
<vscale x 4 x i8>,
<vscale x 4 x i8>,
- i32);
+ iXLen);
-define <vscale x 4 x i8> @intrinsic_vmulh_vv_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i32 %2) nounwind {
+define <vscale x 4 x i8> @intrinsic_vmulh_vv_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmulh_vv_nxv4i8_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
@@ -112,7 +112,7 @@ entry:
<vscale x 4 x i8> undef,
<vscale x 4 x i8> %0,
<vscale x 4 x i8> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 4 x i8> %a
}
@@ -122,10 +122,9 @@ declare <vscale x 4 x i8> @llvm.riscv.vmulh.mask.nxv4i8.nxv4i8(
<vscale x 4 x i8>,
<vscale x 4 x i8>,
<vscale x 4 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 4 x i8> @intrinsic_vmulh_mask_vv_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+define <vscale x 4 x i8> @intrinsic_vmulh_mask_vv_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmulh_mask_vv_nxv4i8_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
@@ -137,7 +136,7 @@ entry:
<vscale x 4 x i8> %1,
<vscale x 4 x i8> %2,
<vscale x 4 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 4 x i8> %a
}
@@ -146,9 +145,9 @@ declare <vscale x 8 x i8> @llvm.riscv.vmulh.nxv8i8.nxv8i8(
<vscale x 8 x i8>,
<vscale x 8 x i8>,
<vscale x 8 x i8>,
- i32);
+ iXLen);
-define <vscale x 8 x i8> @intrinsic_vmulh_vv_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i32 %2) nounwind {
+define <vscale x 8 x i8> @intrinsic_vmulh_vv_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmulh_vv_nxv8i8_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
@@ -159,7 +158,7 @@ entry:
<vscale x 8 x i8> undef,
<vscale x 8 x i8> %0,
<vscale x 8 x i8> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 8 x i8> %a
}
@@ -169,10 +168,9 @@ declare <vscale x 8 x i8> @llvm.riscv.vmulh.mask.nxv8i8.nxv8i8(
<vscale x 8 x i8>,
<vscale x 8 x i8>,
<vscale x 8 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 8 x i8> @intrinsic_vmulh_mask_vv_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+define <vscale x 8 x i8> @intrinsic_vmulh_mask_vv_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmulh_mask_vv_nxv8i8_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
@@ -184,7 +182,7 @@ entry:
<vscale x 8 x i8> %1,
<vscale x 8 x i8> %2,
<vscale x 8 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 8 x i8> %a
}
@@ -193,9 +191,9 @@ declare <vscale x 16 x i8> @llvm.riscv.vmulh.nxv16i8.nxv16i8(
<vscale x 16 x i8>,
<vscale x 16 x i8>,
<vscale x 16 x i8>,
- i32);
+ iXLen);
-define <vscale x 16 x i8> @intrinsic_vmulh_vv_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i32 %2) nounwind {
+define <vscale x 16 x i8> @intrinsic_vmulh_vv_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmulh_vv_nxv16i8_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
@@ -206,7 +204,7 @@ entry:
<vscale x 16 x i8> undef,
<vscale x 16 x i8> %0,
<vscale x 16 x i8> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 16 x i8> %a
}
@@ -216,10 +214,9 @@ declare <vscale x 16 x i8> @llvm.riscv.vmulh.mask.nxv16i8.nxv16i8(
<vscale x 16 x i8>,
<vscale x 16 x i8>,
<vscale x 16 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 16 x i8> @intrinsic_vmulh_mask_vv_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+define <vscale x 16 x i8> @intrinsic_vmulh_mask_vv_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmulh_mask_vv_nxv16i8_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
@@ -231,7 +228,7 @@ entry:
<vscale x 16 x i8> %1,
<vscale x 16 x i8> %2,
<vscale x 16 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 16 x i8> %a
}
@@ -240,9 +237,9 @@ declare <vscale x 32 x i8> @llvm.riscv.vmulh.nxv32i8.nxv32i8(
<vscale x 32 x i8>,
<vscale x 32 x i8>,
<vscale x 32 x i8>,
- i32);
+ iXLen);
-define <vscale x 32 x i8> @intrinsic_vmulh_vv_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i32 %2) nounwind {
+define <vscale x 32 x i8> @intrinsic_vmulh_vv_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmulh_vv_nxv32i8_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
@@ -253,7 +250,7 @@ entry:
<vscale x 32 x i8> undef,
<vscale x 32 x i8> %0,
<vscale x 32 x i8> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 32 x i8> %a
}
@@ -263,10 +260,9 @@ declare <vscale x 32 x i8> @llvm.riscv.vmulh.mask.nxv32i8.nxv32i8(
<vscale x 32 x i8>,
<vscale x 32 x i8>,
<vscale x 32 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 32 x i8> @intrinsic_vmulh_mask_vv_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
+define <vscale x 32 x i8> @intrinsic_vmulh_mask_vv_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmulh_mask_vv_nxv32i8_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
@@ -278,7 +274,7 @@ entry:
<vscale x 32 x i8> %1,
<vscale x 32 x i8> %2,
<vscale x 32 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 32 x i8> %a
}
@@ -287,9 +283,9 @@ declare <vscale x 64 x i8> @llvm.riscv.vmulh.nxv64i8.nxv64i8(
<vscale x 64 x i8>,
<vscale x 64 x i8>,
<vscale x 64 x i8>,
- i32);
+ iXLen);
-define <vscale x 64 x i8> @intrinsic_vmulh_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i32 %2) nounwind {
+define <vscale x 64 x i8> @intrinsic_vmulh_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmulh_vv_nxv64i8_nxv64i8_nxv64i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, mu
@@ -300,7 +296,7 @@ entry:
<vscale x 64 x i8> undef,
<vscale x 64 x i8> %0,
<vscale x 64 x i8> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 64 x i8> %a
}
@@ -310,10 +306,9 @@ declare <vscale x 64 x i8> @llvm.riscv.vmulh.mask.nxv64i8.nxv64i8(
<vscale x 64 x i8>,
<vscale x 64 x i8>,
<vscale x 64 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 64 x i8> @intrinsic_vmulh_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, i32 %4) nounwind {
+define <vscale x 64 x i8> @intrinsic_vmulh_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmulh_mask_vv_nxv64i8_nxv64i8_nxv64i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vl8r.v v24, (a0)
@@ -326,7 +321,7 @@ entry:
<vscale x 64 x i8> %1,
<vscale x 64 x i8> %2,
<vscale x 64 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 64 x i8> %a
}
@@ -335,9 +330,9 @@ declare <vscale x 1 x i16> @llvm.riscv.vmulh.nxv1i16.nxv1i16(
<vscale x 1 x i16>,
<vscale x 1 x i16>,
<vscale x 1 x i16>,
- i32);
+ iXLen);
-define <vscale x 1 x i16> @intrinsic_vmulh_vv_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i32 %2) nounwind {
+define <vscale x 1 x i16> @intrinsic_vmulh_vv_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmulh_vv_nxv1i16_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
@@ -348,7 +343,7 @@ entry:
<vscale x 1 x i16> undef,
<vscale x 1 x i16> %0,
<vscale x 1 x i16> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 1 x i16> %a
}
@@ -358,10 +353,9 @@ declare <vscale x 1 x i16> @llvm.riscv.vmulh.mask.nxv1i16.nxv1i16(
<vscale x 1 x i16>,
<vscale x 1 x i16>,
<vscale x 1 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 1 x i16> @intrinsic_vmulh_mask_vv_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+define <vscale x 1 x i16> @intrinsic_vmulh_mask_vv_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmulh_mask_vv_nxv1i16_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
@@ -373,7 +367,7 @@ entry:
<vscale x 1 x i16> %1,
<vscale x 1 x i16> %2,
<vscale x 1 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 1 x i16> %a
}
@@ -382,9 +376,9 @@ declare <vscale x 2 x i16> @llvm.riscv.vmulh.nxv2i16.nxv2i16(
<vscale x 2 x i16>,
<vscale x 2 x i16>,
<vscale x 2 x i16>,
- i32);
+ iXLen);
-define <vscale x 2 x i16> @intrinsic_vmulh_vv_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i32 %2) nounwind {
+define <vscale x 2 x i16> @intrinsic_vmulh_vv_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmulh_vv_nxv2i16_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
@@ -395,7 +389,7 @@ entry:
<vscale x 2 x i16> undef,
<vscale x 2 x i16> %0,
<vscale x 2 x i16> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 2 x i16> %a
}
@@ -405,10 +399,9 @@ declare <vscale x 2 x i16> @llvm.riscv.vmulh.mask.nxv2i16.nxv2i16(
<vscale x 2 x i16>,
<vscale x 2 x i16>,
<vscale x 2 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 2 x i16> @intrinsic_vmulh_mask_vv_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+define <vscale x 2 x i16> @intrinsic_vmulh_mask_vv_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmulh_mask_vv_nxv2i16_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
@@ -420,7 +413,7 @@ entry:
<vscale x 2 x i16> %1,
<vscale x 2 x i16> %2,
<vscale x 2 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 2 x i16> %a
}
@@ -429,9 +422,9 @@ declare <vscale x 4 x i16> @llvm.riscv.vmulh.nxv4i16.nxv4i16(
<vscale x 4 x i16>,
<vscale x 4 x i16>,
<vscale x 4 x i16>,
- i32);
+ iXLen);
-define <vscale x 4 x i16> @intrinsic_vmulh_vv_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i32 %2) nounwind {
+define <vscale x 4 x i16> @intrinsic_vmulh_vv_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmulh_vv_nxv4i16_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
@@ -442,7 +435,7 @@ entry:
<vscale x 4 x i16> undef,
<vscale x 4 x i16> %0,
<vscale x 4 x i16> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 4 x i16> %a
}
@@ -452,10 +445,9 @@ declare <vscale x 4 x i16> @llvm.riscv.vmulh.mask.nxv4i16.nxv4i16(
<vscale x 4 x i16>,
<vscale x 4 x i16>,
<vscale x 4 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 4 x i16> @intrinsic_vmulh_mask_vv_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+define <vscale x 4 x i16> @intrinsic_vmulh_mask_vv_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmulh_mask_vv_nxv4i16_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
@@ -467,7 +459,7 @@ entry:
<vscale x 4 x i16> %1,
<vscale x 4 x i16> %2,
<vscale x 4 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 4 x i16> %a
}
@@ -476,9 +468,9 @@ declare <vscale x 8 x i16> @llvm.riscv.vmulh.nxv8i16.nxv8i16(
<vscale x 8 x i16>,
<vscale x 8 x i16>,
<vscale x 8 x i16>,
- i32);
+ iXLen);
-define <vscale x 8 x i16> @intrinsic_vmulh_vv_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i32 %2) nounwind {
+define <vscale x 8 x i16> @intrinsic_vmulh_vv_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmulh_vv_nxv8i16_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
@@ -489,7 +481,7 @@ entry:
<vscale x 8 x i16> undef,
<vscale x 8 x i16> %0,
<vscale x 8 x i16> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 8 x i16> %a
}
@@ -499,10 +491,9 @@ declare <vscale x 8 x i16> @llvm.riscv.vmulh.mask.nxv8i16.nxv8i16(
<vscale x 8 x i16>,
<vscale x 8 x i16>,
<vscale x 8 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 8 x i16> @intrinsic_vmulh_mask_vv_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+define <vscale x 8 x i16> @intrinsic_vmulh_mask_vv_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmulh_mask_vv_nxv8i16_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
@@ -514,7 +505,7 @@ entry:
<vscale x 8 x i16> %1,
<vscale x 8 x i16> %2,
<vscale x 8 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 8 x i16> %a
}
@@ -523,9 +514,9 @@ declare <vscale x 16 x i16> @llvm.riscv.vmulh.nxv16i16.nxv16i16(
<vscale x 16 x i16>,
<vscale x 16 x i16>,
<vscale x 16 x i16>,
- i32);
+ iXLen);
-define <vscale x 16 x i16> @intrinsic_vmulh_vv_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i32 %2) nounwind {
+define <vscale x 16 x i16> @intrinsic_vmulh_vv_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmulh_vv_nxv16i16_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
@@ -536,7 +527,7 @@ entry:
<vscale x 16 x i16> undef,
<vscale x 16 x i16> %0,
<vscale x 16 x i16> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 16 x i16> %a
}
@@ -546,10 +537,9 @@ declare <vscale x 16 x i16> @llvm.riscv.vmulh.mask.nxv16i16.nxv16i16(
<vscale x 16 x i16>,
<vscale x 16 x i16>,
<vscale x 16 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 16 x i16> @intrinsic_vmulh_mask_vv_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+define <vscale x 16 x i16> @intrinsic_vmulh_mask_vv_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmulh_mask_vv_nxv16i16_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
@@ -561,7 +551,7 @@ entry:
<vscale x 16 x i16> %1,
<vscale x 16 x i16> %2,
<vscale x 16 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 16 x i16> %a
}
@@ -570,9 +560,9 @@ declare <vscale x 32 x i16> @llvm.riscv.vmulh.nxv32i16.nxv32i16(
<vscale x 32 x i16>,
<vscale x 32 x i16>,
<vscale x 32 x i16>,
- i32);
+ iXLen);
-define <vscale x 32 x i16> @intrinsic_vmulh_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, i32 %2) nounwind {
+define <vscale x 32 x i16> @intrinsic_vmulh_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmulh_vv_nxv32i16_nxv32i16_nxv32i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, mu
@@ -583,7 +573,7 @@ entry:
<vscale x 32 x i16> undef,
<vscale x 32 x i16> %0,
<vscale x 32 x i16> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 32 x i16> %a
}
@@ -593,10 +583,9 @@ declare <vscale x 32 x i16> @llvm.riscv.vmulh.mask.nxv32i16.nxv32i16(
<vscale x 32 x i16>,
<vscale x 32 x i16>,
<vscale x 32 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 32 x i16> @intrinsic_vmulh_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
+define <vscale x 32 x i16> @intrinsic_vmulh_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmulh_mask_vv_nxv32i16_nxv32i16_nxv32i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vl8re16.v v24, (a0)
@@ -609,7 +598,7 @@ entry:
<vscale x 32 x i16> %1,
<vscale x 32 x i16> %2,
<vscale x 32 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 32 x i16> %a
}
@@ -618,9 +607,9 @@ declare <vscale x 1 x i32> @llvm.riscv.vmulh.nxv1i32.nxv1i32(
<vscale x 1 x i32>,
<vscale x 1 x i32>,
<vscale x 1 x i32>,
- i32);
+ iXLen);
-define <vscale x 1 x i32> @intrinsic_vmulh_vv_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2) nounwind {
+define <vscale x 1 x i32> @intrinsic_vmulh_vv_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmulh_vv_nxv1i32_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
@@ -631,7 +620,7 @@ entry:
<vscale x 1 x i32> undef,
<vscale x 1 x i32> %0,
<vscale x 1 x i32> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 1 x i32> %a
}
@@ -641,10 +630,9 @@ declare <vscale x 1 x i32> @llvm.riscv.vmulh.mask.nxv1i32.nxv1i32(
<vscale x 1 x i32>,
<vscale x 1 x i32>,
<vscale x 1 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 1 x i32> @intrinsic_vmulh_mask_vv_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+define <vscale x 1 x i32> @intrinsic_vmulh_mask_vv_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmulh_mask_vv_nxv1i32_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
@@ -656,7 +644,7 @@ entry:
<vscale x 1 x i32> %1,
<vscale x 1 x i32> %2,
<vscale x 1 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 1 x i32> %a
}
@@ -665,9 +653,9 @@ declare <vscale x 2 x i32> @llvm.riscv.vmulh.nxv2i32.nxv2i32(
<vscale x 2 x i32>,
<vscale x 2 x i32>,
<vscale x 2 x i32>,
- i32);
+ iXLen);
-define <vscale x 2 x i32> @intrinsic_vmulh_vv_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2) nounwind {
+define <vscale x 2 x i32> @intrinsic_vmulh_vv_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmulh_vv_nxv2i32_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
@@ -678,7 +666,7 @@ entry:
<vscale x 2 x i32> undef,
<vscale x 2 x i32> %0,
<vscale x 2 x i32> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 2 x i32> %a
}
@@ -688,10 +676,9 @@ declare <vscale x 2 x i32> @llvm.riscv.vmulh.mask.nxv2i32.nxv2i32(
<vscale x 2 x i32>,
<vscale x 2 x i32>,
<vscale x 2 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 2 x i32> @intrinsic_vmulh_mask_vv_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+define <vscale x 2 x i32> @intrinsic_vmulh_mask_vv_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmulh_mask_vv_nxv2i32_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
@@ -703,7 +690,7 @@ entry:
<vscale x 2 x i32> %1,
<vscale x 2 x i32> %2,
<vscale x 2 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 2 x i32> %a
}
@@ -712,9 +699,9 @@ declare <vscale x 4 x i32> @llvm.riscv.vmulh.nxv4i32.nxv4i32(
<vscale x 4 x i32>,
<vscale x 4 x i32>,
<vscale x 4 x i32>,
- i32);
+ iXLen);
-define <vscale x 4 x i32> @intrinsic_vmulh_vv_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2) nounwind {
+define <vscale x 4 x i32> @intrinsic_vmulh_vv_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmulh_vv_nxv4i32_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
@@ -725,7 +712,7 @@ entry:
<vscale x 4 x i32> undef,
<vscale x 4 x i32> %0,
<vscale x 4 x i32> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 4 x i32> %a
}
@@ -735,10 +722,9 @@ declare <vscale x 4 x i32> @llvm.riscv.vmulh.mask.nxv4i32.nxv4i32(
<vscale x 4 x i32>,
<vscale x 4 x i32>,
<vscale x 4 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 4 x i32> @intrinsic_vmulh_mask_vv_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+define <vscale x 4 x i32> @intrinsic_vmulh_mask_vv_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmulh_mask_vv_nxv4i32_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
@@ -750,7 +736,7 @@ entry:
<vscale x 4 x i32> %1,
<vscale x 4 x i32> %2,
<vscale x 4 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 4 x i32> %a
}
@@ -759,9 +745,9 @@ declare <vscale x 8 x i32> @llvm.riscv.vmulh.nxv8i32.nxv8i32(
<vscale x 8 x i32>,
<vscale x 8 x i32>,
<vscale x 8 x i32>,
- i32);
+ iXLen);
-define <vscale x 8 x i32> @intrinsic_vmulh_vv_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2) nounwind {
+define <vscale x 8 x i32> @intrinsic_vmulh_vv_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmulh_vv_nxv8i32_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
@@ -772,7 +758,7 @@ entry:
<vscale x 8 x i32> undef,
<vscale x 8 x i32> %0,
<vscale x 8 x i32> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 8 x i32> %a
}
@@ -782,10 +768,9 @@ declare <vscale x 8 x i32> @llvm.riscv.vmulh.mask.nxv8i32.nxv8i32(
<vscale x 8 x i32>,
<vscale x 8 x i32>,
<vscale x 8 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 8 x i32> @intrinsic_vmulh_mask_vv_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+define <vscale x 8 x i32> @intrinsic_vmulh_mask_vv_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmulh_mask_vv_nxv8i32_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
@@ -797,7 +782,7 @@ entry:
<vscale x 8 x i32> %1,
<vscale x 8 x i32> %2,
<vscale x 8 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 8 x i32> %a
}
@@ -806,9 +791,9 @@ declare <vscale x 16 x i32> @llvm.riscv.vmulh.nxv16i32.nxv16i32(
<vscale x 16 x i32>,
<vscale x 16 x i32>,
<vscale x 16 x i32>,
- i32);
+ iXLen);
-define <vscale x 16 x i32> @intrinsic_vmulh_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2) nounwind {
+define <vscale x 16 x i32> @intrinsic_vmulh_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmulh_vv_nxv16i32_nxv16i32_nxv16i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu
@@ -819,7 +804,7 @@ entry:
<vscale x 16 x i32> undef,
<vscale x 16 x i32> %0,
<vscale x 16 x i32> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 16 x i32> %a
}
@@ -829,10 +814,9 @@ declare <vscale x 16 x i32> @llvm.riscv.vmulh.mask.nxv16i32.nxv16i32(
<vscale x 16 x i32>,
<vscale x 16 x i32>,
<vscale x 16 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 16 x i32> @intrinsic_vmulh_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+define <vscale x 16 x i32> @intrinsic_vmulh_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmulh_mask_vv_nxv16i32_nxv16i32_nxv16i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vl8re32.v v24, (a0)
@@ -845,7 +829,7 @@ entry:
<vscale x 16 x i32> %1,
<vscale x 16 x i32> %2,
<vscale x 16 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 16 x i32> %a
}
@@ -854,9 +838,9 @@ declare <vscale x 1 x i64> @llvm.riscv.vmulh.nxv1i64.nxv1i64(
<vscale x 1 x i64>,
<vscale x 1 x i64>,
<vscale x 1 x i64>,
- i32);
+ iXLen);
-define <vscale x 1 x i64> @intrinsic_vmulh_vv_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i32 %2) nounwind {
+define <vscale x 1 x i64> @intrinsic_vmulh_vv_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmulh_vv_nxv1i64_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
@@ -867,7 +851,7 @@ entry:
<vscale x 1 x i64> undef,
<vscale x 1 x i64> %0,
<vscale x 1 x i64> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 1 x i64> %a
}
@@ -877,10 +861,9 @@ declare <vscale x 1 x i64> @llvm.riscv.vmulh.mask.nxv1i64.nxv1i64(
<vscale x 1 x i64>,
<vscale x 1 x i64>,
<vscale x 1 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 1 x i64> @intrinsic_vmulh_mask_vv_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+define <vscale x 1 x i64> @intrinsic_vmulh_mask_vv_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmulh_mask_vv_nxv1i64_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
@@ -892,7 +875,7 @@ entry:
<vscale x 1 x i64> %1,
<vscale x 1 x i64> %2,
<vscale x 1 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 1 x i64> %a
}
@@ -901,9 +884,9 @@ declare <vscale x 2 x i64> @llvm.riscv.vmulh.nxv2i64.nxv2i64(
<vscale x 2 x i64>,
<vscale x 2 x i64>,
<vscale x 2 x i64>,
- i32);
+ iXLen);
-define <vscale x 2 x i64> @intrinsic_vmulh_vv_nxv2i64_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i32 %2) nounwind {
+define <vscale x 2 x i64> @intrinsic_vmulh_vv_nxv2i64_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmulh_vv_nxv2i64_nxv2i64_nxv2i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
@@ -914,7 +897,7 @@ entry:
<vscale x 2 x i64> undef,
<vscale x 2 x i64> %0,
<vscale x 2 x i64> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 2 x i64> %a
}
@@ -924,10 +907,9 @@ declare <vscale x 2 x i64> @llvm.riscv.vmulh.mask.nxv2i64.nxv2i64(
<vscale x 2 x i64>,
<vscale x 2 x i64>,
<vscale x 2 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 2 x i64> @intrinsic_vmulh_mask_vv_nxv2i64_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+define <vscale x 2 x i64> @intrinsic_vmulh_mask_vv_nxv2i64_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmulh_mask_vv_nxv2i64_nxv2i64_nxv2i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
@@ -939,7 +921,7 @@ entry:
<vscale x 2 x i64> %1,
<vscale x 2 x i64> %2,
<vscale x 2 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 2 x i64> %a
}
@@ -948,9 +930,9 @@ declare <vscale x 4 x i64> @llvm.riscv.vmulh.nxv4i64.nxv4i64(
<vscale x 4 x i64>,
<vscale x 4 x i64>,
<vscale x 4 x i64>,
- i32);
+ iXLen);
-define <vscale x 4 x i64> @intrinsic_vmulh_vv_nxv4i64_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i32 %2) nounwind {
+define <vscale x 4 x i64> @intrinsic_vmulh_vv_nxv4i64_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmulh_vv_nxv4i64_nxv4i64_nxv4i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
@@ -961,7 +943,7 @@ entry:
<vscale x 4 x i64> undef,
<vscale x 4 x i64> %0,
<vscale x 4 x i64> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 4 x i64> %a
}
@@ -971,10 +953,9 @@ declare <vscale x 4 x i64> @llvm.riscv.vmulh.mask.nxv4i64.nxv4i64(
<vscale x 4 x i64>,
<vscale x 4 x i64>,
<vscale x 4 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 4 x i64> @intrinsic_vmulh_mask_vv_nxv4i64_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+define <vscale x 4 x i64> @intrinsic_vmulh_mask_vv_nxv4i64_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmulh_mask_vv_nxv4i64_nxv4i64_nxv4i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
@@ -986,7 +967,7 @@ entry:
<vscale x 4 x i64> %1,
<vscale x 4 x i64> %2,
<vscale x 4 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 4 x i64> %a
}
@@ -995,9 +976,9 @@ declare <vscale x 8 x i64> @llvm.riscv.vmulh.nxv8i64.nxv8i64(
<vscale x 8 x i64>,
<vscale x 8 x i64>,
<vscale x 8 x i64>,
- i32);
+ iXLen);
-define <vscale x 8 x i64> @intrinsic_vmulh_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i32 %2) nounwind {
+define <vscale x 8 x i64> @intrinsic_vmulh_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmulh_vv_nxv8i64_nxv8i64_nxv8i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu
@@ -1008,7 +989,7 @@ entry:
<vscale x 8 x i64> undef,
<vscale x 8 x i64> %0,
<vscale x 8 x i64> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 8 x i64> %a
}
@@ -1018,10 +999,9 @@ declare <vscale x 8 x i64> @llvm.riscv.vmulh.mask.nxv8i64.nxv8i64(
<vscale x 8 x i64>,
<vscale x 8 x i64>,
<vscale x 8 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 8 x i64> @intrinsic_vmulh_mask_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+define <vscale x 8 x i64> @intrinsic_vmulh_mask_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmulh_mask_vv_nxv8i64_nxv8i64_nxv8i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vl8re64.v v24, (a0)
@@ -1034,7 +1014,7 @@ entry:
<vscale x 8 x i64> %1,
<vscale x 8 x i64> %2,
<vscale x 8 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 8 x i64> %a
}
@@ -1043,9 +1023,9 @@ declare <vscale x 1 x i8> @llvm.riscv.vmulh.nxv1i8.i8(
<vscale x 1 x i8>,
<vscale x 1 x i8>,
i8,
- i32);
+ iXLen);
-define <vscale x 1 x i8> @intrinsic_vmulh_vx_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, i8 %1, i32 %2) nounwind {
+define <vscale x 1 x i8> @intrinsic_vmulh_vx_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, i8 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmulh_vx_nxv1i8_nxv1i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
@@ -1056,7 +1036,7 @@ entry:
<vscale x 1 x i8> undef,
<vscale x 1 x i8> %0,
i8 %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 1 x i8> %a
}
@@ -1066,10 +1046,9 @@ declare <vscale x 1 x i8> @llvm.riscv.vmulh.mask.nxv1i8.i8(
<vscale x 1 x i8>,
i8,
<vscale x 1 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 1 x i8> @intrinsic_vmulh_mask_vx_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+define <vscale x 1 x i8> @intrinsic_vmulh_mask_vx_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmulh_mask_vx_nxv1i8_nxv1i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
@@ -1081,7 +1060,7 @@ entry:
<vscale x 1 x i8> %1,
i8 %2,
<vscale x 1 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 1 x i8> %a
}
@@ -1090,9 +1069,9 @@ declare <vscale x 2 x i8> @llvm.riscv.vmulh.nxv2i8.i8(
<vscale x 2 x i8>,
<vscale x 2 x i8>,
i8,
- i32);
+ iXLen);
-define <vscale x 2 x i8> @intrinsic_vmulh_vx_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, i8 %1, i32 %2) nounwind {
+define <vscale x 2 x i8> @intrinsic_vmulh_vx_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, i8 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmulh_vx_nxv2i8_nxv2i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
@@ -1103,7 +1082,7 @@ entry:
<vscale x 2 x i8> undef,
<vscale x 2 x i8> %0,
i8 %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 2 x i8> %a
}
@@ -1113,10 +1092,9 @@ declare <vscale x 2 x i8> @llvm.riscv.vmulh.mask.nxv2i8.i8(
<vscale x 2 x i8>,
i8,
<vscale x 2 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 2 x i8> @intrinsic_vmulh_mask_vx_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+define <vscale x 2 x i8> @intrinsic_vmulh_mask_vx_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmulh_mask_vx_nxv2i8_nxv2i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
@@ -1128,7 +1106,7 @@ entry:
<vscale x 2 x i8> %1,
i8 %2,
<vscale x 2 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 2 x i8> %a
}
@@ -1137,9 +1115,9 @@ declare <vscale x 4 x i8> @llvm.riscv.vmulh.nxv4i8.i8(
<vscale x 4 x i8>,
<vscale x 4 x i8>,
i8,
- i32);
+ iXLen);
-define <vscale x 4 x i8> @intrinsic_vmulh_vx_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, i8 %1, i32 %2) nounwind {
+define <vscale x 4 x i8> @intrinsic_vmulh_vx_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, i8 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmulh_vx_nxv4i8_nxv4i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
@@ -1150,7 +1128,7 @@ entry:
<vscale x 4 x i8> undef,
<vscale x 4 x i8> %0,
i8 %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 4 x i8> %a
}
@@ -1160,10 +1138,9 @@ declare <vscale x 4 x i8> @llvm.riscv.vmulh.mask.nxv4i8.i8(
<vscale x 4 x i8>,
i8,
<vscale x 4 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 4 x i8> @intrinsic_vmulh_mask_vx_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+define <vscale x 4 x i8> @intrinsic_vmulh_mask_vx_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmulh_mask_vx_nxv4i8_nxv4i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
@@ -1175,7 +1152,7 @@ entry:
<vscale x 4 x i8> %1,
i8 %2,
<vscale x 4 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 4 x i8> %a
}
@@ -1184,9 +1161,9 @@ declare <vscale x 8 x i8> @llvm.riscv.vmulh.nxv8i8.i8(
<vscale x 8 x i8>,
<vscale x 8 x i8>,
i8,
- i32);
+ iXLen);
-define <vscale x 8 x i8> @intrinsic_vmulh_vx_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, i8 %1, i32 %2) nounwind {
+define <vscale x 8 x i8> @intrinsic_vmulh_vx_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, i8 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmulh_vx_nxv8i8_nxv8i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
@@ -1197,7 +1174,7 @@ entry:
<vscale x 8 x i8> undef,
<vscale x 8 x i8> %0,
i8 %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 8 x i8> %a
}
@@ -1207,10 +1184,9 @@ declare <vscale x 8 x i8> @llvm.riscv.vmulh.mask.nxv8i8.i8(
<vscale x 8 x i8>,
i8,
<vscale x 8 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 8 x i8> @intrinsic_vmulh_mask_vx_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+define <vscale x 8 x i8> @intrinsic_vmulh_mask_vx_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmulh_mask_vx_nxv8i8_nxv8i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
@@ -1222,7 +1198,7 @@ entry:
<vscale x 8 x i8> %1,
i8 %2,
<vscale x 8 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 8 x i8> %a
}
@@ -1231,9 +1207,9 @@ declare <vscale x 16 x i8> @llvm.riscv.vmulh.nxv16i8.i8(
<vscale x 16 x i8>,
<vscale x 16 x i8>,
i8,
- i32);
+ iXLen);
-define <vscale x 16 x i8> @intrinsic_vmulh_vx_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, i8 %1, i32 %2) nounwind {
+define <vscale x 16 x i8> @intrinsic_vmulh_vx_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, i8 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmulh_vx_nxv16i8_nxv16i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
@@ -1244,7 +1220,7 @@ entry:
<vscale x 16 x i8> undef,
<vscale x 16 x i8> %0,
i8 %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 16 x i8> %a
}
@@ -1254,10 +1230,9 @@ declare <vscale x 16 x i8> @llvm.riscv.vmulh.mask.nxv16i8.i8(
<vscale x 16 x i8>,
i8,
<vscale x 16 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 16 x i8> @intrinsic_vmulh_mask_vx_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+define <vscale x 16 x i8> @intrinsic_vmulh_mask_vx_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmulh_mask_vx_nxv16i8_nxv16i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
@@ -1269,7 +1244,7 @@ entry:
<vscale x 16 x i8> %1,
i8 %2,
<vscale x 16 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 16 x i8> %a
}
@@ -1278,9 +1253,9 @@ declare <vscale x 32 x i8> @llvm.riscv.vmulh.nxv32i8.i8(
<vscale x 32 x i8>,
<vscale x 32 x i8>,
i8,
- i32);
+ iXLen);
-define <vscale x 32 x i8> @intrinsic_vmulh_vx_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, i8 %1, i32 %2) nounwind {
+define <vscale x 32 x i8> @intrinsic_vmulh_vx_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, i8 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmulh_vx_nxv32i8_nxv32i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
@@ -1291,7 +1266,7 @@ entry:
<vscale x 32 x i8> undef,
<vscale x 32 x i8> %0,
i8 %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 32 x i8> %a
}
@@ -1301,10 +1276,9 @@ declare <vscale x 32 x i8> @llvm.riscv.vmulh.mask.nxv32i8.i8(
<vscale x 32 x i8>,
i8,
<vscale x 32 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 32 x i8> @intrinsic_vmulh_mask_vx_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
+define <vscale x 32 x i8> @intrinsic_vmulh_mask_vx_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmulh_mask_vx_nxv32i8_nxv32i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
@@ -1316,7 +1290,7 @@ entry:
<vscale x 32 x i8> %1,
i8 %2,
<vscale x 32 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 32 x i8> %a
}
@@ -1325,9 +1299,9 @@ declare <vscale x 64 x i8> @llvm.riscv.vmulh.nxv64i8.i8(
<vscale x 64 x i8>,
<vscale x 64 x i8>,
i8,
- i32);
+ iXLen);
-define <vscale x 64 x i8> @intrinsic_vmulh_vx_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, i8 %1, i32 %2) nounwind {
+define <vscale x 64 x i8> @intrinsic_vmulh_vx_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, i8 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmulh_vx_nxv64i8_nxv64i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu
@@ -1338,7 +1312,7 @@ entry:
<vscale x 64 x i8> undef,
<vscale x 64 x i8> %0,
i8 %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 64 x i8> %a
}
@@ -1348,10 +1322,9 @@ declare <vscale x 64 x i8> @llvm.riscv.vmulh.mask.nxv64i8.i8(
<vscale x 64 x i8>,
i8,
<vscale x 64 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 64 x i8> @intrinsic_vmulh_mask_vx_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i8 %2, <vscale x 64 x i1> %3, i32 %4) nounwind {
+define <vscale x 64 x i8> @intrinsic_vmulh_mask_vx_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i8 %2, <vscale x 64 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmulh_mask_vx_nxv64i8_nxv64i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu
@@ -1363,7 +1336,7 @@ entry:
<vscale x 64 x i8> %1,
i8 %2,
<vscale x 64 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 64 x i8> %a
}
@@ -1372,9 +1345,9 @@ declare <vscale x 1 x i16> @llvm.riscv.vmulh.nxv1i16.i16(
<vscale x 1 x i16>,
<vscale x 1 x i16>,
i16,
- i32);
+ iXLen);
-define <vscale x 1 x i16> @intrinsic_vmulh_vx_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, i16 %1, i32 %2) nounwind {
+define <vscale x 1 x i16> @intrinsic_vmulh_vx_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, i16 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmulh_vx_nxv1i16_nxv1i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
@@ -1385,7 +1358,7 @@ entry:
<vscale x 1 x i16> undef,
<vscale x 1 x i16> %0,
i16 %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 1 x i16> %a
}
@@ -1395,10 +1368,9 @@ declare <vscale x 1 x i16> @llvm.riscv.vmulh.mask.nxv1i16.i16(
<vscale x 1 x i16>,
i16,
<vscale x 1 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 1 x i16> @intrinsic_vmulh_mask_vx_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+define <vscale x 1 x i16> @intrinsic_vmulh_mask_vx_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmulh_mask_vx_nxv1i16_nxv1i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
@@ -1410,7 +1382,7 @@ entry:
<vscale x 1 x i16> %1,
i16 %2,
<vscale x 1 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 1 x i16> %a
}
@@ -1419,9 +1391,9 @@ declare <vscale x 2 x i16> @llvm.riscv.vmulh.nxv2i16.i16(
<vscale x 2 x i16>,
<vscale x 2 x i16>,
i16,
- i32);
+ iXLen);
-define <vscale x 2 x i16> @intrinsic_vmulh_vx_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, i16 %1, i32 %2) nounwind {
+define <vscale x 2 x i16> @intrinsic_vmulh_vx_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, i16 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmulh_vx_nxv2i16_nxv2i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
@@ -1432,7 +1404,7 @@ entry:
<vscale x 2 x i16> undef,
<vscale x 2 x i16> %0,
i16 %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 2 x i16> %a
}
@@ -1442,10 +1414,9 @@ declare <vscale x 2 x i16> @llvm.riscv.vmulh.mask.nxv2i16.i16(
<vscale x 2 x i16>,
i16,
<vscale x 2 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 2 x i16> @intrinsic_vmulh_mask_vx_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+define <vscale x 2 x i16> @intrinsic_vmulh_mask_vx_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmulh_mask_vx_nxv2i16_nxv2i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
@@ -1457,7 +1428,7 @@ entry:
<vscale x 2 x i16> %1,
i16 %2,
<vscale x 2 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 2 x i16> %a
}
@@ -1466,9 +1437,9 @@ declare <vscale x 4 x i16> @llvm.riscv.vmulh.nxv4i16.i16(
<vscale x 4 x i16>,
<vscale x 4 x i16>,
i16,
- i32);
+ iXLen);
-define <vscale x 4 x i16> @intrinsic_vmulh_vx_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, i16 %1, i32 %2) nounwind {
+define <vscale x 4 x i16> @intrinsic_vmulh_vx_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, i16 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmulh_vx_nxv4i16_nxv4i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
@@ -1479,7 +1450,7 @@ entry:
<vscale x 4 x i16> undef,
<vscale x 4 x i16> %0,
i16 %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 4 x i16> %a
}
@@ -1489,10 +1460,9 @@ declare <vscale x 4 x i16> @llvm.riscv.vmulh.mask.nxv4i16.i16(
<vscale x 4 x i16>,
i16,
<vscale x 4 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 4 x i16> @intrinsic_vmulh_mask_vx_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+define <vscale x 4 x i16> @intrinsic_vmulh_mask_vx_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmulh_mask_vx_nxv4i16_nxv4i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
@@ -1504,7 +1474,7 @@ entry:
<vscale x 4 x i16> %1,
i16 %2,
<vscale x 4 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 4 x i16> %a
}
@@ -1513,9 +1483,9 @@ declare <vscale x 8 x i16> @llvm.riscv.vmulh.nxv8i16.i16(
<vscale x 8 x i16>,
<vscale x 8 x i16>,
i16,
- i32);
+ iXLen);
-define <vscale x 8 x i16> @intrinsic_vmulh_vx_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, i16 %1, i32 %2) nounwind {
+define <vscale x 8 x i16> @intrinsic_vmulh_vx_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, i16 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmulh_vx_nxv8i16_nxv8i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
@@ -1526,7 +1496,7 @@ entry:
<vscale x 8 x i16> undef,
<vscale x 8 x i16> %0,
i16 %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 8 x i16> %a
}
@@ -1536,10 +1506,9 @@ declare <vscale x 8 x i16> @llvm.riscv.vmulh.mask.nxv8i16.i16(
<vscale x 8 x i16>,
i16,
<vscale x 8 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 8 x i16> @intrinsic_vmulh_mask_vx_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+define <vscale x 8 x i16> @intrinsic_vmulh_mask_vx_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmulh_mask_vx_nxv8i16_nxv8i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
@@ -1551,7 +1520,7 @@ entry:
<vscale x 8 x i16> %1,
i16 %2,
<vscale x 8 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 8 x i16> %a
}
@@ -1560,9 +1529,9 @@ declare <vscale x 16 x i16> @llvm.riscv.vmulh.nxv16i16.i16(
<vscale x 16 x i16>,
<vscale x 16 x i16>,
i16,
- i32);
+ iXLen);
-define <vscale x 16 x i16> @intrinsic_vmulh_vx_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, i16 %1, i32 %2) nounwind {
+define <vscale x 16 x i16> @intrinsic_vmulh_vx_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, i16 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmulh_vx_nxv16i16_nxv16i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
@@ -1573,7 +1542,7 @@ entry:
<vscale x 16 x i16> undef,
<vscale x 16 x i16> %0,
i16 %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 16 x i16> %a
}
@@ -1583,10 +1552,9 @@ declare <vscale x 16 x i16> @llvm.riscv.vmulh.mask.nxv16i16.i16(
<vscale x 16 x i16>,
i16,
<vscale x 16 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 16 x i16> @intrinsic_vmulh_mask_vx_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+define <vscale x 16 x i16> @intrinsic_vmulh_mask_vx_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmulh_mask_vx_nxv16i16_nxv16i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
@@ -1598,7 +1566,7 @@ entry:
<vscale x 16 x i16> %1,
i16 %2,
<vscale x 16 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 16 x i16> %a
}
@@ -1607,9 +1575,9 @@ declare <vscale x 32 x i16> @llvm.riscv.vmulh.nxv32i16.i16(
<vscale x 32 x i16>,
<vscale x 32 x i16>,
i16,
- i32);
+ iXLen);
-define <vscale x 32 x i16> @intrinsic_vmulh_vx_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, i16 %1, i32 %2) nounwind {
+define <vscale x 32 x i16> @intrinsic_vmulh_vx_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, i16 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmulh_vx_nxv32i16_nxv32i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu
@@ -1620,7 +1588,7 @@ entry:
<vscale x 32 x i16> undef,
<vscale x 32 x i16> %0,
i16 %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 32 x i16> %a
}
@@ -1630,10 +1598,9 @@ declare <vscale x 32 x i16> @llvm.riscv.vmulh.mask.nxv32i16.i16(
<vscale x 32 x i16>,
i16,
<vscale x 32 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 32 x i16> @intrinsic_vmulh_mask_vx_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, i16 %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
+define <vscale x 32 x i16> @intrinsic_vmulh_mask_vx_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, i16 %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmulh_mask_vx_nxv32i16_nxv32i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu
@@ -1645,7 +1612,7 @@ entry:
<vscale x 32 x i16> %1,
i16 %2,
<vscale x 32 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 32 x i16> %a
}
@@ -1654,9 +1621,9 @@ declare <vscale x 1 x i32> @llvm.riscv.vmulh.nxv1i32.i32(
<vscale x 1 x i32>,
<vscale x 1 x i32>,
i32,
- i32);
+ iXLen);
-define <vscale x 1 x i32> @intrinsic_vmulh_vx_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, i32 %1, i32 %2) nounwind {
+define <vscale x 1 x i32> @intrinsic_vmulh_vx_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, i32 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmulh_vx_nxv1i32_nxv1i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
@@ -1667,7 +1634,7 @@ entry:
<vscale x 1 x i32> undef,
<vscale x 1 x i32> %0,
i32 %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 1 x i32> %a
}
@@ -1677,10 +1644,9 @@ declare <vscale x 1 x i32> @llvm.riscv.vmulh.mask.nxv1i32.i32(
<vscale x 1 x i32>,
i32,
<vscale x 1 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 1 x i32> @intrinsic_vmulh_mask_vx_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+define <vscale x 1 x i32> @intrinsic_vmulh_mask_vx_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmulh_mask_vx_nxv1i32_nxv1i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
@@ -1692,7 +1658,7 @@ entry:
<vscale x 1 x i32> %1,
i32 %2,
<vscale x 1 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 1 x i32> %a
}
@@ -1701,9 +1667,9 @@ declare <vscale x 2 x i32> @llvm.riscv.vmulh.nxv2i32.i32(
<vscale x 2 x i32>,
<vscale x 2 x i32>,
i32,
- i32);
+ iXLen);
-define <vscale x 2 x i32> @intrinsic_vmulh_vx_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, i32 %1, i32 %2) nounwind {
+define <vscale x 2 x i32> @intrinsic_vmulh_vx_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, i32 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmulh_vx_nxv2i32_nxv2i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
@@ -1714,7 +1680,7 @@ entry:
<vscale x 2 x i32> undef,
<vscale x 2 x i32> %0,
i32 %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 2 x i32> %a
}
@@ -1724,10 +1690,9 @@ declare <vscale x 2 x i32> @llvm.riscv.vmulh.mask.nxv2i32.i32(
<vscale x 2 x i32>,
i32,
<vscale x 2 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 2 x i32> @intrinsic_vmulh_mask_vx_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+define <vscale x 2 x i32> @intrinsic_vmulh_mask_vx_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmulh_mask_vx_nxv2i32_nxv2i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
@@ -1739,7 +1704,7 @@ entry:
<vscale x 2 x i32> %1,
i32 %2,
<vscale x 2 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 2 x i32> %a
}
@@ -1748,9 +1713,9 @@ declare <vscale x 4 x i32> @llvm.riscv.vmulh.nxv4i32.i32(
<vscale x 4 x i32>,
<vscale x 4 x i32>,
i32,
- i32);
+ iXLen);
-define <vscale x 4 x i32> @intrinsic_vmulh_vx_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, i32 %1, i32 %2) nounwind {
+define <vscale x 4 x i32> @intrinsic_vmulh_vx_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, i32 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmulh_vx_nxv4i32_nxv4i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
@@ -1761,7 +1726,7 @@ entry:
<vscale x 4 x i32> undef,
<vscale x 4 x i32> %0,
i32 %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 4 x i32> %a
}
@@ -1771,10 +1736,9 @@ declare <vscale x 4 x i32> @llvm.riscv.vmulh.mask.nxv4i32.i32(
<vscale x 4 x i32>,
i32,
<vscale x 4 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 4 x i32> @intrinsic_vmulh_mask_vx_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+define <vscale x 4 x i32> @intrinsic_vmulh_mask_vx_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmulh_mask_vx_nxv4i32_nxv4i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
@@ -1786,7 +1750,7 @@ entry:
<vscale x 4 x i32> %1,
i32 %2,
<vscale x 4 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 4 x i32> %a
}
@@ -1795,9 +1759,9 @@ declare <vscale x 8 x i32> @llvm.riscv.vmulh.nxv8i32.i32(
<vscale x 8 x i32>,
<vscale x 8 x i32>,
i32,
- i32);
+ iXLen);
-define <vscale x 8 x i32> @intrinsic_vmulh_vx_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, i32 %1, i32 %2) nounwind {
+define <vscale x 8 x i32> @intrinsic_vmulh_vx_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, i32 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmulh_vx_nxv8i32_nxv8i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
@@ -1808,7 +1772,7 @@ entry:
<vscale x 8 x i32> undef,
<vscale x 8 x i32> %0,
i32 %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 8 x i32> %a
}
@@ -1818,10 +1782,9 @@ declare <vscale x 8 x i32> @llvm.riscv.vmulh.mask.nxv8i32.i32(
<vscale x 8 x i32>,
i32,
<vscale x 8 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 8 x i32> @intrinsic_vmulh_mask_vx_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+define <vscale x 8 x i32> @intrinsic_vmulh_mask_vx_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmulh_mask_vx_nxv8i32_nxv8i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
@@ -1833,7 +1796,7 @@ entry:
<vscale x 8 x i32> %1,
i32 %2,
<vscale x 8 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 8 x i32> %a
}
@@ -1842,9 +1805,9 @@ declare <vscale x 16 x i32> @llvm.riscv.vmulh.nxv16i32.i32(
<vscale x 16 x i32>,
<vscale x 16 x i32>,
i32,
- i32);
+ iXLen);
-define <vscale x 16 x i32> @intrinsic_vmulh_vx_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, i32 %1, i32 %2) nounwind {
+define <vscale x 16 x i32> @intrinsic_vmulh_vx_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, i32 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmulh_vx_nxv16i32_nxv16i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu
@@ -1855,7 +1818,7 @@ entry:
<vscale x 16 x i32> undef,
<vscale x 16 x i32> %0,
i32 %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 16 x i32> %a
}
@@ -1865,10 +1828,9 @@ declare <vscale x 16 x i32> @llvm.riscv.vmulh.mask.nxv16i32.i32(
<vscale x 16 x i32>,
i32,
<vscale x 16 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 16 x i32> @intrinsic_vmulh_mask_vx_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+define <vscale x 16 x i32> @intrinsic_vmulh_mask_vx_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmulh_mask_vx_nxv16i32_nxv16i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu
@@ -1880,7 +1842,7 @@ entry:
<vscale x 16 x i32> %1,
i32 %2,
<vscale x 16 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 16 x i32> %a
}
@@ -1889,26 +1851,32 @@ declare <vscale x 1 x i64> @llvm.riscv.vmulh.nxv1i64.i64(
<vscale x 1 x i64>,
<vscale x 1 x i64>,
i64,
- i32);
-
-define <vscale x 1 x i64> @intrinsic_vmulh_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmulh_vx_nxv1i64_nxv1i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addi sp, sp, -16
-; CHECK-NEXT: sw a1, 12(sp)
-; CHECK-NEXT: sw a0, 8(sp)
-; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
-; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v9, (a0), zero
-; CHECK-NEXT: vmulh.vv v8, v8, v9
-; CHECK-NEXT: addi sp, sp, 16
-; CHECK-NEXT: ret
+ iXLen);
+
+define <vscale x 1 x i64> @intrinsic_vmulh_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, iXLen %2) nounwind {
+; RV32-LABEL: intrinsic_vmulh_vx_nxv1i64_nxv1i64_i64:
+; RV32: # %bb.0: # %entry
+; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: sw a1, 12(sp)
+; RV32-NEXT: sw a0, 8(sp)
+; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
+; RV32-NEXT: addi a0, sp, 8
+; RV32-NEXT: vlse64.v v9, (a0), zero
+; RV32-NEXT: vmulh.vv v8, v8, v9
+; RV32-NEXT: addi sp, sp, 16
+; RV32-NEXT: ret
+;
+; RV64-LABEL: intrinsic_vmulh_vx_nxv1i64_nxv1i64_i64:
+; RV64: # %bb.0: # %entry
+; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, mu
+; RV64-NEXT: vmulh.vx v8, v8, a0
+; RV64-NEXT: ret
entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vmulh.nxv1i64.i64(
<vscale x 1 x i64> undef,
<vscale x 1 x i64> %0,
i64 %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 1 x i64> %a
}
@@ -1918,28 +1886,33 @@ declare <vscale x 1 x i64> @llvm.riscv.vmulh.mask.nxv1i64.i64(
<vscale x 1 x i64>,
i64,
<vscale x 1 x i1>,
- i32,
- i32);
-
-define <vscale x 1 x i64> @intrinsic_vmulh_mask_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmulh_mask_vx_nxv1i64_nxv1i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addi sp, sp, -16
-; CHECK-NEXT: sw a1, 12(sp)
-; CHECK-NEXT: sw a0, 8(sp)
-; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
-; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v10, (a0), zero
-; CHECK-NEXT: vmulh.vv v8, v9, v10, v0.t
-; CHECK-NEXT: addi sp, sp, 16
-; CHECK-NEXT: ret
+ iXLen, iXLen);
+
+define <vscale x 1 x i64> @intrinsic_vmulh_mask_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
+; RV32-LABEL: intrinsic_vmulh_mask_vx_nxv1i64_nxv1i64_i64:
+; RV32: # %bb.0: # %entry
+; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: sw a1, 12(sp)
+; RV32-NEXT: sw a0, 8(sp)
+; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
+; RV32-NEXT: addi a0, sp, 8
+; RV32-NEXT: vlse64.v v10, (a0), zero
+; RV32-NEXT: vmulh.vv v8, v9, v10, v0.t
+; RV32-NEXT: addi sp, sp, 16
+; RV32-NEXT: ret
+;
+; RV64-LABEL: intrinsic_vmulh_mask_vx_nxv1i64_nxv1i64_i64:
+; RV64: # %bb.0: # %entry
+; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, mu
+; RV64-NEXT: vmulh.vx v8, v9, a0, v0.t
+; RV64-NEXT: ret
entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vmulh.mask.nxv1i64.i64(
<vscale x 1 x i64> %0,
<vscale x 1 x i64> %1,
i64 %2,
<vscale x 1 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 1 x i64> %a
}
@@ -1948,26 +1921,32 @@ declare <vscale x 2 x i64> @llvm.riscv.vmulh.nxv2i64.i64(
<vscale x 2 x i64>,
<vscale x 2 x i64>,
i64,
- i32);
-
-define <vscale x 2 x i64> @intrinsic_vmulh_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmulh_vx_nxv2i64_nxv2i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addi sp, sp, -16
-; CHECK-NEXT: sw a1, 12(sp)
-; CHECK-NEXT: sw a0, 8(sp)
-; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
-; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v10, (a0), zero
-; CHECK-NEXT: vmulh.vv v8, v8, v10
-; CHECK-NEXT: addi sp, sp, 16
-; CHECK-NEXT: ret
+ iXLen);
+
+define <vscale x 2 x i64> @intrinsic_vmulh_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, iXLen %2) nounwind {
+; RV32-LABEL: intrinsic_vmulh_vx_nxv2i64_nxv2i64_i64:
+; RV32: # %bb.0: # %entry
+; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: sw a1, 12(sp)
+; RV32-NEXT: sw a0, 8(sp)
+; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
+; RV32-NEXT: addi a0, sp, 8
+; RV32-NEXT: vlse64.v v10, (a0), zero
+; RV32-NEXT: vmulh.vv v8, v8, v10
+; RV32-NEXT: addi sp, sp, 16
+; RV32-NEXT: ret
+;
+; RV64-LABEL: intrinsic_vmulh_vx_nxv2i64_nxv2i64_i64:
+; RV64: # %bb.0: # %entry
+; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, mu
+; RV64-NEXT: vmulh.vx v8, v8, a0
+; RV64-NEXT: ret
entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vmulh.nxv2i64.i64(
<vscale x 2 x i64> undef,
<vscale x 2 x i64> %0,
i64 %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 2 x i64> %a
}
@@ -1977,28 +1956,33 @@ declare <vscale x 2 x i64> @llvm.riscv.vmulh.mask.nxv2i64.i64(
<vscale x 2 x i64>,
i64,
<vscale x 2 x i1>,
- i32,
- i32);
-
-define <vscale x 2 x i64> @intrinsic_vmulh_mask_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmulh_mask_vx_nxv2i64_nxv2i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addi sp, sp, -16
-; CHECK-NEXT: sw a1, 12(sp)
-; CHECK-NEXT: sw a0, 8(sp)
-; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
-; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v12, (a0), zero
-; CHECK-NEXT: vmulh.vv v8, v10, v12, v0.t
-; CHECK-NEXT: addi sp, sp, 16
-; CHECK-NEXT: ret
+ iXLen, iXLen);
+
+define <vscale x 2 x i64> @intrinsic_vmulh_mask_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
+; RV32-LABEL: intrinsic_vmulh_mask_vx_nxv2i64_nxv2i64_i64:
+; RV32: # %bb.0: # %entry
+; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: sw a1, 12(sp)
+; RV32-NEXT: sw a0, 8(sp)
+; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
+; RV32-NEXT: addi a0, sp, 8
+; RV32-NEXT: vlse64.v v12, (a0), zero
+; RV32-NEXT: vmulh.vv v8, v10, v12, v0.t
+; RV32-NEXT: addi sp, sp, 16
+; RV32-NEXT: ret
+;
+; RV64-LABEL: intrinsic_vmulh_mask_vx_nxv2i64_nxv2i64_i64:
+; RV64: # %bb.0: # %entry
+; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, mu
+; RV64-NEXT: vmulh.vx v8, v10, a0, v0.t
+; RV64-NEXT: ret
entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vmulh.mask.nxv2i64.i64(
<vscale x 2 x i64> %0,
<vscale x 2 x i64> %1,
i64 %2,
<vscale x 2 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 2 x i64> %a
}
@@ -2007,26 +1991,32 @@ declare <vscale x 4 x i64> @llvm.riscv.vmulh.nxv4i64.i64(
<vscale x 4 x i64>,
<vscale x 4 x i64>,
i64,
- i32);
-
-define <vscale x 4 x i64> @intrinsic_vmulh_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmulh_vx_nxv4i64_nxv4i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addi sp, sp, -16
-; CHECK-NEXT: sw a1, 12(sp)
-; CHECK-NEXT: sw a0, 8(sp)
-; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
-; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v12, (a0), zero
-; CHECK-NEXT: vmulh.vv v8, v8, v12
-; CHECK-NEXT: addi sp, sp, 16
-; CHECK-NEXT: ret
+ iXLen);
+
+define <vscale x 4 x i64> @intrinsic_vmulh_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, iXLen %2) nounwind {
+; RV32-LABEL: intrinsic_vmulh_vx_nxv4i64_nxv4i64_i64:
+; RV32: # %bb.0: # %entry
+; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: sw a1, 12(sp)
+; RV32-NEXT: sw a0, 8(sp)
+; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
+; RV32-NEXT: addi a0, sp, 8
+; RV32-NEXT: vlse64.v v12, (a0), zero
+; RV32-NEXT: vmulh.vv v8, v8, v12
+; RV32-NEXT: addi sp, sp, 16
+; RV32-NEXT: ret
+;
+; RV64-LABEL: intrinsic_vmulh_vx_nxv4i64_nxv4i64_i64:
+; RV64: # %bb.0: # %entry
+; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu
+; RV64-NEXT: vmulh.vx v8, v8, a0
+; RV64-NEXT: ret
entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vmulh.nxv4i64.i64(
<vscale x 4 x i64> undef,
<vscale x 4 x i64> %0,
i64 %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 4 x i64> %a
}
@@ -2036,28 +2026,33 @@ declare <vscale x 4 x i64> @llvm.riscv.vmulh.mask.nxv4i64.i64(
<vscale x 4 x i64>,
i64,
<vscale x 4 x i1>,
- i32,
- i32);
-
-define <vscale x 4 x i64> @intrinsic_vmulh_mask_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmulh_mask_vx_nxv4i64_nxv4i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addi sp, sp, -16
-; CHECK-NEXT: sw a1, 12(sp)
-; CHECK-NEXT: sw a0, 8(sp)
-; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
-; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v16, (a0), zero
-; CHECK-NEXT: vmulh.vv v8, v12, v16, v0.t
-; CHECK-NEXT: addi sp, sp, 16
-; CHECK-NEXT: ret
+ iXLen, iXLen);
+
+define <vscale x 4 x i64> @intrinsic_vmulh_mask_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
+; RV32-LABEL: intrinsic_vmulh_mask_vx_nxv4i64_nxv4i64_i64:
+; RV32: # %bb.0: # %entry
+; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: sw a1, 12(sp)
+; RV32-NEXT: sw a0, 8(sp)
+; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
+; RV32-NEXT: addi a0, sp, 8
+; RV32-NEXT: vlse64.v v16, (a0), zero
+; RV32-NEXT: vmulh.vv v8, v12, v16, v0.t
+; RV32-NEXT: addi sp, sp, 16
+; RV32-NEXT: ret
+;
+; RV64-LABEL: intrinsic_vmulh_mask_vx_nxv4i64_nxv4i64_i64:
+; RV64: # %bb.0: # %entry
+; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu
+; RV64-NEXT: vmulh.vx v8, v12, a0, v0.t
+; RV64-NEXT: ret
entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vmulh.mask.nxv4i64.i64(
<vscale x 4 x i64> %0,
<vscale x 4 x i64> %1,
i64 %2,
<vscale x 4 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 4 x i64> %a
}
@@ -2066,26 +2061,32 @@ declare <vscale x 8 x i64> @llvm.riscv.vmulh.nxv8i64.i64(
<vscale x 8 x i64>,
<vscale x 8 x i64>,
i64,
- i32);
-
-define <vscale x 8 x i64> @intrinsic_vmulh_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, i64 %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmulh_vx_nxv8i64_nxv8i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addi sp, sp, -16
-; CHECK-NEXT: sw a1, 12(sp)
-; CHECK-NEXT: sw a0, 8(sp)
-; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, mu
-; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v16, (a0), zero
-; CHECK-NEXT: vmulh.vv v8, v8, v16
-; CHECK-NEXT: addi sp, sp, 16
-; CHECK-NEXT: ret
+ iXLen);
+
+define <vscale x 8 x i64> @intrinsic_vmulh_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, i64 %1, iXLen %2) nounwind {
+; RV32-LABEL: intrinsic_vmulh_vx_nxv8i64_nxv8i64_i64:
+; RV32: # %bb.0: # %entry
+; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: sw a1, 12(sp)
+; RV32-NEXT: sw a0, 8(sp)
+; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu
+; RV32-NEXT: addi a0, sp, 8
+; RV32-NEXT: vlse64.v v16, (a0), zero
+; RV32-NEXT: vmulh.vv v8, v8, v16
+; RV32-NEXT: addi sp, sp, 16
+; RV32-NEXT: ret
+;
+; RV64-LABEL: intrinsic_vmulh_vx_nxv8i64_nxv8i64_i64:
+; RV64: # %bb.0: # %entry
+; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, mu
+; RV64-NEXT: vmulh.vx v8, v8, a0
+; RV64-NEXT: ret
entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vmulh.nxv8i64.i64(
<vscale x 8 x i64> undef,
<vscale x 8 x i64> %0,
i64 %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 8 x i64> %a
}
@@ -2095,28 +2096,33 @@ declare <vscale x 8 x i64> @llvm.riscv.vmulh.mask.nxv8i64.i64(
<vscale x 8 x i64>,
i64,
<vscale x 8 x i1>,
- i32,
- i32);
-
-define <vscale x 8 x i64> @intrinsic_vmulh_mask_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmulh_mask_vx_nxv8i64_nxv8i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addi sp, sp, -16
-; CHECK-NEXT: sw a1, 12(sp)
-; CHECK-NEXT: sw a0, 8(sp)
-; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, mu
-; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v24, (a0), zero
-; CHECK-NEXT: vmulh.vv v8, v16, v24, v0.t
-; CHECK-NEXT: addi sp, sp, 16
-; CHECK-NEXT: ret
+ iXLen, iXLen);
+
+define <vscale x 8 x i64> @intrinsic_vmulh_mask_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
+; RV32-LABEL: intrinsic_vmulh_mask_vx_nxv8i64_nxv8i64_i64:
+; RV32: # %bb.0: # %entry
+; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: sw a1, 12(sp)
+; RV32-NEXT: sw a0, 8(sp)
+; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu
+; RV32-NEXT: addi a0, sp, 8
+; RV32-NEXT: vlse64.v v24, (a0), zero
+; RV32-NEXT: vmulh.vv v8, v16, v24, v0.t
+; RV32-NEXT: addi sp, sp, 16
+; RV32-NEXT: ret
+;
+; RV64-LABEL: intrinsic_vmulh_mask_vx_nxv8i64_nxv8i64_i64:
+; RV64: # %bb.0: # %entry
+; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, mu
+; RV64-NEXT: vmulh.vx v8, v16, a0, v0.t
+; RV64-NEXT: ret
entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vmulh.mask.nxv8i64.i64(
<vscale x 8 x i64> %0,
<vscale x 8 x i64> %1,
i64 %2,
<vscale x 8 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 8 x i64> %a
}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmulhsu-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmulhsu-rv32.ll
deleted file mode 100644
index 28afafa2e0a38..0000000000000
--- a/llvm/test/CodeGen/RISCV/rvv/vmulhsu-rv32.ll
+++ /dev/null
@@ -1,2122 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs \
-; RUN: < %s | FileCheck %s
-declare <vscale x 1 x i8> @llvm.riscv.vmulhsu.nxv1i8.nxv1i8(
- <vscale x 1 x i8>,
- <vscale x 1 x i8>,
- <vscale x 1 x i8>,
- i32);
-
-define <vscale x 1 x i8> @intrinsic_vmulhsu_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmulhsu_vv_nxv1i8_nxv1i8_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
-; CHECK-NEXT: vmulhsu.vv v8, v8, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i8> @llvm.riscv.vmulhsu.nxv1i8.nxv1i8(
- <vscale x 1 x i8> undef,
- <vscale x 1 x i8> %0,
- <vscale x 1 x i8> %1,
- i32 %2)
-
- ret <vscale x 1 x i8> %a
-}
-
-declare <vscale x 1 x i8> @llvm.riscv.vmulhsu.mask.nxv1i8.nxv1i8(
- <vscale x 1 x i8>,
- <vscale x 1 x i8>,
- <vscale x 1 x i8>,
- <vscale x 1 x i1>,
- i32,
- i32);
-
-define <vscale x 1 x i8> @intrinsic_vmulhsu_mask_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmulhsu_mask_vv_nxv1i8_nxv1i8_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
-; CHECK-NEXT: vmulhsu.vv v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i8> @llvm.riscv.vmulhsu.mask.nxv1i8.nxv1i8(
- <vscale x 1 x i8> %0,
- <vscale x 1 x i8> %1,
- <vscale x 1 x i8> %2,
- <vscale x 1 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 1 x i8> %a
-}
-
-declare <vscale x 2 x i8> @llvm.riscv.vmulhsu.nxv2i8.nxv2i8(
- <vscale x 2 x i8>,
- <vscale x 2 x i8>,
- <vscale x 2 x i8>,
- i32);
-
-define <vscale x 2 x i8> @intrinsic_vmulhsu_vv_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmulhsu_vv_nxv2i8_nxv2i8_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
-; CHECK-NEXT: vmulhsu.vv v8, v8, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i8> @llvm.riscv.vmulhsu.nxv2i8.nxv2i8(
- <vscale x 2 x i8> undef,
- <vscale x 2 x i8> %0,
- <vscale x 2 x i8> %1,
- i32 %2)
-
- ret <vscale x 2 x i8> %a
-}
-
-declare <vscale x 2 x i8> @llvm.riscv.vmulhsu.mask.nxv2i8.nxv2i8(
- <vscale x 2 x i8>,
- <vscale x 2 x i8>,
- <vscale x 2 x i8>,
- <vscale x 2 x i1>,
- i32,
- i32);
-
-define <vscale x 2 x i8> @intrinsic_vmulhsu_mask_vv_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmulhsu_mask_vv_nxv2i8_nxv2i8_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
-; CHECK-NEXT: vmulhsu.vv v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i8> @llvm.riscv.vmulhsu.mask.nxv2i8.nxv2i8(
- <vscale x 2 x i8> %0,
- <vscale x 2 x i8> %1,
- <vscale x 2 x i8> %2,
- <vscale x 2 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 2 x i8> %a
-}
-
-declare <vscale x 4 x i8> @llvm.riscv.vmulhsu.nxv4i8.nxv4i8(
- <vscale x 4 x i8>,
- <vscale x 4 x i8>,
- <vscale x 4 x i8>,
- i32);
-
-define <vscale x 4 x i8> @intrinsic_vmulhsu_vv_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmulhsu_vv_nxv4i8_nxv4i8_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
-; CHECK-NEXT: vmulhsu.vv v8, v8, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i8> @llvm.riscv.vmulhsu.nxv4i8.nxv4i8(
- <vscale x 4 x i8> undef,
- <vscale x 4 x i8> %0,
- <vscale x 4 x i8> %1,
- i32 %2)
-
- ret <vscale x 4 x i8> %a
-}
-
-declare <vscale x 4 x i8> @llvm.riscv.vmulhsu.mask.nxv4i8.nxv4i8(
- <vscale x 4 x i8>,
- <vscale x 4 x i8>,
- <vscale x 4 x i8>,
- <vscale x 4 x i1>,
- i32,
- i32);
-
-define <vscale x 4 x i8> @intrinsic_vmulhsu_mask_vv_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmulhsu_mask_vv_nxv4i8_nxv4i8_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
-; CHECK-NEXT: vmulhsu.vv v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i8> @llvm.riscv.vmulhsu.mask.nxv4i8.nxv4i8(
- <vscale x 4 x i8> %0,
- <vscale x 4 x i8> %1,
- <vscale x 4 x i8> %2,
- <vscale x 4 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 4 x i8> %a
-}
-
-declare <vscale x 8 x i8> @llvm.riscv.vmulhsu.nxv8i8.nxv8i8(
- <vscale x 8 x i8>,
- <vscale x 8 x i8>,
- <vscale x 8 x i8>,
- i32);
-
-define <vscale x 8 x i8> @intrinsic_vmulhsu_vv_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmulhsu_vv_nxv8i8_nxv8i8_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
-; CHECK-NEXT: vmulhsu.vv v8, v8, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i8> @llvm.riscv.vmulhsu.nxv8i8.nxv8i8(
- <vscale x 8 x i8> undef,
- <vscale x 8 x i8> %0,
- <vscale x 8 x i8> %1,
- i32 %2)
-
- ret <vscale x 8 x i8> %a
-}
-
-declare <vscale x 8 x i8> @llvm.riscv.vmulhsu.mask.nxv8i8.nxv8i8(
- <vscale x 8 x i8>,
- <vscale x 8 x i8>,
- <vscale x 8 x i8>,
- <vscale x 8 x i1>,
- i32,
- i32);
-
-define <vscale x 8 x i8> @intrinsic_vmulhsu_mask_vv_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmulhsu_mask_vv_nxv8i8_nxv8i8_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
-; CHECK-NEXT: vmulhsu.vv v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i8> @llvm.riscv.vmulhsu.mask.nxv8i8.nxv8i8(
- <vscale x 8 x i8> %0,
- <vscale x 8 x i8> %1,
- <vscale x 8 x i8> %2,
- <vscale x 8 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 8 x i8> %a
-}
-
-declare <vscale x 16 x i8> @llvm.riscv.vmulhsu.nxv16i8.nxv16i8(
- <vscale x 16 x i8>,
- <vscale x 16 x i8>,
- <vscale x 16 x i8>,
- i32);
-
-define <vscale x 16 x i8> @intrinsic_vmulhsu_vv_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmulhsu_vv_nxv16i8_nxv16i8_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
-; CHECK-NEXT: vmulhsu.vv v8, v8, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i8> @llvm.riscv.vmulhsu.nxv16i8.nxv16i8(
- <vscale x 16 x i8> undef,
- <vscale x 16 x i8> %0,
- <vscale x 16 x i8> %1,
- i32 %2)
-
- ret <vscale x 16 x i8> %a
-}
-
-declare <vscale x 16 x i8> @llvm.riscv.vmulhsu.mask.nxv16i8.nxv16i8(
- <vscale x 16 x i8>,
- <vscale x 16 x i8>,
- <vscale x 16 x i8>,
- <vscale x 16 x i1>,
- i32,
- i32);
-
-define <vscale x 16 x i8> @intrinsic_vmulhsu_mask_vv_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmulhsu_mask_vv_nxv16i8_nxv16i8_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
-; CHECK-NEXT: vmulhsu.vv v8, v10, v12, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i8> @llvm.riscv.vmulhsu.mask.nxv16i8.nxv16i8(
- <vscale x 16 x i8> %0,
- <vscale x 16 x i8> %1,
- <vscale x 16 x i8> %2,
- <vscale x 16 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 16 x i8> %a
-}
-
-declare <vscale x 32 x i8> @llvm.riscv.vmulhsu.nxv32i8.nxv32i8(
- <vscale x 32 x i8>,
- <vscale x 32 x i8>,
- <vscale x 32 x i8>,
- i32);
-
-define <vscale x 32 x i8> @intrinsic_vmulhsu_vv_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmulhsu_vv_nxv32i8_nxv32i8_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
-; CHECK-NEXT: vmulhsu.vv v8, v8, v12
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 32 x i8> @llvm.riscv.vmulhsu.nxv32i8.nxv32i8(
- <vscale x 32 x i8> undef,
- <vscale x 32 x i8> %0,
- <vscale x 32 x i8> %1,
- i32 %2)
-
- ret <vscale x 32 x i8> %a
-}
-
-declare <vscale x 32 x i8> @llvm.riscv.vmulhsu.mask.nxv32i8.nxv32i8(
- <vscale x 32 x i8>,
- <vscale x 32 x i8>,
- <vscale x 32 x i8>,
- <vscale x 32 x i1>,
- i32,
- i32);
-
-define <vscale x 32 x i8> @intrinsic_vmulhsu_mask_vv_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmulhsu_mask_vv_nxv32i8_nxv32i8_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
-; CHECK-NEXT: vmulhsu.vv v8, v12, v16, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 32 x i8> @llvm.riscv.vmulhsu.mask.nxv32i8.nxv32i8(
- <vscale x 32 x i8> %0,
- <vscale x 32 x i8> %1,
- <vscale x 32 x i8> %2,
- <vscale x 32 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 32 x i8> %a
-}
-
-declare <vscale x 64 x i8> @llvm.riscv.vmulhsu.nxv64i8.nxv64i8(
- <vscale x 64 x i8>,
- <vscale x 64 x i8>,
- <vscale x 64 x i8>,
- i32);
-
-define <vscale x 64 x i8> @intrinsic_vmulhsu_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmulhsu_vv_nxv64i8_nxv64i8_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, mu
-; CHECK-NEXT: vmulhsu.vv v8, v8, v16
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 64 x i8> @llvm.riscv.vmulhsu.nxv64i8.nxv64i8(
- <vscale x 64 x i8> undef,
- <vscale x 64 x i8> %0,
- <vscale x 64 x i8> %1,
- i32 %2)
-
- ret <vscale x 64 x i8> %a
-}
-
-declare <vscale x 64 x i8> @llvm.riscv.vmulhsu.mask.nxv64i8.nxv64i8(
- <vscale x 64 x i8>,
- <vscale x 64 x i8>,
- <vscale x 64 x i8>,
- <vscale x 64 x i1>,
- i32,
- i32);
-
-define <vscale x 64 x i8> @intrinsic_vmulhsu_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmulhsu_mask_vv_nxv64i8_nxv64i8_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vl8r.v v24, (a0)
-; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu
-; CHECK-NEXT: vmulhsu.vv v8, v16, v24, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 64 x i8> @llvm.riscv.vmulhsu.mask.nxv64i8.nxv64i8(
- <vscale x 64 x i8> %0,
- <vscale x 64 x i8> %1,
- <vscale x 64 x i8> %2,
- <vscale x 64 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 64 x i8> %a
-}
-
-declare <vscale x 1 x i16> @llvm.riscv.vmulhsu.nxv1i16.nxv1i16(
- <vscale x 1 x i16>,
- <vscale x 1 x i16>,
- <vscale x 1 x i16>,
- i32);
-
-define <vscale x 1 x i16> @intrinsic_vmulhsu_vv_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmulhsu_vv_nxv1i16_nxv1i16_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vmulhsu.vv v8, v8, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i16> @llvm.riscv.vmulhsu.nxv1i16.nxv1i16(
- <vscale x 1 x i16> undef,
- <vscale x 1 x i16> %0,
- <vscale x 1 x i16> %1,
- i32 %2)
-
- ret <vscale x 1 x i16> %a
-}
-
-declare <vscale x 1 x i16> @llvm.riscv.vmulhsu.mask.nxv1i16.nxv1i16(
- <vscale x 1 x i16>,
- <vscale x 1 x i16>,
- <vscale x 1 x i16>,
- <vscale x 1 x i1>,
- i32,
- i32);
-
-define <vscale x 1 x i16> @intrinsic_vmulhsu_mask_vv_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmulhsu_mask_vv_nxv1i16_nxv1i16_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vmulhsu.vv v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i16> @llvm.riscv.vmulhsu.mask.nxv1i16.nxv1i16(
- <vscale x 1 x i16> %0,
- <vscale x 1 x i16> %1,
- <vscale x 1 x i16> %2,
- <vscale x 1 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 1 x i16> %a
-}
-
-declare <vscale x 2 x i16> @llvm.riscv.vmulhsu.nxv2i16.nxv2i16(
- <vscale x 2 x i16>,
- <vscale x 2 x i16>,
- <vscale x 2 x i16>,
- i32);
-
-define <vscale x 2 x i16> @intrinsic_vmulhsu_vv_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmulhsu_vv_nxv2i16_nxv2i16_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vmulhsu.vv v8, v8, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i16> @llvm.riscv.vmulhsu.nxv2i16.nxv2i16(
- <vscale x 2 x i16> undef,
- <vscale x 2 x i16> %0,
- <vscale x 2 x i16> %1,
- i32 %2)
-
- ret <vscale x 2 x i16> %a
-}
-
-declare <vscale x 2 x i16> @llvm.riscv.vmulhsu.mask.nxv2i16.nxv2i16(
- <vscale x 2 x i16>,
- <vscale x 2 x i16>,
- <vscale x 2 x i16>,
- <vscale x 2 x i1>,
- i32,
- i32);
-
-define <vscale x 2 x i16> @intrinsic_vmulhsu_mask_vv_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmulhsu_mask_vv_nxv2i16_nxv2i16_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vmulhsu.vv v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i16> @llvm.riscv.vmulhsu.mask.nxv2i16.nxv2i16(
- <vscale x 2 x i16> %0,
- <vscale x 2 x i16> %1,
- <vscale x 2 x i16> %2,
- <vscale x 2 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 2 x i16> %a
-}
-
-declare <vscale x 4 x i16> @llvm.riscv.vmulhsu.nxv4i16.nxv4i16(
- <vscale x 4 x i16>,
- <vscale x 4 x i16>,
- <vscale x 4 x i16>,
- i32);
-
-define <vscale x 4 x i16> @intrinsic_vmulhsu_vv_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmulhsu_vv_nxv4i16_nxv4i16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vmulhsu.vv v8, v8, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i16> @llvm.riscv.vmulhsu.nxv4i16.nxv4i16(
- <vscale x 4 x i16> undef,
- <vscale x 4 x i16> %0,
- <vscale x 4 x i16> %1,
- i32 %2)
-
- ret <vscale x 4 x i16> %a
-}
-
-declare <vscale x 4 x i16> @llvm.riscv.vmulhsu.mask.nxv4i16.nxv4i16(
- <vscale x 4 x i16>,
- <vscale x 4 x i16>,
- <vscale x 4 x i16>,
- <vscale x 4 x i1>,
- i32,
- i32);
-
-define <vscale x 4 x i16> @intrinsic_vmulhsu_mask_vv_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmulhsu_mask_vv_nxv4i16_nxv4i16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vmulhsu.vv v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i16> @llvm.riscv.vmulhsu.mask.nxv4i16.nxv4i16(
- <vscale x 4 x i16> %0,
- <vscale x 4 x i16> %1,
- <vscale x 4 x i16> %2,
- <vscale x 4 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 4 x i16> %a
-}
-
-declare <vscale x 8 x i16> @llvm.riscv.vmulhsu.nxv8i16.nxv8i16(
- <vscale x 8 x i16>,
- <vscale x 8 x i16>,
- <vscale x 8 x i16>,
- i32);
-
-define <vscale x 8 x i16> @intrinsic_vmulhsu_vv_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmulhsu_vv_nxv8i16_nxv8i16_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vmulhsu.vv v8, v8, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i16> @llvm.riscv.vmulhsu.nxv8i16.nxv8i16(
- <vscale x 8 x i16> undef,
- <vscale x 8 x i16> %0,
- <vscale x 8 x i16> %1,
- i32 %2)
-
- ret <vscale x 8 x i16> %a
-}
-
-declare <vscale x 8 x i16> @llvm.riscv.vmulhsu.mask.nxv8i16.nxv8i16(
- <vscale x 8 x i16>,
- <vscale x 8 x i16>,
- <vscale x 8 x i16>,
- <vscale x 8 x i1>,
- i32,
- i32);
-
-define <vscale x 8 x i16> @intrinsic_vmulhsu_mask_vv_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmulhsu_mask_vv_nxv8i16_nxv8i16_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vmulhsu.vv v8, v10, v12, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i16> @llvm.riscv.vmulhsu.mask.nxv8i16.nxv8i16(
- <vscale x 8 x i16> %0,
- <vscale x 8 x i16> %1,
- <vscale x 8 x i16> %2,
- <vscale x 8 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 8 x i16> %a
-}
-
-declare <vscale x 16 x i16> @llvm.riscv.vmulhsu.nxv16i16.nxv16i16(
- <vscale x 16 x i16>,
- <vscale x 16 x i16>,
- <vscale x 16 x i16>,
- i32);
-
-define <vscale x 16 x i16> @intrinsic_vmulhsu_vv_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmulhsu_vv_nxv16i16_nxv16i16_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
-; CHECK-NEXT: vmulhsu.vv v8, v8, v12
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i16> @llvm.riscv.vmulhsu.nxv16i16.nxv16i16(
- <vscale x 16 x i16> undef,
- <vscale x 16 x i16> %0,
- <vscale x 16 x i16> %1,
- i32 %2)
-
- ret <vscale x 16 x i16> %a
-}
-
-declare <vscale x 16 x i16> @llvm.riscv.vmulhsu.mask.nxv16i16.nxv16i16(
- <vscale x 16 x i16>,
- <vscale x 16 x i16>,
- <vscale x 16 x i16>,
- <vscale x 16 x i1>,
- i32,
- i32);
-
-define <vscale x 16 x i16> @intrinsic_vmulhsu_mask_vv_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmulhsu_mask_vv_nxv16i16_nxv16i16_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
-; CHECK-NEXT: vmulhsu.vv v8, v12, v16, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i16> @llvm.riscv.vmulhsu.mask.nxv16i16.nxv16i16(
- <vscale x 16 x i16> %0,
- <vscale x 16 x i16> %1,
- <vscale x 16 x i16> %2,
- <vscale x 16 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 16 x i16> %a
-}
-
-declare <vscale x 32 x i16> @llvm.riscv.vmulhsu.nxv32i16.nxv32i16(
- <vscale x 32 x i16>,
- <vscale x 32 x i16>,
- <vscale x 32 x i16>,
- i32);
-
-define <vscale x 32 x i16> @intrinsic_vmulhsu_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmulhsu_vv_nxv32i16_nxv32i16_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, mu
-; CHECK-NEXT: vmulhsu.vv v8, v8, v16
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 32 x i16> @llvm.riscv.vmulhsu.nxv32i16.nxv32i16(
- <vscale x 32 x i16> undef,
- <vscale x 32 x i16> %0,
- <vscale x 32 x i16> %1,
- i32 %2)
-
- ret <vscale x 32 x i16> %a
-}
-
-declare <vscale x 32 x i16> @llvm.riscv.vmulhsu.mask.nxv32i16.nxv32i16(
- <vscale x 32 x i16>,
- <vscale x 32 x i16>,
- <vscale x 32 x i16>,
- <vscale x 32 x i1>,
- i32,
- i32);
-
-define <vscale x 32 x i16> @intrinsic_vmulhsu_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmulhsu_mask_vv_nxv32i16_nxv32i16_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vl8re16.v v24, (a0)
-; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu
-; CHECK-NEXT: vmulhsu.vv v8, v16, v24, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 32 x i16> @llvm.riscv.vmulhsu.mask.nxv32i16.nxv32i16(
- <vscale x 32 x i16> %0,
- <vscale x 32 x i16> %1,
- <vscale x 32 x i16> %2,
- <vscale x 32 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 32 x i16> %a
-}
-
-declare <vscale x 1 x i32> @llvm.riscv.vmulhsu.nxv1i32.nxv1i32(
- <vscale x 1 x i32>,
- <vscale x 1 x i32>,
- <vscale x 1 x i32>,
- i32);
-
-define <vscale x 1 x i32> @intrinsic_vmulhsu_vv_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmulhsu_vv_nxv1i32_nxv1i32_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vmulhsu.vv v8, v8, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i32> @llvm.riscv.vmulhsu.nxv1i32.nxv1i32(
- <vscale x 1 x i32> undef,
- <vscale x 1 x i32> %0,
- <vscale x 1 x i32> %1,
- i32 %2)
-
- ret <vscale x 1 x i32> %a
-}
-
-declare <vscale x 1 x i32> @llvm.riscv.vmulhsu.mask.nxv1i32.nxv1i32(
- <vscale x 1 x i32>,
- <vscale x 1 x i32>,
- <vscale x 1 x i32>,
- <vscale x 1 x i1>,
- i32,
- i32);
-
-define <vscale x 1 x i32> @intrinsic_vmulhsu_mask_vv_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmulhsu_mask_vv_nxv1i32_nxv1i32_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vmulhsu.vv v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i32> @llvm.riscv.vmulhsu.mask.nxv1i32.nxv1i32(
- <vscale x 1 x i32> %0,
- <vscale x 1 x i32> %1,
- <vscale x 1 x i32> %2,
- <vscale x 1 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 1 x i32> %a
-}
-
-declare <vscale x 2 x i32> @llvm.riscv.vmulhsu.nxv2i32.nxv2i32(
- <vscale x 2 x i32>,
- <vscale x 2 x i32>,
- <vscale x 2 x i32>,
- i32);
-
-define <vscale x 2 x i32> @intrinsic_vmulhsu_vv_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmulhsu_vv_nxv2i32_nxv2i32_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vmulhsu.vv v8, v8, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i32> @llvm.riscv.vmulhsu.nxv2i32.nxv2i32(
- <vscale x 2 x i32> undef,
- <vscale x 2 x i32> %0,
- <vscale x 2 x i32> %1,
- i32 %2)
-
- ret <vscale x 2 x i32> %a
-}
-
-declare <vscale x 2 x i32> @llvm.riscv.vmulhsu.mask.nxv2i32.nxv2i32(
- <vscale x 2 x i32>,
- <vscale x 2 x i32>,
- <vscale x 2 x i32>,
- <vscale x 2 x i1>,
- i32,
- i32);
-
-define <vscale x 2 x i32> @intrinsic_vmulhsu_mask_vv_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmulhsu_mask_vv_nxv2i32_nxv2i32_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vmulhsu.vv v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i32> @llvm.riscv.vmulhsu.mask.nxv2i32.nxv2i32(
- <vscale x 2 x i32> %0,
- <vscale x 2 x i32> %1,
- <vscale x 2 x i32> %2,
- <vscale x 2 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 2 x i32> %a
-}
-
-declare <vscale x 4 x i32> @llvm.riscv.vmulhsu.nxv4i32.nxv4i32(
- <vscale x 4 x i32>,
- <vscale x 4 x i32>,
- <vscale x 4 x i32>,
- i32);
-
-define <vscale x 4 x i32> @intrinsic_vmulhsu_vv_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmulhsu_vv_nxv4i32_nxv4i32_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vmulhsu.vv v8, v8, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i32> @llvm.riscv.vmulhsu.nxv4i32.nxv4i32(
- <vscale x 4 x i32> undef,
- <vscale x 4 x i32> %0,
- <vscale x 4 x i32> %1,
- i32 %2)
-
- ret <vscale x 4 x i32> %a
-}
-
-declare <vscale x 4 x i32> @llvm.riscv.vmulhsu.mask.nxv4i32.nxv4i32(
- <vscale x 4 x i32>,
- <vscale x 4 x i32>,
- <vscale x 4 x i32>,
- <vscale x 4 x i1>,
- i32,
- i32);
-
-define <vscale x 4 x i32> @intrinsic_vmulhsu_mask_vv_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmulhsu_mask_vv_nxv4i32_nxv4i32_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vmulhsu.vv v8, v10, v12, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i32> @llvm.riscv.vmulhsu.mask.nxv4i32.nxv4i32(
- <vscale x 4 x i32> %0,
- <vscale x 4 x i32> %1,
- <vscale x 4 x i32> %2,
- <vscale x 4 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 4 x i32> %a
-}
-
-declare <vscale x 8 x i32> @llvm.riscv.vmulhsu.nxv8i32.nxv8i32(
- <vscale x 8 x i32>,
- <vscale x 8 x i32>,
- <vscale x 8 x i32>,
- i32);
-
-define <vscale x 8 x i32> @intrinsic_vmulhsu_vv_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmulhsu_vv_nxv8i32_nxv8i32_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
-; CHECK-NEXT: vmulhsu.vv v8, v8, v12
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i32> @llvm.riscv.vmulhsu.nxv8i32.nxv8i32(
- <vscale x 8 x i32> undef,
- <vscale x 8 x i32> %0,
- <vscale x 8 x i32> %1,
- i32 %2)
-
- ret <vscale x 8 x i32> %a
-}
-
-declare <vscale x 8 x i32> @llvm.riscv.vmulhsu.mask.nxv8i32.nxv8i32(
- <vscale x 8 x i32>,
- <vscale x 8 x i32>,
- <vscale x 8 x i32>,
- <vscale x 8 x i1>,
- i32,
- i32);
-
-define <vscale x 8 x i32> @intrinsic_vmulhsu_mask_vv_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmulhsu_mask_vv_nxv8i32_nxv8i32_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
-; CHECK-NEXT: vmulhsu.vv v8, v12, v16, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i32> @llvm.riscv.vmulhsu.mask.nxv8i32.nxv8i32(
- <vscale x 8 x i32> %0,
- <vscale x 8 x i32> %1,
- <vscale x 8 x i32> %2,
- <vscale x 8 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 8 x i32> %a
-}
-
-declare <vscale x 16 x i32> @llvm.riscv.vmulhsu.nxv16i32.nxv16i32(
- <vscale x 16 x i32>,
- <vscale x 16 x i32>,
- <vscale x 16 x i32>,
- i32);
-
-define <vscale x 16 x i32> @intrinsic_vmulhsu_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmulhsu_vv_nxv16i32_nxv16i32_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu
-; CHECK-NEXT: vmulhsu.vv v8, v8, v16
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i32> @llvm.riscv.vmulhsu.nxv16i32.nxv16i32(
- <vscale x 16 x i32> undef,
- <vscale x 16 x i32> %0,
- <vscale x 16 x i32> %1,
- i32 %2)
-
- ret <vscale x 16 x i32> %a
-}
-
-declare <vscale x 16 x i32> @llvm.riscv.vmulhsu.mask.nxv16i32.nxv16i32(
- <vscale x 16 x i32>,
- <vscale x 16 x i32>,
- <vscale x 16 x i32>,
- <vscale x 16 x i1>,
- i32,
- i32);
-
-define <vscale x 16 x i32> @intrinsic_vmulhsu_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmulhsu_mask_vv_nxv16i32_nxv16i32_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vl8re32.v v24, (a0)
-; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu
-; CHECK-NEXT: vmulhsu.vv v8, v16, v24, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i32> @llvm.riscv.vmulhsu.mask.nxv16i32.nxv16i32(
- <vscale x 16 x i32> %0,
- <vscale x 16 x i32> %1,
- <vscale x 16 x i32> %2,
- <vscale x 16 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 16 x i32> %a
-}
-
-declare <vscale x 1 x i64> @llvm.riscv.vmulhsu.nxv1i64.nxv1i64(
- <vscale x 1 x i64>,
- <vscale x 1 x i64>,
- <vscale x 1 x i64>,
- i32);
-
-define <vscale x 1 x i64> @intrinsic_vmulhsu_vv_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmulhsu_vv_nxv1i64_nxv1i64_nxv1i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
-; CHECK-NEXT: vmulhsu.vv v8, v8, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i64> @llvm.riscv.vmulhsu.nxv1i64.nxv1i64(
- <vscale x 1 x i64> undef,
- <vscale x 1 x i64> %0,
- <vscale x 1 x i64> %1,
- i32 %2)
-
- ret <vscale x 1 x i64> %a
-}
-
-declare <vscale x 1 x i64> @llvm.riscv.vmulhsu.mask.nxv1i64.nxv1i64(
- <vscale x 1 x i64>,
- <vscale x 1 x i64>,
- <vscale x 1 x i64>,
- <vscale x 1 x i1>,
- i32,
- i32);
-
-define <vscale x 1 x i64> @intrinsic_vmulhsu_mask_vv_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmulhsu_mask_vv_nxv1i64_nxv1i64_nxv1i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
-; CHECK-NEXT: vmulhsu.vv v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i64> @llvm.riscv.vmulhsu.mask.nxv1i64.nxv1i64(
- <vscale x 1 x i64> %0,
- <vscale x 1 x i64> %1,
- <vscale x 1 x i64> %2,
- <vscale x 1 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 1 x i64> %a
-}
-
-declare <vscale x 2 x i64> @llvm.riscv.vmulhsu.nxv2i64.nxv2i64(
- <vscale x 2 x i64>,
- <vscale x 2 x i64>,
- <vscale x 2 x i64>,
- i32);
-
-define <vscale x 2 x i64> @intrinsic_vmulhsu_vv_nxv2i64_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmulhsu_vv_nxv2i64_nxv2i64_nxv2i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
-; CHECK-NEXT: vmulhsu.vv v8, v8, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i64> @llvm.riscv.vmulhsu.nxv2i64.nxv2i64(
- <vscale x 2 x i64> undef,
- <vscale x 2 x i64> %0,
- <vscale x 2 x i64> %1,
- i32 %2)
-
- ret <vscale x 2 x i64> %a
-}
-
-declare <vscale x 2 x i64> @llvm.riscv.vmulhsu.mask.nxv2i64.nxv2i64(
- <vscale x 2 x i64>,
- <vscale x 2 x i64>,
- <vscale x 2 x i64>,
- <vscale x 2 x i1>,
- i32,
- i32);
-
-define <vscale x 2 x i64> @intrinsic_vmulhsu_mask_vv_nxv2i64_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmulhsu_mask_vv_nxv2i64_nxv2i64_nxv2i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
-; CHECK-NEXT: vmulhsu.vv v8, v10, v12, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i64> @llvm.riscv.vmulhsu.mask.nxv2i64.nxv2i64(
- <vscale x 2 x i64> %0,
- <vscale x 2 x i64> %1,
- <vscale x 2 x i64> %2,
- <vscale x 2 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 2 x i64> %a
-}
-
-declare <vscale x 4 x i64> @llvm.riscv.vmulhsu.nxv4i64.nxv4i64(
- <vscale x 4 x i64>,
- <vscale x 4 x i64>,
- <vscale x 4 x i64>,
- i32);
-
-define <vscale x 4 x i64> @intrinsic_vmulhsu_vv_nxv4i64_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmulhsu_vv_nxv4i64_nxv4i64_nxv4i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
-; CHECK-NEXT: vmulhsu.vv v8, v8, v12
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i64> @llvm.riscv.vmulhsu.nxv4i64.nxv4i64(
- <vscale x 4 x i64> undef,
- <vscale x 4 x i64> %0,
- <vscale x 4 x i64> %1,
- i32 %2)
-
- ret <vscale x 4 x i64> %a
-}
-
-declare <vscale x 4 x i64> @llvm.riscv.vmulhsu.mask.nxv4i64.nxv4i64(
- <vscale x 4 x i64>,
- <vscale x 4 x i64>,
- <vscale x 4 x i64>,
- <vscale x 4 x i1>,
- i32,
- i32);
-
-define <vscale x 4 x i64> @intrinsic_vmulhsu_mask_vv_nxv4i64_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmulhsu_mask_vv_nxv4i64_nxv4i64_nxv4i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
-; CHECK-NEXT: vmulhsu.vv v8, v12, v16, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i64> @llvm.riscv.vmulhsu.mask.nxv4i64.nxv4i64(
- <vscale x 4 x i64> %0,
- <vscale x 4 x i64> %1,
- <vscale x 4 x i64> %2,
- <vscale x 4 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 4 x i64> %a
-}
-
-declare <vscale x 8 x i64> @llvm.riscv.vmulhsu.nxv8i64.nxv8i64(
- <vscale x 8 x i64>,
- <vscale x 8 x i64>,
- <vscale x 8 x i64>,
- i32);
-
-define <vscale x 8 x i64> @intrinsic_vmulhsu_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmulhsu_vv_nxv8i64_nxv8i64_nxv8i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu
-; CHECK-NEXT: vmulhsu.vv v8, v8, v16
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i64> @llvm.riscv.vmulhsu.nxv8i64.nxv8i64(
- <vscale x 8 x i64> undef,
- <vscale x 8 x i64> %0,
- <vscale x 8 x i64> %1,
- i32 %2)
-
- ret <vscale x 8 x i64> %a
-}
-
-declare <vscale x 8 x i64> @llvm.riscv.vmulhsu.mask.nxv8i64.nxv8i64(
- <vscale x 8 x i64>,
- <vscale x 8 x i64>,
- <vscale x 8 x i64>,
- <vscale x 8 x i1>,
- i32,
- i32);
-
-define <vscale x 8 x i64> @intrinsic_vmulhsu_mask_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmulhsu_mask_vv_nxv8i64_nxv8i64_nxv8i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vl8re64.v v24, (a0)
-; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu
-; CHECK-NEXT: vmulhsu.vv v8, v16, v24, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i64> @llvm.riscv.vmulhsu.mask.nxv8i64.nxv8i64(
- <vscale x 8 x i64> %0,
- <vscale x 8 x i64> %1,
- <vscale x 8 x i64> %2,
- <vscale x 8 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 8 x i64> %a
-}
-
-declare <vscale x 1 x i8> @llvm.riscv.vmulhsu.nxv1i8.i8(
- <vscale x 1 x i8>,
- <vscale x 1 x i8>,
- i8,
- i32);
-
-define <vscale x 1 x i8> @intrinsic_vmulhsu_vx_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, i8 %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmulhsu_vx_nxv1i8_nxv1i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
-; CHECK-NEXT: vmulhsu.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i8> @llvm.riscv.vmulhsu.nxv1i8.i8(
- <vscale x 1 x i8> undef,
- <vscale x 1 x i8> %0,
- i8 %1,
- i32 %2)
-
- ret <vscale x 1 x i8> %a
-}
-
-declare <vscale x 1 x i8> @llvm.riscv.vmulhsu.mask.nxv1i8.i8(
- <vscale x 1 x i8>,
- <vscale x 1 x i8>,
- i8,
- <vscale x 1 x i1>,
- i32,
- i32);
-
-define <vscale x 1 x i8> @intrinsic_vmulhsu_mask_vx_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmulhsu_mask_vx_nxv1i8_nxv1i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
-; CHECK-NEXT: vmulhsu.vx v8, v9, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i8> @llvm.riscv.vmulhsu.mask.nxv1i8.i8(
- <vscale x 1 x i8> %0,
- <vscale x 1 x i8> %1,
- i8 %2,
- <vscale x 1 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 1 x i8> %a
-}
-
-declare <vscale x 2 x i8> @llvm.riscv.vmulhsu.nxv2i8.i8(
- <vscale x 2 x i8>,
- <vscale x 2 x i8>,
- i8,
- i32);
-
-define <vscale x 2 x i8> @intrinsic_vmulhsu_vx_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, i8 %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmulhsu_vx_nxv2i8_nxv2i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
-; CHECK-NEXT: vmulhsu.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i8> @llvm.riscv.vmulhsu.nxv2i8.i8(
- <vscale x 2 x i8> undef,
- <vscale x 2 x i8> %0,
- i8 %1,
- i32 %2)
-
- ret <vscale x 2 x i8> %a
-}
-
-declare <vscale x 2 x i8> @llvm.riscv.vmulhsu.mask.nxv2i8.i8(
- <vscale x 2 x i8>,
- <vscale x 2 x i8>,
- i8,
- <vscale x 2 x i1>,
- i32,
- i32);
-
-define <vscale x 2 x i8> @intrinsic_vmulhsu_mask_vx_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmulhsu_mask_vx_nxv2i8_nxv2i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
-; CHECK-NEXT: vmulhsu.vx v8, v9, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i8> @llvm.riscv.vmulhsu.mask.nxv2i8.i8(
- <vscale x 2 x i8> %0,
- <vscale x 2 x i8> %1,
- i8 %2,
- <vscale x 2 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 2 x i8> %a
-}
-
-declare <vscale x 4 x i8> @llvm.riscv.vmulhsu.nxv4i8.i8(
- <vscale x 4 x i8>,
- <vscale x 4 x i8>,
- i8,
- i32);
-
-define <vscale x 4 x i8> @intrinsic_vmulhsu_vx_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, i8 %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmulhsu_vx_nxv4i8_nxv4i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
-; CHECK-NEXT: vmulhsu.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i8> @llvm.riscv.vmulhsu.nxv4i8.i8(
- <vscale x 4 x i8> undef,
- <vscale x 4 x i8> %0,
- i8 %1,
- i32 %2)
-
- ret <vscale x 4 x i8> %a
-}
-
-declare <vscale x 4 x i8> @llvm.riscv.vmulhsu.mask.nxv4i8.i8(
- <vscale x 4 x i8>,
- <vscale x 4 x i8>,
- i8,
- <vscale x 4 x i1>,
- i32,
- i32);
-
-define <vscale x 4 x i8> @intrinsic_vmulhsu_mask_vx_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmulhsu_mask_vx_nxv4i8_nxv4i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
-; CHECK-NEXT: vmulhsu.vx v8, v9, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i8> @llvm.riscv.vmulhsu.mask.nxv4i8.i8(
- <vscale x 4 x i8> %0,
- <vscale x 4 x i8> %1,
- i8 %2,
- <vscale x 4 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 4 x i8> %a
-}
-
-declare <vscale x 8 x i8> @llvm.riscv.vmulhsu.nxv8i8.i8(
- <vscale x 8 x i8>,
- <vscale x 8 x i8>,
- i8,
- i32);
-
-define <vscale x 8 x i8> @intrinsic_vmulhsu_vx_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, i8 %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmulhsu_vx_nxv8i8_nxv8i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
-; CHECK-NEXT: vmulhsu.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i8> @llvm.riscv.vmulhsu.nxv8i8.i8(
- <vscale x 8 x i8> undef,
- <vscale x 8 x i8> %0,
- i8 %1,
- i32 %2)
-
- ret <vscale x 8 x i8> %a
-}
-
-declare <vscale x 8 x i8> @llvm.riscv.vmulhsu.mask.nxv8i8.i8(
- <vscale x 8 x i8>,
- <vscale x 8 x i8>,
- i8,
- <vscale x 8 x i1>,
- i32,
- i32);
-
-define <vscale x 8 x i8> @intrinsic_vmulhsu_mask_vx_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmulhsu_mask_vx_nxv8i8_nxv8i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
-; CHECK-NEXT: vmulhsu.vx v8, v9, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i8> @llvm.riscv.vmulhsu.mask.nxv8i8.i8(
- <vscale x 8 x i8> %0,
- <vscale x 8 x i8> %1,
- i8 %2,
- <vscale x 8 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 8 x i8> %a
-}
-
-declare <vscale x 16 x i8> @llvm.riscv.vmulhsu.nxv16i8.i8(
- <vscale x 16 x i8>,
- <vscale x 16 x i8>,
- i8,
- i32);
-
-define <vscale x 16 x i8> @intrinsic_vmulhsu_vx_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, i8 %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmulhsu_vx_nxv16i8_nxv16i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
-; CHECK-NEXT: vmulhsu.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i8> @llvm.riscv.vmulhsu.nxv16i8.i8(
- <vscale x 16 x i8> undef,
- <vscale x 16 x i8> %0,
- i8 %1,
- i32 %2)
-
- ret <vscale x 16 x i8> %a
-}
-
-declare <vscale x 16 x i8> @llvm.riscv.vmulhsu.mask.nxv16i8.i8(
- <vscale x 16 x i8>,
- <vscale x 16 x i8>,
- i8,
- <vscale x 16 x i1>,
- i32,
- i32);
-
-define <vscale x 16 x i8> @intrinsic_vmulhsu_mask_vx_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmulhsu_mask_vx_nxv16i8_nxv16i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
-; CHECK-NEXT: vmulhsu.vx v8, v10, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i8> @llvm.riscv.vmulhsu.mask.nxv16i8.i8(
- <vscale x 16 x i8> %0,
- <vscale x 16 x i8> %1,
- i8 %2,
- <vscale x 16 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 16 x i8> %a
-}
-
-declare <vscale x 32 x i8> @llvm.riscv.vmulhsu.nxv32i8.i8(
- <vscale x 32 x i8>,
- <vscale x 32 x i8>,
- i8,
- i32);
-
-define <vscale x 32 x i8> @intrinsic_vmulhsu_vx_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, i8 %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmulhsu_vx_nxv32i8_nxv32i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
-; CHECK-NEXT: vmulhsu.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 32 x i8> @llvm.riscv.vmulhsu.nxv32i8.i8(
- <vscale x 32 x i8> undef,
- <vscale x 32 x i8> %0,
- i8 %1,
- i32 %2)
-
- ret <vscale x 32 x i8> %a
-}
-
-declare <vscale x 32 x i8> @llvm.riscv.vmulhsu.mask.nxv32i8.i8(
- <vscale x 32 x i8>,
- <vscale x 32 x i8>,
- i8,
- <vscale x 32 x i1>,
- i32,
- i32);
-
-define <vscale x 32 x i8> @intrinsic_vmulhsu_mask_vx_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmulhsu_mask_vx_nxv32i8_nxv32i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
-; CHECK-NEXT: vmulhsu.vx v8, v12, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 32 x i8> @llvm.riscv.vmulhsu.mask.nxv32i8.i8(
- <vscale x 32 x i8> %0,
- <vscale x 32 x i8> %1,
- i8 %2,
- <vscale x 32 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 32 x i8> %a
-}
-
-declare <vscale x 64 x i8> @llvm.riscv.vmulhsu.nxv64i8.i8(
- <vscale x 64 x i8>,
- <vscale x 64 x i8>,
- i8,
- i32);
-
-define <vscale x 64 x i8> @intrinsic_vmulhsu_vx_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, i8 %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmulhsu_vx_nxv64i8_nxv64i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu
-; CHECK-NEXT: vmulhsu.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 64 x i8> @llvm.riscv.vmulhsu.nxv64i8.i8(
- <vscale x 64 x i8> undef,
- <vscale x 64 x i8> %0,
- i8 %1,
- i32 %2)
-
- ret <vscale x 64 x i8> %a
-}
-
-declare <vscale x 64 x i8> @llvm.riscv.vmulhsu.mask.nxv64i8.i8(
- <vscale x 64 x i8>,
- <vscale x 64 x i8>,
- i8,
- <vscale x 64 x i1>,
- i32,
- i32);
-
-define <vscale x 64 x i8> @intrinsic_vmulhsu_mask_vx_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i8 %2, <vscale x 64 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmulhsu_mask_vx_nxv64i8_nxv64i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu
-; CHECK-NEXT: vmulhsu.vx v8, v16, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 64 x i8> @llvm.riscv.vmulhsu.mask.nxv64i8.i8(
- <vscale x 64 x i8> %0,
- <vscale x 64 x i8> %1,
- i8 %2,
- <vscale x 64 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 64 x i8> %a
-}
-
-declare <vscale x 1 x i16> @llvm.riscv.vmulhsu.nxv1i16.i16(
- <vscale x 1 x i16>,
- <vscale x 1 x i16>,
- i16,
- i32);
-
-define <vscale x 1 x i16> @intrinsic_vmulhsu_vx_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, i16 %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmulhsu_vx_nxv1i16_nxv1i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
-; CHECK-NEXT: vmulhsu.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i16> @llvm.riscv.vmulhsu.nxv1i16.i16(
- <vscale x 1 x i16> undef,
- <vscale x 1 x i16> %0,
- i16 %1,
- i32 %2)
-
- ret <vscale x 1 x i16> %a
-}
-
-declare <vscale x 1 x i16> @llvm.riscv.vmulhsu.mask.nxv1i16.i16(
- <vscale x 1 x i16>,
- <vscale x 1 x i16>,
- i16,
- <vscale x 1 x i1>,
- i32,
- i32);
-
-define <vscale x 1 x i16> @intrinsic_vmulhsu_mask_vx_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmulhsu_mask_vx_nxv1i16_nxv1i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
-; CHECK-NEXT: vmulhsu.vx v8, v9, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i16> @llvm.riscv.vmulhsu.mask.nxv1i16.i16(
- <vscale x 1 x i16> %0,
- <vscale x 1 x i16> %1,
- i16 %2,
- <vscale x 1 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 1 x i16> %a
-}
-
-declare <vscale x 2 x i16> @llvm.riscv.vmulhsu.nxv2i16.i16(
- <vscale x 2 x i16>,
- <vscale x 2 x i16>,
- i16,
- i32);
-
-define <vscale x 2 x i16> @intrinsic_vmulhsu_vx_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, i16 %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmulhsu_vx_nxv2i16_nxv2i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
-; CHECK-NEXT: vmulhsu.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i16> @llvm.riscv.vmulhsu.nxv2i16.i16(
- <vscale x 2 x i16> undef,
- <vscale x 2 x i16> %0,
- i16 %1,
- i32 %2)
-
- ret <vscale x 2 x i16> %a
-}
-
-declare <vscale x 2 x i16> @llvm.riscv.vmulhsu.mask.nxv2i16.i16(
- <vscale x 2 x i16>,
- <vscale x 2 x i16>,
- i16,
- <vscale x 2 x i1>,
- i32,
- i32);
-
-define <vscale x 2 x i16> @intrinsic_vmulhsu_mask_vx_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmulhsu_mask_vx_nxv2i16_nxv2i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
-; CHECK-NEXT: vmulhsu.vx v8, v9, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i16> @llvm.riscv.vmulhsu.mask.nxv2i16.i16(
- <vscale x 2 x i16> %0,
- <vscale x 2 x i16> %1,
- i16 %2,
- <vscale x 2 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 2 x i16> %a
-}
-
-declare <vscale x 4 x i16> @llvm.riscv.vmulhsu.nxv4i16.i16(
- <vscale x 4 x i16>,
- <vscale x 4 x i16>,
- i16,
- i32);
-
-define <vscale x 4 x i16> @intrinsic_vmulhsu_vx_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, i16 %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmulhsu_vx_nxv4i16_nxv4i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
-; CHECK-NEXT: vmulhsu.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i16> @llvm.riscv.vmulhsu.nxv4i16.i16(
- <vscale x 4 x i16> undef,
- <vscale x 4 x i16> %0,
- i16 %1,
- i32 %2)
-
- ret <vscale x 4 x i16> %a
-}
-
-declare <vscale x 4 x i16> @llvm.riscv.vmulhsu.mask.nxv4i16.i16(
- <vscale x 4 x i16>,
- <vscale x 4 x i16>,
- i16,
- <vscale x 4 x i1>,
- i32,
- i32);
-
-define <vscale x 4 x i16> @intrinsic_vmulhsu_mask_vx_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmulhsu_mask_vx_nxv4i16_nxv4i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
-; CHECK-NEXT: vmulhsu.vx v8, v9, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i16> @llvm.riscv.vmulhsu.mask.nxv4i16.i16(
- <vscale x 4 x i16> %0,
- <vscale x 4 x i16> %1,
- i16 %2,
- <vscale x 4 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 4 x i16> %a
-}
-
-declare <vscale x 8 x i16> @llvm.riscv.vmulhsu.nxv8i16.i16(
- <vscale x 8 x i16>,
- <vscale x 8 x i16>,
- i16,
- i32);
-
-define <vscale x 8 x i16> @intrinsic_vmulhsu_vx_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, i16 %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmulhsu_vx_nxv8i16_nxv8i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
-; CHECK-NEXT: vmulhsu.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i16> @llvm.riscv.vmulhsu.nxv8i16.i16(
- <vscale x 8 x i16> undef,
- <vscale x 8 x i16> %0,
- i16 %1,
- i32 %2)
-
- ret <vscale x 8 x i16> %a
-}
-
-declare <vscale x 8 x i16> @llvm.riscv.vmulhsu.mask.nxv8i16.i16(
- <vscale x 8 x i16>,
- <vscale x 8 x i16>,
- i16,
- <vscale x 8 x i1>,
- i32,
- i32);
-
-define <vscale x 8 x i16> @intrinsic_vmulhsu_mask_vx_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmulhsu_mask_vx_nxv8i16_nxv8i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
-; CHECK-NEXT: vmulhsu.vx v8, v10, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i16> @llvm.riscv.vmulhsu.mask.nxv8i16.i16(
- <vscale x 8 x i16> %0,
- <vscale x 8 x i16> %1,
- i16 %2,
- <vscale x 8 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 8 x i16> %a
-}
-
-declare <vscale x 16 x i16> @llvm.riscv.vmulhsu.nxv16i16.i16(
- <vscale x 16 x i16>,
- <vscale x 16 x i16>,
- i16,
- i32);
-
-define <vscale x 16 x i16> @intrinsic_vmulhsu_vx_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, i16 %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmulhsu_vx_nxv16i16_nxv16i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
-; CHECK-NEXT: vmulhsu.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i16> @llvm.riscv.vmulhsu.nxv16i16.i16(
- <vscale x 16 x i16> undef,
- <vscale x 16 x i16> %0,
- i16 %1,
- i32 %2)
-
- ret <vscale x 16 x i16> %a
-}
-
-declare <vscale x 16 x i16> @llvm.riscv.vmulhsu.mask.nxv16i16.i16(
- <vscale x 16 x i16>,
- <vscale x 16 x i16>,
- i16,
- <vscale x 16 x i1>,
- i32,
- i32);
-
-define <vscale x 16 x i16> @intrinsic_vmulhsu_mask_vx_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmulhsu_mask_vx_nxv16i16_nxv16i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
-; CHECK-NEXT: vmulhsu.vx v8, v12, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i16> @llvm.riscv.vmulhsu.mask.nxv16i16.i16(
- <vscale x 16 x i16> %0,
- <vscale x 16 x i16> %1,
- i16 %2,
- <vscale x 16 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 16 x i16> %a
-}
-
-declare <vscale x 32 x i16> @llvm.riscv.vmulhsu.nxv32i16.i16(
- <vscale x 32 x i16>,
- <vscale x 32 x i16>,
- i16,
- i32);
-
-define <vscale x 32 x i16> @intrinsic_vmulhsu_vx_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, i16 %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmulhsu_vx_nxv32i16_nxv32i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu
-; CHECK-NEXT: vmulhsu.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 32 x i16> @llvm.riscv.vmulhsu.nxv32i16.i16(
- <vscale x 32 x i16> undef,
- <vscale x 32 x i16> %0,
- i16 %1,
- i32 %2)
-
- ret <vscale x 32 x i16> %a
-}
-
-declare <vscale x 32 x i16> @llvm.riscv.vmulhsu.mask.nxv32i16.i16(
- <vscale x 32 x i16>,
- <vscale x 32 x i16>,
- i16,
- <vscale x 32 x i1>,
- i32,
- i32);
-
-define <vscale x 32 x i16> @intrinsic_vmulhsu_mask_vx_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, i16 %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmulhsu_mask_vx_nxv32i16_nxv32i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu
-; CHECK-NEXT: vmulhsu.vx v8, v16, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 32 x i16> @llvm.riscv.vmulhsu.mask.nxv32i16.i16(
- <vscale x 32 x i16> %0,
- <vscale x 32 x i16> %1,
- i16 %2,
- <vscale x 32 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 32 x i16> %a
-}
-
-declare <vscale x 1 x i32> @llvm.riscv.vmulhsu.nxv1i32.i32(
- <vscale x 1 x i32>,
- <vscale x 1 x i32>,
- i32,
- i32);
-
-define <vscale x 1 x i32> @intrinsic_vmulhsu_vx_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, i32 %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmulhsu_vx_nxv1i32_nxv1i32_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
-; CHECK-NEXT: vmulhsu.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i32> @llvm.riscv.vmulhsu.nxv1i32.i32(
- <vscale x 1 x i32> undef,
- <vscale x 1 x i32> %0,
- i32 %1,
- i32 %2)
-
- ret <vscale x 1 x i32> %a
-}
-
-declare <vscale x 1 x i32> @llvm.riscv.vmulhsu.mask.nxv1i32.i32(
- <vscale x 1 x i32>,
- <vscale x 1 x i32>,
- i32,
- <vscale x 1 x i1>,
- i32,
- i32);
-
-define <vscale x 1 x i32> @intrinsic_vmulhsu_mask_vx_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmulhsu_mask_vx_nxv1i32_nxv1i32_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
-; CHECK-NEXT: vmulhsu.vx v8, v9, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i32> @llvm.riscv.vmulhsu.mask.nxv1i32.i32(
- <vscale x 1 x i32> %0,
- <vscale x 1 x i32> %1,
- i32 %2,
- <vscale x 1 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 1 x i32> %a
-}
-
-declare <vscale x 2 x i32> @llvm.riscv.vmulhsu.nxv2i32.i32(
- <vscale x 2 x i32>,
- <vscale x 2 x i32>,
- i32,
- i32);
-
-define <vscale x 2 x i32> @intrinsic_vmulhsu_vx_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, i32 %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmulhsu_vx_nxv2i32_nxv2i32_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
-; CHECK-NEXT: vmulhsu.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i32> @llvm.riscv.vmulhsu.nxv2i32.i32(
- <vscale x 2 x i32> undef,
- <vscale x 2 x i32> %0,
- i32 %1,
- i32 %2)
-
- ret <vscale x 2 x i32> %a
-}
-
-declare <vscale x 2 x i32> @llvm.riscv.vmulhsu.mask.nxv2i32.i32(
- <vscale x 2 x i32>,
- <vscale x 2 x i32>,
- i32,
- <vscale x 2 x i1>,
- i32,
- i32);
-
-define <vscale x 2 x i32> @intrinsic_vmulhsu_mask_vx_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmulhsu_mask_vx_nxv2i32_nxv2i32_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
-; CHECK-NEXT: vmulhsu.vx v8, v9, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i32> @llvm.riscv.vmulhsu.mask.nxv2i32.i32(
- <vscale x 2 x i32> %0,
- <vscale x 2 x i32> %1,
- i32 %2,
- <vscale x 2 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 2 x i32> %a
-}
-
-declare <vscale x 4 x i32> @llvm.riscv.vmulhsu.nxv4i32.i32(
- <vscale x 4 x i32>,
- <vscale x 4 x i32>,
- i32,
- i32);
-
-define <vscale x 4 x i32> @intrinsic_vmulhsu_vx_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, i32 %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmulhsu_vx_nxv4i32_nxv4i32_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; CHECK-NEXT: vmulhsu.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i32> @llvm.riscv.vmulhsu.nxv4i32.i32(
- <vscale x 4 x i32> undef,
- <vscale x 4 x i32> %0,
- i32 %1,
- i32 %2)
-
- ret <vscale x 4 x i32> %a
-}
-
-declare <vscale x 4 x i32> @llvm.riscv.vmulhsu.mask.nxv4i32.i32(
- <vscale x 4 x i32>,
- <vscale x 4 x i32>,
- i32,
- <vscale x 4 x i1>,
- i32,
- i32);
-
-define <vscale x 4 x i32> @intrinsic_vmulhsu_mask_vx_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmulhsu_mask_vx_nxv4i32_nxv4i32_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; CHECK-NEXT: vmulhsu.vx v8, v10, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i32> @llvm.riscv.vmulhsu.mask.nxv4i32.i32(
- <vscale x 4 x i32> %0,
- <vscale x 4 x i32> %1,
- i32 %2,
- <vscale x 4 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 4 x i32> %a
-}
-
-declare <vscale x 8 x i32> @llvm.riscv.vmulhsu.nxv8i32.i32(
- <vscale x 8 x i32>,
- <vscale x 8 x i32>,
- i32,
- i32);
-
-define <vscale x 8 x i32> @intrinsic_vmulhsu_vx_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, i32 %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmulhsu_vx_nxv8i32_nxv8i32_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
-; CHECK-NEXT: vmulhsu.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i32> @llvm.riscv.vmulhsu.nxv8i32.i32(
- <vscale x 8 x i32> undef,
- <vscale x 8 x i32> %0,
- i32 %1,
- i32 %2)
-
- ret <vscale x 8 x i32> %a
-}
-
-declare <vscale x 8 x i32> @llvm.riscv.vmulhsu.mask.nxv8i32.i32(
- <vscale x 8 x i32>,
- <vscale x 8 x i32>,
- i32,
- <vscale x 8 x i1>,
- i32,
- i32);
-
-define <vscale x 8 x i32> @intrinsic_vmulhsu_mask_vx_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmulhsu_mask_vx_nxv8i32_nxv8i32_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
-; CHECK-NEXT: vmulhsu.vx v8, v12, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i32> @llvm.riscv.vmulhsu.mask.nxv8i32.i32(
- <vscale x 8 x i32> %0,
- <vscale x 8 x i32> %1,
- i32 %2,
- <vscale x 8 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 8 x i32> %a
-}
-
-declare <vscale x 16 x i32> @llvm.riscv.vmulhsu.nxv16i32.i32(
- <vscale x 16 x i32>,
- <vscale x 16 x i32>,
- i32,
- i32);
-
-define <vscale x 16 x i32> @intrinsic_vmulhsu_vx_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, i32 %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmulhsu_vx_nxv16i32_nxv16i32_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu
-; CHECK-NEXT: vmulhsu.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i32> @llvm.riscv.vmulhsu.nxv16i32.i32(
- <vscale x 16 x i32> undef,
- <vscale x 16 x i32> %0,
- i32 %1,
- i32 %2)
-
- ret <vscale x 16 x i32> %a
-}
-
-declare <vscale x 16 x i32> @llvm.riscv.vmulhsu.mask.nxv16i32.i32(
- <vscale x 16 x i32>,
- <vscale x 16 x i32>,
- i32,
- <vscale x 16 x i1>,
- i32,
- i32);
-
-define <vscale x 16 x i32> @intrinsic_vmulhsu_mask_vx_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmulhsu_mask_vx_nxv16i32_nxv16i32_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu
-; CHECK-NEXT: vmulhsu.vx v8, v16, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i32> @llvm.riscv.vmulhsu.mask.nxv16i32.i32(
- <vscale x 16 x i32> %0,
- <vscale x 16 x i32> %1,
- i32 %2,
- <vscale x 16 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 16 x i32> %a
-}
-
-declare <vscale x 1 x i64> @llvm.riscv.vmulhsu.nxv1i64.i64(
- <vscale x 1 x i64>,
- <vscale x 1 x i64>,
- i64,
- i32);
-
-define <vscale x 1 x i64> @intrinsic_vmulhsu_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmulhsu_vx_nxv1i64_nxv1i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addi sp, sp, -16
-; CHECK-NEXT: sw a1, 12(sp)
-; CHECK-NEXT: sw a0, 8(sp)
-; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
-; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v9, (a0), zero
-; CHECK-NEXT: vmulhsu.vv v8, v8, v9
-; CHECK-NEXT: addi sp, sp, 16
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i64> @llvm.riscv.vmulhsu.nxv1i64.i64(
- <vscale x 1 x i64> undef,
- <vscale x 1 x i64> %0,
- i64 %1,
- i32 %2)
-
- ret <vscale x 1 x i64> %a
-}
-
-declare <vscale x 1 x i64> @llvm.riscv.vmulhsu.mask.nxv1i64.i64(
- <vscale x 1 x i64>,
- <vscale x 1 x i64>,
- i64,
- <vscale x 1 x i1>,
- i32,
- i32);
-
-define <vscale x 1 x i64> @intrinsic_vmulhsu_mask_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmulhsu_mask_vx_nxv1i64_nxv1i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addi sp, sp, -16
-; CHECK-NEXT: sw a1, 12(sp)
-; CHECK-NEXT: sw a0, 8(sp)
-; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
-; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v10, (a0), zero
-; CHECK-NEXT: vmulhsu.vv v8, v9, v10, v0.t
-; CHECK-NEXT: addi sp, sp, 16
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i64> @llvm.riscv.vmulhsu.mask.nxv1i64.i64(
- <vscale x 1 x i64> %0,
- <vscale x 1 x i64> %1,
- i64 %2,
- <vscale x 1 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 1 x i64> %a
-}
-
-declare <vscale x 2 x i64> @llvm.riscv.vmulhsu.nxv2i64.i64(
- <vscale x 2 x i64>,
- <vscale x 2 x i64>,
- i64,
- i32);
-
-define <vscale x 2 x i64> @intrinsic_vmulhsu_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmulhsu_vx_nxv2i64_nxv2i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addi sp, sp, -16
-; CHECK-NEXT: sw a1, 12(sp)
-; CHECK-NEXT: sw a0, 8(sp)
-; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
-; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v10, (a0), zero
-; CHECK-NEXT: vmulhsu.vv v8, v8, v10
-; CHECK-NEXT: addi sp, sp, 16
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i64> @llvm.riscv.vmulhsu.nxv2i64.i64(
- <vscale x 2 x i64> undef,
- <vscale x 2 x i64> %0,
- i64 %1,
- i32 %2)
-
- ret <vscale x 2 x i64> %a
-}
-
-declare <vscale x 2 x i64> @llvm.riscv.vmulhsu.mask.nxv2i64.i64(
- <vscale x 2 x i64>,
- <vscale x 2 x i64>,
- i64,
- <vscale x 2 x i1>,
- i32,
- i32);
-
-define <vscale x 2 x i64> @intrinsic_vmulhsu_mask_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmulhsu_mask_vx_nxv2i64_nxv2i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addi sp, sp, -16
-; CHECK-NEXT: sw a1, 12(sp)
-; CHECK-NEXT: sw a0, 8(sp)
-; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
-; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v12, (a0), zero
-; CHECK-NEXT: vmulhsu.vv v8, v10, v12, v0.t
-; CHECK-NEXT: addi sp, sp, 16
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i64> @llvm.riscv.vmulhsu.mask.nxv2i64.i64(
- <vscale x 2 x i64> %0,
- <vscale x 2 x i64> %1,
- i64 %2,
- <vscale x 2 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 2 x i64> %a
-}
-
-declare <vscale x 4 x i64> @llvm.riscv.vmulhsu.nxv4i64.i64(
- <vscale x 4 x i64>,
- <vscale x 4 x i64>,
- i64,
- i32);
-
-define <vscale x 4 x i64> @intrinsic_vmulhsu_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmulhsu_vx_nxv4i64_nxv4i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addi sp, sp, -16
-; CHECK-NEXT: sw a1, 12(sp)
-; CHECK-NEXT: sw a0, 8(sp)
-; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
-; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v12, (a0), zero
-; CHECK-NEXT: vmulhsu.vv v8, v8, v12
-; CHECK-NEXT: addi sp, sp, 16
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i64> @llvm.riscv.vmulhsu.nxv4i64.i64(
- <vscale x 4 x i64> undef,
- <vscale x 4 x i64> %0,
- i64 %1,
- i32 %2)
-
- ret <vscale x 4 x i64> %a
-}
-
-declare <vscale x 4 x i64> @llvm.riscv.vmulhsu.mask.nxv4i64.i64(
- <vscale x 4 x i64>,
- <vscale x 4 x i64>,
- i64,
- <vscale x 4 x i1>,
- i32,
- i32);
-
-define <vscale x 4 x i64> @intrinsic_vmulhsu_mask_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmulhsu_mask_vx_nxv4i64_nxv4i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addi sp, sp, -16
-; CHECK-NEXT: sw a1, 12(sp)
-; CHECK-NEXT: sw a0, 8(sp)
-; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
-; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v16, (a0), zero
-; CHECK-NEXT: vmulhsu.vv v8, v12, v16, v0.t
-; CHECK-NEXT: addi sp, sp, 16
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i64> @llvm.riscv.vmulhsu.mask.nxv4i64.i64(
- <vscale x 4 x i64> %0,
- <vscale x 4 x i64> %1,
- i64 %2,
- <vscale x 4 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 4 x i64> %a
-}
-
-declare <vscale x 8 x i64> @llvm.riscv.vmulhsu.nxv8i64.i64(
- <vscale x 8 x i64>,
- <vscale x 8 x i64>,
- i64,
- i32);
-
-define <vscale x 8 x i64> @intrinsic_vmulhsu_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, i64 %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmulhsu_vx_nxv8i64_nxv8i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addi sp, sp, -16
-; CHECK-NEXT: sw a1, 12(sp)
-; CHECK-NEXT: sw a0, 8(sp)
-; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, mu
-; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v16, (a0), zero
-; CHECK-NEXT: vmulhsu.vv v8, v8, v16
-; CHECK-NEXT: addi sp, sp, 16
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i64> @llvm.riscv.vmulhsu.nxv8i64.i64(
- <vscale x 8 x i64> undef,
- <vscale x 8 x i64> %0,
- i64 %1,
- i32 %2)
-
- ret <vscale x 8 x i64> %a
-}
-
-declare <vscale x 8 x i64> @llvm.riscv.vmulhsu.mask.nxv8i64.i64(
- <vscale x 8 x i64>,
- <vscale x 8 x i64>,
- i64,
- <vscale x 8 x i1>,
- i32,
- i32);
-
-define <vscale x 8 x i64> @intrinsic_vmulhsu_mask_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmulhsu_mask_vx_nxv8i64_nxv8i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addi sp, sp, -16
-; CHECK-NEXT: sw a1, 12(sp)
-; CHECK-NEXT: sw a0, 8(sp)
-; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, mu
-; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v24, (a0), zero
-; CHECK-NEXT: vmulhsu.vv v8, v16, v24, v0.t
-; CHECK-NEXT: addi sp, sp, 16
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i64> @llvm.riscv.vmulhsu.mask.nxv8i64.i64(
- <vscale x 8 x i64> %0,
- <vscale x 8 x i64> %1,
- i64 %2,
- <vscale x 8 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 8 x i64> %a
-}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmulhsu-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vmulhsu.ll
similarity index 80%
rename from llvm/test/CodeGen/RISCV/rvv/vmulhsu-rv64.ll
rename to llvm/test/CodeGen/RISCV/rvv/vmulhsu.ll
index fd7f4a120ccff..a9a1527368dac 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vmulhsu-rv64.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vmulhsu.ll
@@ -1,13 +1,15 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs \
-; RUN: < %s | FileCheck %s
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v \
+; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,RV32
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v \
+; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,RV64
declare <vscale x 1 x i8> @llvm.riscv.vmulhsu.nxv1i8.nxv1i8(
<vscale x 1 x i8>,
<vscale x 1 x i8>,
<vscale x 1 x i8>,
- i64);
+ iXLen);
-define <vscale x 1 x i8> @intrinsic_vmulhsu_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2) nounwind {
+define <vscale x 1 x i8> @intrinsic_vmulhsu_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmulhsu_vv_nxv1i8_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
@@ -18,7 +20,7 @@ entry:
<vscale x 1 x i8> undef,
<vscale x 1 x i8> %0,
<vscale x 1 x i8> %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 1 x i8> %a
}
@@ -28,10 +30,9 @@ declare <vscale x 1 x i8> @llvm.riscv.vmulhsu.mask.nxv1i8.nxv1i8(
<vscale x 1 x i8>,
<vscale x 1 x i8>,
<vscale x 1 x i1>,
- i64,
- i64);
+ iXLen, iXLen);
-define <vscale x 1 x i8> @intrinsic_vmulhsu_mask_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+define <vscale x 1 x i8> @intrinsic_vmulhsu_mask_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmulhsu_mask_vv_nxv1i8_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
@@ -43,7 +44,7 @@ entry:
<vscale x 1 x i8> %1,
<vscale x 1 x i8> %2,
<vscale x 1 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 1 x i8> %a
}
@@ -52,9 +53,9 @@ declare <vscale x 2 x i8> @llvm.riscv.vmulhsu.nxv2i8.nxv2i8(
<vscale x 2 x i8>,
<vscale x 2 x i8>,
<vscale x 2 x i8>,
- i64);
+ iXLen);
-define <vscale x 2 x i8> @intrinsic_vmulhsu_vv_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2) nounwind {
+define <vscale x 2 x i8> @intrinsic_vmulhsu_vv_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmulhsu_vv_nxv2i8_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
@@ -65,7 +66,7 @@ entry:
<vscale x 2 x i8> undef,
<vscale x 2 x i8> %0,
<vscale x 2 x i8> %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 2 x i8> %a
}
@@ -75,10 +76,9 @@ declare <vscale x 2 x i8> @llvm.riscv.vmulhsu.mask.nxv2i8.nxv2i8(
<vscale x 2 x i8>,
<vscale x 2 x i8>,
<vscale x 2 x i1>,
- i64,
- i64);
+ iXLen, iXLen);
-define <vscale x 2 x i8> @intrinsic_vmulhsu_mask_vv_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+define <vscale x 2 x i8> @intrinsic_vmulhsu_mask_vv_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmulhsu_mask_vv_nxv2i8_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
@@ -90,7 +90,7 @@ entry:
<vscale x 2 x i8> %1,
<vscale x 2 x i8> %2,
<vscale x 2 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 2 x i8> %a
}
@@ -99,9 +99,9 @@ declare <vscale x 4 x i8> @llvm.riscv.vmulhsu.nxv4i8.nxv4i8(
<vscale x 4 x i8>,
<vscale x 4 x i8>,
<vscale x 4 x i8>,
- i64);
+ iXLen);
-define <vscale x 4 x i8> @intrinsic_vmulhsu_vv_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2) nounwind {
+define <vscale x 4 x i8> @intrinsic_vmulhsu_vv_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmulhsu_vv_nxv4i8_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
@@ -112,7 +112,7 @@ entry:
<vscale x 4 x i8> undef,
<vscale x 4 x i8> %0,
<vscale x 4 x i8> %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 4 x i8> %a
}
@@ -122,10 +122,9 @@ declare <vscale x 4 x i8> @llvm.riscv.vmulhsu.mask.nxv4i8.nxv4i8(
<vscale x 4 x i8>,
<vscale x 4 x i8>,
<vscale x 4 x i1>,
- i64,
- i64);
+ iXLen, iXLen);
-define <vscale x 4 x i8> @intrinsic_vmulhsu_mask_vv_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+define <vscale x 4 x i8> @intrinsic_vmulhsu_mask_vv_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmulhsu_mask_vv_nxv4i8_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
@@ -137,7 +136,7 @@ entry:
<vscale x 4 x i8> %1,
<vscale x 4 x i8> %2,
<vscale x 4 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 4 x i8> %a
}
@@ -146,9 +145,9 @@ declare <vscale x 8 x i8> @llvm.riscv.vmulhsu.nxv8i8.nxv8i8(
<vscale x 8 x i8>,
<vscale x 8 x i8>,
<vscale x 8 x i8>,
- i64);
+ iXLen);
-define <vscale x 8 x i8> @intrinsic_vmulhsu_vv_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2) nounwind {
+define <vscale x 8 x i8> @intrinsic_vmulhsu_vv_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmulhsu_vv_nxv8i8_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
@@ -159,7 +158,7 @@ entry:
<vscale x 8 x i8> undef,
<vscale x 8 x i8> %0,
<vscale x 8 x i8> %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 8 x i8> %a
}
@@ -169,10 +168,9 @@ declare <vscale x 8 x i8> @llvm.riscv.vmulhsu.mask.nxv8i8.nxv8i8(
<vscale x 8 x i8>,
<vscale x 8 x i8>,
<vscale x 8 x i1>,
- i64,
- i64);
+ iXLen, iXLen);
-define <vscale x 8 x i8> @intrinsic_vmulhsu_mask_vv_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+define <vscale x 8 x i8> @intrinsic_vmulhsu_mask_vv_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmulhsu_mask_vv_nxv8i8_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
@@ -184,7 +182,7 @@ entry:
<vscale x 8 x i8> %1,
<vscale x 8 x i8> %2,
<vscale x 8 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 8 x i8> %a
}
@@ -193,9 +191,9 @@ declare <vscale x 16 x i8> @llvm.riscv.vmulhsu.nxv16i8.nxv16i8(
<vscale x 16 x i8>,
<vscale x 16 x i8>,
<vscale x 16 x i8>,
- i64);
+ iXLen);
-define <vscale x 16 x i8> @intrinsic_vmulhsu_vv_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2) nounwind {
+define <vscale x 16 x i8> @intrinsic_vmulhsu_vv_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmulhsu_vv_nxv16i8_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
@@ -206,7 +204,7 @@ entry:
<vscale x 16 x i8> undef,
<vscale x 16 x i8> %0,
<vscale x 16 x i8> %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 16 x i8> %a
}
@@ -216,10 +214,9 @@ declare <vscale x 16 x i8> @llvm.riscv.vmulhsu.mask.nxv16i8.nxv16i8(
<vscale x 16 x i8>,
<vscale x 16 x i8>,
<vscale x 16 x i1>,
- i64,
- i64);
+ iXLen, iXLen);
-define <vscale x 16 x i8> @intrinsic_vmulhsu_mask_vv_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+define <vscale x 16 x i8> @intrinsic_vmulhsu_mask_vv_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmulhsu_mask_vv_nxv16i8_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
@@ -231,7 +228,7 @@ entry:
<vscale x 16 x i8> %1,
<vscale x 16 x i8> %2,
<vscale x 16 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 16 x i8> %a
}
@@ -240,9 +237,9 @@ declare <vscale x 32 x i8> @llvm.riscv.vmulhsu.nxv32i8.nxv32i8(
<vscale x 32 x i8>,
<vscale x 32 x i8>,
<vscale x 32 x i8>,
- i64);
+ iXLen);
-define <vscale x 32 x i8> @intrinsic_vmulhsu_vv_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i64 %2) nounwind {
+define <vscale x 32 x i8> @intrinsic_vmulhsu_vv_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmulhsu_vv_nxv32i8_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
@@ -253,7 +250,7 @@ entry:
<vscale x 32 x i8> undef,
<vscale x 32 x i8> %0,
<vscale x 32 x i8> %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 32 x i8> %a
}
@@ -263,10 +260,9 @@ declare <vscale x 32 x i8> @llvm.riscv.vmulhsu.mask.nxv32i8.nxv32i8(
<vscale x 32 x i8>,
<vscale x 32 x i8>,
<vscale x 32 x i1>,
- i64,
- i64);
+ iXLen, iXLen);
-define <vscale x 32 x i8> @intrinsic_vmulhsu_mask_vv_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
+define <vscale x 32 x i8> @intrinsic_vmulhsu_mask_vv_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmulhsu_mask_vv_nxv32i8_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
@@ -278,7 +274,7 @@ entry:
<vscale x 32 x i8> %1,
<vscale x 32 x i8> %2,
<vscale x 32 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 32 x i8> %a
}
@@ -287,9 +283,9 @@ declare <vscale x 64 x i8> @llvm.riscv.vmulhsu.nxv64i8.nxv64i8(
<vscale x 64 x i8>,
<vscale x 64 x i8>,
<vscale x 64 x i8>,
- i64);
+ iXLen);
-define <vscale x 64 x i8> @intrinsic_vmulhsu_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i64 %2) nounwind {
+define <vscale x 64 x i8> @intrinsic_vmulhsu_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmulhsu_vv_nxv64i8_nxv64i8_nxv64i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, mu
@@ -300,7 +296,7 @@ entry:
<vscale x 64 x i8> undef,
<vscale x 64 x i8> %0,
<vscale x 64 x i8> %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 64 x i8> %a
}
@@ -310,10 +306,9 @@ declare <vscale x 64 x i8> @llvm.riscv.vmulhsu.mask.nxv64i8.nxv64i8(
<vscale x 64 x i8>,
<vscale x 64 x i8>,
<vscale x 64 x i1>,
- i64,
- i64);
+ iXLen, iXLen);
-define <vscale x 64 x i8> @intrinsic_vmulhsu_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, i64 %4) nounwind {
+define <vscale x 64 x i8> @intrinsic_vmulhsu_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmulhsu_mask_vv_nxv64i8_nxv64i8_nxv64i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vl8r.v v24, (a0)
@@ -326,7 +321,7 @@ entry:
<vscale x 64 x i8> %1,
<vscale x 64 x i8> %2,
<vscale x 64 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 64 x i8> %a
}
@@ -335,9 +330,9 @@ declare <vscale x 1 x i16> @llvm.riscv.vmulhsu.nxv1i16.nxv1i16(
<vscale x 1 x i16>,
<vscale x 1 x i16>,
<vscale x 1 x i16>,
- i64);
+ iXLen);
-define <vscale x 1 x i16> @intrinsic_vmulhsu_vv_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i64 %2) nounwind {
+define <vscale x 1 x i16> @intrinsic_vmulhsu_vv_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmulhsu_vv_nxv1i16_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
@@ -348,7 +343,7 @@ entry:
<vscale x 1 x i16> undef,
<vscale x 1 x i16> %0,
<vscale x 1 x i16> %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 1 x i16> %a
}
@@ -358,10 +353,9 @@ declare <vscale x 1 x i16> @llvm.riscv.vmulhsu.mask.nxv1i16.nxv1i16(
<vscale x 1 x i16>,
<vscale x 1 x i16>,
<vscale x 1 x i1>,
- i64,
- i64);
+ iXLen, iXLen);
-define <vscale x 1 x i16> @intrinsic_vmulhsu_mask_vv_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+define <vscale x 1 x i16> @intrinsic_vmulhsu_mask_vv_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmulhsu_mask_vv_nxv1i16_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
@@ -373,7 +367,7 @@ entry:
<vscale x 1 x i16> %1,
<vscale x 1 x i16> %2,
<vscale x 1 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 1 x i16> %a
}
@@ -382,9 +376,9 @@ declare <vscale x 2 x i16> @llvm.riscv.vmulhsu.nxv2i16.nxv2i16(
<vscale x 2 x i16>,
<vscale x 2 x i16>,
<vscale x 2 x i16>,
- i64);
+ iXLen);
-define <vscale x 2 x i16> @intrinsic_vmulhsu_vv_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i64 %2) nounwind {
+define <vscale x 2 x i16> @intrinsic_vmulhsu_vv_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmulhsu_vv_nxv2i16_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
@@ -395,7 +389,7 @@ entry:
<vscale x 2 x i16> undef,
<vscale x 2 x i16> %0,
<vscale x 2 x i16> %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 2 x i16> %a
}
@@ -405,10 +399,9 @@ declare <vscale x 2 x i16> @llvm.riscv.vmulhsu.mask.nxv2i16.nxv2i16(
<vscale x 2 x i16>,
<vscale x 2 x i16>,
<vscale x 2 x i1>,
- i64,
- i64);
+ iXLen, iXLen);
-define <vscale x 2 x i16> @intrinsic_vmulhsu_mask_vv_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+define <vscale x 2 x i16> @intrinsic_vmulhsu_mask_vv_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmulhsu_mask_vv_nxv2i16_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
@@ -420,7 +413,7 @@ entry:
<vscale x 2 x i16> %1,
<vscale x 2 x i16> %2,
<vscale x 2 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 2 x i16> %a
}
@@ -429,9 +422,9 @@ declare <vscale x 4 x i16> @llvm.riscv.vmulhsu.nxv4i16.nxv4i16(
<vscale x 4 x i16>,
<vscale x 4 x i16>,
<vscale x 4 x i16>,
- i64);
+ iXLen);
-define <vscale x 4 x i16> @intrinsic_vmulhsu_vv_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i64 %2) nounwind {
+define <vscale x 4 x i16> @intrinsic_vmulhsu_vv_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmulhsu_vv_nxv4i16_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
@@ -442,7 +435,7 @@ entry:
<vscale x 4 x i16> undef,
<vscale x 4 x i16> %0,
<vscale x 4 x i16> %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 4 x i16> %a
}
@@ -452,10 +445,9 @@ declare <vscale x 4 x i16> @llvm.riscv.vmulhsu.mask.nxv4i16.nxv4i16(
<vscale x 4 x i16>,
<vscale x 4 x i16>,
<vscale x 4 x i1>,
- i64,
- i64);
+ iXLen, iXLen);
-define <vscale x 4 x i16> @intrinsic_vmulhsu_mask_vv_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+define <vscale x 4 x i16> @intrinsic_vmulhsu_mask_vv_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmulhsu_mask_vv_nxv4i16_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
@@ -467,7 +459,7 @@ entry:
<vscale x 4 x i16> %1,
<vscale x 4 x i16> %2,
<vscale x 4 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 4 x i16> %a
}
@@ -476,9 +468,9 @@ declare <vscale x 8 x i16> @llvm.riscv.vmulhsu.nxv8i16.nxv8i16(
<vscale x 8 x i16>,
<vscale x 8 x i16>,
<vscale x 8 x i16>,
- i64);
+ iXLen);
-define <vscale x 8 x i16> @intrinsic_vmulhsu_vv_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i64 %2) nounwind {
+define <vscale x 8 x i16> @intrinsic_vmulhsu_vv_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmulhsu_vv_nxv8i16_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
@@ -489,7 +481,7 @@ entry:
<vscale x 8 x i16> undef,
<vscale x 8 x i16> %0,
<vscale x 8 x i16> %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 8 x i16> %a
}
@@ -499,10 +491,9 @@ declare <vscale x 8 x i16> @llvm.riscv.vmulhsu.mask.nxv8i16.nxv8i16(
<vscale x 8 x i16>,
<vscale x 8 x i16>,
<vscale x 8 x i1>,
- i64,
- i64);
+ iXLen, iXLen);
-define <vscale x 8 x i16> @intrinsic_vmulhsu_mask_vv_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+define <vscale x 8 x i16> @intrinsic_vmulhsu_mask_vv_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmulhsu_mask_vv_nxv8i16_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
@@ -514,7 +505,7 @@ entry:
<vscale x 8 x i16> %1,
<vscale x 8 x i16> %2,
<vscale x 8 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 8 x i16> %a
}
@@ -523,9 +514,9 @@ declare <vscale x 16 x i16> @llvm.riscv.vmulhsu.nxv16i16.nxv16i16(
<vscale x 16 x i16>,
<vscale x 16 x i16>,
<vscale x 16 x i16>,
- i64);
+ iXLen);
-define <vscale x 16 x i16> @intrinsic_vmulhsu_vv_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i64 %2) nounwind {
+define <vscale x 16 x i16> @intrinsic_vmulhsu_vv_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmulhsu_vv_nxv16i16_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
@@ -536,7 +527,7 @@ entry:
<vscale x 16 x i16> undef,
<vscale x 16 x i16> %0,
<vscale x 16 x i16> %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 16 x i16> %a
}
@@ -546,10 +537,9 @@ declare <vscale x 16 x i16> @llvm.riscv.vmulhsu.mask.nxv16i16.nxv16i16(
<vscale x 16 x i16>,
<vscale x 16 x i16>,
<vscale x 16 x i1>,
- i64,
- i64);
+ iXLen, iXLen);
-define <vscale x 16 x i16> @intrinsic_vmulhsu_mask_vv_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+define <vscale x 16 x i16> @intrinsic_vmulhsu_mask_vv_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmulhsu_mask_vv_nxv16i16_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
@@ -561,7 +551,7 @@ entry:
<vscale x 16 x i16> %1,
<vscale x 16 x i16> %2,
<vscale x 16 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 16 x i16> %a
}
@@ -570,9 +560,9 @@ declare <vscale x 32 x i16> @llvm.riscv.vmulhsu.nxv32i16.nxv32i16(
<vscale x 32 x i16>,
<vscale x 32 x i16>,
<vscale x 32 x i16>,
- i64);
+ iXLen);
-define <vscale x 32 x i16> @intrinsic_vmulhsu_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, i64 %2) nounwind {
+define <vscale x 32 x i16> @intrinsic_vmulhsu_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmulhsu_vv_nxv32i16_nxv32i16_nxv32i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, mu
@@ -583,7 +573,7 @@ entry:
<vscale x 32 x i16> undef,
<vscale x 32 x i16> %0,
<vscale x 32 x i16> %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 32 x i16> %a
}
@@ -593,10 +583,9 @@ declare <vscale x 32 x i16> @llvm.riscv.vmulhsu.mask.nxv32i16.nxv32i16(
<vscale x 32 x i16>,
<vscale x 32 x i16>,
<vscale x 32 x i1>,
- i64,
- i64);
+ iXLen, iXLen);
-define <vscale x 32 x i16> @intrinsic_vmulhsu_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
+define <vscale x 32 x i16> @intrinsic_vmulhsu_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmulhsu_mask_vv_nxv32i16_nxv32i16_nxv32i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vl8re16.v v24, (a0)
@@ -609,7 +598,7 @@ entry:
<vscale x 32 x i16> %1,
<vscale x 32 x i16> %2,
<vscale x 32 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 32 x i16> %a
}
@@ -618,9 +607,9 @@ declare <vscale x 1 x i32> @llvm.riscv.vmulhsu.nxv1i32.nxv1i32(
<vscale x 1 x i32>,
<vscale x 1 x i32>,
<vscale x 1 x i32>,
- i64);
+ iXLen);
-define <vscale x 1 x i32> @intrinsic_vmulhsu_vv_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2) nounwind {
+define <vscale x 1 x i32> @intrinsic_vmulhsu_vv_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmulhsu_vv_nxv1i32_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
@@ -631,7 +620,7 @@ entry:
<vscale x 1 x i32> undef,
<vscale x 1 x i32> %0,
<vscale x 1 x i32> %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 1 x i32> %a
}
@@ -641,10 +630,9 @@ declare <vscale x 1 x i32> @llvm.riscv.vmulhsu.mask.nxv1i32.nxv1i32(
<vscale x 1 x i32>,
<vscale x 1 x i32>,
<vscale x 1 x i1>,
- i64,
- i64);
+ iXLen, iXLen);
-define <vscale x 1 x i32> @intrinsic_vmulhsu_mask_vv_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+define <vscale x 1 x i32> @intrinsic_vmulhsu_mask_vv_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmulhsu_mask_vv_nxv1i32_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
@@ -656,7 +644,7 @@ entry:
<vscale x 1 x i32> %1,
<vscale x 1 x i32> %2,
<vscale x 1 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 1 x i32> %a
}
@@ -665,9 +653,9 @@ declare <vscale x 2 x i32> @llvm.riscv.vmulhsu.nxv2i32.nxv2i32(
<vscale x 2 x i32>,
<vscale x 2 x i32>,
<vscale x 2 x i32>,
- i64);
+ iXLen);
-define <vscale x 2 x i32> @intrinsic_vmulhsu_vv_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2) nounwind {
+define <vscale x 2 x i32> @intrinsic_vmulhsu_vv_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmulhsu_vv_nxv2i32_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
@@ -678,7 +666,7 @@ entry:
<vscale x 2 x i32> undef,
<vscale x 2 x i32> %0,
<vscale x 2 x i32> %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 2 x i32> %a
}
@@ -688,10 +676,9 @@ declare <vscale x 2 x i32> @llvm.riscv.vmulhsu.mask.nxv2i32.nxv2i32(
<vscale x 2 x i32>,
<vscale x 2 x i32>,
<vscale x 2 x i1>,
- i64,
- i64);
+ iXLen, iXLen);
-define <vscale x 2 x i32> @intrinsic_vmulhsu_mask_vv_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+define <vscale x 2 x i32> @intrinsic_vmulhsu_mask_vv_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmulhsu_mask_vv_nxv2i32_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
@@ -703,7 +690,7 @@ entry:
<vscale x 2 x i32> %1,
<vscale x 2 x i32> %2,
<vscale x 2 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 2 x i32> %a
}
@@ -712,9 +699,9 @@ declare <vscale x 4 x i32> @llvm.riscv.vmulhsu.nxv4i32.nxv4i32(
<vscale x 4 x i32>,
<vscale x 4 x i32>,
<vscale x 4 x i32>,
- i64);
+ iXLen);
-define <vscale x 4 x i32> @intrinsic_vmulhsu_vv_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i64 %2) nounwind {
+define <vscale x 4 x i32> @intrinsic_vmulhsu_vv_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmulhsu_vv_nxv4i32_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
@@ -725,7 +712,7 @@ entry:
<vscale x 4 x i32> undef,
<vscale x 4 x i32> %0,
<vscale x 4 x i32> %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 4 x i32> %a
}
@@ -735,10 +722,9 @@ declare <vscale x 4 x i32> @llvm.riscv.vmulhsu.mask.nxv4i32.nxv4i32(
<vscale x 4 x i32>,
<vscale x 4 x i32>,
<vscale x 4 x i1>,
- i64,
- i64);
+ iXLen, iXLen);
-define <vscale x 4 x i32> @intrinsic_vmulhsu_mask_vv_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+define <vscale x 4 x i32> @intrinsic_vmulhsu_mask_vv_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmulhsu_mask_vv_nxv4i32_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
@@ -750,7 +736,7 @@ entry:
<vscale x 4 x i32> %1,
<vscale x 4 x i32> %2,
<vscale x 4 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 4 x i32> %a
}
@@ -759,9 +745,9 @@ declare <vscale x 8 x i32> @llvm.riscv.vmulhsu.nxv8i32.nxv8i32(
<vscale x 8 x i32>,
<vscale x 8 x i32>,
<vscale x 8 x i32>,
- i64);
+ iXLen);
-define <vscale x 8 x i32> @intrinsic_vmulhsu_vv_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i64 %2) nounwind {
+define <vscale x 8 x i32> @intrinsic_vmulhsu_vv_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmulhsu_vv_nxv8i32_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
@@ -772,7 +758,7 @@ entry:
<vscale x 8 x i32> undef,
<vscale x 8 x i32> %0,
<vscale x 8 x i32> %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 8 x i32> %a
}
@@ -782,10 +768,9 @@ declare <vscale x 8 x i32> @llvm.riscv.vmulhsu.mask.nxv8i32.nxv8i32(
<vscale x 8 x i32>,
<vscale x 8 x i32>,
<vscale x 8 x i1>,
- i64,
- i64);
+ iXLen, iXLen);
-define <vscale x 8 x i32> @intrinsic_vmulhsu_mask_vv_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+define <vscale x 8 x i32> @intrinsic_vmulhsu_mask_vv_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmulhsu_mask_vv_nxv8i32_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
@@ -797,7 +782,7 @@ entry:
<vscale x 8 x i32> %1,
<vscale x 8 x i32> %2,
<vscale x 8 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 8 x i32> %a
}
@@ -806,9 +791,9 @@ declare <vscale x 16 x i32> @llvm.riscv.vmulhsu.nxv16i32.nxv16i32(
<vscale x 16 x i32>,
<vscale x 16 x i32>,
<vscale x 16 x i32>,
- i64);
+ iXLen);
-define <vscale x 16 x i32> @intrinsic_vmulhsu_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i64 %2) nounwind {
+define <vscale x 16 x i32> @intrinsic_vmulhsu_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmulhsu_vv_nxv16i32_nxv16i32_nxv16i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu
@@ -819,7 +804,7 @@ entry:
<vscale x 16 x i32> undef,
<vscale x 16 x i32> %0,
<vscale x 16 x i32> %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 16 x i32> %a
}
@@ -829,10 +814,9 @@ declare <vscale x 16 x i32> @llvm.riscv.vmulhsu.mask.nxv16i32.nxv16i32(
<vscale x 16 x i32>,
<vscale x 16 x i32>,
<vscale x 16 x i1>,
- i64,
- i64);
+ iXLen, iXLen);
-define <vscale x 16 x i32> @intrinsic_vmulhsu_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+define <vscale x 16 x i32> @intrinsic_vmulhsu_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmulhsu_mask_vv_nxv16i32_nxv16i32_nxv16i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vl8re32.v v24, (a0)
@@ -845,7 +829,7 @@ entry:
<vscale x 16 x i32> %1,
<vscale x 16 x i32> %2,
<vscale x 16 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 16 x i32> %a
}
@@ -854,9 +838,9 @@ declare <vscale x 1 x i64> @llvm.riscv.vmulhsu.nxv1i64.nxv1i64(
<vscale x 1 x i64>,
<vscale x 1 x i64>,
<vscale x 1 x i64>,
- i64);
+ iXLen);
-define <vscale x 1 x i64> @intrinsic_vmulhsu_vv_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2) nounwind {
+define <vscale x 1 x i64> @intrinsic_vmulhsu_vv_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmulhsu_vv_nxv1i64_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
@@ -867,7 +851,7 @@ entry:
<vscale x 1 x i64> undef,
<vscale x 1 x i64> %0,
<vscale x 1 x i64> %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 1 x i64> %a
}
@@ -877,10 +861,9 @@ declare <vscale x 1 x i64> @llvm.riscv.vmulhsu.mask.nxv1i64.nxv1i64(
<vscale x 1 x i64>,
<vscale x 1 x i64>,
<vscale x 1 x i1>,
- i64,
- i64);
+ iXLen, iXLen);
-define <vscale x 1 x i64> @intrinsic_vmulhsu_mask_vv_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+define <vscale x 1 x i64> @intrinsic_vmulhsu_mask_vv_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmulhsu_mask_vv_nxv1i64_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
@@ -892,7 +875,7 @@ entry:
<vscale x 1 x i64> %1,
<vscale x 1 x i64> %2,
<vscale x 1 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 1 x i64> %a
}
@@ -901,9 +884,9 @@ declare <vscale x 2 x i64> @llvm.riscv.vmulhsu.nxv2i64.nxv2i64(
<vscale x 2 x i64>,
<vscale x 2 x i64>,
<vscale x 2 x i64>,
- i64);
+ iXLen);
-define <vscale x 2 x i64> @intrinsic_vmulhsu_vv_nxv2i64_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2) nounwind {
+define <vscale x 2 x i64> @intrinsic_vmulhsu_vv_nxv2i64_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmulhsu_vv_nxv2i64_nxv2i64_nxv2i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
@@ -914,7 +897,7 @@ entry:
<vscale x 2 x i64> undef,
<vscale x 2 x i64> %0,
<vscale x 2 x i64> %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 2 x i64> %a
}
@@ -924,10 +907,9 @@ declare <vscale x 2 x i64> @llvm.riscv.vmulhsu.mask.nxv2i64.nxv2i64(
<vscale x 2 x i64>,
<vscale x 2 x i64>,
<vscale x 2 x i1>,
- i64,
- i64);
+ iXLen, iXLen);
-define <vscale x 2 x i64> @intrinsic_vmulhsu_mask_vv_nxv2i64_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+define <vscale x 2 x i64> @intrinsic_vmulhsu_mask_vv_nxv2i64_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmulhsu_mask_vv_nxv2i64_nxv2i64_nxv2i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
@@ -939,7 +921,7 @@ entry:
<vscale x 2 x i64> %1,
<vscale x 2 x i64> %2,
<vscale x 2 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 2 x i64> %a
}
@@ -948,9 +930,9 @@ declare <vscale x 4 x i64> @llvm.riscv.vmulhsu.nxv4i64.nxv4i64(
<vscale x 4 x i64>,
<vscale x 4 x i64>,
<vscale x 4 x i64>,
- i64);
+ iXLen);
-define <vscale x 4 x i64> @intrinsic_vmulhsu_vv_nxv4i64_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2) nounwind {
+define <vscale x 4 x i64> @intrinsic_vmulhsu_vv_nxv4i64_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmulhsu_vv_nxv4i64_nxv4i64_nxv4i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
@@ -961,7 +943,7 @@ entry:
<vscale x 4 x i64> undef,
<vscale x 4 x i64> %0,
<vscale x 4 x i64> %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 4 x i64> %a
}
@@ -971,10 +953,9 @@ declare <vscale x 4 x i64> @llvm.riscv.vmulhsu.mask.nxv4i64.nxv4i64(
<vscale x 4 x i64>,
<vscale x 4 x i64>,
<vscale x 4 x i1>,
- i64,
- i64);
+ iXLen, iXLen);
-define <vscale x 4 x i64> @intrinsic_vmulhsu_mask_vv_nxv4i64_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+define <vscale x 4 x i64> @intrinsic_vmulhsu_mask_vv_nxv4i64_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmulhsu_mask_vv_nxv4i64_nxv4i64_nxv4i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
@@ -986,7 +967,7 @@ entry:
<vscale x 4 x i64> %1,
<vscale x 4 x i64> %2,
<vscale x 4 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 4 x i64> %a
}
@@ -995,9 +976,9 @@ declare <vscale x 8 x i64> @llvm.riscv.vmulhsu.nxv8i64.nxv8i64(
<vscale x 8 x i64>,
<vscale x 8 x i64>,
<vscale x 8 x i64>,
- i64);
+ iXLen);
-define <vscale x 8 x i64> @intrinsic_vmulhsu_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2) nounwind {
+define <vscale x 8 x i64> @intrinsic_vmulhsu_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmulhsu_vv_nxv8i64_nxv8i64_nxv8i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu
@@ -1008,7 +989,7 @@ entry:
<vscale x 8 x i64> undef,
<vscale x 8 x i64> %0,
<vscale x 8 x i64> %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 8 x i64> %a
}
@@ -1018,10 +999,9 @@ declare <vscale x 8 x i64> @llvm.riscv.vmulhsu.mask.nxv8i64.nxv8i64(
<vscale x 8 x i64>,
<vscale x 8 x i64>,
<vscale x 8 x i1>,
- i64,
- i64);
+ iXLen, iXLen);
-define <vscale x 8 x i64> @intrinsic_vmulhsu_mask_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+define <vscale x 8 x i64> @intrinsic_vmulhsu_mask_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmulhsu_mask_vv_nxv8i64_nxv8i64_nxv8i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vl8re64.v v24, (a0)
@@ -1034,7 +1014,7 @@ entry:
<vscale x 8 x i64> %1,
<vscale x 8 x i64> %2,
<vscale x 8 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 8 x i64> %a
}
@@ -1043,9 +1023,9 @@ declare <vscale x 1 x i8> @llvm.riscv.vmulhsu.nxv1i8.i8(
<vscale x 1 x i8>,
<vscale x 1 x i8>,
i8,
- i64);
+ iXLen);
-define <vscale x 1 x i8> @intrinsic_vmulhsu_vx_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, i8 %1, i64 %2) nounwind {
+define <vscale x 1 x i8> @intrinsic_vmulhsu_vx_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, i8 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmulhsu_vx_nxv1i8_nxv1i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
@@ -1056,7 +1036,7 @@ entry:
<vscale x 1 x i8> undef,
<vscale x 1 x i8> %0,
i8 %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 1 x i8> %a
}
@@ -1066,10 +1046,9 @@ declare <vscale x 1 x i8> @llvm.riscv.vmulhsu.mask.nxv1i8.i8(
<vscale x 1 x i8>,
i8,
<vscale x 1 x i1>,
- i64,
- i64);
+ iXLen, iXLen);
-define <vscale x 1 x i8> @intrinsic_vmulhsu_mask_vx_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+define <vscale x 1 x i8> @intrinsic_vmulhsu_mask_vx_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmulhsu_mask_vx_nxv1i8_nxv1i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
@@ -1081,7 +1060,7 @@ entry:
<vscale x 1 x i8> %1,
i8 %2,
<vscale x 1 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 1 x i8> %a
}
@@ -1090,9 +1069,9 @@ declare <vscale x 2 x i8> @llvm.riscv.vmulhsu.nxv2i8.i8(
<vscale x 2 x i8>,
<vscale x 2 x i8>,
i8,
- i64);
+ iXLen);
-define <vscale x 2 x i8> @intrinsic_vmulhsu_vx_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, i8 %1, i64 %2) nounwind {
+define <vscale x 2 x i8> @intrinsic_vmulhsu_vx_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, i8 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmulhsu_vx_nxv2i8_nxv2i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
@@ -1103,7 +1082,7 @@ entry:
<vscale x 2 x i8> undef,
<vscale x 2 x i8> %0,
i8 %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 2 x i8> %a
}
@@ -1113,10 +1092,9 @@ declare <vscale x 2 x i8> @llvm.riscv.vmulhsu.mask.nxv2i8.i8(
<vscale x 2 x i8>,
i8,
<vscale x 2 x i1>,
- i64,
- i64);
+ iXLen, iXLen);
-define <vscale x 2 x i8> @intrinsic_vmulhsu_mask_vx_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+define <vscale x 2 x i8> @intrinsic_vmulhsu_mask_vx_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmulhsu_mask_vx_nxv2i8_nxv2i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
@@ -1128,7 +1106,7 @@ entry:
<vscale x 2 x i8> %1,
i8 %2,
<vscale x 2 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 2 x i8> %a
}
@@ -1137,9 +1115,9 @@ declare <vscale x 4 x i8> @llvm.riscv.vmulhsu.nxv4i8.i8(
<vscale x 4 x i8>,
<vscale x 4 x i8>,
i8,
- i64);
+ iXLen);
-define <vscale x 4 x i8> @intrinsic_vmulhsu_vx_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, i8 %1, i64 %2) nounwind {
+define <vscale x 4 x i8> @intrinsic_vmulhsu_vx_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, i8 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmulhsu_vx_nxv4i8_nxv4i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
@@ -1150,7 +1128,7 @@ entry:
<vscale x 4 x i8> undef,
<vscale x 4 x i8> %0,
i8 %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 4 x i8> %a
}
@@ -1160,10 +1138,9 @@ declare <vscale x 4 x i8> @llvm.riscv.vmulhsu.mask.nxv4i8.i8(
<vscale x 4 x i8>,
i8,
<vscale x 4 x i1>,
- i64,
- i64);
+ iXLen, iXLen);
-define <vscale x 4 x i8> @intrinsic_vmulhsu_mask_vx_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+define <vscale x 4 x i8> @intrinsic_vmulhsu_mask_vx_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmulhsu_mask_vx_nxv4i8_nxv4i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
@@ -1175,7 +1152,7 @@ entry:
<vscale x 4 x i8> %1,
i8 %2,
<vscale x 4 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 4 x i8> %a
}
@@ -1184,9 +1161,9 @@ declare <vscale x 8 x i8> @llvm.riscv.vmulhsu.nxv8i8.i8(
<vscale x 8 x i8>,
<vscale x 8 x i8>,
i8,
- i64);
+ iXLen);
-define <vscale x 8 x i8> @intrinsic_vmulhsu_vx_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, i8 %1, i64 %2) nounwind {
+define <vscale x 8 x i8> @intrinsic_vmulhsu_vx_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, i8 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmulhsu_vx_nxv8i8_nxv8i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
@@ -1197,7 +1174,7 @@ entry:
<vscale x 8 x i8> undef,
<vscale x 8 x i8> %0,
i8 %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 8 x i8> %a
}
@@ -1207,10 +1184,9 @@ declare <vscale x 8 x i8> @llvm.riscv.vmulhsu.mask.nxv8i8.i8(
<vscale x 8 x i8>,
i8,
<vscale x 8 x i1>,
- i64,
- i64);
+ iXLen, iXLen);
-define <vscale x 8 x i8> @intrinsic_vmulhsu_mask_vx_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+define <vscale x 8 x i8> @intrinsic_vmulhsu_mask_vx_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmulhsu_mask_vx_nxv8i8_nxv8i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
@@ -1222,7 +1198,7 @@ entry:
<vscale x 8 x i8> %1,
i8 %2,
<vscale x 8 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 8 x i8> %a
}
@@ -1231,9 +1207,9 @@ declare <vscale x 16 x i8> @llvm.riscv.vmulhsu.nxv16i8.i8(
<vscale x 16 x i8>,
<vscale x 16 x i8>,
i8,
- i64);
+ iXLen);
-define <vscale x 16 x i8> @intrinsic_vmulhsu_vx_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, i8 %1, i64 %2) nounwind {
+define <vscale x 16 x i8> @intrinsic_vmulhsu_vx_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, i8 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmulhsu_vx_nxv16i8_nxv16i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
@@ -1244,7 +1220,7 @@ entry:
<vscale x 16 x i8> undef,
<vscale x 16 x i8> %0,
i8 %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 16 x i8> %a
}
@@ -1254,10 +1230,9 @@ declare <vscale x 16 x i8> @llvm.riscv.vmulhsu.mask.nxv16i8.i8(
<vscale x 16 x i8>,
i8,
<vscale x 16 x i1>,
- i64,
- i64);
+ iXLen, iXLen);
-define <vscale x 16 x i8> @intrinsic_vmulhsu_mask_vx_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+define <vscale x 16 x i8> @intrinsic_vmulhsu_mask_vx_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmulhsu_mask_vx_nxv16i8_nxv16i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
@@ -1269,7 +1244,7 @@ entry:
<vscale x 16 x i8> %1,
i8 %2,
<vscale x 16 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 16 x i8> %a
}
@@ -1278,9 +1253,9 @@ declare <vscale x 32 x i8> @llvm.riscv.vmulhsu.nxv32i8.i8(
<vscale x 32 x i8>,
<vscale x 32 x i8>,
i8,
- i64);
+ iXLen);
-define <vscale x 32 x i8> @intrinsic_vmulhsu_vx_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, i8 %1, i64 %2) nounwind {
+define <vscale x 32 x i8> @intrinsic_vmulhsu_vx_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, i8 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmulhsu_vx_nxv32i8_nxv32i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
@@ -1291,7 +1266,7 @@ entry:
<vscale x 32 x i8> undef,
<vscale x 32 x i8> %0,
i8 %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 32 x i8> %a
}
@@ -1301,10 +1276,9 @@ declare <vscale x 32 x i8> @llvm.riscv.vmulhsu.mask.nxv32i8.i8(
<vscale x 32 x i8>,
i8,
<vscale x 32 x i1>,
- i64,
- i64);
+ iXLen, iXLen);
-define <vscale x 32 x i8> @intrinsic_vmulhsu_mask_vx_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
+define <vscale x 32 x i8> @intrinsic_vmulhsu_mask_vx_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmulhsu_mask_vx_nxv32i8_nxv32i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
@@ -1316,7 +1290,7 @@ entry:
<vscale x 32 x i8> %1,
i8 %2,
<vscale x 32 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 32 x i8> %a
}
@@ -1325,9 +1299,9 @@ declare <vscale x 64 x i8> @llvm.riscv.vmulhsu.nxv64i8.i8(
<vscale x 64 x i8>,
<vscale x 64 x i8>,
i8,
- i64);
+ iXLen);
-define <vscale x 64 x i8> @intrinsic_vmulhsu_vx_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, i8 %1, i64 %2) nounwind {
+define <vscale x 64 x i8> @intrinsic_vmulhsu_vx_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, i8 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmulhsu_vx_nxv64i8_nxv64i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu
@@ -1338,7 +1312,7 @@ entry:
<vscale x 64 x i8> undef,
<vscale x 64 x i8> %0,
i8 %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 64 x i8> %a
}
@@ -1348,10 +1322,9 @@ declare <vscale x 64 x i8> @llvm.riscv.vmulhsu.mask.nxv64i8.i8(
<vscale x 64 x i8>,
i8,
<vscale x 64 x i1>,
- i64,
- i64);
+ iXLen, iXLen);
-define <vscale x 64 x i8> @intrinsic_vmulhsu_mask_vx_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i8 %2, <vscale x 64 x i1> %3, i64 %4) nounwind {
+define <vscale x 64 x i8> @intrinsic_vmulhsu_mask_vx_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i8 %2, <vscale x 64 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmulhsu_mask_vx_nxv64i8_nxv64i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu
@@ -1363,7 +1336,7 @@ entry:
<vscale x 64 x i8> %1,
i8 %2,
<vscale x 64 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 64 x i8> %a
}
@@ -1372,9 +1345,9 @@ declare <vscale x 1 x i16> @llvm.riscv.vmulhsu.nxv1i16.i16(
<vscale x 1 x i16>,
<vscale x 1 x i16>,
i16,
- i64);
+ iXLen);
-define <vscale x 1 x i16> @intrinsic_vmulhsu_vx_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, i16 %1, i64 %2) nounwind {
+define <vscale x 1 x i16> @intrinsic_vmulhsu_vx_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, i16 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmulhsu_vx_nxv1i16_nxv1i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
@@ -1385,7 +1358,7 @@ entry:
<vscale x 1 x i16> undef,
<vscale x 1 x i16> %0,
i16 %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 1 x i16> %a
}
@@ -1395,10 +1368,9 @@ declare <vscale x 1 x i16> @llvm.riscv.vmulhsu.mask.nxv1i16.i16(
<vscale x 1 x i16>,
i16,
<vscale x 1 x i1>,
- i64,
- i64);
+ iXLen, iXLen);
-define <vscale x 1 x i16> @intrinsic_vmulhsu_mask_vx_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+define <vscale x 1 x i16> @intrinsic_vmulhsu_mask_vx_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmulhsu_mask_vx_nxv1i16_nxv1i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
@@ -1410,7 +1382,7 @@ entry:
<vscale x 1 x i16> %1,
i16 %2,
<vscale x 1 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 1 x i16> %a
}
@@ -1419,9 +1391,9 @@ declare <vscale x 2 x i16> @llvm.riscv.vmulhsu.nxv2i16.i16(
<vscale x 2 x i16>,
<vscale x 2 x i16>,
i16,
- i64);
+ iXLen);
-define <vscale x 2 x i16> @intrinsic_vmulhsu_vx_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, i16 %1, i64 %2) nounwind {
+define <vscale x 2 x i16> @intrinsic_vmulhsu_vx_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, i16 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmulhsu_vx_nxv2i16_nxv2i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
@@ -1432,7 +1404,7 @@ entry:
<vscale x 2 x i16> undef,
<vscale x 2 x i16> %0,
i16 %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 2 x i16> %a
}
@@ -1442,10 +1414,9 @@ declare <vscale x 2 x i16> @llvm.riscv.vmulhsu.mask.nxv2i16.i16(
<vscale x 2 x i16>,
i16,
<vscale x 2 x i1>,
- i64,
- i64);
+ iXLen, iXLen);
-define <vscale x 2 x i16> @intrinsic_vmulhsu_mask_vx_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+define <vscale x 2 x i16> @intrinsic_vmulhsu_mask_vx_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmulhsu_mask_vx_nxv2i16_nxv2i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
@@ -1457,7 +1428,7 @@ entry:
<vscale x 2 x i16> %1,
i16 %2,
<vscale x 2 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 2 x i16> %a
}
@@ -1466,9 +1437,9 @@ declare <vscale x 4 x i16> @llvm.riscv.vmulhsu.nxv4i16.i16(
<vscale x 4 x i16>,
<vscale x 4 x i16>,
i16,
- i64);
+ iXLen);
-define <vscale x 4 x i16> @intrinsic_vmulhsu_vx_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, i16 %1, i64 %2) nounwind {
+define <vscale x 4 x i16> @intrinsic_vmulhsu_vx_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, i16 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmulhsu_vx_nxv4i16_nxv4i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
@@ -1479,7 +1450,7 @@ entry:
<vscale x 4 x i16> undef,
<vscale x 4 x i16> %0,
i16 %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 4 x i16> %a
}
@@ -1489,10 +1460,9 @@ declare <vscale x 4 x i16> @llvm.riscv.vmulhsu.mask.nxv4i16.i16(
<vscale x 4 x i16>,
i16,
<vscale x 4 x i1>,
- i64,
- i64);
+ iXLen, iXLen);
-define <vscale x 4 x i16> @intrinsic_vmulhsu_mask_vx_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+define <vscale x 4 x i16> @intrinsic_vmulhsu_mask_vx_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmulhsu_mask_vx_nxv4i16_nxv4i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
@@ -1504,7 +1474,7 @@ entry:
<vscale x 4 x i16> %1,
i16 %2,
<vscale x 4 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 4 x i16> %a
}
@@ -1513,9 +1483,9 @@ declare <vscale x 8 x i16> @llvm.riscv.vmulhsu.nxv8i16.i16(
<vscale x 8 x i16>,
<vscale x 8 x i16>,
i16,
- i64);
+ iXLen);
-define <vscale x 8 x i16> @intrinsic_vmulhsu_vx_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, i16 %1, i64 %2) nounwind {
+define <vscale x 8 x i16> @intrinsic_vmulhsu_vx_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, i16 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmulhsu_vx_nxv8i16_nxv8i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
@@ -1526,7 +1496,7 @@ entry:
<vscale x 8 x i16> undef,
<vscale x 8 x i16> %0,
i16 %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 8 x i16> %a
}
@@ -1536,10 +1506,9 @@ declare <vscale x 8 x i16> @llvm.riscv.vmulhsu.mask.nxv8i16.i16(
<vscale x 8 x i16>,
i16,
<vscale x 8 x i1>,
- i64,
- i64);
+ iXLen, iXLen);
-define <vscale x 8 x i16> @intrinsic_vmulhsu_mask_vx_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+define <vscale x 8 x i16> @intrinsic_vmulhsu_mask_vx_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmulhsu_mask_vx_nxv8i16_nxv8i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
@@ -1551,7 +1520,7 @@ entry:
<vscale x 8 x i16> %1,
i16 %2,
<vscale x 8 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 8 x i16> %a
}
@@ -1560,9 +1529,9 @@ declare <vscale x 16 x i16> @llvm.riscv.vmulhsu.nxv16i16.i16(
<vscale x 16 x i16>,
<vscale x 16 x i16>,
i16,
- i64);
+ iXLen);
-define <vscale x 16 x i16> @intrinsic_vmulhsu_vx_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, i16 %1, i64 %2) nounwind {
+define <vscale x 16 x i16> @intrinsic_vmulhsu_vx_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, i16 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmulhsu_vx_nxv16i16_nxv16i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
@@ -1573,7 +1542,7 @@ entry:
<vscale x 16 x i16> undef,
<vscale x 16 x i16> %0,
i16 %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 16 x i16> %a
}
@@ -1583,10 +1552,9 @@ declare <vscale x 16 x i16> @llvm.riscv.vmulhsu.mask.nxv16i16.i16(
<vscale x 16 x i16>,
i16,
<vscale x 16 x i1>,
- i64,
- i64);
+ iXLen, iXLen);
-define <vscale x 16 x i16> @intrinsic_vmulhsu_mask_vx_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+define <vscale x 16 x i16> @intrinsic_vmulhsu_mask_vx_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmulhsu_mask_vx_nxv16i16_nxv16i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
@@ -1598,7 +1566,7 @@ entry:
<vscale x 16 x i16> %1,
i16 %2,
<vscale x 16 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 16 x i16> %a
}
@@ -1607,9 +1575,9 @@ declare <vscale x 32 x i16> @llvm.riscv.vmulhsu.nxv32i16.i16(
<vscale x 32 x i16>,
<vscale x 32 x i16>,
i16,
- i64);
+ iXLen);
-define <vscale x 32 x i16> @intrinsic_vmulhsu_vx_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, i16 %1, i64 %2) nounwind {
+define <vscale x 32 x i16> @intrinsic_vmulhsu_vx_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, i16 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmulhsu_vx_nxv32i16_nxv32i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu
@@ -1620,7 +1588,7 @@ entry:
<vscale x 32 x i16> undef,
<vscale x 32 x i16> %0,
i16 %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 32 x i16> %a
}
@@ -1630,10 +1598,9 @@ declare <vscale x 32 x i16> @llvm.riscv.vmulhsu.mask.nxv32i16.i16(
<vscale x 32 x i16>,
i16,
<vscale x 32 x i1>,
- i64,
- i64);
+ iXLen, iXLen);
-define <vscale x 32 x i16> @intrinsic_vmulhsu_mask_vx_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, i16 %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
+define <vscale x 32 x i16> @intrinsic_vmulhsu_mask_vx_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, i16 %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmulhsu_mask_vx_nxv32i16_nxv32i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu
@@ -1645,7 +1612,7 @@ entry:
<vscale x 32 x i16> %1,
i16 %2,
<vscale x 32 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 32 x i16> %a
}
@@ -1654,9 +1621,9 @@ declare <vscale x 1 x i32> @llvm.riscv.vmulhsu.nxv1i32.i32(
<vscale x 1 x i32>,
<vscale x 1 x i32>,
i32,
- i64);
+ iXLen);
-define <vscale x 1 x i32> @intrinsic_vmulhsu_vx_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, i32 %1, i64 %2) nounwind {
+define <vscale x 1 x i32> @intrinsic_vmulhsu_vx_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, i32 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmulhsu_vx_nxv1i32_nxv1i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
@@ -1667,7 +1634,7 @@ entry:
<vscale x 1 x i32> undef,
<vscale x 1 x i32> %0,
i32 %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 1 x i32> %a
}
@@ -1677,10 +1644,9 @@ declare <vscale x 1 x i32> @llvm.riscv.vmulhsu.mask.nxv1i32.i32(
<vscale x 1 x i32>,
i32,
<vscale x 1 x i1>,
- i64,
- i64);
+ iXLen, iXLen);
-define <vscale x 1 x i32> @intrinsic_vmulhsu_mask_vx_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+define <vscale x 1 x i32> @intrinsic_vmulhsu_mask_vx_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmulhsu_mask_vx_nxv1i32_nxv1i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
@@ -1692,7 +1658,7 @@ entry:
<vscale x 1 x i32> %1,
i32 %2,
<vscale x 1 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 1 x i32> %a
}
@@ -1701,9 +1667,9 @@ declare <vscale x 2 x i32> @llvm.riscv.vmulhsu.nxv2i32.i32(
<vscale x 2 x i32>,
<vscale x 2 x i32>,
i32,
- i64);
+ iXLen);
-define <vscale x 2 x i32> @intrinsic_vmulhsu_vx_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, i32 %1, i64 %2) nounwind {
+define <vscale x 2 x i32> @intrinsic_vmulhsu_vx_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, i32 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmulhsu_vx_nxv2i32_nxv2i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
@@ -1714,7 +1680,7 @@ entry:
<vscale x 2 x i32> undef,
<vscale x 2 x i32> %0,
i32 %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 2 x i32> %a
}
@@ -1724,10 +1690,9 @@ declare <vscale x 2 x i32> @llvm.riscv.vmulhsu.mask.nxv2i32.i32(
<vscale x 2 x i32>,
i32,
<vscale x 2 x i1>,
- i64,
- i64);
+ iXLen, iXLen);
-define <vscale x 2 x i32> @intrinsic_vmulhsu_mask_vx_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+define <vscale x 2 x i32> @intrinsic_vmulhsu_mask_vx_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmulhsu_mask_vx_nxv2i32_nxv2i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
@@ -1739,7 +1704,7 @@ entry:
<vscale x 2 x i32> %1,
i32 %2,
<vscale x 2 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 2 x i32> %a
}
@@ -1748,9 +1713,9 @@ declare <vscale x 4 x i32> @llvm.riscv.vmulhsu.nxv4i32.i32(
<vscale x 4 x i32>,
<vscale x 4 x i32>,
i32,
- i64);
+ iXLen);
-define <vscale x 4 x i32> @intrinsic_vmulhsu_vx_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, i32 %1, i64 %2) nounwind {
+define <vscale x 4 x i32> @intrinsic_vmulhsu_vx_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, i32 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmulhsu_vx_nxv4i32_nxv4i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
@@ -1761,7 +1726,7 @@ entry:
<vscale x 4 x i32> undef,
<vscale x 4 x i32> %0,
i32 %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 4 x i32> %a
}
@@ -1771,10 +1736,9 @@ declare <vscale x 4 x i32> @llvm.riscv.vmulhsu.mask.nxv4i32.i32(
<vscale x 4 x i32>,
i32,
<vscale x 4 x i1>,
- i64,
- i64);
+ iXLen, iXLen);
-define <vscale x 4 x i32> @intrinsic_vmulhsu_mask_vx_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+define <vscale x 4 x i32> @intrinsic_vmulhsu_mask_vx_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmulhsu_mask_vx_nxv4i32_nxv4i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
@@ -1786,7 +1750,7 @@ entry:
<vscale x 4 x i32> %1,
i32 %2,
<vscale x 4 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 4 x i32> %a
}
@@ -1795,9 +1759,9 @@ declare <vscale x 8 x i32> @llvm.riscv.vmulhsu.nxv8i32.i32(
<vscale x 8 x i32>,
<vscale x 8 x i32>,
i32,
- i64);
+ iXLen);
-define <vscale x 8 x i32> @intrinsic_vmulhsu_vx_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, i32 %1, i64 %2) nounwind {
+define <vscale x 8 x i32> @intrinsic_vmulhsu_vx_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, i32 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmulhsu_vx_nxv8i32_nxv8i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
@@ -1808,7 +1772,7 @@ entry:
<vscale x 8 x i32> undef,
<vscale x 8 x i32> %0,
i32 %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 8 x i32> %a
}
@@ -1818,10 +1782,9 @@ declare <vscale x 8 x i32> @llvm.riscv.vmulhsu.mask.nxv8i32.i32(
<vscale x 8 x i32>,
i32,
<vscale x 8 x i1>,
- i64,
- i64);
+ iXLen, iXLen);
-define <vscale x 8 x i32> @intrinsic_vmulhsu_mask_vx_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+define <vscale x 8 x i32> @intrinsic_vmulhsu_mask_vx_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmulhsu_mask_vx_nxv8i32_nxv8i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
@@ -1833,7 +1796,7 @@ entry:
<vscale x 8 x i32> %1,
i32 %2,
<vscale x 8 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 8 x i32> %a
}
@@ -1842,9 +1805,9 @@ declare <vscale x 16 x i32> @llvm.riscv.vmulhsu.nxv16i32.i32(
<vscale x 16 x i32>,
<vscale x 16 x i32>,
i32,
- i64);
+ iXLen);
-define <vscale x 16 x i32> @intrinsic_vmulhsu_vx_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, i32 %1, i64 %2) nounwind {
+define <vscale x 16 x i32> @intrinsic_vmulhsu_vx_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, i32 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmulhsu_vx_nxv16i32_nxv16i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu
@@ -1855,7 +1818,7 @@ entry:
<vscale x 16 x i32> undef,
<vscale x 16 x i32> %0,
i32 %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 16 x i32> %a
}
@@ -1865,10 +1828,9 @@ declare <vscale x 16 x i32> @llvm.riscv.vmulhsu.mask.nxv16i32.i32(
<vscale x 16 x i32>,
i32,
<vscale x 16 x i1>,
- i64,
- i64);
+ iXLen, iXLen);
-define <vscale x 16 x i32> @intrinsic_vmulhsu_mask_vx_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+define <vscale x 16 x i32> @intrinsic_vmulhsu_mask_vx_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmulhsu_mask_vx_nxv16i32_nxv16i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu
@@ -1880,7 +1842,7 @@ entry:
<vscale x 16 x i32> %1,
i32 %2,
<vscale x 16 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 16 x i32> %a
}
@@ -1889,20 +1851,32 @@ declare <vscale x 1 x i64> @llvm.riscv.vmulhsu.nxv1i64.i64(
<vscale x 1 x i64>,
<vscale x 1 x i64>,
i64,
- i64);
-
-define <vscale x 1 x i64> @intrinsic_vmulhsu_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmulhsu_vx_nxv1i64_nxv1i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
-; CHECK-NEXT: vmulhsu.vx v8, v8, a0
-; CHECK-NEXT: ret
+ iXLen);
+
+define <vscale x 1 x i64> @intrinsic_vmulhsu_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, iXLen %2) nounwind {
+; RV32-LABEL: intrinsic_vmulhsu_vx_nxv1i64_nxv1i64_i64:
+; RV32: # %bb.0: # %entry
+; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: sw a1, 12(sp)
+; RV32-NEXT: sw a0, 8(sp)
+; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
+; RV32-NEXT: addi a0, sp, 8
+; RV32-NEXT: vlse64.v v9, (a0), zero
+; RV32-NEXT: vmulhsu.vv v8, v8, v9
+; RV32-NEXT: addi sp, sp, 16
+; RV32-NEXT: ret
+;
+; RV64-LABEL: intrinsic_vmulhsu_vx_nxv1i64_nxv1i64_i64:
+; RV64: # %bb.0: # %entry
+; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, mu
+; RV64-NEXT: vmulhsu.vx v8, v8, a0
+; RV64-NEXT: ret
entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vmulhsu.nxv1i64.i64(
<vscale x 1 x i64> undef,
<vscale x 1 x i64> %0,
i64 %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 1 x i64> %a
}
@@ -1912,22 +1886,33 @@ declare <vscale x 1 x i64> @llvm.riscv.vmulhsu.mask.nxv1i64.i64(
<vscale x 1 x i64>,
i64,
<vscale x 1 x i1>,
- i64,
- i64);
-
-define <vscale x 1 x i64> @intrinsic_vmulhsu_mask_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmulhsu_mask_vx_nxv1i64_nxv1i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
-; CHECK-NEXT: vmulhsu.vx v8, v9, a0, v0.t
-; CHECK-NEXT: ret
+ iXLen, iXLen);
+
+define <vscale x 1 x i64> @intrinsic_vmulhsu_mask_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
+; RV32-LABEL: intrinsic_vmulhsu_mask_vx_nxv1i64_nxv1i64_i64:
+; RV32: # %bb.0: # %entry
+; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: sw a1, 12(sp)
+; RV32-NEXT: sw a0, 8(sp)
+; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
+; RV32-NEXT: addi a0, sp, 8
+; RV32-NEXT: vlse64.v v10, (a0), zero
+; RV32-NEXT: vmulhsu.vv v8, v9, v10, v0.t
+; RV32-NEXT: addi sp, sp, 16
+; RV32-NEXT: ret
+;
+; RV64-LABEL: intrinsic_vmulhsu_mask_vx_nxv1i64_nxv1i64_i64:
+; RV64: # %bb.0: # %entry
+; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, mu
+; RV64-NEXT: vmulhsu.vx v8, v9, a0, v0.t
+; RV64-NEXT: ret
entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vmulhsu.mask.nxv1i64.i64(
<vscale x 1 x i64> %0,
<vscale x 1 x i64> %1,
i64 %2,
<vscale x 1 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 1 x i64> %a
}
@@ -1936,20 +1921,32 @@ declare <vscale x 2 x i64> @llvm.riscv.vmulhsu.nxv2i64.i64(
<vscale x 2 x i64>,
<vscale x 2 x i64>,
i64,
- i64);
-
-define <vscale x 2 x i64> @intrinsic_vmulhsu_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmulhsu_vx_nxv2i64_nxv2i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
-; CHECK-NEXT: vmulhsu.vx v8, v8, a0
-; CHECK-NEXT: ret
+ iXLen);
+
+define <vscale x 2 x i64> @intrinsic_vmulhsu_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, iXLen %2) nounwind {
+; RV32-LABEL: intrinsic_vmulhsu_vx_nxv2i64_nxv2i64_i64:
+; RV32: # %bb.0: # %entry
+; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: sw a1, 12(sp)
+; RV32-NEXT: sw a0, 8(sp)
+; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
+; RV32-NEXT: addi a0, sp, 8
+; RV32-NEXT: vlse64.v v10, (a0), zero
+; RV32-NEXT: vmulhsu.vv v8, v8, v10
+; RV32-NEXT: addi sp, sp, 16
+; RV32-NEXT: ret
+;
+; RV64-LABEL: intrinsic_vmulhsu_vx_nxv2i64_nxv2i64_i64:
+; RV64: # %bb.0: # %entry
+; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, mu
+; RV64-NEXT: vmulhsu.vx v8, v8, a0
+; RV64-NEXT: ret
entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vmulhsu.nxv2i64.i64(
<vscale x 2 x i64> undef,
<vscale x 2 x i64> %0,
i64 %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 2 x i64> %a
}
@@ -1959,22 +1956,33 @@ declare <vscale x 2 x i64> @llvm.riscv.vmulhsu.mask.nxv2i64.i64(
<vscale x 2 x i64>,
i64,
<vscale x 2 x i1>,
- i64,
- i64);
-
-define <vscale x 2 x i64> @intrinsic_vmulhsu_mask_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmulhsu_mask_vx_nxv2i64_nxv2i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
-; CHECK-NEXT: vmulhsu.vx v8, v10, a0, v0.t
-; CHECK-NEXT: ret
+ iXLen, iXLen);
+
+define <vscale x 2 x i64> @intrinsic_vmulhsu_mask_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
+; RV32-LABEL: intrinsic_vmulhsu_mask_vx_nxv2i64_nxv2i64_i64:
+; RV32: # %bb.0: # %entry
+; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: sw a1, 12(sp)
+; RV32-NEXT: sw a0, 8(sp)
+; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
+; RV32-NEXT: addi a0, sp, 8
+; RV32-NEXT: vlse64.v v12, (a0), zero
+; RV32-NEXT: vmulhsu.vv v8, v10, v12, v0.t
+; RV32-NEXT: addi sp, sp, 16
+; RV32-NEXT: ret
+;
+; RV64-LABEL: intrinsic_vmulhsu_mask_vx_nxv2i64_nxv2i64_i64:
+; RV64: # %bb.0: # %entry
+; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, mu
+; RV64-NEXT: vmulhsu.vx v8, v10, a0, v0.t
+; RV64-NEXT: ret
entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vmulhsu.mask.nxv2i64.i64(
<vscale x 2 x i64> %0,
<vscale x 2 x i64> %1,
i64 %2,
<vscale x 2 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 2 x i64> %a
}
@@ -1983,20 +1991,32 @@ declare <vscale x 4 x i64> @llvm.riscv.vmulhsu.nxv4i64.i64(
<vscale x 4 x i64>,
<vscale x 4 x i64>,
i64,
- i64);
-
-define <vscale x 4 x i64> @intrinsic_vmulhsu_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmulhsu_vx_nxv4i64_nxv4i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
-; CHECK-NEXT: vmulhsu.vx v8, v8, a0
-; CHECK-NEXT: ret
+ iXLen);
+
+define <vscale x 4 x i64> @intrinsic_vmulhsu_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, iXLen %2) nounwind {
+; RV32-LABEL: intrinsic_vmulhsu_vx_nxv4i64_nxv4i64_i64:
+; RV32: # %bb.0: # %entry
+; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: sw a1, 12(sp)
+; RV32-NEXT: sw a0, 8(sp)
+; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
+; RV32-NEXT: addi a0, sp, 8
+; RV32-NEXT: vlse64.v v12, (a0), zero
+; RV32-NEXT: vmulhsu.vv v8, v8, v12
+; RV32-NEXT: addi sp, sp, 16
+; RV32-NEXT: ret
+;
+; RV64-LABEL: intrinsic_vmulhsu_vx_nxv4i64_nxv4i64_i64:
+; RV64: # %bb.0: # %entry
+; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu
+; RV64-NEXT: vmulhsu.vx v8, v8, a0
+; RV64-NEXT: ret
entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vmulhsu.nxv4i64.i64(
<vscale x 4 x i64> undef,
<vscale x 4 x i64> %0,
i64 %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 4 x i64> %a
}
@@ -2006,22 +2026,33 @@ declare <vscale x 4 x i64> @llvm.riscv.vmulhsu.mask.nxv4i64.i64(
<vscale x 4 x i64>,
i64,
<vscale x 4 x i1>,
- i64,
- i64);
-
-define <vscale x 4 x i64> @intrinsic_vmulhsu_mask_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmulhsu_mask_vx_nxv4i64_nxv4i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
-; CHECK-NEXT: vmulhsu.vx v8, v12, a0, v0.t
-; CHECK-NEXT: ret
+ iXLen, iXLen);
+
+define <vscale x 4 x i64> @intrinsic_vmulhsu_mask_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
+; RV32-LABEL: intrinsic_vmulhsu_mask_vx_nxv4i64_nxv4i64_i64:
+; RV32: # %bb.0: # %entry
+; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: sw a1, 12(sp)
+; RV32-NEXT: sw a0, 8(sp)
+; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
+; RV32-NEXT: addi a0, sp, 8
+; RV32-NEXT: vlse64.v v16, (a0), zero
+; RV32-NEXT: vmulhsu.vv v8, v12, v16, v0.t
+; RV32-NEXT: addi sp, sp, 16
+; RV32-NEXT: ret
+;
+; RV64-LABEL: intrinsic_vmulhsu_mask_vx_nxv4i64_nxv4i64_i64:
+; RV64: # %bb.0: # %entry
+; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu
+; RV64-NEXT: vmulhsu.vx v8, v12, a0, v0.t
+; RV64-NEXT: ret
entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vmulhsu.mask.nxv4i64.i64(
<vscale x 4 x i64> %0,
<vscale x 4 x i64> %1,
i64 %2,
<vscale x 4 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 4 x i64> %a
}
@@ -2030,20 +2061,32 @@ declare <vscale x 8 x i64> @llvm.riscv.vmulhsu.nxv8i64.i64(
<vscale x 8 x i64>,
<vscale x 8 x i64>,
i64,
- i64);
-
-define <vscale x 8 x i64> @intrinsic_vmulhsu_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, i64 %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmulhsu_vx_nxv8i64_nxv8i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu
-; CHECK-NEXT: vmulhsu.vx v8, v8, a0
-; CHECK-NEXT: ret
+ iXLen);
+
+define <vscale x 8 x i64> @intrinsic_vmulhsu_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, i64 %1, iXLen %2) nounwind {
+; RV32-LABEL: intrinsic_vmulhsu_vx_nxv8i64_nxv8i64_i64:
+; RV32: # %bb.0: # %entry
+; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: sw a1, 12(sp)
+; RV32-NEXT: sw a0, 8(sp)
+; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu
+; RV32-NEXT: addi a0, sp, 8
+; RV32-NEXT: vlse64.v v16, (a0), zero
+; RV32-NEXT: vmulhsu.vv v8, v8, v16
+; RV32-NEXT: addi sp, sp, 16
+; RV32-NEXT: ret
+;
+; RV64-LABEL: intrinsic_vmulhsu_vx_nxv8i64_nxv8i64_i64:
+; RV64: # %bb.0: # %entry
+; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, mu
+; RV64-NEXT: vmulhsu.vx v8, v8, a0
+; RV64-NEXT: ret
entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vmulhsu.nxv8i64.i64(
<vscale x 8 x i64> undef,
<vscale x 8 x i64> %0,
i64 %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 8 x i64> %a
}
@@ -2053,22 +2096,33 @@ declare <vscale x 8 x i64> @llvm.riscv.vmulhsu.mask.nxv8i64.i64(
<vscale x 8 x i64>,
i64,
<vscale x 8 x i1>,
- i64,
- i64);
-
-define <vscale x 8 x i64> @intrinsic_vmulhsu_mask_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmulhsu_mask_vx_nxv8i64_nxv8i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu
-; CHECK-NEXT: vmulhsu.vx v8, v16, a0, v0.t
-; CHECK-NEXT: ret
+ iXLen, iXLen);
+
+define <vscale x 8 x i64> @intrinsic_vmulhsu_mask_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
+; RV32-LABEL: intrinsic_vmulhsu_mask_vx_nxv8i64_nxv8i64_i64:
+; RV32: # %bb.0: # %entry
+; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: sw a1, 12(sp)
+; RV32-NEXT: sw a0, 8(sp)
+; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu
+; RV32-NEXT: addi a0, sp, 8
+; RV32-NEXT: vlse64.v v24, (a0), zero
+; RV32-NEXT: vmulhsu.vv v8, v16, v24, v0.t
+; RV32-NEXT: addi sp, sp, 16
+; RV32-NEXT: ret
+;
+; RV64-LABEL: intrinsic_vmulhsu_mask_vx_nxv8i64_nxv8i64_i64:
+; RV64: # %bb.0: # %entry
+; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, mu
+; RV64-NEXT: vmulhsu.vx v8, v16, a0, v0.t
+; RV64-NEXT: ret
entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vmulhsu.mask.nxv8i64.i64(
<vscale x 8 x i64> %0,
<vscale x 8 x i64> %1,
i64 %2,
<vscale x 8 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 8 x i64> %a
}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmulhu-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmulhu-rv32.ll
deleted file mode 100644
index a20149f9b23d4..0000000000000
--- a/llvm/test/CodeGen/RISCV/rvv/vmulhu-rv32.ll
+++ /dev/null
@@ -1,2122 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs \
-; RUN: < %s | FileCheck %s
-declare <vscale x 1 x i8> @llvm.riscv.vmulhu.nxv1i8.nxv1i8(
- <vscale x 1 x i8>,
- <vscale x 1 x i8>,
- <vscale x 1 x i8>,
- i32);
-
-define <vscale x 1 x i8> @intrinsic_vmulhu_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmulhu_vv_nxv1i8_nxv1i8_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
-; CHECK-NEXT: vmulhu.vv v8, v8, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i8> @llvm.riscv.vmulhu.nxv1i8.nxv1i8(
- <vscale x 1 x i8> undef,
- <vscale x 1 x i8> %0,
- <vscale x 1 x i8> %1,
- i32 %2)
-
- ret <vscale x 1 x i8> %a
-}
-
-declare <vscale x 1 x i8> @llvm.riscv.vmulhu.mask.nxv1i8.nxv1i8(
- <vscale x 1 x i8>,
- <vscale x 1 x i8>,
- <vscale x 1 x i8>,
- <vscale x 1 x i1>,
- i32,
- i32);
-
-define <vscale x 1 x i8> @intrinsic_vmulhu_mask_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmulhu_mask_vv_nxv1i8_nxv1i8_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
-; CHECK-NEXT: vmulhu.vv v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i8> @llvm.riscv.vmulhu.mask.nxv1i8.nxv1i8(
- <vscale x 1 x i8> %0,
- <vscale x 1 x i8> %1,
- <vscale x 1 x i8> %2,
- <vscale x 1 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 1 x i8> %a
-}
-
-declare <vscale x 2 x i8> @llvm.riscv.vmulhu.nxv2i8.nxv2i8(
- <vscale x 2 x i8>,
- <vscale x 2 x i8>,
- <vscale x 2 x i8>,
- i32);
-
-define <vscale x 2 x i8> @intrinsic_vmulhu_vv_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmulhu_vv_nxv2i8_nxv2i8_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
-; CHECK-NEXT: vmulhu.vv v8, v8, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i8> @llvm.riscv.vmulhu.nxv2i8.nxv2i8(
- <vscale x 2 x i8> undef,
- <vscale x 2 x i8> %0,
- <vscale x 2 x i8> %1,
- i32 %2)
-
- ret <vscale x 2 x i8> %a
-}
-
-declare <vscale x 2 x i8> @llvm.riscv.vmulhu.mask.nxv2i8.nxv2i8(
- <vscale x 2 x i8>,
- <vscale x 2 x i8>,
- <vscale x 2 x i8>,
- <vscale x 2 x i1>,
- i32,
- i32);
-
-define <vscale x 2 x i8> @intrinsic_vmulhu_mask_vv_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmulhu_mask_vv_nxv2i8_nxv2i8_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
-; CHECK-NEXT: vmulhu.vv v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i8> @llvm.riscv.vmulhu.mask.nxv2i8.nxv2i8(
- <vscale x 2 x i8> %0,
- <vscale x 2 x i8> %1,
- <vscale x 2 x i8> %2,
- <vscale x 2 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 2 x i8> %a
-}
-
-declare <vscale x 4 x i8> @llvm.riscv.vmulhu.nxv4i8.nxv4i8(
- <vscale x 4 x i8>,
- <vscale x 4 x i8>,
- <vscale x 4 x i8>,
- i32);
-
-define <vscale x 4 x i8> @intrinsic_vmulhu_vv_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmulhu_vv_nxv4i8_nxv4i8_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
-; CHECK-NEXT: vmulhu.vv v8, v8, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i8> @llvm.riscv.vmulhu.nxv4i8.nxv4i8(
- <vscale x 4 x i8> undef,
- <vscale x 4 x i8> %0,
- <vscale x 4 x i8> %1,
- i32 %2)
-
- ret <vscale x 4 x i8> %a
-}
-
-declare <vscale x 4 x i8> @llvm.riscv.vmulhu.mask.nxv4i8.nxv4i8(
- <vscale x 4 x i8>,
- <vscale x 4 x i8>,
- <vscale x 4 x i8>,
- <vscale x 4 x i1>,
- i32,
- i32);
-
-define <vscale x 4 x i8> @intrinsic_vmulhu_mask_vv_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmulhu_mask_vv_nxv4i8_nxv4i8_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
-; CHECK-NEXT: vmulhu.vv v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i8> @llvm.riscv.vmulhu.mask.nxv4i8.nxv4i8(
- <vscale x 4 x i8> %0,
- <vscale x 4 x i8> %1,
- <vscale x 4 x i8> %2,
- <vscale x 4 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 4 x i8> %a
-}
-
-declare <vscale x 8 x i8> @llvm.riscv.vmulhu.nxv8i8.nxv8i8(
- <vscale x 8 x i8>,
- <vscale x 8 x i8>,
- <vscale x 8 x i8>,
- i32);
-
-define <vscale x 8 x i8> @intrinsic_vmulhu_vv_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmulhu_vv_nxv8i8_nxv8i8_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
-; CHECK-NEXT: vmulhu.vv v8, v8, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i8> @llvm.riscv.vmulhu.nxv8i8.nxv8i8(
- <vscale x 8 x i8> undef,
- <vscale x 8 x i8> %0,
- <vscale x 8 x i8> %1,
- i32 %2)
-
- ret <vscale x 8 x i8> %a
-}
-
-declare <vscale x 8 x i8> @llvm.riscv.vmulhu.mask.nxv8i8.nxv8i8(
- <vscale x 8 x i8>,
- <vscale x 8 x i8>,
- <vscale x 8 x i8>,
- <vscale x 8 x i1>,
- i32,
- i32);
-
-define <vscale x 8 x i8> @intrinsic_vmulhu_mask_vv_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmulhu_mask_vv_nxv8i8_nxv8i8_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
-; CHECK-NEXT: vmulhu.vv v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i8> @llvm.riscv.vmulhu.mask.nxv8i8.nxv8i8(
- <vscale x 8 x i8> %0,
- <vscale x 8 x i8> %1,
- <vscale x 8 x i8> %2,
- <vscale x 8 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 8 x i8> %a
-}
-
-declare <vscale x 16 x i8> @llvm.riscv.vmulhu.nxv16i8.nxv16i8(
- <vscale x 16 x i8>,
- <vscale x 16 x i8>,
- <vscale x 16 x i8>,
- i32);
-
-define <vscale x 16 x i8> @intrinsic_vmulhu_vv_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmulhu_vv_nxv16i8_nxv16i8_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
-; CHECK-NEXT: vmulhu.vv v8, v8, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i8> @llvm.riscv.vmulhu.nxv16i8.nxv16i8(
- <vscale x 16 x i8> undef,
- <vscale x 16 x i8> %0,
- <vscale x 16 x i8> %1,
- i32 %2)
-
- ret <vscale x 16 x i8> %a
-}
-
-declare <vscale x 16 x i8> @llvm.riscv.vmulhu.mask.nxv16i8.nxv16i8(
- <vscale x 16 x i8>,
- <vscale x 16 x i8>,
- <vscale x 16 x i8>,
- <vscale x 16 x i1>,
- i32,
- i32);
-
-define <vscale x 16 x i8> @intrinsic_vmulhu_mask_vv_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmulhu_mask_vv_nxv16i8_nxv16i8_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
-; CHECK-NEXT: vmulhu.vv v8, v10, v12, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i8> @llvm.riscv.vmulhu.mask.nxv16i8.nxv16i8(
- <vscale x 16 x i8> %0,
- <vscale x 16 x i8> %1,
- <vscale x 16 x i8> %2,
- <vscale x 16 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 16 x i8> %a
-}
-
-declare <vscale x 32 x i8> @llvm.riscv.vmulhu.nxv32i8.nxv32i8(
- <vscale x 32 x i8>,
- <vscale x 32 x i8>,
- <vscale x 32 x i8>,
- i32);
-
-define <vscale x 32 x i8> @intrinsic_vmulhu_vv_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmulhu_vv_nxv32i8_nxv32i8_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
-; CHECK-NEXT: vmulhu.vv v8, v8, v12
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 32 x i8> @llvm.riscv.vmulhu.nxv32i8.nxv32i8(
- <vscale x 32 x i8> undef,
- <vscale x 32 x i8> %0,
- <vscale x 32 x i8> %1,
- i32 %2)
-
- ret <vscale x 32 x i8> %a
-}
-
-declare <vscale x 32 x i8> @llvm.riscv.vmulhu.mask.nxv32i8.nxv32i8(
- <vscale x 32 x i8>,
- <vscale x 32 x i8>,
- <vscale x 32 x i8>,
- <vscale x 32 x i1>,
- i32,
- i32);
-
-define <vscale x 32 x i8> @intrinsic_vmulhu_mask_vv_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmulhu_mask_vv_nxv32i8_nxv32i8_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
-; CHECK-NEXT: vmulhu.vv v8, v12, v16, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 32 x i8> @llvm.riscv.vmulhu.mask.nxv32i8.nxv32i8(
- <vscale x 32 x i8> %0,
- <vscale x 32 x i8> %1,
- <vscale x 32 x i8> %2,
- <vscale x 32 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 32 x i8> %a
-}
-
-declare <vscale x 64 x i8> @llvm.riscv.vmulhu.nxv64i8.nxv64i8(
- <vscale x 64 x i8>,
- <vscale x 64 x i8>,
- <vscale x 64 x i8>,
- i32);
-
-define <vscale x 64 x i8> @intrinsic_vmulhu_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmulhu_vv_nxv64i8_nxv64i8_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, mu
-; CHECK-NEXT: vmulhu.vv v8, v8, v16
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 64 x i8> @llvm.riscv.vmulhu.nxv64i8.nxv64i8(
- <vscale x 64 x i8> undef,
- <vscale x 64 x i8> %0,
- <vscale x 64 x i8> %1,
- i32 %2)
-
- ret <vscale x 64 x i8> %a
-}
-
-declare <vscale x 64 x i8> @llvm.riscv.vmulhu.mask.nxv64i8.nxv64i8(
- <vscale x 64 x i8>,
- <vscale x 64 x i8>,
- <vscale x 64 x i8>,
- <vscale x 64 x i1>,
- i32,
- i32);
-
-define <vscale x 64 x i8> @intrinsic_vmulhu_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmulhu_mask_vv_nxv64i8_nxv64i8_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vl8r.v v24, (a0)
-; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu
-; CHECK-NEXT: vmulhu.vv v8, v16, v24, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 64 x i8> @llvm.riscv.vmulhu.mask.nxv64i8.nxv64i8(
- <vscale x 64 x i8> %0,
- <vscale x 64 x i8> %1,
- <vscale x 64 x i8> %2,
- <vscale x 64 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 64 x i8> %a
-}
-
-declare <vscale x 1 x i16> @llvm.riscv.vmulhu.nxv1i16.nxv1i16(
- <vscale x 1 x i16>,
- <vscale x 1 x i16>,
- <vscale x 1 x i16>,
- i32);
-
-define <vscale x 1 x i16> @intrinsic_vmulhu_vv_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmulhu_vv_nxv1i16_nxv1i16_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vmulhu.vv v8, v8, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i16> @llvm.riscv.vmulhu.nxv1i16.nxv1i16(
- <vscale x 1 x i16> undef,
- <vscale x 1 x i16> %0,
- <vscale x 1 x i16> %1,
- i32 %2)
-
- ret <vscale x 1 x i16> %a
-}
-
-declare <vscale x 1 x i16> @llvm.riscv.vmulhu.mask.nxv1i16.nxv1i16(
- <vscale x 1 x i16>,
- <vscale x 1 x i16>,
- <vscale x 1 x i16>,
- <vscale x 1 x i1>,
- i32,
- i32);
-
-define <vscale x 1 x i16> @intrinsic_vmulhu_mask_vv_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmulhu_mask_vv_nxv1i16_nxv1i16_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vmulhu.vv v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i16> @llvm.riscv.vmulhu.mask.nxv1i16.nxv1i16(
- <vscale x 1 x i16> %0,
- <vscale x 1 x i16> %1,
- <vscale x 1 x i16> %2,
- <vscale x 1 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 1 x i16> %a
-}
-
-declare <vscale x 2 x i16> @llvm.riscv.vmulhu.nxv2i16.nxv2i16(
- <vscale x 2 x i16>,
- <vscale x 2 x i16>,
- <vscale x 2 x i16>,
- i32);
-
-define <vscale x 2 x i16> @intrinsic_vmulhu_vv_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmulhu_vv_nxv2i16_nxv2i16_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vmulhu.vv v8, v8, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i16> @llvm.riscv.vmulhu.nxv2i16.nxv2i16(
- <vscale x 2 x i16> undef,
- <vscale x 2 x i16> %0,
- <vscale x 2 x i16> %1,
- i32 %2)
-
- ret <vscale x 2 x i16> %a
-}
-
-declare <vscale x 2 x i16> @llvm.riscv.vmulhu.mask.nxv2i16.nxv2i16(
- <vscale x 2 x i16>,
- <vscale x 2 x i16>,
- <vscale x 2 x i16>,
- <vscale x 2 x i1>,
- i32,
- i32);
-
-define <vscale x 2 x i16> @intrinsic_vmulhu_mask_vv_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmulhu_mask_vv_nxv2i16_nxv2i16_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vmulhu.vv v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i16> @llvm.riscv.vmulhu.mask.nxv2i16.nxv2i16(
- <vscale x 2 x i16> %0,
- <vscale x 2 x i16> %1,
- <vscale x 2 x i16> %2,
- <vscale x 2 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 2 x i16> %a
-}
-
-declare <vscale x 4 x i16> @llvm.riscv.vmulhu.nxv4i16.nxv4i16(
- <vscale x 4 x i16>,
- <vscale x 4 x i16>,
- <vscale x 4 x i16>,
- i32);
-
-define <vscale x 4 x i16> @intrinsic_vmulhu_vv_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmulhu_vv_nxv4i16_nxv4i16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vmulhu.vv v8, v8, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i16> @llvm.riscv.vmulhu.nxv4i16.nxv4i16(
- <vscale x 4 x i16> undef,
- <vscale x 4 x i16> %0,
- <vscale x 4 x i16> %1,
- i32 %2)
-
- ret <vscale x 4 x i16> %a
-}
-
-declare <vscale x 4 x i16> @llvm.riscv.vmulhu.mask.nxv4i16.nxv4i16(
- <vscale x 4 x i16>,
- <vscale x 4 x i16>,
- <vscale x 4 x i16>,
- <vscale x 4 x i1>,
- i32,
- i32);
-
-define <vscale x 4 x i16> @intrinsic_vmulhu_mask_vv_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmulhu_mask_vv_nxv4i16_nxv4i16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vmulhu.vv v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i16> @llvm.riscv.vmulhu.mask.nxv4i16.nxv4i16(
- <vscale x 4 x i16> %0,
- <vscale x 4 x i16> %1,
- <vscale x 4 x i16> %2,
- <vscale x 4 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 4 x i16> %a
-}
-
-declare <vscale x 8 x i16> @llvm.riscv.vmulhu.nxv8i16.nxv8i16(
- <vscale x 8 x i16>,
- <vscale x 8 x i16>,
- <vscale x 8 x i16>,
- i32);
-
-define <vscale x 8 x i16> @intrinsic_vmulhu_vv_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmulhu_vv_nxv8i16_nxv8i16_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vmulhu.vv v8, v8, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i16> @llvm.riscv.vmulhu.nxv8i16.nxv8i16(
- <vscale x 8 x i16> undef,
- <vscale x 8 x i16> %0,
- <vscale x 8 x i16> %1,
- i32 %2)
-
- ret <vscale x 8 x i16> %a
-}
-
-declare <vscale x 8 x i16> @llvm.riscv.vmulhu.mask.nxv8i16.nxv8i16(
- <vscale x 8 x i16>,
- <vscale x 8 x i16>,
- <vscale x 8 x i16>,
- <vscale x 8 x i1>,
- i32,
- i32);
-
-define <vscale x 8 x i16> @intrinsic_vmulhu_mask_vv_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmulhu_mask_vv_nxv8i16_nxv8i16_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vmulhu.vv v8, v10, v12, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i16> @llvm.riscv.vmulhu.mask.nxv8i16.nxv8i16(
- <vscale x 8 x i16> %0,
- <vscale x 8 x i16> %1,
- <vscale x 8 x i16> %2,
- <vscale x 8 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 8 x i16> %a
-}
-
-declare <vscale x 16 x i16> @llvm.riscv.vmulhu.nxv16i16.nxv16i16(
- <vscale x 16 x i16>,
- <vscale x 16 x i16>,
- <vscale x 16 x i16>,
- i32);
-
-define <vscale x 16 x i16> @intrinsic_vmulhu_vv_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmulhu_vv_nxv16i16_nxv16i16_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
-; CHECK-NEXT: vmulhu.vv v8, v8, v12
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i16> @llvm.riscv.vmulhu.nxv16i16.nxv16i16(
- <vscale x 16 x i16> undef,
- <vscale x 16 x i16> %0,
- <vscale x 16 x i16> %1,
- i32 %2)
-
- ret <vscale x 16 x i16> %a
-}
-
-declare <vscale x 16 x i16> @llvm.riscv.vmulhu.mask.nxv16i16.nxv16i16(
- <vscale x 16 x i16>,
- <vscale x 16 x i16>,
- <vscale x 16 x i16>,
- <vscale x 16 x i1>,
- i32,
- i32);
-
-define <vscale x 16 x i16> @intrinsic_vmulhu_mask_vv_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmulhu_mask_vv_nxv16i16_nxv16i16_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
-; CHECK-NEXT: vmulhu.vv v8, v12, v16, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i16> @llvm.riscv.vmulhu.mask.nxv16i16.nxv16i16(
- <vscale x 16 x i16> %0,
- <vscale x 16 x i16> %1,
- <vscale x 16 x i16> %2,
- <vscale x 16 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 16 x i16> %a
-}
-
-declare <vscale x 32 x i16> @llvm.riscv.vmulhu.nxv32i16.nxv32i16(
- <vscale x 32 x i16>,
- <vscale x 32 x i16>,
- <vscale x 32 x i16>,
- i32);
-
-define <vscale x 32 x i16> @intrinsic_vmulhu_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmulhu_vv_nxv32i16_nxv32i16_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, mu
-; CHECK-NEXT: vmulhu.vv v8, v8, v16
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 32 x i16> @llvm.riscv.vmulhu.nxv32i16.nxv32i16(
- <vscale x 32 x i16> undef,
- <vscale x 32 x i16> %0,
- <vscale x 32 x i16> %1,
- i32 %2)
-
- ret <vscale x 32 x i16> %a
-}
-
-declare <vscale x 32 x i16> @llvm.riscv.vmulhu.mask.nxv32i16.nxv32i16(
- <vscale x 32 x i16>,
- <vscale x 32 x i16>,
- <vscale x 32 x i16>,
- <vscale x 32 x i1>,
- i32,
- i32);
-
-define <vscale x 32 x i16> @intrinsic_vmulhu_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmulhu_mask_vv_nxv32i16_nxv32i16_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vl8re16.v v24, (a0)
-; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu
-; CHECK-NEXT: vmulhu.vv v8, v16, v24, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 32 x i16> @llvm.riscv.vmulhu.mask.nxv32i16.nxv32i16(
- <vscale x 32 x i16> %0,
- <vscale x 32 x i16> %1,
- <vscale x 32 x i16> %2,
- <vscale x 32 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 32 x i16> %a
-}
-
-declare <vscale x 1 x i32> @llvm.riscv.vmulhu.nxv1i32.nxv1i32(
- <vscale x 1 x i32>,
- <vscale x 1 x i32>,
- <vscale x 1 x i32>,
- i32);
-
-define <vscale x 1 x i32> @intrinsic_vmulhu_vv_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmulhu_vv_nxv1i32_nxv1i32_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vmulhu.vv v8, v8, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i32> @llvm.riscv.vmulhu.nxv1i32.nxv1i32(
- <vscale x 1 x i32> undef,
- <vscale x 1 x i32> %0,
- <vscale x 1 x i32> %1,
- i32 %2)
-
- ret <vscale x 1 x i32> %a
-}
-
-declare <vscale x 1 x i32> @llvm.riscv.vmulhu.mask.nxv1i32.nxv1i32(
- <vscale x 1 x i32>,
- <vscale x 1 x i32>,
- <vscale x 1 x i32>,
- <vscale x 1 x i1>,
- i32,
- i32);
-
-define <vscale x 1 x i32> @intrinsic_vmulhu_mask_vv_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmulhu_mask_vv_nxv1i32_nxv1i32_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vmulhu.vv v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i32> @llvm.riscv.vmulhu.mask.nxv1i32.nxv1i32(
- <vscale x 1 x i32> %0,
- <vscale x 1 x i32> %1,
- <vscale x 1 x i32> %2,
- <vscale x 1 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 1 x i32> %a
-}
-
-declare <vscale x 2 x i32> @llvm.riscv.vmulhu.nxv2i32.nxv2i32(
- <vscale x 2 x i32>,
- <vscale x 2 x i32>,
- <vscale x 2 x i32>,
- i32);
-
-define <vscale x 2 x i32> @intrinsic_vmulhu_vv_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmulhu_vv_nxv2i32_nxv2i32_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vmulhu.vv v8, v8, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i32> @llvm.riscv.vmulhu.nxv2i32.nxv2i32(
- <vscale x 2 x i32> undef,
- <vscale x 2 x i32> %0,
- <vscale x 2 x i32> %1,
- i32 %2)
-
- ret <vscale x 2 x i32> %a
-}
-
-declare <vscale x 2 x i32> @llvm.riscv.vmulhu.mask.nxv2i32.nxv2i32(
- <vscale x 2 x i32>,
- <vscale x 2 x i32>,
- <vscale x 2 x i32>,
- <vscale x 2 x i1>,
- i32,
- i32);
-
-define <vscale x 2 x i32> @intrinsic_vmulhu_mask_vv_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmulhu_mask_vv_nxv2i32_nxv2i32_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vmulhu.vv v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i32> @llvm.riscv.vmulhu.mask.nxv2i32.nxv2i32(
- <vscale x 2 x i32> %0,
- <vscale x 2 x i32> %1,
- <vscale x 2 x i32> %2,
- <vscale x 2 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 2 x i32> %a
-}
-
-declare <vscale x 4 x i32> @llvm.riscv.vmulhu.nxv4i32.nxv4i32(
- <vscale x 4 x i32>,
- <vscale x 4 x i32>,
- <vscale x 4 x i32>,
- i32);
-
-define <vscale x 4 x i32> @intrinsic_vmulhu_vv_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmulhu_vv_nxv4i32_nxv4i32_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vmulhu.vv v8, v8, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i32> @llvm.riscv.vmulhu.nxv4i32.nxv4i32(
- <vscale x 4 x i32> undef,
- <vscale x 4 x i32> %0,
- <vscale x 4 x i32> %1,
- i32 %2)
-
- ret <vscale x 4 x i32> %a
-}
-
-declare <vscale x 4 x i32> @llvm.riscv.vmulhu.mask.nxv4i32.nxv4i32(
- <vscale x 4 x i32>,
- <vscale x 4 x i32>,
- <vscale x 4 x i32>,
- <vscale x 4 x i1>,
- i32,
- i32);
-
-define <vscale x 4 x i32> @intrinsic_vmulhu_mask_vv_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmulhu_mask_vv_nxv4i32_nxv4i32_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vmulhu.vv v8, v10, v12, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i32> @llvm.riscv.vmulhu.mask.nxv4i32.nxv4i32(
- <vscale x 4 x i32> %0,
- <vscale x 4 x i32> %1,
- <vscale x 4 x i32> %2,
- <vscale x 4 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 4 x i32> %a
-}
-
-declare <vscale x 8 x i32> @llvm.riscv.vmulhu.nxv8i32.nxv8i32(
- <vscale x 8 x i32>,
- <vscale x 8 x i32>,
- <vscale x 8 x i32>,
- i32);
-
-define <vscale x 8 x i32> @intrinsic_vmulhu_vv_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmulhu_vv_nxv8i32_nxv8i32_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
-; CHECK-NEXT: vmulhu.vv v8, v8, v12
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i32> @llvm.riscv.vmulhu.nxv8i32.nxv8i32(
- <vscale x 8 x i32> undef,
- <vscale x 8 x i32> %0,
- <vscale x 8 x i32> %1,
- i32 %2)
-
- ret <vscale x 8 x i32> %a
-}
-
-declare <vscale x 8 x i32> @llvm.riscv.vmulhu.mask.nxv8i32.nxv8i32(
- <vscale x 8 x i32>,
- <vscale x 8 x i32>,
- <vscale x 8 x i32>,
- <vscale x 8 x i1>,
- i32,
- i32);
-
-define <vscale x 8 x i32> @intrinsic_vmulhu_mask_vv_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmulhu_mask_vv_nxv8i32_nxv8i32_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
-; CHECK-NEXT: vmulhu.vv v8, v12, v16, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i32> @llvm.riscv.vmulhu.mask.nxv8i32.nxv8i32(
- <vscale x 8 x i32> %0,
- <vscale x 8 x i32> %1,
- <vscale x 8 x i32> %2,
- <vscale x 8 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 8 x i32> %a
-}
-
-declare <vscale x 16 x i32> @llvm.riscv.vmulhu.nxv16i32.nxv16i32(
- <vscale x 16 x i32>,
- <vscale x 16 x i32>,
- <vscale x 16 x i32>,
- i32);
-
-define <vscale x 16 x i32> @intrinsic_vmulhu_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmulhu_vv_nxv16i32_nxv16i32_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu
-; CHECK-NEXT: vmulhu.vv v8, v8, v16
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i32> @llvm.riscv.vmulhu.nxv16i32.nxv16i32(
- <vscale x 16 x i32> undef,
- <vscale x 16 x i32> %0,
- <vscale x 16 x i32> %1,
- i32 %2)
-
- ret <vscale x 16 x i32> %a
-}
-
-declare <vscale x 16 x i32> @llvm.riscv.vmulhu.mask.nxv16i32.nxv16i32(
- <vscale x 16 x i32>,
- <vscale x 16 x i32>,
- <vscale x 16 x i32>,
- <vscale x 16 x i1>,
- i32,
- i32);
-
-define <vscale x 16 x i32> @intrinsic_vmulhu_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmulhu_mask_vv_nxv16i32_nxv16i32_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vl8re32.v v24, (a0)
-; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu
-; CHECK-NEXT: vmulhu.vv v8, v16, v24, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i32> @llvm.riscv.vmulhu.mask.nxv16i32.nxv16i32(
- <vscale x 16 x i32> %0,
- <vscale x 16 x i32> %1,
- <vscale x 16 x i32> %2,
- <vscale x 16 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 16 x i32> %a
-}
-
-declare <vscale x 1 x i64> @llvm.riscv.vmulhu.nxv1i64.nxv1i64(
- <vscale x 1 x i64>,
- <vscale x 1 x i64>,
- <vscale x 1 x i64>,
- i32);
-
-define <vscale x 1 x i64> @intrinsic_vmulhu_vv_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmulhu_vv_nxv1i64_nxv1i64_nxv1i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
-; CHECK-NEXT: vmulhu.vv v8, v8, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i64> @llvm.riscv.vmulhu.nxv1i64.nxv1i64(
- <vscale x 1 x i64> undef,
- <vscale x 1 x i64> %0,
- <vscale x 1 x i64> %1,
- i32 %2)
-
- ret <vscale x 1 x i64> %a
-}
-
-declare <vscale x 1 x i64> @llvm.riscv.vmulhu.mask.nxv1i64.nxv1i64(
- <vscale x 1 x i64>,
- <vscale x 1 x i64>,
- <vscale x 1 x i64>,
- <vscale x 1 x i1>,
- i32,
- i32);
-
-define <vscale x 1 x i64> @intrinsic_vmulhu_mask_vv_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmulhu_mask_vv_nxv1i64_nxv1i64_nxv1i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
-; CHECK-NEXT: vmulhu.vv v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i64> @llvm.riscv.vmulhu.mask.nxv1i64.nxv1i64(
- <vscale x 1 x i64> %0,
- <vscale x 1 x i64> %1,
- <vscale x 1 x i64> %2,
- <vscale x 1 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 1 x i64> %a
-}
-
-declare <vscale x 2 x i64> @llvm.riscv.vmulhu.nxv2i64.nxv2i64(
- <vscale x 2 x i64>,
- <vscale x 2 x i64>,
- <vscale x 2 x i64>,
- i32);
-
-define <vscale x 2 x i64> @intrinsic_vmulhu_vv_nxv2i64_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmulhu_vv_nxv2i64_nxv2i64_nxv2i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
-; CHECK-NEXT: vmulhu.vv v8, v8, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i64> @llvm.riscv.vmulhu.nxv2i64.nxv2i64(
- <vscale x 2 x i64> undef,
- <vscale x 2 x i64> %0,
- <vscale x 2 x i64> %1,
- i32 %2)
-
- ret <vscale x 2 x i64> %a
-}
-
-declare <vscale x 2 x i64> @llvm.riscv.vmulhu.mask.nxv2i64.nxv2i64(
- <vscale x 2 x i64>,
- <vscale x 2 x i64>,
- <vscale x 2 x i64>,
- <vscale x 2 x i1>,
- i32,
- i32);
-
-define <vscale x 2 x i64> @intrinsic_vmulhu_mask_vv_nxv2i64_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmulhu_mask_vv_nxv2i64_nxv2i64_nxv2i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
-; CHECK-NEXT: vmulhu.vv v8, v10, v12, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i64> @llvm.riscv.vmulhu.mask.nxv2i64.nxv2i64(
- <vscale x 2 x i64> %0,
- <vscale x 2 x i64> %1,
- <vscale x 2 x i64> %2,
- <vscale x 2 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 2 x i64> %a
-}
-
-declare <vscale x 4 x i64> @llvm.riscv.vmulhu.nxv4i64.nxv4i64(
- <vscale x 4 x i64>,
- <vscale x 4 x i64>,
- <vscale x 4 x i64>,
- i32);
-
-define <vscale x 4 x i64> @intrinsic_vmulhu_vv_nxv4i64_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmulhu_vv_nxv4i64_nxv4i64_nxv4i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
-; CHECK-NEXT: vmulhu.vv v8, v8, v12
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i64> @llvm.riscv.vmulhu.nxv4i64.nxv4i64(
- <vscale x 4 x i64> undef,
- <vscale x 4 x i64> %0,
- <vscale x 4 x i64> %1,
- i32 %2)
-
- ret <vscale x 4 x i64> %a
-}
-
-declare <vscale x 4 x i64> @llvm.riscv.vmulhu.mask.nxv4i64.nxv4i64(
- <vscale x 4 x i64>,
- <vscale x 4 x i64>,
- <vscale x 4 x i64>,
- <vscale x 4 x i1>,
- i32,
- i32);
-
-define <vscale x 4 x i64> @intrinsic_vmulhu_mask_vv_nxv4i64_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmulhu_mask_vv_nxv4i64_nxv4i64_nxv4i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
-; CHECK-NEXT: vmulhu.vv v8, v12, v16, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i64> @llvm.riscv.vmulhu.mask.nxv4i64.nxv4i64(
- <vscale x 4 x i64> %0,
- <vscale x 4 x i64> %1,
- <vscale x 4 x i64> %2,
- <vscale x 4 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 4 x i64> %a
-}
-
-declare <vscale x 8 x i64> @llvm.riscv.vmulhu.nxv8i64.nxv8i64(
- <vscale x 8 x i64>,
- <vscale x 8 x i64>,
- <vscale x 8 x i64>,
- i32);
-
-define <vscale x 8 x i64> @intrinsic_vmulhu_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmulhu_vv_nxv8i64_nxv8i64_nxv8i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu
-; CHECK-NEXT: vmulhu.vv v8, v8, v16
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i64> @llvm.riscv.vmulhu.nxv8i64.nxv8i64(
- <vscale x 8 x i64> undef,
- <vscale x 8 x i64> %0,
- <vscale x 8 x i64> %1,
- i32 %2)
-
- ret <vscale x 8 x i64> %a
-}
-
-declare <vscale x 8 x i64> @llvm.riscv.vmulhu.mask.nxv8i64.nxv8i64(
- <vscale x 8 x i64>,
- <vscale x 8 x i64>,
- <vscale x 8 x i64>,
- <vscale x 8 x i1>,
- i32,
- i32);
-
-define <vscale x 8 x i64> @intrinsic_vmulhu_mask_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmulhu_mask_vv_nxv8i64_nxv8i64_nxv8i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vl8re64.v v24, (a0)
-; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu
-; CHECK-NEXT: vmulhu.vv v8, v16, v24, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i64> @llvm.riscv.vmulhu.mask.nxv8i64.nxv8i64(
- <vscale x 8 x i64> %0,
- <vscale x 8 x i64> %1,
- <vscale x 8 x i64> %2,
- <vscale x 8 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 8 x i64> %a
-}
-
-declare <vscale x 1 x i8> @llvm.riscv.vmulhu.nxv1i8.i8(
- <vscale x 1 x i8>,
- <vscale x 1 x i8>,
- i8,
- i32);
-
-define <vscale x 1 x i8> @intrinsic_vmulhu_vx_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, i8 %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmulhu_vx_nxv1i8_nxv1i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
-; CHECK-NEXT: vmulhu.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i8> @llvm.riscv.vmulhu.nxv1i8.i8(
- <vscale x 1 x i8> undef,
- <vscale x 1 x i8> %0,
- i8 %1,
- i32 %2)
-
- ret <vscale x 1 x i8> %a
-}
-
-declare <vscale x 1 x i8> @llvm.riscv.vmulhu.mask.nxv1i8.i8(
- <vscale x 1 x i8>,
- <vscale x 1 x i8>,
- i8,
- <vscale x 1 x i1>,
- i32,
- i32);
-
-define <vscale x 1 x i8> @intrinsic_vmulhu_mask_vx_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmulhu_mask_vx_nxv1i8_nxv1i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
-; CHECK-NEXT: vmulhu.vx v8, v9, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i8> @llvm.riscv.vmulhu.mask.nxv1i8.i8(
- <vscale x 1 x i8> %0,
- <vscale x 1 x i8> %1,
- i8 %2,
- <vscale x 1 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 1 x i8> %a
-}
-
-declare <vscale x 2 x i8> @llvm.riscv.vmulhu.nxv2i8.i8(
- <vscale x 2 x i8>,
- <vscale x 2 x i8>,
- i8,
- i32);
-
-define <vscale x 2 x i8> @intrinsic_vmulhu_vx_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, i8 %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmulhu_vx_nxv2i8_nxv2i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
-; CHECK-NEXT: vmulhu.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i8> @llvm.riscv.vmulhu.nxv2i8.i8(
- <vscale x 2 x i8> undef,
- <vscale x 2 x i8> %0,
- i8 %1,
- i32 %2)
-
- ret <vscale x 2 x i8> %a
-}
-
-declare <vscale x 2 x i8> @llvm.riscv.vmulhu.mask.nxv2i8.i8(
- <vscale x 2 x i8>,
- <vscale x 2 x i8>,
- i8,
- <vscale x 2 x i1>,
- i32,
- i32);
-
-define <vscale x 2 x i8> @intrinsic_vmulhu_mask_vx_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmulhu_mask_vx_nxv2i8_nxv2i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
-; CHECK-NEXT: vmulhu.vx v8, v9, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i8> @llvm.riscv.vmulhu.mask.nxv2i8.i8(
- <vscale x 2 x i8> %0,
- <vscale x 2 x i8> %1,
- i8 %2,
- <vscale x 2 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 2 x i8> %a
-}
-
-declare <vscale x 4 x i8> @llvm.riscv.vmulhu.nxv4i8.i8(
- <vscale x 4 x i8>,
- <vscale x 4 x i8>,
- i8,
- i32);
-
-define <vscale x 4 x i8> @intrinsic_vmulhu_vx_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, i8 %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmulhu_vx_nxv4i8_nxv4i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
-; CHECK-NEXT: vmulhu.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i8> @llvm.riscv.vmulhu.nxv4i8.i8(
- <vscale x 4 x i8> undef,
- <vscale x 4 x i8> %0,
- i8 %1,
- i32 %2)
-
- ret <vscale x 4 x i8> %a
-}
-
-declare <vscale x 4 x i8> @llvm.riscv.vmulhu.mask.nxv4i8.i8(
- <vscale x 4 x i8>,
- <vscale x 4 x i8>,
- i8,
- <vscale x 4 x i1>,
- i32,
- i32);
-
-define <vscale x 4 x i8> @intrinsic_vmulhu_mask_vx_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmulhu_mask_vx_nxv4i8_nxv4i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
-; CHECK-NEXT: vmulhu.vx v8, v9, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i8> @llvm.riscv.vmulhu.mask.nxv4i8.i8(
- <vscale x 4 x i8> %0,
- <vscale x 4 x i8> %1,
- i8 %2,
- <vscale x 4 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 4 x i8> %a
-}
-
-declare <vscale x 8 x i8> @llvm.riscv.vmulhu.nxv8i8.i8(
- <vscale x 8 x i8>,
- <vscale x 8 x i8>,
- i8,
- i32);
-
-define <vscale x 8 x i8> @intrinsic_vmulhu_vx_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, i8 %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmulhu_vx_nxv8i8_nxv8i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
-; CHECK-NEXT: vmulhu.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i8> @llvm.riscv.vmulhu.nxv8i8.i8(
- <vscale x 8 x i8> undef,
- <vscale x 8 x i8> %0,
- i8 %1,
- i32 %2)
-
- ret <vscale x 8 x i8> %a
-}
-
-declare <vscale x 8 x i8> @llvm.riscv.vmulhu.mask.nxv8i8.i8(
- <vscale x 8 x i8>,
- <vscale x 8 x i8>,
- i8,
- <vscale x 8 x i1>,
- i32,
- i32);
-
-define <vscale x 8 x i8> @intrinsic_vmulhu_mask_vx_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmulhu_mask_vx_nxv8i8_nxv8i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
-; CHECK-NEXT: vmulhu.vx v8, v9, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i8> @llvm.riscv.vmulhu.mask.nxv8i8.i8(
- <vscale x 8 x i8> %0,
- <vscale x 8 x i8> %1,
- i8 %2,
- <vscale x 8 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 8 x i8> %a
-}
-
-declare <vscale x 16 x i8> @llvm.riscv.vmulhu.nxv16i8.i8(
- <vscale x 16 x i8>,
- <vscale x 16 x i8>,
- i8,
- i32);
-
-define <vscale x 16 x i8> @intrinsic_vmulhu_vx_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, i8 %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmulhu_vx_nxv16i8_nxv16i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
-; CHECK-NEXT: vmulhu.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i8> @llvm.riscv.vmulhu.nxv16i8.i8(
- <vscale x 16 x i8> undef,
- <vscale x 16 x i8> %0,
- i8 %1,
- i32 %2)
-
- ret <vscale x 16 x i8> %a
-}
-
-declare <vscale x 16 x i8> @llvm.riscv.vmulhu.mask.nxv16i8.i8(
- <vscale x 16 x i8>,
- <vscale x 16 x i8>,
- i8,
- <vscale x 16 x i1>,
- i32,
- i32);
-
-define <vscale x 16 x i8> @intrinsic_vmulhu_mask_vx_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmulhu_mask_vx_nxv16i8_nxv16i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
-; CHECK-NEXT: vmulhu.vx v8, v10, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i8> @llvm.riscv.vmulhu.mask.nxv16i8.i8(
- <vscale x 16 x i8> %0,
- <vscale x 16 x i8> %1,
- i8 %2,
- <vscale x 16 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 16 x i8> %a
-}
-
-declare <vscale x 32 x i8> @llvm.riscv.vmulhu.nxv32i8.i8(
- <vscale x 32 x i8>,
- <vscale x 32 x i8>,
- i8,
- i32);
-
-define <vscale x 32 x i8> @intrinsic_vmulhu_vx_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, i8 %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmulhu_vx_nxv32i8_nxv32i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
-; CHECK-NEXT: vmulhu.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 32 x i8> @llvm.riscv.vmulhu.nxv32i8.i8(
- <vscale x 32 x i8> undef,
- <vscale x 32 x i8> %0,
- i8 %1,
- i32 %2)
-
- ret <vscale x 32 x i8> %a
-}
-
-declare <vscale x 32 x i8> @llvm.riscv.vmulhu.mask.nxv32i8.i8(
- <vscale x 32 x i8>,
- <vscale x 32 x i8>,
- i8,
- <vscale x 32 x i1>,
- i32,
- i32);
-
-define <vscale x 32 x i8> @intrinsic_vmulhu_mask_vx_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmulhu_mask_vx_nxv32i8_nxv32i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
-; CHECK-NEXT: vmulhu.vx v8, v12, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 32 x i8> @llvm.riscv.vmulhu.mask.nxv32i8.i8(
- <vscale x 32 x i8> %0,
- <vscale x 32 x i8> %1,
- i8 %2,
- <vscale x 32 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 32 x i8> %a
-}
-
-declare <vscale x 64 x i8> @llvm.riscv.vmulhu.nxv64i8.i8(
- <vscale x 64 x i8>,
- <vscale x 64 x i8>,
- i8,
- i32);
-
-define <vscale x 64 x i8> @intrinsic_vmulhu_vx_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, i8 %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmulhu_vx_nxv64i8_nxv64i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu
-; CHECK-NEXT: vmulhu.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 64 x i8> @llvm.riscv.vmulhu.nxv64i8.i8(
- <vscale x 64 x i8> undef,
- <vscale x 64 x i8> %0,
- i8 %1,
- i32 %2)
-
- ret <vscale x 64 x i8> %a
-}
-
-declare <vscale x 64 x i8> @llvm.riscv.vmulhu.mask.nxv64i8.i8(
- <vscale x 64 x i8>,
- <vscale x 64 x i8>,
- i8,
- <vscale x 64 x i1>,
- i32,
- i32);
-
-define <vscale x 64 x i8> @intrinsic_vmulhu_mask_vx_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i8 %2, <vscale x 64 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmulhu_mask_vx_nxv64i8_nxv64i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu
-; CHECK-NEXT: vmulhu.vx v8, v16, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 64 x i8> @llvm.riscv.vmulhu.mask.nxv64i8.i8(
- <vscale x 64 x i8> %0,
- <vscale x 64 x i8> %1,
- i8 %2,
- <vscale x 64 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 64 x i8> %a
-}
-
-declare <vscale x 1 x i16> @llvm.riscv.vmulhu.nxv1i16.i16(
- <vscale x 1 x i16>,
- <vscale x 1 x i16>,
- i16,
- i32);
-
-define <vscale x 1 x i16> @intrinsic_vmulhu_vx_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, i16 %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmulhu_vx_nxv1i16_nxv1i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
-; CHECK-NEXT: vmulhu.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i16> @llvm.riscv.vmulhu.nxv1i16.i16(
- <vscale x 1 x i16> undef,
- <vscale x 1 x i16> %0,
- i16 %1,
- i32 %2)
-
- ret <vscale x 1 x i16> %a
-}
-
-declare <vscale x 1 x i16> @llvm.riscv.vmulhu.mask.nxv1i16.i16(
- <vscale x 1 x i16>,
- <vscale x 1 x i16>,
- i16,
- <vscale x 1 x i1>,
- i32,
- i32);
-
-define <vscale x 1 x i16> @intrinsic_vmulhu_mask_vx_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmulhu_mask_vx_nxv1i16_nxv1i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
-; CHECK-NEXT: vmulhu.vx v8, v9, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i16> @llvm.riscv.vmulhu.mask.nxv1i16.i16(
- <vscale x 1 x i16> %0,
- <vscale x 1 x i16> %1,
- i16 %2,
- <vscale x 1 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 1 x i16> %a
-}
-
-declare <vscale x 2 x i16> @llvm.riscv.vmulhu.nxv2i16.i16(
- <vscale x 2 x i16>,
- <vscale x 2 x i16>,
- i16,
- i32);
-
-define <vscale x 2 x i16> @intrinsic_vmulhu_vx_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, i16 %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmulhu_vx_nxv2i16_nxv2i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
-; CHECK-NEXT: vmulhu.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i16> @llvm.riscv.vmulhu.nxv2i16.i16(
- <vscale x 2 x i16> undef,
- <vscale x 2 x i16> %0,
- i16 %1,
- i32 %2)
-
- ret <vscale x 2 x i16> %a
-}
-
-declare <vscale x 2 x i16> @llvm.riscv.vmulhu.mask.nxv2i16.i16(
- <vscale x 2 x i16>,
- <vscale x 2 x i16>,
- i16,
- <vscale x 2 x i1>,
- i32,
- i32);
-
-define <vscale x 2 x i16> @intrinsic_vmulhu_mask_vx_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmulhu_mask_vx_nxv2i16_nxv2i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
-; CHECK-NEXT: vmulhu.vx v8, v9, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i16> @llvm.riscv.vmulhu.mask.nxv2i16.i16(
- <vscale x 2 x i16> %0,
- <vscale x 2 x i16> %1,
- i16 %2,
- <vscale x 2 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 2 x i16> %a
-}
-
-declare <vscale x 4 x i16> @llvm.riscv.vmulhu.nxv4i16.i16(
- <vscale x 4 x i16>,
- <vscale x 4 x i16>,
- i16,
- i32);
-
-define <vscale x 4 x i16> @intrinsic_vmulhu_vx_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, i16 %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmulhu_vx_nxv4i16_nxv4i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
-; CHECK-NEXT: vmulhu.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i16> @llvm.riscv.vmulhu.nxv4i16.i16(
- <vscale x 4 x i16> undef,
- <vscale x 4 x i16> %0,
- i16 %1,
- i32 %2)
-
- ret <vscale x 4 x i16> %a
-}
-
-declare <vscale x 4 x i16> @llvm.riscv.vmulhu.mask.nxv4i16.i16(
- <vscale x 4 x i16>,
- <vscale x 4 x i16>,
- i16,
- <vscale x 4 x i1>,
- i32,
- i32);
-
-define <vscale x 4 x i16> @intrinsic_vmulhu_mask_vx_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmulhu_mask_vx_nxv4i16_nxv4i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
-; CHECK-NEXT: vmulhu.vx v8, v9, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i16> @llvm.riscv.vmulhu.mask.nxv4i16.i16(
- <vscale x 4 x i16> %0,
- <vscale x 4 x i16> %1,
- i16 %2,
- <vscale x 4 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 4 x i16> %a
-}
-
-declare <vscale x 8 x i16> @llvm.riscv.vmulhu.nxv8i16.i16(
- <vscale x 8 x i16>,
- <vscale x 8 x i16>,
- i16,
- i32);
-
-define <vscale x 8 x i16> @intrinsic_vmulhu_vx_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, i16 %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmulhu_vx_nxv8i16_nxv8i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
-; CHECK-NEXT: vmulhu.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i16> @llvm.riscv.vmulhu.nxv8i16.i16(
- <vscale x 8 x i16> undef,
- <vscale x 8 x i16> %0,
- i16 %1,
- i32 %2)
-
- ret <vscale x 8 x i16> %a
-}
-
-declare <vscale x 8 x i16> @llvm.riscv.vmulhu.mask.nxv8i16.i16(
- <vscale x 8 x i16>,
- <vscale x 8 x i16>,
- i16,
- <vscale x 8 x i1>,
- i32,
- i32);
-
-define <vscale x 8 x i16> @intrinsic_vmulhu_mask_vx_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmulhu_mask_vx_nxv8i16_nxv8i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
-; CHECK-NEXT: vmulhu.vx v8, v10, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i16> @llvm.riscv.vmulhu.mask.nxv8i16.i16(
- <vscale x 8 x i16> %0,
- <vscale x 8 x i16> %1,
- i16 %2,
- <vscale x 8 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 8 x i16> %a
-}
-
-declare <vscale x 16 x i16> @llvm.riscv.vmulhu.nxv16i16.i16(
- <vscale x 16 x i16>,
- <vscale x 16 x i16>,
- i16,
- i32);
-
-define <vscale x 16 x i16> @intrinsic_vmulhu_vx_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, i16 %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmulhu_vx_nxv16i16_nxv16i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
-; CHECK-NEXT: vmulhu.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i16> @llvm.riscv.vmulhu.nxv16i16.i16(
- <vscale x 16 x i16> undef,
- <vscale x 16 x i16> %0,
- i16 %1,
- i32 %2)
-
- ret <vscale x 16 x i16> %a
-}
-
-declare <vscale x 16 x i16> @llvm.riscv.vmulhu.mask.nxv16i16.i16(
- <vscale x 16 x i16>,
- <vscale x 16 x i16>,
- i16,
- <vscale x 16 x i1>,
- i32,
- i32);
-
-define <vscale x 16 x i16> @intrinsic_vmulhu_mask_vx_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmulhu_mask_vx_nxv16i16_nxv16i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
-; CHECK-NEXT: vmulhu.vx v8, v12, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i16> @llvm.riscv.vmulhu.mask.nxv16i16.i16(
- <vscale x 16 x i16> %0,
- <vscale x 16 x i16> %1,
- i16 %2,
- <vscale x 16 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 16 x i16> %a
-}
-
-declare <vscale x 32 x i16> @llvm.riscv.vmulhu.nxv32i16.i16(
- <vscale x 32 x i16>,
- <vscale x 32 x i16>,
- i16,
- i32);
-
-define <vscale x 32 x i16> @intrinsic_vmulhu_vx_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, i16 %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmulhu_vx_nxv32i16_nxv32i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu
-; CHECK-NEXT: vmulhu.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 32 x i16> @llvm.riscv.vmulhu.nxv32i16.i16(
- <vscale x 32 x i16> undef,
- <vscale x 32 x i16> %0,
- i16 %1,
- i32 %2)
-
- ret <vscale x 32 x i16> %a
-}
-
-declare <vscale x 32 x i16> @llvm.riscv.vmulhu.mask.nxv32i16.i16(
- <vscale x 32 x i16>,
- <vscale x 32 x i16>,
- i16,
- <vscale x 32 x i1>,
- i32,
- i32);
-
-define <vscale x 32 x i16> @intrinsic_vmulhu_mask_vx_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, i16 %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmulhu_mask_vx_nxv32i16_nxv32i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu
-; CHECK-NEXT: vmulhu.vx v8, v16, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 32 x i16> @llvm.riscv.vmulhu.mask.nxv32i16.i16(
- <vscale x 32 x i16> %0,
- <vscale x 32 x i16> %1,
- i16 %2,
- <vscale x 32 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 32 x i16> %a
-}
-
-declare <vscale x 1 x i32> @llvm.riscv.vmulhu.nxv1i32.i32(
- <vscale x 1 x i32>,
- <vscale x 1 x i32>,
- i32,
- i32);
-
-define <vscale x 1 x i32> @intrinsic_vmulhu_vx_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, i32 %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmulhu_vx_nxv1i32_nxv1i32_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
-; CHECK-NEXT: vmulhu.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i32> @llvm.riscv.vmulhu.nxv1i32.i32(
- <vscale x 1 x i32> undef,
- <vscale x 1 x i32> %0,
- i32 %1,
- i32 %2)
-
- ret <vscale x 1 x i32> %a
-}
-
-declare <vscale x 1 x i32> @llvm.riscv.vmulhu.mask.nxv1i32.i32(
- <vscale x 1 x i32>,
- <vscale x 1 x i32>,
- i32,
- <vscale x 1 x i1>,
- i32,
- i32);
-
-define <vscale x 1 x i32> @intrinsic_vmulhu_mask_vx_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmulhu_mask_vx_nxv1i32_nxv1i32_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
-; CHECK-NEXT: vmulhu.vx v8, v9, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i32> @llvm.riscv.vmulhu.mask.nxv1i32.i32(
- <vscale x 1 x i32> %0,
- <vscale x 1 x i32> %1,
- i32 %2,
- <vscale x 1 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 1 x i32> %a
-}
-
-declare <vscale x 2 x i32> @llvm.riscv.vmulhu.nxv2i32.i32(
- <vscale x 2 x i32>,
- <vscale x 2 x i32>,
- i32,
- i32);
-
-define <vscale x 2 x i32> @intrinsic_vmulhu_vx_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, i32 %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmulhu_vx_nxv2i32_nxv2i32_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
-; CHECK-NEXT: vmulhu.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i32> @llvm.riscv.vmulhu.nxv2i32.i32(
- <vscale x 2 x i32> undef,
- <vscale x 2 x i32> %0,
- i32 %1,
- i32 %2)
-
- ret <vscale x 2 x i32> %a
-}
-
-declare <vscale x 2 x i32> @llvm.riscv.vmulhu.mask.nxv2i32.i32(
- <vscale x 2 x i32>,
- <vscale x 2 x i32>,
- i32,
- <vscale x 2 x i1>,
- i32,
- i32);
-
-define <vscale x 2 x i32> @intrinsic_vmulhu_mask_vx_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmulhu_mask_vx_nxv2i32_nxv2i32_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
-; CHECK-NEXT: vmulhu.vx v8, v9, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i32> @llvm.riscv.vmulhu.mask.nxv2i32.i32(
- <vscale x 2 x i32> %0,
- <vscale x 2 x i32> %1,
- i32 %2,
- <vscale x 2 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 2 x i32> %a
-}
-
-declare <vscale x 4 x i32> @llvm.riscv.vmulhu.nxv4i32.i32(
- <vscale x 4 x i32>,
- <vscale x 4 x i32>,
- i32,
- i32);
-
-define <vscale x 4 x i32> @intrinsic_vmulhu_vx_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, i32 %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmulhu_vx_nxv4i32_nxv4i32_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; CHECK-NEXT: vmulhu.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i32> @llvm.riscv.vmulhu.nxv4i32.i32(
- <vscale x 4 x i32> undef,
- <vscale x 4 x i32> %0,
- i32 %1,
- i32 %2)
-
- ret <vscale x 4 x i32> %a
-}
-
-declare <vscale x 4 x i32> @llvm.riscv.vmulhu.mask.nxv4i32.i32(
- <vscale x 4 x i32>,
- <vscale x 4 x i32>,
- i32,
- <vscale x 4 x i1>,
- i32,
- i32);
-
-define <vscale x 4 x i32> @intrinsic_vmulhu_mask_vx_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmulhu_mask_vx_nxv4i32_nxv4i32_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; CHECK-NEXT: vmulhu.vx v8, v10, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i32> @llvm.riscv.vmulhu.mask.nxv4i32.i32(
- <vscale x 4 x i32> %0,
- <vscale x 4 x i32> %1,
- i32 %2,
- <vscale x 4 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 4 x i32> %a
-}
-
-declare <vscale x 8 x i32> @llvm.riscv.vmulhu.nxv8i32.i32(
- <vscale x 8 x i32>,
- <vscale x 8 x i32>,
- i32,
- i32);
-
-define <vscale x 8 x i32> @intrinsic_vmulhu_vx_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, i32 %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmulhu_vx_nxv8i32_nxv8i32_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
-; CHECK-NEXT: vmulhu.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i32> @llvm.riscv.vmulhu.nxv8i32.i32(
- <vscale x 8 x i32> undef,
- <vscale x 8 x i32> %0,
- i32 %1,
- i32 %2)
-
- ret <vscale x 8 x i32> %a
-}
-
-declare <vscale x 8 x i32> @llvm.riscv.vmulhu.mask.nxv8i32.i32(
- <vscale x 8 x i32>,
- <vscale x 8 x i32>,
- i32,
- <vscale x 8 x i1>,
- i32,
- i32);
-
-define <vscale x 8 x i32> @intrinsic_vmulhu_mask_vx_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmulhu_mask_vx_nxv8i32_nxv8i32_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
-; CHECK-NEXT: vmulhu.vx v8, v12, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i32> @llvm.riscv.vmulhu.mask.nxv8i32.i32(
- <vscale x 8 x i32> %0,
- <vscale x 8 x i32> %1,
- i32 %2,
- <vscale x 8 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 8 x i32> %a
-}
-
-declare <vscale x 16 x i32> @llvm.riscv.vmulhu.nxv16i32.i32(
- <vscale x 16 x i32>,
- <vscale x 16 x i32>,
- i32,
- i32);
-
-define <vscale x 16 x i32> @intrinsic_vmulhu_vx_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, i32 %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmulhu_vx_nxv16i32_nxv16i32_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu
-; CHECK-NEXT: vmulhu.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i32> @llvm.riscv.vmulhu.nxv16i32.i32(
- <vscale x 16 x i32> undef,
- <vscale x 16 x i32> %0,
- i32 %1,
- i32 %2)
-
- ret <vscale x 16 x i32> %a
-}
-
-declare <vscale x 16 x i32> @llvm.riscv.vmulhu.mask.nxv16i32.i32(
- <vscale x 16 x i32>,
- <vscale x 16 x i32>,
- i32,
- <vscale x 16 x i1>,
- i32,
- i32);
-
-define <vscale x 16 x i32> @intrinsic_vmulhu_mask_vx_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmulhu_mask_vx_nxv16i32_nxv16i32_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu
-; CHECK-NEXT: vmulhu.vx v8, v16, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i32> @llvm.riscv.vmulhu.mask.nxv16i32.i32(
- <vscale x 16 x i32> %0,
- <vscale x 16 x i32> %1,
- i32 %2,
- <vscale x 16 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 16 x i32> %a
-}
-
-declare <vscale x 1 x i64> @llvm.riscv.vmulhu.nxv1i64.i64(
- <vscale x 1 x i64>,
- <vscale x 1 x i64>,
- i64,
- i32);
-
-define <vscale x 1 x i64> @intrinsic_vmulhu_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmulhu_vx_nxv1i64_nxv1i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addi sp, sp, -16
-; CHECK-NEXT: sw a1, 12(sp)
-; CHECK-NEXT: sw a0, 8(sp)
-; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
-; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v9, (a0), zero
-; CHECK-NEXT: vmulhu.vv v8, v8, v9
-; CHECK-NEXT: addi sp, sp, 16
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i64> @llvm.riscv.vmulhu.nxv1i64.i64(
- <vscale x 1 x i64> undef,
- <vscale x 1 x i64> %0,
- i64 %1,
- i32 %2)
-
- ret <vscale x 1 x i64> %a
-}
-
-declare <vscale x 1 x i64> @llvm.riscv.vmulhu.mask.nxv1i64.i64(
- <vscale x 1 x i64>,
- <vscale x 1 x i64>,
- i64,
- <vscale x 1 x i1>,
- i32,
- i32);
-
-define <vscale x 1 x i64> @intrinsic_vmulhu_mask_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmulhu_mask_vx_nxv1i64_nxv1i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addi sp, sp, -16
-; CHECK-NEXT: sw a1, 12(sp)
-; CHECK-NEXT: sw a0, 8(sp)
-; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
-; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v10, (a0), zero
-; CHECK-NEXT: vmulhu.vv v8, v9, v10, v0.t
-; CHECK-NEXT: addi sp, sp, 16
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i64> @llvm.riscv.vmulhu.mask.nxv1i64.i64(
- <vscale x 1 x i64> %0,
- <vscale x 1 x i64> %1,
- i64 %2,
- <vscale x 1 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 1 x i64> %a
-}
-
-declare <vscale x 2 x i64> @llvm.riscv.vmulhu.nxv2i64.i64(
- <vscale x 2 x i64>,
- <vscale x 2 x i64>,
- i64,
- i32);
-
-define <vscale x 2 x i64> @intrinsic_vmulhu_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmulhu_vx_nxv2i64_nxv2i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addi sp, sp, -16
-; CHECK-NEXT: sw a1, 12(sp)
-; CHECK-NEXT: sw a0, 8(sp)
-; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
-; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v10, (a0), zero
-; CHECK-NEXT: vmulhu.vv v8, v8, v10
-; CHECK-NEXT: addi sp, sp, 16
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i64> @llvm.riscv.vmulhu.nxv2i64.i64(
- <vscale x 2 x i64> undef,
- <vscale x 2 x i64> %0,
- i64 %1,
- i32 %2)
-
- ret <vscale x 2 x i64> %a
-}
-
-declare <vscale x 2 x i64> @llvm.riscv.vmulhu.mask.nxv2i64.i64(
- <vscale x 2 x i64>,
- <vscale x 2 x i64>,
- i64,
- <vscale x 2 x i1>,
- i32,
- i32);
-
-define <vscale x 2 x i64> @intrinsic_vmulhu_mask_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmulhu_mask_vx_nxv2i64_nxv2i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addi sp, sp, -16
-; CHECK-NEXT: sw a1, 12(sp)
-; CHECK-NEXT: sw a0, 8(sp)
-; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
-; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v12, (a0), zero
-; CHECK-NEXT: vmulhu.vv v8, v10, v12, v0.t
-; CHECK-NEXT: addi sp, sp, 16
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i64> @llvm.riscv.vmulhu.mask.nxv2i64.i64(
- <vscale x 2 x i64> %0,
- <vscale x 2 x i64> %1,
- i64 %2,
- <vscale x 2 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 2 x i64> %a
-}
-
-declare <vscale x 4 x i64> @llvm.riscv.vmulhu.nxv4i64.i64(
- <vscale x 4 x i64>,
- <vscale x 4 x i64>,
- i64,
- i32);
-
-define <vscale x 4 x i64> @intrinsic_vmulhu_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmulhu_vx_nxv4i64_nxv4i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addi sp, sp, -16
-; CHECK-NEXT: sw a1, 12(sp)
-; CHECK-NEXT: sw a0, 8(sp)
-; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
-; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v12, (a0), zero
-; CHECK-NEXT: vmulhu.vv v8, v8, v12
-; CHECK-NEXT: addi sp, sp, 16
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i64> @llvm.riscv.vmulhu.nxv4i64.i64(
- <vscale x 4 x i64> undef,
- <vscale x 4 x i64> %0,
- i64 %1,
- i32 %2)
-
- ret <vscale x 4 x i64> %a
-}
-
-declare <vscale x 4 x i64> @llvm.riscv.vmulhu.mask.nxv4i64.i64(
- <vscale x 4 x i64>,
- <vscale x 4 x i64>,
- i64,
- <vscale x 4 x i1>,
- i32,
- i32);
-
-define <vscale x 4 x i64> @intrinsic_vmulhu_mask_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmulhu_mask_vx_nxv4i64_nxv4i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addi sp, sp, -16
-; CHECK-NEXT: sw a1, 12(sp)
-; CHECK-NEXT: sw a0, 8(sp)
-; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
-; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v16, (a0), zero
-; CHECK-NEXT: vmulhu.vv v8, v12, v16, v0.t
-; CHECK-NEXT: addi sp, sp, 16
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i64> @llvm.riscv.vmulhu.mask.nxv4i64.i64(
- <vscale x 4 x i64> %0,
- <vscale x 4 x i64> %1,
- i64 %2,
- <vscale x 4 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 4 x i64> %a
-}
-
-declare <vscale x 8 x i64> @llvm.riscv.vmulhu.nxv8i64.i64(
- <vscale x 8 x i64>,
- <vscale x 8 x i64>,
- i64,
- i32);
-
-define <vscale x 8 x i64> @intrinsic_vmulhu_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, i64 %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmulhu_vx_nxv8i64_nxv8i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addi sp, sp, -16
-; CHECK-NEXT: sw a1, 12(sp)
-; CHECK-NEXT: sw a0, 8(sp)
-; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, mu
-; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v16, (a0), zero
-; CHECK-NEXT: vmulhu.vv v8, v8, v16
-; CHECK-NEXT: addi sp, sp, 16
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i64> @llvm.riscv.vmulhu.nxv8i64.i64(
- <vscale x 8 x i64> undef,
- <vscale x 8 x i64> %0,
- i64 %1,
- i32 %2)
-
- ret <vscale x 8 x i64> %a
-}
-
-declare <vscale x 8 x i64> @llvm.riscv.vmulhu.mask.nxv8i64.i64(
- <vscale x 8 x i64>,
- <vscale x 8 x i64>,
- i64,
- <vscale x 8 x i1>,
- i32,
- i32);
-
-define <vscale x 8 x i64> @intrinsic_vmulhu_mask_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmulhu_mask_vx_nxv8i64_nxv8i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addi sp, sp, -16
-; CHECK-NEXT: sw a1, 12(sp)
-; CHECK-NEXT: sw a0, 8(sp)
-; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, mu
-; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v24, (a0), zero
-; CHECK-NEXT: vmulhu.vv v8, v16, v24, v0.t
-; CHECK-NEXT: addi sp, sp, 16
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i64> @llvm.riscv.vmulhu.mask.nxv8i64.i64(
- <vscale x 8 x i64> %0,
- <vscale x 8 x i64> %1,
- i64 %2,
- <vscale x 8 x i1> %3,
- i32 %4, i32 1)
-
- ret <vscale x 8 x i64> %a
-}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmulhu-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vmulhu.ll
similarity index 80%
rename from llvm/test/CodeGen/RISCV/rvv/vmulhu-rv64.ll
rename to llvm/test/CodeGen/RISCV/rvv/vmulhu.ll
index b3b7352810971..c7beacecb02f1 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vmulhu-rv64.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vmulhu.ll
@@ -1,13 +1,15 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs \
-; RUN: < %s | FileCheck %s
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v \
+; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,RV32
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v \
+; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,RV64
declare <vscale x 1 x i8> @llvm.riscv.vmulhu.nxv1i8.nxv1i8(
<vscale x 1 x i8>,
<vscale x 1 x i8>,
<vscale x 1 x i8>,
- i64);
+ iXLen);
-define <vscale x 1 x i8> @intrinsic_vmulhu_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2) nounwind {
+define <vscale x 1 x i8> @intrinsic_vmulhu_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmulhu_vv_nxv1i8_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
@@ -18,7 +20,7 @@ entry:
<vscale x 1 x i8> undef,
<vscale x 1 x i8> %0,
<vscale x 1 x i8> %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 1 x i8> %a
}
@@ -28,10 +30,9 @@ declare <vscale x 1 x i8> @llvm.riscv.vmulhu.mask.nxv1i8.nxv1i8(
<vscale x 1 x i8>,
<vscale x 1 x i8>,
<vscale x 1 x i1>,
- i64,
- i64);
+ iXLen, iXLen);
-define <vscale x 1 x i8> @intrinsic_vmulhu_mask_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+define <vscale x 1 x i8> @intrinsic_vmulhu_mask_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmulhu_mask_vv_nxv1i8_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
@@ -43,7 +44,7 @@ entry:
<vscale x 1 x i8> %1,
<vscale x 1 x i8> %2,
<vscale x 1 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 1 x i8> %a
}
@@ -52,9 +53,9 @@ declare <vscale x 2 x i8> @llvm.riscv.vmulhu.nxv2i8.nxv2i8(
<vscale x 2 x i8>,
<vscale x 2 x i8>,
<vscale x 2 x i8>,
- i64);
+ iXLen);
-define <vscale x 2 x i8> @intrinsic_vmulhu_vv_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2) nounwind {
+define <vscale x 2 x i8> @intrinsic_vmulhu_vv_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmulhu_vv_nxv2i8_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
@@ -65,7 +66,7 @@ entry:
<vscale x 2 x i8> undef,
<vscale x 2 x i8> %0,
<vscale x 2 x i8> %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 2 x i8> %a
}
@@ -75,10 +76,9 @@ declare <vscale x 2 x i8> @llvm.riscv.vmulhu.mask.nxv2i8.nxv2i8(
<vscale x 2 x i8>,
<vscale x 2 x i8>,
<vscale x 2 x i1>,
- i64,
- i64);
+ iXLen, iXLen);
-define <vscale x 2 x i8> @intrinsic_vmulhu_mask_vv_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+define <vscale x 2 x i8> @intrinsic_vmulhu_mask_vv_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmulhu_mask_vv_nxv2i8_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
@@ -90,7 +90,7 @@ entry:
<vscale x 2 x i8> %1,
<vscale x 2 x i8> %2,
<vscale x 2 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 2 x i8> %a
}
@@ -99,9 +99,9 @@ declare <vscale x 4 x i8> @llvm.riscv.vmulhu.nxv4i8.nxv4i8(
<vscale x 4 x i8>,
<vscale x 4 x i8>,
<vscale x 4 x i8>,
- i64);
+ iXLen);
-define <vscale x 4 x i8> @intrinsic_vmulhu_vv_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2) nounwind {
+define <vscale x 4 x i8> @intrinsic_vmulhu_vv_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmulhu_vv_nxv4i8_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
@@ -112,7 +112,7 @@ entry:
<vscale x 4 x i8> undef,
<vscale x 4 x i8> %0,
<vscale x 4 x i8> %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 4 x i8> %a
}
@@ -122,10 +122,9 @@ declare <vscale x 4 x i8> @llvm.riscv.vmulhu.mask.nxv4i8.nxv4i8(
<vscale x 4 x i8>,
<vscale x 4 x i8>,
<vscale x 4 x i1>,
- i64,
- i64);
+ iXLen, iXLen);
-define <vscale x 4 x i8> @intrinsic_vmulhu_mask_vv_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+define <vscale x 4 x i8> @intrinsic_vmulhu_mask_vv_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmulhu_mask_vv_nxv4i8_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
@@ -137,7 +136,7 @@ entry:
<vscale x 4 x i8> %1,
<vscale x 4 x i8> %2,
<vscale x 4 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 4 x i8> %a
}
@@ -146,9 +145,9 @@ declare <vscale x 8 x i8> @llvm.riscv.vmulhu.nxv8i8.nxv8i8(
<vscale x 8 x i8>,
<vscale x 8 x i8>,
<vscale x 8 x i8>,
- i64);
+ iXLen);
-define <vscale x 8 x i8> @intrinsic_vmulhu_vv_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2) nounwind {
+define <vscale x 8 x i8> @intrinsic_vmulhu_vv_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmulhu_vv_nxv8i8_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
@@ -159,7 +158,7 @@ entry:
<vscale x 8 x i8> undef,
<vscale x 8 x i8> %0,
<vscale x 8 x i8> %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 8 x i8> %a
}
@@ -169,10 +168,9 @@ declare <vscale x 8 x i8> @llvm.riscv.vmulhu.mask.nxv8i8.nxv8i8(
<vscale x 8 x i8>,
<vscale x 8 x i8>,
<vscale x 8 x i1>,
- i64,
- i64);
+ iXLen, iXLen);
-define <vscale x 8 x i8> @intrinsic_vmulhu_mask_vv_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+define <vscale x 8 x i8> @intrinsic_vmulhu_mask_vv_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmulhu_mask_vv_nxv8i8_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
@@ -184,7 +182,7 @@ entry:
<vscale x 8 x i8> %1,
<vscale x 8 x i8> %2,
<vscale x 8 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 8 x i8> %a
}
@@ -193,9 +191,9 @@ declare <vscale x 16 x i8> @llvm.riscv.vmulhu.nxv16i8.nxv16i8(
<vscale x 16 x i8>,
<vscale x 16 x i8>,
<vscale x 16 x i8>,
- i64);
+ iXLen);
-define <vscale x 16 x i8> @intrinsic_vmulhu_vv_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2) nounwind {
+define <vscale x 16 x i8> @intrinsic_vmulhu_vv_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmulhu_vv_nxv16i8_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
@@ -206,7 +204,7 @@ entry:
<vscale x 16 x i8> undef,
<vscale x 16 x i8> %0,
<vscale x 16 x i8> %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 16 x i8> %a
}
@@ -216,10 +214,9 @@ declare <vscale x 16 x i8> @llvm.riscv.vmulhu.mask.nxv16i8.nxv16i8(
<vscale x 16 x i8>,
<vscale x 16 x i8>,
<vscale x 16 x i1>,
- i64,
- i64);
+ iXLen, iXLen);
-define <vscale x 16 x i8> @intrinsic_vmulhu_mask_vv_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+define <vscale x 16 x i8> @intrinsic_vmulhu_mask_vv_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmulhu_mask_vv_nxv16i8_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
@@ -231,7 +228,7 @@ entry:
<vscale x 16 x i8> %1,
<vscale x 16 x i8> %2,
<vscale x 16 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 16 x i8> %a
}
@@ -240,9 +237,9 @@ declare <vscale x 32 x i8> @llvm.riscv.vmulhu.nxv32i8.nxv32i8(
<vscale x 32 x i8>,
<vscale x 32 x i8>,
<vscale x 32 x i8>,
- i64);
+ iXLen);
-define <vscale x 32 x i8> @intrinsic_vmulhu_vv_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i64 %2) nounwind {
+define <vscale x 32 x i8> @intrinsic_vmulhu_vv_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmulhu_vv_nxv32i8_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
@@ -253,7 +250,7 @@ entry:
<vscale x 32 x i8> undef,
<vscale x 32 x i8> %0,
<vscale x 32 x i8> %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 32 x i8> %a
}
@@ -263,10 +260,9 @@ declare <vscale x 32 x i8> @llvm.riscv.vmulhu.mask.nxv32i8.nxv32i8(
<vscale x 32 x i8>,
<vscale x 32 x i8>,
<vscale x 32 x i1>,
- i64,
- i64);
+ iXLen, iXLen);
-define <vscale x 32 x i8> @intrinsic_vmulhu_mask_vv_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
+define <vscale x 32 x i8> @intrinsic_vmulhu_mask_vv_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmulhu_mask_vv_nxv32i8_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
@@ -278,7 +274,7 @@ entry:
<vscale x 32 x i8> %1,
<vscale x 32 x i8> %2,
<vscale x 32 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 32 x i8> %a
}
@@ -287,9 +283,9 @@ declare <vscale x 64 x i8> @llvm.riscv.vmulhu.nxv64i8.nxv64i8(
<vscale x 64 x i8>,
<vscale x 64 x i8>,
<vscale x 64 x i8>,
- i64);
+ iXLen);
-define <vscale x 64 x i8> @intrinsic_vmulhu_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i64 %2) nounwind {
+define <vscale x 64 x i8> @intrinsic_vmulhu_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmulhu_vv_nxv64i8_nxv64i8_nxv64i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, mu
@@ -300,7 +296,7 @@ entry:
<vscale x 64 x i8> undef,
<vscale x 64 x i8> %0,
<vscale x 64 x i8> %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 64 x i8> %a
}
@@ -310,10 +306,9 @@ declare <vscale x 64 x i8> @llvm.riscv.vmulhu.mask.nxv64i8.nxv64i8(
<vscale x 64 x i8>,
<vscale x 64 x i8>,
<vscale x 64 x i1>,
- i64,
- i64);
+ iXLen, iXLen);
-define <vscale x 64 x i8> @intrinsic_vmulhu_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, i64 %4) nounwind {
+define <vscale x 64 x i8> @intrinsic_vmulhu_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmulhu_mask_vv_nxv64i8_nxv64i8_nxv64i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vl8r.v v24, (a0)
@@ -326,7 +321,7 @@ entry:
<vscale x 64 x i8> %1,
<vscale x 64 x i8> %2,
<vscale x 64 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 64 x i8> %a
}
@@ -335,9 +330,9 @@ declare <vscale x 1 x i16> @llvm.riscv.vmulhu.nxv1i16.nxv1i16(
<vscale x 1 x i16>,
<vscale x 1 x i16>,
<vscale x 1 x i16>,
- i64);
+ iXLen);
-define <vscale x 1 x i16> @intrinsic_vmulhu_vv_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i64 %2) nounwind {
+define <vscale x 1 x i16> @intrinsic_vmulhu_vv_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmulhu_vv_nxv1i16_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
@@ -348,7 +343,7 @@ entry:
<vscale x 1 x i16> undef,
<vscale x 1 x i16> %0,
<vscale x 1 x i16> %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 1 x i16> %a
}
@@ -358,10 +353,9 @@ declare <vscale x 1 x i16> @llvm.riscv.vmulhu.mask.nxv1i16.nxv1i16(
<vscale x 1 x i16>,
<vscale x 1 x i16>,
<vscale x 1 x i1>,
- i64,
- i64);
+ iXLen, iXLen);
-define <vscale x 1 x i16> @intrinsic_vmulhu_mask_vv_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+define <vscale x 1 x i16> @intrinsic_vmulhu_mask_vv_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmulhu_mask_vv_nxv1i16_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
@@ -373,7 +367,7 @@ entry:
<vscale x 1 x i16> %1,
<vscale x 1 x i16> %2,
<vscale x 1 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 1 x i16> %a
}
@@ -382,9 +376,9 @@ declare <vscale x 2 x i16> @llvm.riscv.vmulhu.nxv2i16.nxv2i16(
<vscale x 2 x i16>,
<vscale x 2 x i16>,
<vscale x 2 x i16>,
- i64);
+ iXLen);
-define <vscale x 2 x i16> @intrinsic_vmulhu_vv_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i64 %2) nounwind {
+define <vscale x 2 x i16> @intrinsic_vmulhu_vv_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmulhu_vv_nxv2i16_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
@@ -395,7 +389,7 @@ entry:
<vscale x 2 x i16> undef,
<vscale x 2 x i16> %0,
<vscale x 2 x i16> %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 2 x i16> %a
}
@@ -405,10 +399,9 @@ declare <vscale x 2 x i16> @llvm.riscv.vmulhu.mask.nxv2i16.nxv2i16(
<vscale x 2 x i16>,
<vscale x 2 x i16>,
<vscale x 2 x i1>,
- i64,
- i64);
+ iXLen, iXLen);
-define <vscale x 2 x i16> @intrinsic_vmulhu_mask_vv_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+define <vscale x 2 x i16> @intrinsic_vmulhu_mask_vv_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmulhu_mask_vv_nxv2i16_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
@@ -420,7 +413,7 @@ entry:
<vscale x 2 x i16> %1,
<vscale x 2 x i16> %2,
<vscale x 2 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 2 x i16> %a
}
@@ -429,9 +422,9 @@ declare <vscale x 4 x i16> @llvm.riscv.vmulhu.nxv4i16.nxv4i16(
<vscale x 4 x i16>,
<vscale x 4 x i16>,
<vscale x 4 x i16>,
- i64);
+ iXLen);
-define <vscale x 4 x i16> @intrinsic_vmulhu_vv_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i64 %2) nounwind {
+define <vscale x 4 x i16> @intrinsic_vmulhu_vv_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmulhu_vv_nxv4i16_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
@@ -442,7 +435,7 @@ entry:
<vscale x 4 x i16> undef,
<vscale x 4 x i16> %0,
<vscale x 4 x i16> %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 4 x i16> %a
}
@@ -452,10 +445,9 @@ declare <vscale x 4 x i16> @llvm.riscv.vmulhu.mask.nxv4i16.nxv4i16(
<vscale x 4 x i16>,
<vscale x 4 x i16>,
<vscale x 4 x i1>,
- i64,
- i64);
+ iXLen, iXLen);
-define <vscale x 4 x i16> @intrinsic_vmulhu_mask_vv_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+define <vscale x 4 x i16> @intrinsic_vmulhu_mask_vv_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmulhu_mask_vv_nxv4i16_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
@@ -467,7 +459,7 @@ entry:
<vscale x 4 x i16> %1,
<vscale x 4 x i16> %2,
<vscale x 4 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 4 x i16> %a
}
@@ -476,9 +468,9 @@ declare <vscale x 8 x i16> @llvm.riscv.vmulhu.nxv8i16.nxv8i16(
<vscale x 8 x i16>,
<vscale x 8 x i16>,
<vscale x 8 x i16>,
- i64);
+ iXLen);
-define <vscale x 8 x i16> @intrinsic_vmulhu_vv_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i64 %2) nounwind {
+define <vscale x 8 x i16> @intrinsic_vmulhu_vv_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmulhu_vv_nxv8i16_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
@@ -489,7 +481,7 @@ entry:
<vscale x 8 x i16> undef,
<vscale x 8 x i16> %0,
<vscale x 8 x i16> %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 8 x i16> %a
}
@@ -499,10 +491,9 @@ declare <vscale x 8 x i16> @llvm.riscv.vmulhu.mask.nxv8i16.nxv8i16(
<vscale x 8 x i16>,
<vscale x 8 x i16>,
<vscale x 8 x i1>,
- i64,
- i64);
+ iXLen, iXLen);
-define <vscale x 8 x i16> @intrinsic_vmulhu_mask_vv_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+define <vscale x 8 x i16> @intrinsic_vmulhu_mask_vv_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmulhu_mask_vv_nxv8i16_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
@@ -514,7 +505,7 @@ entry:
<vscale x 8 x i16> %1,
<vscale x 8 x i16> %2,
<vscale x 8 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 8 x i16> %a
}
@@ -523,9 +514,9 @@ declare <vscale x 16 x i16> @llvm.riscv.vmulhu.nxv16i16.nxv16i16(
<vscale x 16 x i16>,
<vscale x 16 x i16>,
<vscale x 16 x i16>,
- i64);
+ iXLen);
-define <vscale x 16 x i16> @intrinsic_vmulhu_vv_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i64 %2) nounwind {
+define <vscale x 16 x i16> @intrinsic_vmulhu_vv_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmulhu_vv_nxv16i16_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
@@ -536,7 +527,7 @@ entry:
<vscale x 16 x i16> undef,
<vscale x 16 x i16> %0,
<vscale x 16 x i16> %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 16 x i16> %a
}
@@ -546,10 +537,9 @@ declare <vscale x 16 x i16> @llvm.riscv.vmulhu.mask.nxv16i16.nxv16i16(
<vscale x 16 x i16>,
<vscale x 16 x i16>,
<vscale x 16 x i1>,
- i64,
- i64);
+ iXLen, iXLen);
-define <vscale x 16 x i16> @intrinsic_vmulhu_mask_vv_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+define <vscale x 16 x i16> @intrinsic_vmulhu_mask_vv_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmulhu_mask_vv_nxv16i16_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
@@ -561,7 +551,7 @@ entry:
<vscale x 16 x i16> %1,
<vscale x 16 x i16> %2,
<vscale x 16 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 16 x i16> %a
}
@@ -570,9 +560,9 @@ declare <vscale x 32 x i16> @llvm.riscv.vmulhu.nxv32i16.nxv32i16(
<vscale x 32 x i16>,
<vscale x 32 x i16>,
<vscale x 32 x i16>,
- i64);
+ iXLen);
-define <vscale x 32 x i16> @intrinsic_vmulhu_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, i64 %2) nounwind {
+define <vscale x 32 x i16> @intrinsic_vmulhu_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmulhu_vv_nxv32i16_nxv32i16_nxv32i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, mu
@@ -583,7 +573,7 @@ entry:
<vscale x 32 x i16> undef,
<vscale x 32 x i16> %0,
<vscale x 32 x i16> %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 32 x i16> %a
}
@@ -593,10 +583,9 @@ declare <vscale x 32 x i16> @llvm.riscv.vmulhu.mask.nxv32i16.nxv32i16(
<vscale x 32 x i16>,
<vscale x 32 x i16>,
<vscale x 32 x i1>,
- i64,
- i64);
+ iXLen, iXLen);
-define <vscale x 32 x i16> @intrinsic_vmulhu_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
+define <vscale x 32 x i16> @intrinsic_vmulhu_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmulhu_mask_vv_nxv32i16_nxv32i16_nxv32i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vl8re16.v v24, (a0)
@@ -609,7 +598,7 @@ entry:
<vscale x 32 x i16> %1,
<vscale x 32 x i16> %2,
<vscale x 32 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 32 x i16> %a
}
@@ -618,9 +607,9 @@ declare <vscale x 1 x i32> @llvm.riscv.vmulhu.nxv1i32.nxv1i32(
<vscale x 1 x i32>,
<vscale x 1 x i32>,
<vscale x 1 x i32>,
- i64);
+ iXLen);
-define <vscale x 1 x i32> @intrinsic_vmulhu_vv_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2) nounwind {
+define <vscale x 1 x i32> @intrinsic_vmulhu_vv_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmulhu_vv_nxv1i32_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
@@ -631,7 +620,7 @@ entry:
<vscale x 1 x i32> undef,
<vscale x 1 x i32> %0,
<vscale x 1 x i32> %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 1 x i32> %a
}
@@ -641,10 +630,9 @@ declare <vscale x 1 x i32> @llvm.riscv.vmulhu.mask.nxv1i32.nxv1i32(
<vscale x 1 x i32>,
<vscale x 1 x i32>,
<vscale x 1 x i1>,
- i64,
- i64);
+ iXLen, iXLen);
-define <vscale x 1 x i32> @intrinsic_vmulhu_mask_vv_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+define <vscale x 1 x i32> @intrinsic_vmulhu_mask_vv_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmulhu_mask_vv_nxv1i32_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
@@ -656,7 +644,7 @@ entry:
<vscale x 1 x i32> %1,
<vscale x 1 x i32> %2,
<vscale x 1 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 1 x i32> %a
}
@@ -665,9 +653,9 @@ declare <vscale x 2 x i32> @llvm.riscv.vmulhu.nxv2i32.nxv2i32(
<vscale x 2 x i32>,
<vscale x 2 x i32>,
<vscale x 2 x i32>,
- i64);
+ iXLen);
-define <vscale x 2 x i32> @intrinsic_vmulhu_vv_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2) nounwind {
+define <vscale x 2 x i32> @intrinsic_vmulhu_vv_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmulhu_vv_nxv2i32_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
@@ -678,7 +666,7 @@ entry:
<vscale x 2 x i32> undef,
<vscale x 2 x i32> %0,
<vscale x 2 x i32> %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 2 x i32> %a
}
@@ -688,10 +676,9 @@ declare <vscale x 2 x i32> @llvm.riscv.vmulhu.mask.nxv2i32.nxv2i32(
<vscale x 2 x i32>,
<vscale x 2 x i32>,
<vscale x 2 x i1>,
- i64,
- i64);
+ iXLen, iXLen);
-define <vscale x 2 x i32> @intrinsic_vmulhu_mask_vv_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+define <vscale x 2 x i32> @intrinsic_vmulhu_mask_vv_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmulhu_mask_vv_nxv2i32_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
@@ -703,7 +690,7 @@ entry:
<vscale x 2 x i32> %1,
<vscale x 2 x i32> %2,
<vscale x 2 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 2 x i32> %a
}
@@ -712,9 +699,9 @@ declare <vscale x 4 x i32> @llvm.riscv.vmulhu.nxv4i32.nxv4i32(
<vscale x 4 x i32>,
<vscale x 4 x i32>,
<vscale x 4 x i32>,
- i64);
+ iXLen);
-define <vscale x 4 x i32> @intrinsic_vmulhu_vv_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i64 %2) nounwind {
+define <vscale x 4 x i32> @intrinsic_vmulhu_vv_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmulhu_vv_nxv4i32_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
@@ -725,7 +712,7 @@ entry:
<vscale x 4 x i32> undef,
<vscale x 4 x i32> %0,
<vscale x 4 x i32> %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 4 x i32> %a
}
@@ -735,10 +722,9 @@ declare <vscale x 4 x i32> @llvm.riscv.vmulhu.mask.nxv4i32.nxv4i32(
<vscale x 4 x i32>,
<vscale x 4 x i32>,
<vscale x 4 x i1>,
- i64,
- i64);
+ iXLen, iXLen);
-define <vscale x 4 x i32> @intrinsic_vmulhu_mask_vv_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+define <vscale x 4 x i32> @intrinsic_vmulhu_mask_vv_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmulhu_mask_vv_nxv4i32_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
@@ -750,7 +736,7 @@ entry:
<vscale x 4 x i32> %1,
<vscale x 4 x i32> %2,
<vscale x 4 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 4 x i32> %a
}
@@ -759,9 +745,9 @@ declare <vscale x 8 x i32> @llvm.riscv.vmulhu.nxv8i32.nxv8i32(
<vscale x 8 x i32>,
<vscale x 8 x i32>,
<vscale x 8 x i32>,
- i64);
+ iXLen);
-define <vscale x 8 x i32> @intrinsic_vmulhu_vv_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i64 %2) nounwind {
+define <vscale x 8 x i32> @intrinsic_vmulhu_vv_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmulhu_vv_nxv8i32_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
@@ -772,7 +758,7 @@ entry:
<vscale x 8 x i32> undef,
<vscale x 8 x i32> %0,
<vscale x 8 x i32> %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 8 x i32> %a
}
@@ -782,10 +768,9 @@ declare <vscale x 8 x i32> @llvm.riscv.vmulhu.mask.nxv8i32.nxv8i32(
<vscale x 8 x i32>,
<vscale x 8 x i32>,
<vscale x 8 x i1>,
- i64,
- i64);
+ iXLen, iXLen);
-define <vscale x 8 x i32> @intrinsic_vmulhu_mask_vv_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+define <vscale x 8 x i32> @intrinsic_vmulhu_mask_vv_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmulhu_mask_vv_nxv8i32_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
@@ -797,7 +782,7 @@ entry:
<vscale x 8 x i32> %1,
<vscale x 8 x i32> %2,
<vscale x 8 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 8 x i32> %a
}
@@ -806,9 +791,9 @@ declare <vscale x 16 x i32> @llvm.riscv.vmulhu.nxv16i32.nxv16i32(
<vscale x 16 x i32>,
<vscale x 16 x i32>,
<vscale x 16 x i32>,
- i64);
+ iXLen);
-define <vscale x 16 x i32> @intrinsic_vmulhu_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i64 %2) nounwind {
+define <vscale x 16 x i32> @intrinsic_vmulhu_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmulhu_vv_nxv16i32_nxv16i32_nxv16i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu
@@ -819,7 +804,7 @@ entry:
<vscale x 16 x i32> undef,
<vscale x 16 x i32> %0,
<vscale x 16 x i32> %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 16 x i32> %a
}
@@ -829,10 +814,9 @@ declare <vscale x 16 x i32> @llvm.riscv.vmulhu.mask.nxv16i32.nxv16i32(
<vscale x 16 x i32>,
<vscale x 16 x i32>,
<vscale x 16 x i1>,
- i64,
- i64);
+ iXLen, iXLen);
-define <vscale x 16 x i32> @intrinsic_vmulhu_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+define <vscale x 16 x i32> @intrinsic_vmulhu_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmulhu_mask_vv_nxv16i32_nxv16i32_nxv16i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vl8re32.v v24, (a0)
@@ -845,7 +829,7 @@ entry:
<vscale x 16 x i32> %1,
<vscale x 16 x i32> %2,
<vscale x 16 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 16 x i32> %a
}
@@ -854,9 +838,9 @@ declare <vscale x 1 x i64> @llvm.riscv.vmulhu.nxv1i64.nxv1i64(
<vscale x 1 x i64>,
<vscale x 1 x i64>,
<vscale x 1 x i64>,
- i64);
+ iXLen);
-define <vscale x 1 x i64> @intrinsic_vmulhu_vv_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2) nounwind {
+define <vscale x 1 x i64> @intrinsic_vmulhu_vv_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmulhu_vv_nxv1i64_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
@@ -867,7 +851,7 @@ entry:
<vscale x 1 x i64> undef,
<vscale x 1 x i64> %0,
<vscale x 1 x i64> %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 1 x i64> %a
}
@@ -877,10 +861,9 @@ declare <vscale x 1 x i64> @llvm.riscv.vmulhu.mask.nxv1i64.nxv1i64(
<vscale x 1 x i64>,
<vscale x 1 x i64>,
<vscale x 1 x i1>,
- i64,
- i64);
+ iXLen, iXLen);
-define <vscale x 1 x i64> @intrinsic_vmulhu_mask_vv_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+define <vscale x 1 x i64> @intrinsic_vmulhu_mask_vv_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmulhu_mask_vv_nxv1i64_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
@@ -892,7 +875,7 @@ entry:
<vscale x 1 x i64> %1,
<vscale x 1 x i64> %2,
<vscale x 1 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 1 x i64> %a
}
@@ -901,9 +884,9 @@ declare <vscale x 2 x i64> @llvm.riscv.vmulhu.nxv2i64.nxv2i64(
<vscale x 2 x i64>,
<vscale x 2 x i64>,
<vscale x 2 x i64>,
- i64);
+ iXLen);
-define <vscale x 2 x i64> @intrinsic_vmulhu_vv_nxv2i64_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2) nounwind {
+define <vscale x 2 x i64> @intrinsic_vmulhu_vv_nxv2i64_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmulhu_vv_nxv2i64_nxv2i64_nxv2i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
@@ -914,7 +897,7 @@ entry:
<vscale x 2 x i64> undef,
<vscale x 2 x i64> %0,
<vscale x 2 x i64> %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 2 x i64> %a
}
@@ -924,10 +907,9 @@ declare <vscale x 2 x i64> @llvm.riscv.vmulhu.mask.nxv2i64.nxv2i64(
<vscale x 2 x i64>,
<vscale x 2 x i64>,
<vscale x 2 x i1>,
- i64,
- i64);
+ iXLen, iXLen);
-define <vscale x 2 x i64> @intrinsic_vmulhu_mask_vv_nxv2i64_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+define <vscale x 2 x i64> @intrinsic_vmulhu_mask_vv_nxv2i64_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmulhu_mask_vv_nxv2i64_nxv2i64_nxv2i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
@@ -939,7 +921,7 @@ entry:
<vscale x 2 x i64> %1,
<vscale x 2 x i64> %2,
<vscale x 2 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 2 x i64> %a
}
@@ -948,9 +930,9 @@ declare <vscale x 4 x i64> @llvm.riscv.vmulhu.nxv4i64.nxv4i64(
<vscale x 4 x i64>,
<vscale x 4 x i64>,
<vscale x 4 x i64>,
- i64);
+ iXLen);
-define <vscale x 4 x i64> @intrinsic_vmulhu_vv_nxv4i64_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2) nounwind {
+define <vscale x 4 x i64> @intrinsic_vmulhu_vv_nxv4i64_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmulhu_vv_nxv4i64_nxv4i64_nxv4i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
@@ -961,7 +943,7 @@ entry:
<vscale x 4 x i64> undef,
<vscale x 4 x i64> %0,
<vscale x 4 x i64> %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 4 x i64> %a
}
@@ -971,10 +953,9 @@ declare <vscale x 4 x i64> @llvm.riscv.vmulhu.mask.nxv4i64.nxv4i64(
<vscale x 4 x i64>,
<vscale x 4 x i64>,
<vscale x 4 x i1>,
- i64,
- i64);
+ iXLen, iXLen);
-define <vscale x 4 x i64> @intrinsic_vmulhu_mask_vv_nxv4i64_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+define <vscale x 4 x i64> @intrinsic_vmulhu_mask_vv_nxv4i64_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmulhu_mask_vv_nxv4i64_nxv4i64_nxv4i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
@@ -986,7 +967,7 @@ entry:
<vscale x 4 x i64> %1,
<vscale x 4 x i64> %2,
<vscale x 4 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 4 x i64> %a
}
@@ -995,9 +976,9 @@ declare <vscale x 8 x i64> @llvm.riscv.vmulhu.nxv8i64.nxv8i64(
<vscale x 8 x i64>,
<vscale x 8 x i64>,
<vscale x 8 x i64>,
- i64);
+ iXLen);
-define <vscale x 8 x i64> @intrinsic_vmulhu_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2) nounwind {
+define <vscale x 8 x i64> @intrinsic_vmulhu_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmulhu_vv_nxv8i64_nxv8i64_nxv8i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu
@@ -1008,7 +989,7 @@ entry:
<vscale x 8 x i64> undef,
<vscale x 8 x i64> %0,
<vscale x 8 x i64> %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 8 x i64> %a
}
@@ -1018,10 +999,9 @@ declare <vscale x 8 x i64> @llvm.riscv.vmulhu.mask.nxv8i64.nxv8i64(
<vscale x 8 x i64>,
<vscale x 8 x i64>,
<vscale x 8 x i1>,
- i64,
- i64);
+ iXLen, iXLen);
-define <vscale x 8 x i64> @intrinsic_vmulhu_mask_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+define <vscale x 8 x i64> @intrinsic_vmulhu_mask_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmulhu_mask_vv_nxv8i64_nxv8i64_nxv8i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vl8re64.v v24, (a0)
@@ -1034,7 +1014,7 @@ entry:
<vscale x 8 x i64> %1,
<vscale x 8 x i64> %2,
<vscale x 8 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 8 x i64> %a
}
@@ -1043,9 +1023,9 @@ declare <vscale x 1 x i8> @llvm.riscv.vmulhu.nxv1i8.i8(
<vscale x 1 x i8>,
<vscale x 1 x i8>,
i8,
- i64);
+ iXLen);
-define <vscale x 1 x i8> @intrinsic_vmulhu_vx_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, i8 %1, i64 %2) nounwind {
+define <vscale x 1 x i8> @intrinsic_vmulhu_vx_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, i8 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmulhu_vx_nxv1i8_nxv1i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
@@ -1056,7 +1036,7 @@ entry:
<vscale x 1 x i8> undef,
<vscale x 1 x i8> %0,
i8 %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 1 x i8> %a
}
@@ -1066,10 +1046,9 @@ declare <vscale x 1 x i8> @llvm.riscv.vmulhu.mask.nxv1i8.i8(
<vscale x 1 x i8>,
i8,
<vscale x 1 x i1>,
- i64,
- i64);
+ iXLen, iXLen);
-define <vscale x 1 x i8> @intrinsic_vmulhu_mask_vx_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+define <vscale x 1 x i8> @intrinsic_vmulhu_mask_vx_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmulhu_mask_vx_nxv1i8_nxv1i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
@@ -1081,7 +1060,7 @@ entry:
<vscale x 1 x i8> %1,
i8 %2,
<vscale x 1 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 1 x i8> %a
}
@@ -1090,9 +1069,9 @@ declare <vscale x 2 x i8> @llvm.riscv.vmulhu.nxv2i8.i8(
<vscale x 2 x i8>,
<vscale x 2 x i8>,
i8,
- i64);
+ iXLen);
-define <vscale x 2 x i8> @intrinsic_vmulhu_vx_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, i8 %1, i64 %2) nounwind {
+define <vscale x 2 x i8> @intrinsic_vmulhu_vx_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, i8 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmulhu_vx_nxv2i8_nxv2i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
@@ -1103,7 +1082,7 @@ entry:
<vscale x 2 x i8> undef,
<vscale x 2 x i8> %0,
i8 %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 2 x i8> %a
}
@@ -1113,10 +1092,9 @@ declare <vscale x 2 x i8> @llvm.riscv.vmulhu.mask.nxv2i8.i8(
<vscale x 2 x i8>,
i8,
<vscale x 2 x i1>,
- i64,
- i64);
+ iXLen, iXLen);
-define <vscale x 2 x i8> @intrinsic_vmulhu_mask_vx_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+define <vscale x 2 x i8> @intrinsic_vmulhu_mask_vx_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmulhu_mask_vx_nxv2i8_nxv2i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
@@ -1128,7 +1106,7 @@ entry:
<vscale x 2 x i8> %1,
i8 %2,
<vscale x 2 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 2 x i8> %a
}
@@ -1137,9 +1115,9 @@ declare <vscale x 4 x i8> @llvm.riscv.vmulhu.nxv4i8.i8(
<vscale x 4 x i8>,
<vscale x 4 x i8>,
i8,
- i64);
+ iXLen);
-define <vscale x 4 x i8> @intrinsic_vmulhu_vx_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, i8 %1, i64 %2) nounwind {
+define <vscale x 4 x i8> @intrinsic_vmulhu_vx_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, i8 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmulhu_vx_nxv4i8_nxv4i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
@@ -1150,7 +1128,7 @@ entry:
<vscale x 4 x i8> undef,
<vscale x 4 x i8> %0,
i8 %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 4 x i8> %a
}
@@ -1160,10 +1138,9 @@ declare <vscale x 4 x i8> @llvm.riscv.vmulhu.mask.nxv4i8.i8(
<vscale x 4 x i8>,
i8,
<vscale x 4 x i1>,
- i64,
- i64);
+ iXLen, iXLen);
-define <vscale x 4 x i8> @intrinsic_vmulhu_mask_vx_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+define <vscale x 4 x i8> @intrinsic_vmulhu_mask_vx_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmulhu_mask_vx_nxv4i8_nxv4i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
@@ -1175,7 +1152,7 @@ entry:
<vscale x 4 x i8> %1,
i8 %2,
<vscale x 4 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 4 x i8> %a
}
@@ -1184,9 +1161,9 @@ declare <vscale x 8 x i8> @llvm.riscv.vmulhu.nxv8i8.i8(
<vscale x 8 x i8>,
<vscale x 8 x i8>,
i8,
- i64);
+ iXLen);
-define <vscale x 8 x i8> @intrinsic_vmulhu_vx_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, i8 %1, i64 %2) nounwind {
+define <vscale x 8 x i8> @intrinsic_vmulhu_vx_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, i8 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmulhu_vx_nxv8i8_nxv8i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
@@ -1197,7 +1174,7 @@ entry:
<vscale x 8 x i8> undef,
<vscale x 8 x i8> %0,
i8 %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 8 x i8> %a
}
@@ -1207,10 +1184,9 @@ declare <vscale x 8 x i8> @llvm.riscv.vmulhu.mask.nxv8i8.i8(
<vscale x 8 x i8>,
i8,
<vscale x 8 x i1>,
- i64,
- i64);
+ iXLen, iXLen);
-define <vscale x 8 x i8> @intrinsic_vmulhu_mask_vx_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+define <vscale x 8 x i8> @intrinsic_vmulhu_mask_vx_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmulhu_mask_vx_nxv8i8_nxv8i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
@@ -1222,7 +1198,7 @@ entry:
<vscale x 8 x i8> %1,
i8 %2,
<vscale x 8 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 8 x i8> %a
}
@@ -1231,9 +1207,9 @@ declare <vscale x 16 x i8> @llvm.riscv.vmulhu.nxv16i8.i8(
<vscale x 16 x i8>,
<vscale x 16 x i8>,
i8,
- i64);
+ iXLen);
-define <vscale x 16 x i8> @intrinsic_vmulhu_vx_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, i8 %1, i64 %2) nounwind {
+define <vscale x 16 x i8> @intrinsic_vmulhu_vx_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, i8 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmulhu_vx_nxv16i8_nxv16i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
@@ -1244,7 +1220,7 @@ entry:
<vscale x 16 x i8> undef,
<vscale x 16 x i8> %0,
i8 %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 16 x i8> %a
}
@@ -1254,10 +1230,9 @@ declare <vscale x 16 x i8> @llvm.riscv.vmulhu.mask.nxv16i8.i8(
<vscale x 16 x i8>,
i8,
<vscale x 16 x i1>,
- i64,
- i64);
+ iXLen, iXLen);
-define <vscale x 16 x i8> @intrinsic_vmulhu_mask_vx_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+define <vscale x 16 x i8> @intrinsic_vmulhu_mask_vx_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmulhu_mask_vx_nxv16i8_nxv16i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
@@ -1269,7 +1244,7 @@ entry:
<vscale x 16 x i8> %1,
i8 %2,
<vscale x 16 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 16 x i8> %a
}
@@ -1278,9 +1253,9 @@ declare <vscale x 32 x i8> @llvm.riscv.vmulhu.nxv32i8.i8(
<vscale x 32 x i8>,
<vscale x 32 x i8>,
i8,
- i64);
+ iXLen);
-define <vscale x 32 x i8> @intrinsic_vmulhu_vx_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, i8 %1, i64 %2) nounwind {
+define <vscale x 32 x i8> @intrinsic_vmulhu_vx_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, i8 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmulhu_vx_nxv32i8_nxv32i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
@@ -1291,7 +1266,7 @@ entry:
<vscale x 32 x i8> undef,
<vscale x 32 x i8> %0,
i8 %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 32 x i8> %a
}
@@ -1301,10 +1276,9 @@ declare <vscale x 32 x i8> @llvm.riscv.vmulhu.mask.nxv32i8.i8(
<vscale x 32 x i8>,
i8,
<vscale x 32 x i1>,
- i64,
- i64);
+ iXLen, iXLen);
-define <vscale x 32 x i8> @intrinsic_vmulhu_mask_vx_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
+define <vscale x 32 x i8> @intrinsic_vmulhu_mask_vx_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmulhu_mask_vx_nxv32i8_nxv32i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
@@ -1316,7 +1290,7 @@ entry:
<vscale x 32 x i8> %1,
i8 %2,
<vscale x 32 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 32 x i8> %a
}
@@ -1325,9 +1299,9 @@ declare <vscale x 64 x i8> @llvm.riscv.vmulhu.nxv64i8.i8(
<vscale x 64 x i8>,
<vscale x 64 x i8>,
i8,
- i64);
+ iXLen);
-define <vscale x 64 x i8> @intrinsic_vmulhu_vx_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, i8 %1, i64 %2) nounwind {
+define <vscale x 64 x i8> @intrinsic_vmulhu_vx_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, i8 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmulhu_vx_nxv64i8_nxv64i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu
@@ -1338,7 +1312,7 @@ entry:
<vscale x 64 x i8> undef,
<vscale x 64 x i8> %0,
i8 %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 64 x i8> %a
}
@@ -1348,10 +1322,9 @@ declare <vscale x 64 x i8> @llvm.riscv.vmulhu.mask.nxv64i8.i8(
<vscale x 64 x i8>,
i8,
<vscale x 64 x i1>,
- i64,
- i64);
+ iXLen, iXLen);
-define <vscale x 64 x i8> @intrinsic_vmulhu_mask_vx_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i8 %2, <vscale x 64 x i1> %3, i64 %4) nounwind {
+define <vscale x 64 x i8> @intrinsic_vmulhu_mask_vx_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i8 %2, <vscale x 64 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmulhu_mask_vx_nxv64i8_nxv64i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu
@@ -1363,7 +1336,7 @@ entry:
<vscale x 64 x i8> %1,
i8 %2,
<vscale x 64 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 64 x i8> %a
}
@@ -1372,9 +1345,9 @@ declare <vscale x 1 x i16> @llvm.riscv.vmulhu.nxv1i16.i16(
<vscale x 1 x i16>,
<vscale x 1 x i16>,
i16,
- i64);
+ iXLen);
-define <vscale x 1 x i16> @intrinsic_vmulhu_vx_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, i16 %1, i64 %2) nounwind {
+define <vscale x 1 x i16> @intrinsic_vmulhu_vx_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, i16 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmulhu_vx_nxv1i16_nxv1i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
@@ -1385,7 +1358,7 @@ entry:
<vscale x 1 x i16> undef,
<vscale x 1 x i16> %0,
i16 %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 1 x i16> %a
}
@@ -1395,10 +1368,9 @@ declare <vscale x 1 x i16> @llvm.riscv.vmulhu.mask.nxv1i16.i16(
<vscale x 1 x i16>,
i16,
<vscale x 1 x i1>,
- i64,
- i64);
+ iXLen, iXLen);
-define <vscale x 1 x i16> @intrinsic_vmulhu_mask_vx_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+define <vscale x 1 x i16> @intrinsic_vmulhu_mask_vx_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmulhu_mask_vx_nxv1i16_nxv1i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
@@ -1410,7 +1382,7 @@ entry:
<vscale x 1 x i16> %1,
i16 %2,
<vscale x 1 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 1 x i16> %a
}
@@ -1419,9 +1391,9 @@ declare <vscale x 2 x i16> @llvm.riscv.vmulhu.nxv2i16.i16(
<vscale x 2 x i16>,
<vscale x 2 x i16>,
i16,
- i64);
+ iXLen);
-define <vscale x 2 x i16> @intrinsic_vmulhu_vx_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, i16 %1, i64 %2) nounwind {
+define <vscale x 2 x i16> @intrinsic_vmulhu_vx_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, i16 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmulhu_vx_nxv2i16_nxv2i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
@@ -1432,7 +1404,7 @@ entry:
<vscale x 2 x i16> undef,
<vscale x 2 x i16> %0,
i16 %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 2 x i16> %a
}
@@ -1442,10 +1414,9 @@ declare <vscale x 2 x i16> @llvm.riscv.vmulhu.mask.nxv2i16.i16(
<vscale x 2 x i16>,
i16,
<vscale x 2 x i1>,
- i64,
- i64);
+ iXLen, iXLen);
-define <vscale x 2 x i16> @intrinsic_vmulhu_mask_vx_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+define <vscale x 2 x i16> @intrinsic_vmulhu_mask_vx_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmulhu_mask_vx_nxv2i16_nxv2i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
@@ -1457,7 +1428,7 @@ entry:
<vscale x 2 x i16> %1,
i16 %2,
<vscale x 2 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 2 x i16> %a
}
@@ -1466,9 +1437,9 @@ declare <vscale x 4 x i16> @llvm.riscv.vmulhu.nxv4i16.i16(
<vscale x 4 x i16>,
<vscale x 4 x i16>,
i16,
- i64);
+ iXLen);
-define <vscale x 4 x i16> @intrinsic_vmulhu_vx_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, i16 %1, i64 %2) nounwind {
+define <vscale x 4 x i16> @intrinsic_vmulhu_vx_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, i16 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmulhu_vx_nxv4i16_nxv4i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
@@ -1479,7 +1450,7 @@ entry:
<vscale x 4 x i16> undef,
<vscale x 4 x i16> %0,
i16 %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 4 x i16> %a
}
@@ -1489,10 +1460,9 @@ declare <vscale x 4 x i16> @llvm.riscv.vmulhu.mask.nxv4i16.i16(
<vscale x 4 x i16>,
i16,
<vscale x 4 x i1>,
- i64,
- i64);
+ iXLen, iXLen);
-define <vscale x 4 x i16> @intrinsic_vmulhu_mask_vx_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+define <vscale x 4 x i16> @intrinsic_vmulhu_mask_vx_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmulhu_mask_vx_nxv4i16_nxv4i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
@@ -1504,7 +1474,7 @@ entry:
<vscale x 4 x i16> %1,
i16 %2,
<vscale x 4 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 4 x i16> %a
}
@@ -1513,9 +1483,9 @@ declare <vscale x 8 x i16> @llvm.riscv.vmulhu.nxv8i16.i16(
<vscale x 8 x i16>,
<vscale x 8 x i16>,
i16,
- i64);
+ iXLen);
-define <vscale x 8 x i16> @intrinsic_vmulhu_vx_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, i16 %1, i64 %2) nounwind {
+define <vscale x 8 x i16> @intrinsic_vmulhu_vx_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, i16 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmulhu_vx_nxv8i16_nxv8i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
@@ -1526,7 +1496,7 @@ entry:
<vscale x 8 x i16> undef,
<vscale x 8 x i16> %0,
i16 %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 8 x i16> %a
}
@@ -1536,10 +1506,9 @@ declare <vscale x 8 x i16> @llvm.riscv.vmulhu.mask.nxv8i16.i16(
<vscale x 8 x i16>,
i16,
<vscale x 8 x i1>,
- i64,
- i64);
+ iXLen, iXLen);
-define <vscale x 8 x i16> @intrinsic_vmulhu_mask_vx_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+define <vscale x 8 x i16> @intrinsic_vmulhu_mask_vx_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmulhu_mask_vx_nxv8i16_nxv8i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
@@ -1551,7 +1520,7 @@ entry:
<vscale x 8 x i16> %1,
i16 %2,
<vscale x 8 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 8 x i16> %a
}
@@ -1560,9 +1529,9 @@ declare <vscale x 16 x i16> @llvm.riscv.vmulhu.nxv16i16.i16(
<vscale x 16 x i16>,
<vscale x 16 x i16>,
i16,
- i64);
+ iXLen);
-define <vscale x 16 x i16> @intrinsic_vmulhu_vx_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, i16 %1, i64 %2) nounwind {
+define <vscale x 16 x i16> @intrinsic_vmulhu_vx_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, i16 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmulhu_vx_nxv16i16_nxv16i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
@@ -1573,7 +1542,7 @@ entry:
<vscale x 16 x i16> undef,
<vscale x 16 x i16> %0,
i16 %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 16 x i16> %a
}
@@ -1583,10 +1552,9 @@ declare <vscale x 16 x i16> @llvm.riscv.vmulhu.mask.nxv16i16.i16(
<vscale x 16 x i16>,
i16,
<vscale x 16 x i1>,
- i64,
- i64);
+ iXLen, iXLen);
-define <vscale x 16 x i16> @intrinsic_vmulhu_mask_vx_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+define <vscale x 16 x i16> @intrinsic_vmulhu_mask_vx_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmulhu_mask_vx_nxv16i16_nxv16i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
@@ -1598,7 +1566,7 @@ entry:
<vscale x 16 x i16> %1,
i16 %2,
<vscale x 16 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 16 x i16> %a
}
@@ -1607,9 +1575,9 @@ declare <vscale x 32 x i16> @llvm.riscv.vmulhu.nxv32i16.i16(
<vscale x 32 x i16>,
<vscale x 32 x i16>,
i16,
- i64);
+ iXLen);
-define <vscale x 32 x i16> @intrinsic_vmulhu_vx_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, i16 %1, i64 %2) nounwind {
+define <vscale x 32 x i16> @intrinsic_vmulhu_vx_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, i16 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmulhu_vx_nxv32i16_nxv32i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu
@@ -1620,7 +1588,7 @@ entry:
<vscale x 32 x i16> undef,
<vscale x 32 x i16> %0,
i16 %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 32 x i16> %a
}
@@ -1630,10 +1598,9 @@ declare <vscale x 32 x i16> @llvm.riscv.vmulhu.mask.nxv32i16.i16(
<vscale x 32 x i16>,
i16,
<vscale x 32 x i1>,
- i64,
- i64);
+ iXLen, iXLen);
-define <vscale x 32 x i16> @intrinsic_vmulhu_mask_vx_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, i16 %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
+define <vscale x 32 x i16> @intrinsic_vmulhu_mask_vx_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, i16 %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmulhu_mask_vx_nxv32i16_nxv32i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu
@@ -1645,7 +1612,7 @@ entry:
<vscale x 32 x i16> %1,
i16 %2,
<vscale x 32 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 32 x i16> %a
}
@@ -1654,9 +1621,9 @@ declare <vscale x 1 x i32> @llvm.riscv.vmulhu.nxv1i32.i32(
<vscale x 1 x i32>,
<vscale x 1 x i32>,
i32,
- i64);
+ iXLen);
-define <vscale x 1 x i32> @intrinsic_vmulhu_vx_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, i32 %1, i64 %2) nounwind {
+define <vscale x 1 x i32> @intrinsic_vmulhu_vx_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, i32 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmulhu_vx_nxv1i32_nxv1i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
@@ -1667,7 +1634,7 @@ entry:
<vscale x 1 x i32> undef,
<vscale x 1 x i32> %0,
i32 %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 1 x i32> %a
}
@@ -1677,10 +1644,9 @@ declare <vscale x 1 x i32> @llvm.riscv.vmulhu.mask.nxv1i32.i32(
<vscale x 1 x i32>,
i32,
<vscale x 1 x i1>,
- i64,
- i64);
+ iXLen, iXLen);
-define <vscale x 1 x i32> @intrinsic_vmulhu_mask_vx_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+define <vscale x 1 x i32> @intrinsic_vmulhu_mask_vx_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmulhu_mask_vx_nxv1i32_nxv1i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
@@ -1692,7 +1658,7 @@ entry:
<vscale x 1 x i32> %1,
i32 %2,
<vscale x 1 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 1 x i32> %a
}
@@ -1701,9 +1667,9 @@ declare <vscale x 2 x i32> @llvm.riscv.vmulhu.nxv2i32.i32(
<vscale x 2 x i32>,
<vscale x 2 x i32>,
i32,
- i64);
+ iXLen);
-define <vscale x 2 x i32> @intrinsic_vmulhu_vx_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, i32 %1, i64 %2) nounwind {
+define <vscale x 2 x i32> @intrinsic_vmulhu_vx_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, i32 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmulhu_vx_nxv2i32_nxv2i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
@@ -1714,7 +1680,7 @@ entry:
<vscale x 2 x i32> undef,
<vscale x 2 x i32> %0,
i32 %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 2 x i32> %a
}
@@ -1724,10 +1690,9 @@ declare <vscale x 2 x i32> @llvm.riscv.vmulhu.mask.nxv2i32.i32(
<vscale x 2 x i32>,
i32,
<vscale x 2 x i1>,
- i64,
- i64);
+ iXLen, iXLen);
-define <vscale x 2 x i32> @intrinsic_vmulhu_mask_vx_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+define <vscale x 2 x i32> @intrinsic_vmulhu_mask_vx_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmulhu_mask_vx_nxv2i32_nxv2i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
@@ -1739,7 +1704,7 @@ entry:
<vscale x 2 x i32> %1,
i32 %2,
<vscale x 2 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 2 x i32> %a
}
@@ -1748,9 +1713,9 @@ declare <vscale x 4 x i32> @llvm.riscv.vmulhu.nxv4i32.i32(
<vscale x 4 x i32>,
<vscale x 4 x i32>,
i32,
- i64);
+ iXLen);
-define <vscale x 4 x i32> @intrinsic_vmulhu_vx_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, i32 %1, i64 %2) nounwind {
+define <vscale x 4 x i32> @intrinsic_vmulhu_vx_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, i32 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmulhu_vx_nxv4i32_nxv4i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
@@ -1761,7 +1726,7 @@ entry:
<vscale x 4 x i32> undef,
<vscale x 4 x i32> %0,
i32 %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 4 x i32> %a
}
@@ -1771,10 +1736,9 @@ declare <vscale x 4 x i32> @llvm.riscv.vmulhu.mask.nxv4i32.i32(
<vscale x 4 x i32>,
i32,
<vscale x 4 x i1>,
- i64,
- i64);
+ iXLen, iXLen);
-define <vscale x 4 x i32> @intrinsic_vmulhu_mask_vx_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+define <vscale x 4 x i32> @intrinsic_vmulhu_mask_vx_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmulhu_mask_vx_nxv4i32_nxv4i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
@@ -1786,7 +1750,7 @@ entry:
<vscale x 4 x i32> %1,
i32 %2,
<vscale x 4 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 4 x i32> %a
}
@@ -1795,9 +1759,9 @@ declare <vscale x 8 x i32> @llvm.riscv.vmulhu.nxv8i32.i32(
<vscale x 8 x i32>,
<vscale x 8 x i32>,
i32,
- i64);
+ iXLen);
-define <vscale x 8 x i32> @intrinsic_vmulhu_vx_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, i32 %1, i64 %2) nounwind {
+define <vscale x 8 x i32> @intrinsic_vmulhu_vx_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, i32 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmulhu_vx_nxv8i32_nxv8i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
@@ -1808,7 +1772,7 @@ entry:
<vscale x 8 x i32> undef,
<vscale x 8 x i32> %0,
i32 %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 8 x i32> %a
}
@@ -1818,10 +1782,9 @@ declare <vscale x 8 x i32> @llvm.riscv.vmulhu.mask.nxv8i32.i32(
<vscale x 8 x i32>,
i32,
<vscale x 8 x i1>,
- i64,
- i64);
+ iXLen, iXLen);
-define <vscale x 8 x i32> @intrinsic_vmulhu_mask_vx_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+define <vscale x 8 x i32> @intrinsic_vmulhu_mask_vx_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmulhu_mask_vx_nxv8i32_nxv8i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
@@ -1833,7 +1796,7 @@ entry:
<vscale x 8 x i32> %1,
i32 %2,
<vscale x 8 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 8 x i32> %a
}
@@ -1842,9 +1805,9 @@ declare <vscale x 16 x i32> @llvm.riscv.vmulhu.nxv16i32.i32(
<vscale x 16 x i32>,
<vscale x 16 x i32>,
i32,
- i64);
+ iXLen);
-define <vscale x 16 x i32> @intrinsic_vmulhu_vx_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, i32 %1, i64 %2) nounwind {
+define <vscale x 16 x i32> @intrinsic_vmulhu_vx_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, i32 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vmulhu_vx_nxv16i32_nxv16i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu
@@ -1855,7 +1818,7 @@ entry:
<vscale x 16 x i32> undef,
<vscale x 16 x i32> %0,
i32 %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 16 x i32> %a
}
@@ -1865,10 +1828,9 @@ declare <vscale x 16 x i32> @llvm.riscv.vmulhu.mask.nxv16i32.i32(
<vscale x 16 x i32>,
i32,
<vscale x 16 x i1>,
- i64,
- i64);
+ iXLen, iXLen);
-define <vscale x 16 x i32> @intrinsic_vmulhu_mask_vx_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+define <vscale x 16 x i32> @intrinsic_vmulhu_mask_vx_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmulhu_mask_vx_nxv16i32_nxv16i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu
@@ -1880,7 +1842,7 @@ entry:
<vscale x 16 x i32> %1,
i32 %2,
<vscale x 16 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 16 x i32> %a
}
@@ -1889,20 +1851,32 @@ declare <vscale x 1 x i64> @llvm.riscv.vmulhu.nxv1i64.i64(
<vscale x 1 x i64>,
<vscale x 1 x i64>,
i64,
- i64);
-
-define <vscale x 1 x i64> @intrinsic_vmulhu_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmulhu_vx_nxv1i64_nxv1i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
-; CHECK-NEXT: vmulhu.vx v8, v8, a0
-; CHECK-NEXT: ret
+ iXLen);
+
+define <vscale x 1 x i64> @intrinsic_vmulhu_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, iXLen %2) nounwind {
+; RV32-LABEL: intrinsic_vmulhu_vx_nxv1i64_nxv1i64_i64:
+; RV32: # %bb.0: # %entry
+; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: sw a1, 12(sp)
+; RV32-NEXT: sw a0, 8(sp)
+; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
+; RV32-NEXT: addi a0, sp, 8
+; RV32-NEXT: vlse64.v v9, (a0), zero
+; RV32-NEXT: vmulhu.vv v8, v8, v9
+; RV32-NEXT: addi sp, sp, 16
+; RV32-NEXT: ret
+;
+; RV64-LABEL: intrinsic_vmulhu_vx_nxv1i64_nxv1i64_i64:
+; RV64: # %bb.0: # %entry
+; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, mu
+; RV64-NEXT: vmulhu.vx v8, v8, a0
+; RV64-NEXT: ret
entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vmulhu.nxv1i64.i64(
<vscale x 1 x i64> undef,
<vscale x 1 x i64> %0,
i64 %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 1 x i64> %a
}
@@ -1912,22 +1886,33 @@ declare <vscale x 1 x i64> @llvm.riscv.vmulhu.mask.nxv1i64.i64(
<vscale x 1 x i64>,
i64,
<vscale x 1 x i1>,
- i64,
- i64);
-
-define <vscale x 1 x i64> @intrinsic_vmulhu_mask_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmulhu_mask_vx_nxv1i64_nxv1i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
-; CHECK-NEXT: vmulhu.vx v8, v9, a0, v0.t
-; CHECK-NEXT: ret
+ iXLen, iXLen);
+
+define <vscale x 1 x i64> @intrinsic_vmulhu_mask_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
+; RV32-LABEL: intrinsic_vmulhu_mask_vx_nxv1i64_nxv1i64_i64:
+; RV32: # %bb.0: # %entry
+; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: sw a1, 12(sp)
+; RV32-NEXT: sw a0, 8(sp)
+; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
+; RV32-NEXT: addi a0, sp, 8
+; RV32-NEXT: vlse64.v v10, (a0), zero
+; RV32-NEXT: vmulhu.vv v8, v9, v10, v0.t
+; RV32-NEXT: addi sp, sp, 16
+; RV32-NEXT: ret
+;
+; RV64-LABEL: intrinsic_vmulhu_mask_vx_nxv1i64_nxv1i64_i64:
+; RV64: # %bb.0: # %entry
+; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, mu
+; RV64-NEXT: vmulhu.vx v8, v9, a0, v0.t
+; RV64-NEXT: ret
entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vmulhu.mask.nxv1i64.i64(
<vscale x 1 x i64> %0,
<vscale x 1 x i64> %1,
i64 %2,
<vscale x 1 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 1 x i64> %a
}
@@ -1936,20 +1921,32 @@ declare <vscale x 2 x i64> @llvm.riscv.vmulhu.nxv2i64.i64(
<vscale x 2 x i64>,
<vscale x 2 x i64>,
i64,
- i64);
-
-define <vscale x 2 x i64> @intrinsic_vmulhu_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmulhu_vx_nxv2i64_nxv2i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
-; CHECK-NEXT: vmulhu.vx v8, v8, a0
-; CHECK-NEXT: ret
+ iXLen);
+
+define <vscale x 2 x i64> @intrinsic_vmulhu_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, iXLen %2) nounwind {
+; RV32-LABEL: intrinsic_vmulhu_vx_nxv2i64_nxv2i64_i64:
+; RV32: # %bb.0: # %entry
+; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: sw a1, 12(sp)
+; RV32-NEXT: sw a0, 8(sp)
+; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
+; RV32-NEXT: addi a0, sp, 8
+; RV32-NEXT: vlse64.v v10, (a0), zero
+; RV32-NEXT: vmulhu.vv v8, v8, v10
+; RV32-NEXT: addi sp, sp, 16
+; RV32-NEXT: ret
+;
+; RV64-LABEL: intrinsic_vmulhu_vx_nxv2i64_nxv2i64_i64:
+; RV64: # %bb.0: # %entry
+; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, mu
+; RV64-NEXT: vmulhu.vx v8, v8, a0
+; RV64-NEXT: ret
entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vmulhu.nxv2i64.i64(
<vscale x 2 x i64> undef,
<vscale x 2 x i64> %0,
i64 %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 2 x i64> %a
}
@@ -1959,22 +1956,33 @@ declare <vscale x 2 x i64> @llvm.riscv.vmulhu.mask.nxv2i64.i64(
<vscale x 2 x i64>,
i64,
<vscale x 2 x i1>,
- i64,
- i64);
-
-define <vscale x 2 x i64> @intrinsic_vmulhu_mask_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmulhu_mask_vx_nxv2i64_nxv2i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
-; CHECK-NEXT: vmulhu.vx v8, v10, a0, v0.t
-; CHECK-NEXT: ret
+ iXLen, iXLen);
+
+define <vscale x 2 x i64> @intrinsic_vmulhu_mask_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
+; RV32-LABEL: intrinsic_vmulhu_mask_vx_nxv2i64_nxv2i64_i64:
+; RV32: # %bb.0: # %entry
+; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: sw a1, 12(sp)
+; RV32-NEXT: sw a0, 8(sp)
+; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
+; RV32-NEXT: addi a0, sp, 8
+; RV32-NEXT: vlse64.v v12, (a0), zero
+; RV32-NEXT: vmulhu.vv v8, v10, v12, v0.t
+; RV32-NEXT: addi sp, sp, 16
+; RV32-NEXT: ret
+;
+; RV64-LABEL: intrinsic_vmulhu_mask_vx_nxv2i64_nxv2i64_i64:
+; RV64: # %bb.0: # %entry
+; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, mu
+; RV64-NEXT: vmulhu.vx v8, v10, a0, v0.t
+; RV64-NEXT: ret
entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vmulhu.mask.nxv2i64.i64(
<vscale x 2 x i64> %0,
<vscale x 2 x i64> %1,
i64 %2,
<vscale x 2 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 2 x i64> %a
}
@@ -1983,20 +1991,32 @@ declare <vscale x 4 x i64> @llvm.riscv.vmulhu.nxv4i64.i64(
<vscale x 4 x i64>,
<vscale x 4 x i64>,
i64,
- i64);
-
-define <vscale x 4 x i64> @intrinsic_vmulhu_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmulhu_vx_nxv4i64_nxv4i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
-; CHECK-NEXT: vmulhu.vx v8, v8, a0
-; CHECK-NEXT: ret
+ iXLen);
+
+define <vscale x 4 x i64> @intrinsic_vmulhu_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, iXLen %2) nounwind {
+; RV32-LABEL: intrinsic_vmulhu_vx_nxv4i64_nxv4i64_i64:
+; RV32: # %bb.0: # %entry
+; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: sw a1, 12(sp)
+; RV32-NEXT: sw a0, 8(sp)
+; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
+; RV32-NEXT: addi a0, sp, 8
+; RV32-NEXT: vlse64.v v12, (a0), zero
+; RV32-NEXT: vmulhu.vv v8, v8, v12
+; RV32-NEXT: addi sp, sp, 16
+; RV32-NEXT: ret
+;
+; RV64-LABEL: intrinsic_vmulhu_vx_nxv4i64_nxv4i64_i64:
+; RV64: # %bb.0: # %entry
+; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu
+; RV64-NEXT: vmulhu.vx v8, v8, a0
+; RV64-NEXT: ret
entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vmulhu.nxv4i64.i64(
<vscale x 4 x i64> undef,
<vscale x 4 x i64> %0,
i64 %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 4 x i64> %a
}
@@ -2006,22 +2026,33 @@ declare <vscale x 4 x i64> @llvm.riscv.vmulhu.mask.nxv4i64.i64(
<vscale x 4 x i64>,
i64,
<vscale x 4 x i1>,
- i64,
- i64);
-
-define <vscale x 4 x i64> @intrinsic_vmulhu_mask_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmulhu_mask_vx_nxv4i64_nxv4i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
-; CHECK-NEXT: vmulhu.vx v8, v12, a0, v0.t
-; CHECK-NEXT: ret
+ iXLen, iXLen);
+
+define <vscale x 4 x i64> @intrinsic_vmulhu_mask_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
+; RV32-LABEL: intrinsic_vmulhu_mask_vx_nxv4i64_nxv4i64_i64:
+; RV32: # %bb.0: # %entry
+; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: sw a1, 12(sp)
+; RV32-NEXT: sw a0, 8(sp)
+; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
+; RV32-NEXT: addi a0, sp, 8
+; RV32-NEXT: vlse64.v v16, (a0), zero
+; RV32-NEXT: vmulhu.vv v8, v12, v16, v0.t
+; RV32-NEXT: addi sp, sp, 16
+; RV32-NEXT: ret
+;
+; RV64-LABEL: intrinsic_vmulhu_mask_vx_nxv4i64_nxv4i64_i64:
+; RV64: # %bb.0: # %entry
+; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu
+; RV64-NEXT: vmulhu.vx v8, v12, a0, v0.t
+; RV64-NEXT: ret
entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vmulhu.mask.nxv4i64.i64(
<vscale x 4 x i64> %0,
<vscale x 4 x i64> %1,
i64 %2,
<vscale x 4 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 4 x i64> %a
}
@@ -2030,20 +2061,32 @@ declare <vscale x 8 x i64> @llvm.riscv.vmulhu.nxv8i64.i64(
<vscale x 8 x i64>,
<vscale x 8 x i64>,
i64,
- i64);
-
-define <vscale x 8 x i64> @intrinsic_vmulhu_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, i64 %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vmulhu_vx_nxv8i64_nxv8i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu
-; CHECK-NEXT: vmulhu.vx v8, v8, a0
-; CHECK-NEXT: ret
+ iXLen);
+
+define <vscale x 8 x i64> @intrinsic_vmulhu_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, i64 %1, iXLen %2) nounwind {
+; RV32-LABEL: intrinsic_vmulhu_vx_nxv8i64_nxv8i64_i64:
+; RV32: # %bb.0: # %entry
+; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: sw a1, 12(sp)
+; RV32-NEXT: sw a0, 8(sp)
+; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu
+; RV32-NEXT: addi a0, sp, 8
+; RV32-NEXT: vlse64.v v16, (a0), zero
+; RV32-NEXT: vmulhu.vv v8, v8, v16
+; RV32-NEXT: addi sp, sp, 16
+; RV32-NEXT: ret
+;
+; RV64-LABEL: intrinsic_vmulhu_vx_nxv8i64_nxv8i64_i64:
+; RV64: # %bb.0: # %entry
+; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, mu
+; RV64-NEXT: vmulhu.vx v8, v8, a0
+; RV64-NEXT: ret
entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vmulhu.nxv8i64.i64(
<vscale x 8 x i64> undef,
<vscale x 8 x i64> %0,
i64 %1,
- i64 %2)
+ iXLen %2)
ret <vscale x 8 x i64> %a
}
@@ -2053,22 +2096,33 @@ declare <vscale x 8 x i64> @llvm.riscv.vmulhu.mask.nxv8i64.i64(
<vscale x 8 x i64>,
i64,
<vscale x 8 x i1>,
- i64,
- i64);
-
-define <vscale x 8 x i64> @intrinsic_vmulhu_mask_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vmulhu_mask_vx_nxv8i64_nxv8i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu
-; CHECK-NEXT: vmulhu.vx v8, v16, a0, v0.t
-; CHECK-NEXT: ret
+ iXLen, iXLen);
+
+define <vscale x 8 x i64> @intrinsic_vmulhu_mask_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
+; RV32-LABEL: intrinsic_vmulhu_mask_vx_nxv8i64_nxv8i64_i64:
+; RV32: # %bb.0: # %entry
+; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: sw a1, 12(sp)
+; RV32-NEXT: sw a0, 8(sp)
+; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu
+; RV32-NEXT: addi a0, sp, 8
+; RV32-NEXT: vlse64.v v24, (a0), zero
+; RV32-NEXT: vmulhu.vv v8, v16, v24, v0.t
+; RV32-NEXT: addi sp, sp, 16
+; RV32-NEXT: ret
+;
+; RV64-LABEL: intrinsic_vmulhu_mask_vx_nxv8i64_nxv8i64_i64:
+; RV64: # %bb.0: # %entry
+; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, mu
+; RV64-NEXT: vmulhu.vx v8, v16, a0, v0.t
+; RV64-NEXT: ret
entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vmulhu.mask.nxv8i64.i64(
<vscale x 8 x i64> %0,
<vscale x 8 x i64> %1,
i64 %2,
<vscale x 8 x i1> %3,
- i64 %4, i64 1)
+ iXLen %4, iXLen 1)
ret <vscale x 8 x i64> %a
}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vrsub-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vrsub-rv64.ll
deleted file mode 100644
index 372a7cbd560da..0000000000000
--- a/llvm/test/CodeGen/RISCV/rvv/vrsub-rv64.ll
+++ /dev/null
@@ -1,1762 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs \
-; RUN: < %s | FileCheck %s
-declare <vscale x 1 x i8> @llvm.riscv.vrsub.nxv1i8.i8(
- <vscale x 1 x i8>,
- <vscale x 1 x i8>,
- i8,
- i64);
-
-define <vscale x 1 x i8> @intrinsic_vrsub_vx_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, i8 %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vrsub_vx_nxv1i8_nxv1i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
-; CHECK-NEXT: vrsub.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i8> @llvm.riscv.vrsub.nxv1i8.i8(
- <vscale x 1 x i8> undef,
- <vscale x 1 x i8> %0,
- i8 %1,
- i64 %2)
-
- ret <vscale x 1 x i8> %a
-}
-
-declare <vscale x 1 x i8> @llvm.riscv.vrsub.mask.nxv1i8.i8(
- <vscale x 1 x i8>,
- <vscale x 1 x i8>,
- i8,
- <vscale x 1 x i1>,
- i64,
- i64);
-
-define <vscale x 1 x i8> @intrinsic_vrsub_mask_vx_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vrsub_mask_vx_nxv1i8_nxv1i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
-; CHECK-NEXT: vrsub.vx v8, v9, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i8> @llvm.riscv.vrsub.mask.nxv1i8.i8(
- <vscale x 1 x i8> %0,
- <vscale x 1 x i8> %1,
- i8 %2,
- <vscale x 1 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 1 x i8> %a
-}
-
-declare <vscale x 2 x i8> @llvm.riscv.vrsub.nxv2i8.i8(
- <vscale x 2 x i8>,
- <vscale x 2 x i8>,
- i8,
- i64);
-
-define <vscale x 2 x i8> @intrinsic_vrsub_vx_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, i8 %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vrsub_vx_nxv2i8_nxv2i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
-; CHECK-NEXT: vrsub.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i8> @llvm.riscv.vrsub.nxv2i8.i8(
- <vscale x 2 x i8> undef,
- <vscale x 2 x i8> %0,
- i8 %1,
- i64 %2)
-
- ret <vscale x 2 x i8> %a
-}
-
-declare <vscale x 2 x i8> @llvm.riscv.vrsub.mask.nxv2i8.i8(
- <vscale x 2 x i8>,
- <vscale x 2 x i8>,
- i8,
- <vscale x 2 x i1>,
- i64,
- i64);
-
-define <vscale x 2 x i8> @intrinsic_vrsub_mask_vx_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vrsub_mask_vx_nxv2i8_nxv2i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
-; CHECK-NEXT: vrsub.vx v8, v9, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i8> @llvm.riscv.vrsub.mask.nxv2i8.i8(
- <vscale x 2 x i8> %0,
- <vscale x 2 x i8> %1,
- i8 %2,
- <vscale x 2 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 2 x i8> %a
-}
-
-declare <vscale x 4 x i8> @llvm.riscv.vrsub.nxv4i8.i8(
- <vscale x 4 x i8>,
- <vscale x 4 x i8>,
- i8,
- i64);
-
-define <vscale x 4 x i8> @intrinsic_vrsub_vx_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, i8 %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vrsub_vx_nxv4i8_nxv4i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
-; CHECK-NEXT: vrsub.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i8> @llvm.riscv.vrsub.nxv4i8.i8(
- <vscale x 4 x i8> undef,
- <vscale x 4 x i8> %0,
- i8 %1,
- i64 %2)
-
- ret <vscale x 4 x i8> %a
-}
-
-declare <vscale x 4 x i8> @llvm.riscv.vrsub.mask.nxv4i8.i8(
- <vscale x 4 x i8>,
- <vscale x 4 x i8>,
- i8,
- <vscale x 4 x i1>,
- i64,
- i64);
-
-define <vscale x 4 x i8> @intrinsic_vrsub_mask_vx_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vrsub_mask_vx_nxv4i8_nxv4i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
-; CHECK-NEXT: vrsub.vx v8, v9, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i8> @llvm.riscv.vrsub.mask.nxv4i8.i8(
- <vscale x 4 x i8> %0,
- <vscale x 4 x i8> %1,
- i8 %2,
- <vscale x 4 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 4 x i8> %a
-}
-
-declare <vscale x 8 x i8> @llvm.riscv.vrsub.nxv8i8.i8(
- <vscale x 8 x i8>,
- <vscale x 8 x i8>,
- i8,
- i64);
-
-define <vscale x 8 x i8> @intrinsic_vrsub_vx_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, i8 %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vrsub_vx_nxv8i8_nxv8i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
-; CHECK-NEXT: vrsub.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i8> @llvm.riscv.vrsub.nxv8i8.i8(
- <vscale x 8 x i8> undef,
- <vscale x 8 x i8> %0,
- i8 %1,
- i64 %2)
-
- ret <vscale x 8 x i8> %a
-}
-
-declare <vscale x 8 x i8> @llvm.riscv.vrsub.mask.nxv8i8.i8(
- <vscale x 8 x i8>,
- <vscale x 8 x i8>,
- i8,
- <vscale x 8 x i1>,
- i64,
- i64);
-
-define <vscale x 8 x i8> @intrinsic_vrsub_mask_vx_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vrsub_mask_vx_nxv8i8_nxv8i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
-; CHECK-NEXT: vrsub.vx v8, v9, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i8> @llvm.riscv.vrsub.mask.nxv8i8.i8(
- <vscale x 8 x i8> %0,
- <vscale x 8 x i8> %1,
- i8 %2,
- <vscale x 8 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 8 x i8> %a
-}
-
-declare <vscale x 16 x i8> @llvm.riscv.vrsub.nxv16i8.i8(
- <vscale x 16 x i8>,
- <vscale x 16 x i8>,
- i8,
- i64);
-
-define <vscale x 16 x i8> @intrinsic_vrsub_vx_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, i8 %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vrsub_vx_nxv16i8_nxv16i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
-; CHECK-NEXT: vrsub.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i8> @llvm.riscv.vrsub.nxv16i8.i8(
- <vscale x 16 x i8> undef,
- <vscale x 16 x i8> %0,
- i8 %1,
- i64 %2)
-
- ret <vscale x 16 x i8> %a
-}
-
-declare <vscale x 16 x i8> @llvm.riscv.vrsub.mask.nxv16i8.i8(
- <vscale x 16 x i8>,
- <vscale x 16 x i8>,
- i8,
- <vscale x 16 x i1>,
- i64,
- i64);
-
-define <vscale x 16 x i8> @intrinsic_vrsub_mask_vx_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vrsub_mask_vx_nxv16i8_nxv16i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
-; CHECK-NEXT: vrsub.vx v8, v10, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i8> @llvm.riscv.vrsub.mask.nxv16i8.i8(
- <vscale x 16 x i8> %0,
- <vscale x 16 x i8> %1,
- i8 %2,
- <vscale x 16 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 16 x i8> %a
-}
-
-declare <vscale x 32 x i8> @llvm.riscv.vrsub.nxv32i8.i8(
- <vscale x 32 x i8>,
- <vscale x 32 x i8>,
- i8,
- i64);
-
-define <vscale x 32 x i8> @intrinsic_vrsub_vx_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, i8 %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vrsub_vx_nxv32i8_nxv32i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
-; CHECK-NEXT: vrsub.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 32 x i8> @llvm.riscv.vrsub.nxv32i8.i8(
- <vscale x 32 x i8> undef,
- <vscale x 32 x i8> %0,
- i8 %1,
- i64 %2)
-
- ret <vscale x 32 x i8> %a
-}
-
-declare <vscale x 32 x i8> @llvm.riscv.vrsub.mask.nxv32i8.i8(
- <vscale x 32 x i8>,
- <vscale x 32 x i8>,
- i8,
- <vscale x 32 x i1>,
- i64,
- i64);
-
-define <vscale x 32 x i8> @intrinsic_vrsub_mask_vx_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vrsub_mask_vx_nxv32i8_nxv32i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
-; CHECK-NEXT: vrsub.vx v8, v12, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 32 x i8> @llvm.riscv.vrsub.mask.nxv32i8.i8(
- <vscale x 32 x i8> %0,
- <vscale x 32 x i8> %1,
- i8 %2,
- <vscale x 32 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 32 x i8> %a
-}
-
-declare <vscale x 64 x i8> @llvm.riscv.vrsub.nxv64i8.i8(
- <vscale x 64 x i8>,
- <vscale x 64 x i8>,
- i8,
- i64);
-
-define <vscale x 64 x i8> @intrinsic_vrsub_vx_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, i8 %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vrsub_vx_nxv64i8_nxv64i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu
-; CHECK-NEXT: vrsub.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 64 x i8> @llvm.riscv.vrsub.nxv64i8.i8(
- <vscale x 64 x i8> undef,
- <vscale x 64 x i8> %0,
- i8 %1,
- i64 %2)
-
- ret <vscale x 64 x i8> %a
-}
-
-declare <vscale x 64 x i8> @llvm.riscv.vrsub.mask.nxv64i8.i8(
- <vscale x 64 x i8>,
- <vscale x 64 x i8>,
- i8,
- <vscale x 64 x i1>,
- i64,
- i64);
-
-define <vscale x 64 x i8> @intrinsic_vrsub_mask_vx_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i8 %2, <vscale x 64 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vrsub_mask_vx_nxv64i8_nxv64i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu
-; CHECK-NEXT: vrsub.vx v8, v16, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 64 x i8> @llvm.riscv.vrsub.mask.nxv64i8.i8(
- <vscale x 64 x i8> %0,
- <vscale x 64 x i8> %1,
- i8 %2,
- <vscale x 64 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 64 x i8> %a
-}
-
-declare <vscale x 1 x i16> @llvm.riscv.vrsub.nxv1i16.i16(
- <vscale x 1 x i16>,
- <vscale x 1 x i16>,
- i16,
- i64);
-
-define <vscale x 1 x i16> @intrinsic_vrsub_vx_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, i16 %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vrsub_vx_nxv1i16_nxv1i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
-; CHECK-NEXT: vrsub.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i16> @llvm.riscv.vrsub.nxv1i16.i16(
- <vscale x 1 x i16> undef,
- <vscale x 1 x i16> %0,
- i16 %1,
- i64 %2)
-
- ret <vscale x 1 x i16> %a
-}
-
-declare <vscale x 1 x i16> @llvm.riscv.vrsub.mask.nxv1i16.i16(
- <vscale x 1 x i16>,
- <vscale x 1 x i16>,
- i16,
- <vscale x 1 x i1>,
- i64,
- i64);
-
-define <vscale x 1 x i16> @intrinsic_vrsub_mask_vx_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vrsub_mask_vx_nxv1i16_nxv1i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
-; CHECK-NEXT: vrsub.vx v8, v9, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i16> @llvm.riscv.vrsub.mask.nxv1i16.i16(
- <vscale x 1 x i16> %0,
- <vscale x 1 x i16> %1,
- i16 %2,
- <vscale x 1 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 1 x i16> %a
-}
-
-declare <vscale x 2 x i16> @llvm.riscv.vrsub.nxv2i16.i16(
- <vscale x 2 x i16>,
- <vscale x 2 x i16>,
- i16,
- i64);
-
-define <vscale x 2 x i16> @intrinsic_vrsub_vx_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, i16 %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vrsub_vx_nxv2i16_nxv2i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
-; CHECK-NEXT: vrsub.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i16> @llvm.riscv.vrsub.nxv2i16.i16(
- <vscale x 2 x i16> undef,
- <vscale x 2 x i16> %0,
- i16 %1,
- i64 %2)
-
- ret <vscale x 2 x i16> %a
-}
-
-declare <vscale x 2 x i16> @llvm.riscv.vrsub.mask.nxv2i16.i16(
- <vscale x 2 x i16>,
- <vscale x 2 x i16>,
- i16,
- <vscale x 2 x i1>,
- i64,
- i64);
-
-define <vscale x 2 x i16> @intrinsic_vrsub_mask_vx_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vrsub_mask_vx_nxv2i16_nxv2i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
-; CHECK-NEXT: vrsub.vx v8, v9, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i16> @llvm.riscv.vrsub.mask.nxv2i16.i16(
- <vscale x 2 x i16> %0,
- <vscale x 2 x i16> %1,
- i16 %2,
- <vscale x 2 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 2 x i16> %a
-}
-
-declare <vscale x 4 x i16> @llvm.riscv.vrsub.nxv4i16.i16(
- <vscale x 4 x i16>,
- <vscale x 4 x i16>,
- i16,
- i64);
-
-define <vscale x 4 x i16> @intrinsic_vrsub_vx_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, i16 %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vrsub_vx_nxv4i16_nxv4i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
-; CHECK-NEXT: vrsub.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i16> @llvm.riscv.vrsub.nxv4i16.i16(
- <vscale x 4 x i16> undef,
- <vscale x 4 x i16> %0,
- i16 %1,
- i64 %2)
-
- ret <vscale x 4 x i16> %a
-}
-
-declare <vscale x 4 x i16> @llvm.riscv.vrsub.mask.nxv4i16.i16(
- <vscale x 4 x i16>,
- <vscale x 4 x i16>,
- i16,
- <vscale x 4 x i1>,
- i64,
- i64);
-
-define <vscale x 4 x i16> @intrinsic_vrsub_mask_vx_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vrsub_mask_vx_nxv4i16_nxv4i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
-; CHECK-NEXT: vrsub.vx v8, v9, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i16> @llvm.riscv.vrsub.mask.nxv4i16.i16(
- <vscale x 4 x i16> %0,
- <vscale x 4 x i16> %1,
- i16 %2,
- <vscale x 4 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 4 x i16> %a
-}
-
-declare <vscale x 8 x i16> @llvm.riscv.vrsub.nxv8i16.i16(
- <vscale x 8 x i16>,
- <vscale x 8 x i16>,
- i16,
- i64);
-
-define <vscale x 8 x i16> @intrinsic_vrsub_vx_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, i16 %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vrsub_vx_nxv8i16_nxv8i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
-; CHECK-NEXT: vrsub.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i16> @llvm.riscv.vrsub.nxv8i16.i16(
- <vscale x 8 x i16> undef,
- <vscale x 8 x i16> %0,
- i16 %1,
- i64 %2)
-
- ret <vscale x 8 x i16> %a
-}
-
-declare <vscale x 8 x i16> @llvm.riscv.vrsub.mask.nxv8i16.i16(
- <vscale x 8 x i16>,
- <vscale x 8 x i16>,
- i16,
- <vscale x 8 x i1>,
- i64,
- i64);
-
-define <vscale x 8 x i16> @intrinsic_vrsub_mask_vx_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vrsub_mask_vx_nxv8i16_nxv8i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
-; CHECK-NEXT: vrsub.vx v8, v10, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i16> @llvm.riscv.vrsub.mask.nxv8i16.i16(
- <vscale x 8 x i16> %0,
- <vscale x 8 x i16> %1,
- i16 %2,
- <vscale x 8 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 8 x i16> %a
-}
-
-declare <vscale x 16 x i16> @llvm.riscv.vrsub.nxv16i16.i16(
- <vscale x 16 x i16>,
- <vscale x 16 x i16>,
- i16,
- i64);
-
-define <vscale x 16 x i16> @intrinsic_vrsub_vx_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, i16 %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vrsub_vx_nxv16i16_nxv16i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
-; CHECK-NEXT: vrsub.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i16> @llvm.riscv.vrsub.nxv16i16.i16(
- <vscale x 16 x i16> undef,
- <vscale x 16 x i16> %0,
- i16 %1,
- i64 %2)
-
- ret <vscale x 16 x i16> %a
-}
-
-declare <vscale x 16 x i16> @llvm.riscv.vrsub.mask.nxv16i16.i16(
- <vscale x 16 x i16>,
- <vscale x 16 x i16>,
- i16,
- <vscale x 16 x i1>,
- i64,
- i64);
-
-define <vscale x 16 x i16> @intrinsic_vrsub_mask_vx_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vrsub_mask_vx_nxv16i16_nxv16i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
-; CHECK-NEXT: vrsub.vx v8, v12, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i16> @llvm.riscv.vrsub.mask.nxv16i16.i16(
- <vscale x 16 x i16> %0,
- <vscale x 16 x i16> %1,
- i16 %2,
- <vscale x 16 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 16 x i16> %a
-}
-
-declare <vscale x 32 x i16> @llvm.riscv.vrsub.nxv32i16.i16(
- <vscale x 32 x i16>,
- <vscale x 32 x i16>,
- i16,
- i64);
-
-define <vscale x 32 x i16> @intrinsic_vrsub_vx_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, i16 %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vrsub_vx_nxv32i16_nxv32i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu
-; CHECK-NEXT: vrsub.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 32 x i16> @llvm.riscv.vrsub.nxv32i16.i16(
- <vscale x 32 x i16> undef,
- <vscale x 32 x i16> %0,
- i16 %1,
- i64 %2)
-
- ret <vscale x 32 x i16> %a
-}
-
-declare <vscale x 32 x i16> @llvm.riscv.vrsub.mask.nxv32i16.i16(
- <vscale x 32 x i16>,
- <vscale x 32 x i16>,
- i16,
- <vscale x 32 x i1>,
- i64,
- i64);
-
-define <vscale x 32 x i16> @intrinsic_vrsub_mask_vx_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, i16 %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vrsub_mask_vx_nxv32i16_nxv32i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu
-; CHECK-NEXT: vrsub.vx v8, v16, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 32 x i16> @llvm.riscv.vrsub.mask.nxv32i16.i16(
- <vscale x 32 x i16> %0,
- <vscale x 32 x i16> %1,
- i16 %2,
- <vscale x 32 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 32 x i16> %a
-}
-
-declare <vscale x 1 x i32> @llvm.riscv.vrsub.nxv1i32.i32(
- <vscale x 1 x i32>,
- <vscale x 1 x i32>,
- i32,
- i64);
-
-define <vscale x 1 x i32> @intrinsic_vrsub_vx_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, i32 %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vrsub_vx_nxv1i32_nxv1i32_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
-; CHECK-NEXT: vrsub.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i32> @llvm.riscv.vrsub.nxv1i32.i32(
- <vscale x 1 x i32> undef,
- <vscale x 1 x i32> %0,
- i32 %1,
- i64 %2)
-
- ret <vscale x 1 x i32> %a
-}
-
-declare <vscale x 1 x i32> @llvm.riscv.vrsub.mask.nxv1i32.i32(
- <vscale x 1 x i32>,
- <vscale x 1 x i32>,
- i32,
- <vscale x 1 x i1>,
- i64,
- i64);
-
-define <vscale x 1 x i32> @intrinsic_vrsub_mask_vx_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vrsub_mask_vx_nxv1i32_nxv1i32_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
-; CHECK-NEXT: vrsub.vx v8, v9, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i32> @llvm.riscv.vrsub.mask.nxv1i32.i32(
- <vscale x 1 x i32> %0,
- <vscale x 1 x i32> %1,
- i32 %2,
- <vscale x 1 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 1 x i32> %a
-}
-
-declare <vscale x 2 x i32> @llvm.riscv.vrsub.nxv2i32.i32(
- <vscale x 2 x i32>,
- <vscale x 2 x i32>,
- i32,
- i64);
-
-define <vscale x 2 x i32> @intrinsic_vrsub_vx_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, i32 %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vrsub_vx_nxv2i32_nxv2i32_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
-; CHECK-NEXT: vrsub.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i32> @llvm.riscv.vrsub.nxv2i32.i32(
- <vscale x 2 x i32> undef,
- <vscale x 2 x i32> %0,
- i32 %1,
- i64 %2)
-
- ret <vscale x 2 x i32> %a
-}
-
-declare <vscale x 2 x i32> @llvm.riscv.vrsub.mask.nxv2i32.i32(
- <vscale x 2 x i32>,
- <vscale x 2 x i32>,
- i32,
- <vscale x 2 x i1>,
- i64,
- i64);
-
-define <vscale x 2 x i32> @intrinsic_vrsub_mask_vx_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vrsub_mask_vx_nxv2i32_nxv2i32_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
-; CHECK-NEXT: vrsub.vx v8, v9, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i32> @llvm.riscv.vrsub.mask.nxv2i32.i32(
- <vscale x 2 x i32> %0,
- <vscale x 2 x i32> %1,
- i32 %2,
- <vscale x 2 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 2 x i32> %a
-}
-
-declare <vscale x 4 x i32> @llvm.riscv.vrsub.nxv4i32.i32(
- <vscale x 4 x i32>,
- <vscale x 4 x i32>,
- i32,
- i64);
-
-define <vscale x 4 x i32> @intrinsic_vrsub_vx_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, i32 %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vrsub_vx_nxv4i32_nxv4i32_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; CHECK-NEXT: vrsub.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i32> @llvm.riscv.vrsub.nxv4i32.i32(
- <vscale x 4 x i32> undef,
- <vscale x 4 x i32> %0,
- i32 %1,
- i64 %2)
-
- ret <vscale x 4 x i32> %a
-}
-
-declare <vscale x 4 x i32> @llvm.riscv.vrsub.mask.nxv4i32.i32(
- <vscale x 4 x i32>,
- <vscale x 4 x i32>,
- i32,
- <vscale x 4 x i1>,
- i64,
- i64);
-
-define <vscale x 4 x i32> @intrinsic_vrsub_mask_vx_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vrsub_mask_vx_nxv4i32_nxv4i32_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; CHECK-NEXT: vrsub.vx v8, v10, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i32> @llvm.riscv.vrsub.mask.nxv4i32.i32(
- <vscale x 4 x i32> %0,
- <vscale x 4 x i32> %1,
- i32 %2,
- <vscale x 4 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 4 x i32> %a
-}
-
-declare <vscale x 8 x i32> @llvm.riscv.vrsub.nxv8i32.i32(
- <vscale x 8 x i32>,
- <vscale x 8 x i32>,
- i32,
- i64);
-
-define <vscale x 8 x i32> @intrinsic_vrsub_vx_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, i32 %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vrsub_vx_nxv8i32_nxv8i32_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
-; CHECK-NEXT: vrsub.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i32> @llvm.riscv.vrsub.nxv8i32.i32(
- <vscale x 8 x i32> undef,
- <vscale x 8 x i32> %0,
- i32 %1,
- i64 %2)
-
- ret <vscale x 8 x i32> %a
-}
-
-declare <vscale x 8 x i32> @llvm.riscv.vrsub.mask.nxv8i32.i32(
- <vscale x 8 x i32>,
- <vscale x 8 x i32>,
- i32,
- <vscale x 8 x i1>,
- i64,
- i64);
-
-define <vscale x 8 x i32> @intrinsic_vrsub_mask_vx_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vrsub_mask_vx_nxv8i32_nxv8i32_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
-; CHECK-NEXT: vrsub.vx v8, v12, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i32> @llvm.riscv.vrsub.mask.nxv8i32.i32(
- <vscale x 8 x i32> %0,
- <vscale x 8 x i32> %1,
- i32 %2,
- <vscale x 8 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 8 x i32> %a
-}
-
-declare <vscale x 16 x i32> @llvm.riscv.vrsub.nxv16i32.i32(
- <vscale x 16 x i32>,
- <vscale x 16 x i32>,
- i32,
- i64);
-
-define <vscale x 16 x i32> @intrinsic_vrsub_vx_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, i32 %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vrsub_vx_nxv16i32_nxv16i32_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu
-; CHECK-NEXT: vrsub.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i32> @llvm.riscv.vrsub.nxv16i32.i32(
- <vscale x 16 x i32> undef,
- <vscale x 16 x i32> %0,
- i32 %1,
- i64 %2)
-
- ret <vscale x 16 x i32> %a
-}
-
-declare <vscale x 16 x i32> @llvm.riscv.vrsub.mask.nxv16i32.i32(
- <vscale x 16 x i32>,
- <vscale x 16 x i32>,
- i32,
- <vscale x 16 x i1>,
- i64,
- i64);
-
-define <vscale x 16 x i32> @intrinsic_vrsub_mask_vx_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vrsub_mask_vx_nxv16i32_nxv16i32_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu
-; CHECK-NEXT: vrsub.vx v8, v16, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i32> @llvm.riscv.vrsub.mask.nxv16i32.i32(
- <vscale x 16 x i32> %0,
- <vscale x 16 x i32> %1,
- i32 %2,
- <vscale x 16 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 16 x i32> %a
-}
-
-declare <vscale x 1 x i64> @llvm.riscv.vrsub.nxv1i64.i64(
- <vscale x 1 x i64>,
- <vscale x 1 x i64>,
- i64,
- i64);
-
-define <vscale x 1 x i64> @intrinsic_vrsub_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vrsub_vx_nxv1i64_nxv1i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
-; CHECK-NEXT: vrsub.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i64> @llvm.riscv.vrsub.nxv1i64.i64(
- <vscale x 1 x i64> undef,
- <vscale x 1 x i64> %0,
- i64 %1,
- i64 %2)
-
- ret <vscale x 1 x i64> %a
-}
-
-declare <vscale x 1 x i64> @llvm.riscv.vrsub.mask.nxv1i64.i64(
- <vscale x 1 x i64>,
- <vscale x 1 x i64>,
- i64,
- <vscale x 1 x i1>,
- i64,
- i64);
-
-define <vscale x 1 x i64> @intrinsic_vrsub_mask_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vrsub_mask_vx_nxv1i64_nxv1i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
-; CHECK-NEXT: vrsub.vx v8, v9, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i64> @llvm.riscv.vrsub.mask.nxv1i64.i64(
- <vscale x 1 x i64> %0,
- <vscale x 1 x i64> %1,
- i64 %2,
- <vscale x 1 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 1 x i64> %a
-}
-
-declare <vscale x 2 x i64> @llvm.riscv.vrsub.nxv2i64.i64(
- <vscale x 2 x i64>,
- <vscale x 2 x i64>,
- i64,
- i64);
-
-define <vscale x 2 x i64> @intrinsic_vrsub_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vrsub_vx_nxv2i64_nxv2i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
-; CHECK-NEXT: vrsub.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i64> @llvm.riscv.vrsub.nxv2i64.i64(
- <vscale x 2 x i64> undef,
- <vscale x 2 x i64> %0,
- i64 %1,
- i64 %2)
-
- ret <vscale x 2 x i64> %a
-}
-
-declare <vscale x 2 x i64> @llvm.riscv.vrsub.mask.nxv2i64.i64(
- <vscale x 2 x i64>,
- <vscale x 2 x i64>,
- i64,
- <vscale x 2 x i1>,
- i64,
- i64);
-
-define <vscale x 2 x i64> @intrinsic_vrsub_mask_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vrsub_mask_vx_nxv2i64_nxv2i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
-; CHECK-NEXT: vrsub.vx v8, v10, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i64> @llvm.riscv.vrsub.mask.nxv2i64.i64(
- <vscale x 2 x i64> %0,
- <vscale x 2 x i64> %1,
- i64 %2,
- <vscale x 2 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 2 x i64> %a
-}
-
-declare <vscale x 4 x i64> @llvm.riscv.vrsub.nxv4i64.i64(
- <vscale x 4 x i64>,
- <vscale x 4 x i64>,
- i64,
- i64);
-
-define <vscale x 4 x i64> @intrinsic_vrsub_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vrsub_vx_nxv4i64_nxv4i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
-; CHECK-NEXT: vrsub.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i64> @llvm.riscv.vrsub.nxv4i64.i64(
- <vscale x 4 x i64> undef,
- <vscale x 4 x i64> %0,
- i64 %1,
- i64 %2)
-
- ret <vscale x 4 x i64> %a
-}
-
-declare <vscale x 4 x i64> @llvm.riscv.vrsub.mask.nxv4i64.i64(
- <vscale x 4 x i64>,
- <vscale x 4 x i64>,
- i64,
- <vscale x 4 x i1>,
- i64,
- i64);
-
-define <vscale x 4 x i64> @intrinsic_vrsub_mask_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vrsub_mask_vx_nxv4i64_nxv4i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
-; CHECK-NEXT: vrsub.vx v8, v12, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i64> @llvm.riscv.vrsub.mask.nxv4i64.i64(
- <vscale x 4 x i64> %0,
- <vscale x 4 x i64> %1,
- i64 %2,
- <vscale x 4 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 4 x i64> %a
-}
-
-declare <vscale x 8 x i64> @llvm.riscv.vrsub.nxv8i64.i64(
- <vscale x 8 x i64>,
- <vscale x 8 x i64>,
- i64,
- i64);
-
-define <vscale x 8 x i64> @intrinsic_vrsub_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, i64 %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vrsub_vx_nxv8i64_nxv8i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu
-; CHECK-NEXT: vrsub.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i64> @llvm.riscv.vrsub.nxv8i64.i64(
- <vscale x 8 x i64> undef,
- <vscale x 8 x i64> %0,
- i64 %1,
- i64 %2)
-
- ret <vscale x 8 x i64> %a
-}
-
-declare <vscale x 8 x i64> @llvm.riscv.vrsub.mask.nxv8i64.i64(
- <vscale x 8 x i64>,
- <vscale x 8 x i64>,
- i64,
- <vscale x 8 x i1>,
- i64,
- i64);
-
-define <vscale x 8 x i64> @intrinsic_vrsub_mask_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vrsub_mask_vx_nxv8i64_nxv8i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu
-; CHECK-NEXT: vrsub.vx v8, v16, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i64> @llvm.riscv.vrsub.mask.nxv8i64.i64(
- <vscale x 8 x i64> %0,
- <vscale x 8 x i64> %1,
- i64 %2,
- <vscale x 8 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 8 x i64> %a
-}
-
-define <vscale x 1 x i8> @intrinsic_vrsub_vi_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, i64 %1) nounwind {
-; CHECK-LABEL: intrinsic_vrsub_vi_nxv1i8_nxv1i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
-; CHECK-NEXT: vrsub.vi v8, v8, 9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i8> @llvm.riscv.vrsub.nxv1i8.i8(
- <vscale x 1 x i8> undef,
- <vscale x 1 x i8> %0,
- i8 9,
- i64 %1)
-
- ret <vscale x 1 x i8> %a
-}
-
-define <vscale x 1 x i8> @intrinsic_vrsub_mask_vi_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv1i8_nxv1i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
-; CHECK-NEXT: vrsub.vi v8, v9, 9, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i8> @llvm.riscv.vrsub.mask.nxv1i8.i8(
- <vscale x 1 x i8> %0,
- <vscale x 1 x i8> %1,
- i8 9,
- <vscale x 1 x i1> %2,
- i64 %3, i64 1)
-
- ret <vscale x 1 x i8> %a
-}
-
-define <vscale x 2 x i8> @intrinsic_vrsub_vi_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, i64 %1) nounwind {
-; CHECK-LABEL: intrinsic_vrsub_vi_nxv2i8_nxv2i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
-; CHECK-NEXT: vrsub.vi v8, v8, 9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i8> @llvm.riscv.vrsub.nxv2i8.i8(
- <vscale x 2 x i8> undef,
- <vscale x 2 x i8> %0,
- i8 9,
- i64 %1)
-
- ret <vscale x 2 x i8> %a
-}
-
-define <vscale x 2 x i8> @intrinsic_vrsub_mask_vi_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv2i8_nxv2i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
-; CHECK-NEXT: vrsub.vi v8, v9, 9, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i8> @llvm.riscv.vrsub.mask.nxv2i8.i8(
- <vscale x 2 x i8> %0,
- <vscale x 2 x i8> %1,
- i8 9,
- <vscale x 2 x i1> %2,
- i64 %3, i64 1)
-
- ret <vscale x 2 x i8> %a
-}
-
-define <vscale x 4 x i8> @intrinsic_vrsub_vi_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, i64 %1) nounwind {
-; CHECK-LABEL: intrinsic_vrsub_vi_nxv4i8_nxv4i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
-; CHECK-NEXT: vrsub.vi v8, v8, 9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i8> @llvm.riscv.vrsub.nxv4i8.i8(
- <vscale x 4 x i8> undef,
- <vscale x 4 x i8> %0,
- i8 9,
- i64 %1)
-
- ret <vscale x 4 x i8> %a
-}
-
-define <vscale x 4 x i8> @intrinsic_vrsub_mask_vi_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv4i8_nxv4i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
-; CHECK-NEXT: vrsub.vi v8, v9, 9, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i8> @llvm.riscv.vrsub.mask.nxv4i8.i8(
- <vscale x 4 x i8> %0,
- <vscale x 4 x i8> %1,
- i8 9,
- <vscale x 4 x i1> %2,
- i64 %3, i64 1)
-
- ret <vscale x 4 x i8> %a
-}
-
-define <vscale x 8 x i8> @intrinsic_vrsub_vi_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, i64 %1) nounwind {
-; CHECK-LABEL: intrinsic_vrsub_vi_nxv8i8_nxv8i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
-; CHECK-NEXT: vrsub.vi v8, v8, 9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i8> @llvm.riscv.vrsub.nxv8i8.i8(
- <vscale x 8 x i8> undef,
- <vscale x 8 x i8> %0,
- i8 9,
- i64 %1)
-
- ret <vscale x 8 x i8> %a
-}
-
-define <vscale x 8 x i8> @intrinsic_vrsub_mask_vi_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv8i8_nxv8i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
-; CHECK-NEXT: vrsub.vi v8, v9, 9, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i8> @llvm.riscv.vrsub.mask.nxv8i8.i8(
- <vscale x 8 x i8> %0,
- <vscale x 8 x i8> %1,
- i8 9,
- <vscale x 8 x i1> %2,
- i64 %3, i64 1)
-
- ret <vscale x 8 x i8> %a
-}
-
-define <vscale x 16 x i8> @intrinsic_vrsub_vi_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, i64 %1) nounwind {
-; CHECK-LABEL: intrinsic_vrsub_vi_nxv16i8_nxv16i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
-; CHECK-NEXT: vrsub.vi v8, v8, 9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i8> @llvm.riscv.vrsub.nxv16i8.i8(
- <vscale x 16 x i8> undef,
- <vscale x 16 x i8> %0,
- i8 9,
- i64 %1)
-
- ret <vscale x 16 x i8> %a
-}
-
-define <vscale x 16 x i8> @intrinsic_vrsub_mask_vi_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i1> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv16i8_nxv16i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
-; CHECK-NEXT: vrsub.vi v8, v10, 9, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i8> @llvm.riscv.vrsub.mask.nxv16i8.i8(
- <vscale x 16 x i8> %0,
- <vscale x 16 x i8> %1,
- i8 9,
- <vscale x 16 x i1> %2,
- i64 %3, i64 1)
-
- ret <vscale x 16 x i8> %a
-}
-
-define <vscale x 32 x i8> @intrinsic_vrsub_vi_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, i64 %1) nounwind {
-; CHECK-LABEL: intrinsic_vrsub_vi_nxv32i8_nxv32i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
-; CHECK-NEXT: vrsub.vi v8, v8, 9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 32 x i8> @llvm.riscv.vrsub.nxv32i8.i8(
- <vscale x 32 x i8> undef,
- <vscale x 32 x i8> %0,
- i8 9,
- i64 %1)
-
- ret <vscale x 32 x i8> %a
-}
-
-define <vscale x 32 x i8> @intrinsic_vrsub_mask_vi_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i1> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv32i8_nxv32i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
-; CHECK-NEXT: vrsub.vi v8, v12, 9, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 32 x i8> @llvm.riscv.vrsub.mask.nxv32i8.i8(
- <vscale x 32 x i8> %0,
- <vscale x 32 x i8> %1,
- i8 9,
- <vscale x 32 x i1> %2,
- i64 %3, i64 1)
-
- ret <vscale x 32 x i8> %a
-}
-
-define <vscale x 64 x i8> @intrinsic_vrsub_vi_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, i64 %1) nounwind {
-; CHECK-LABEL: intrinsic_vrsub_vi_nxv64i8_nxv64i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, mu
-; CHECK-NEXT: vrsub.vi v8, v8, 9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 64 x i8> @llvm.riscv.vrsub.nxv64i8.i8(
- <vscale x 64 x i8> undef,
- <vscale x 64 x i8> %0,
- i8 9,
- i64 %1)
-
- ret <vscale x 64 x i8> %a
-}
-
-define <vscale x 64 x i8> @intrinsic_vrsub_mask_vi_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i1> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv64i8_nxv64i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, mu
-; CHECK-NEXT: vrsub.vi v8, v16, 9, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 64 x i8> @llvm.riscv.vrsub.mask.nxv64i8.i8(
- <vscale x 64 x i8> %0,
- <vscale x 64 x i8> %1,
- i8 9,
- <vscale x 64 x i1> %2,
- i64 %3, i64 1)
-
- ret <vscale x 64 x i8> %a
-}
-
-define <vscale x 1 x i16> @intrinsic_vrsub_vi_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, i64 %1) nounwind {
-; CHECK-LABEL: intrinsic_vrsub_vi_nxv1i16_nxv1i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vrsub.vi v8, v8, 9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i16> @llvm.riscv.vrsub.nxv1i16.i16(
- <vscale x 1 x i16> undef,
- <vscale x 1 x i16> %0,
- i16 9,
- i64 %1)
-
- ret <vscale x 1 x i16> %a
-}
-
-define <vscale x 1 x i16> @intrinsic_vrsub_mask_vi_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv1i16_nxv1i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vrsub.vi v8, v9, 9, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i16> @llvm.riscv.vrsub.mask.nxv1i16.i16(
- <vscale x 1 x i16> %0,
- <vscale x 1 x i16> %1,
- i16 9,
- <vscale x 1 x i1> %2,
- i64 %3, i64 1)
-
- ret <vscale x 1 x i16> %a
-}
-
-define <vscale x 2 x i16> @intrinsic_vrsub_vi_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, i64 %1) nounwind {
-; CHECK-LABEL: intrinsic_vrsub_vi_nxv2i16_nxv2i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vrsub.vi v8, v8, 9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i16> @llvm.riscv.vrsub.nxv2i16.i16(
- <vscale x 2 x i16> undef,
- <vscale x 2 x i16> %0,
- i16 9,
- i64 %1)
-
- ret <vscale x 2 x i16> %a
-}
-
-define <vscale x 2 x i16> @intrinsic_vrsub_mask_vi_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv2i16_nxv2i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vrsub.vi v8, v9, 9, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i16> @llvm.riscv.vrsub.mask.nxv2i16.i16(
- <vscale x 2 x i16> %0,
- <vscale x 2 x i16> %1,
- i16 9,
- <vscale x 2 x i1> %2,
- i64 %3, i64 1)
-
- ret <vscale x 2 x i16> %a
-}
-
-define <vscale x 4 x i16> @intrinsic_vrsub_vi_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, i64 %1) nounwind {
-; CHECK-LABEL: intrinsic_vrsub_vi_nxv4i16_nxv4i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vrsub.vi v8, v8, 9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i16> @llvm.riscv.vrsub.nxv4i16.i16(
- <vscale x 4 x i16> undef,
- <vscale x 4 x i16> %0,
- i16 9,
- i64 %1)
-
- ret <vscale x 4 x i16> %a
-}
-
-define <vscale x 4 x i16> @intrinsic_vrsub_mask_vi_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv4i16_nxv4i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vrsub.vi v8, v9, 9, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i16> @llvm.riscv.vrsub.mask.nxv4i16.i16(
- <vscale x 4 x i16> %0,
- <vscale x 4 x i16> %1,
- i16 9,
- <vscale x 4 x i1> %2,
- i64 %3, i64 1)
-
- ret <vscale x 4 x i16> %a
-}
-
-define <vscale x 8 x i16> @intrinsic_vrsub_vi_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, i64 %1) nounwind {
-; CHECK-LABEL: intrinsic_vrsub_vi_nxv8i16_nxv8i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vrsub.vi v8, v8, 9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i16> @llvm.riscv.vrsub.nxv8i16.i16(
- <vscale x 8 x i16> undef,
- <vscale x 8 x i16> %0,
- i16 9,
- i64 %1)
-
- ret <vscale x 8 x i16> %a
-}
-
-define <vscale x 8 x i16> @intrinsic_vrsub_mask_vi_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv8i16_nxv8i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vrsub.vi v8, v10, 9, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i16> @llvm.riscv.vrsub.mask.nxv8i16.i16(
- <vscale x 8 x i16> %0,
- <vscale x 8 x i16> %1,
- i16 9,
- <vscale x 8 x i1> %2,
- i64 %3, i64 1)
-
- ret <vscale x 8 x i16> %a
-}
-
-define <vscale x 16 x i16> @intrinsic_vrsub_vi_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, i64 %1) nounwind {
-; CHECK-LABEL: intrinsic_vrsub_vi_nxv16i16_nxv16i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
-; CHECK-NEXT: vrsub.vi v8, v8, 9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i16> @llvm.riscv.vrsub.nxv16i16.i16(
- <vscale x 16 x i16> undef,
- <vscale x 16 x i16> %0,
- i16 9,
- i64 %1)
-
- ret <vscale x 16 x i16> %a
-}
-
-define <vscale x 16 x i16> @intrinsic_vrsub_mask_vi_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i1> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv16i16_nxv16i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
-; CHECK-NEXT: vrsub.vi v8, v12, 9, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i16> @llvm.riscv.vrsub.mask.nxv16i16.i16(
- <vscale x 16 x i16> %0,
- <vscale x 16 x i16> %1,
- i16 9,
- <vscale x 16 x i1> %2,
- i64 %3, i64 1)
-
- ret <vscale x 16 x i16> %a
-}
-
-define <vscale x 32 x i16> @intrinsic_vrsub_vi_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, i64 %1) nounwind {
-; CHECK-LABEL: intrinsic_vrsub_vi_nxv32i16_nxv32i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, mu
-; CHECK-NEXT: vrsub.vi v8, v8, 9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 32 x i16> @llvm.riscv.vrsub.nxv32i16.i16(
- <vscale x 32 x i16> undef,
- <vscale x 32 x i16> %0,
- i16 9,
- i64 %1)
-
- ret <vscale x 32 x i16> %a
-}
-
-define <vscale x 32 x i16> @intrinsic_vrsub_mask_vi_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i1> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv32i16_nxv32i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, mu
-; CHECK-NEXT: vrsub.vi v8, v16, 9, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 32 x i16> @llvm.riscv.vrsub.mask.nxv32i16.i16(
- <vscale x 32 x i16> %0,
- <vscale x 32 x i16> %1,
- i16 9,
- <vscale x 32 x i1> %2,
- i64 %3, i64 1)
-
- ret <vscale x 32 x i16> %a
-}
-
-define <vscale x 1 x i32> @intrinsic_vrsub_vi_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, i64 %1) nounwind {
-; CHECK-LABEL: intrinsic_vrsub_vi_nxv1i32_nxv1i32_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vrsub.vi v8, v8, 9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i32> @llvm.riscv.vrsub.nxv1i32.i32(
- <vscale x 1 x i32> undef,
- <vscale x 1 x i32> %0,
- i32 9,
- i64 %1)
-
- ret <vscale x 1 x i32> %a
-}
-
-define <vscale x 1 x i32> @intrinsic_vrsub_mask_vi_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv1i32_nxv1i32_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vrsub.vi v8, v9, 9, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i32> @llvm.riscv.vrsub.mask.nxv1i32.i32(
- <vscale x 1 x i32> %0,
- <vscale x 1 x i32> %1,
- i32 9,
- <vscale x 1 x i1> %2,
- i64 %3, i64 1)
-
- ret <vscale x 1 x i32> %a
-}
-
-define <vscale x 2 x i32> @intrinsic_vrsub_vi_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, i64 %1) nounwind {
-; CHECK-LABEL: intrinsic_vrsub_vi_nxv2i32_nxv2i32_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vrsub.vi v8, v8, 9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i32> @llvm.riscv.vrsub.nxv2i32.i32(
- <vscale x 2 x i32> undef,
- <vscale x 2 x i32> %0,
- i32 9,
- i64 %1)
-
- ret <vscale x 2 x i32> %a
-}
-
-define <vscale x 2 x i32> @intrinsic_vrsub_mask_vi_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv2i32_nxv2i32_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vrsub.vi v8, v9, 9, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i32> @llvm.riscv.vrsub.mask.nxv2i32.i32(
- <vscale x 2 x i32> %0,
- <vscale x 2 x i32> %1,
- i32 9,
- <vscale x 2 x i1> %2,
- i64 %3, i64 1)
-
- ret <vscale x 2 x i32> %a
-}
-
-define <vscale x 4 x i32> @intrinsic_vrsub_vi_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, i64 %1) nounwind {
-; CHECK-LABEL: intrinsic_vrsub_vi_nxv4i32_nxv4i32_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vrsub.vi v8, v8, 9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i32> @llvm.riscv.vrsub.nxv4i32.i32(
- <vscale x 4 x i32> undef,
- <vscale x 4 x i32> %0,
- i32 9,
- i64 %1)
-
- ret <vscale x 4 x i32> %a
-}
-
-define <vscale x 4 x i32> @intrinsic_vrsub_mask_vi_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv4i32_nxv4i32_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vrsub.vi v8, v10, 9, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i32> @llvm.riscv.vrsub.mask.nxv4i32.i32(
- <vscale x 4 x i32> %0,
- <vscale x 4 x i32> %1,
- i32 9,
- <vscale x 4 x i1> %2,
- i64 %3, i64 1)
-
- ret <vscale x 4 x i32> %a
-}
-
-define <vscale x 8 x i32> @intrinsic_vrsub_vi_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, i64 %1) nounwind {
-; CHECK-LABEL: intrinsic_vrsub_vi_nxv8i32_nxv8i32_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
-; CHECK-NEXT: vrsub.vi v8, v8, 9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i32> @llvm.riscv.vrsub.nxv8i32.i32(
- <vscale x 8 x i32> undef,
- <vscale x 8 x i32> %0,
- i32 9,
- i64 %1)
-
- ret <vscale x 8 x i32> %a
-}
-
-define <vscale x 8 x i32> @intrinsic_vrsub_mask_vi_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv8i32_nxv8i32_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
-; CHECK-NEXT: vrsub.vi v8, v12, 9, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i32> @llvm.riscv.vrsub.mask.nxv8i32.i32(
- <vscale x 8 x i32> %0,
- <vscale x 8 x i32> %1,
- i32 9,
- <vscale x 8 x i1> %2,
- i64 %3, i64 1)
-
- ret <vscale x 8 x i32> %a
-}
-
-define <vscale x 16 x i32> @intrinsic_vrsub_vi_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, i64 %1) nounwind {
-; CHECK-LABEL: intrinsic_vrsub_vi_nxv16i32_nxv16i32_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu
-; CHECK-NEXT: vrsub.vi v8, v8, 9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i32> @llvm.riscv.vrsub.nxv16i32.i32(
- <vscale x 16 x i32> undef,
- <vscale x 16 x i32> %0,
- i32 9,
- i64 %1)
-
- ret <vscale x 16 x i32> %a
-}
-
-define <vscale x 16 x i32> @intrinsic_vrsub_mask_vi_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i1> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv16i32_nxv16i32_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu
-; CHECK-NEXT: vrsub.vi v8, v16, 9, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i32> @llvm.riscv.vrsub.mask.nxv16i32.i32(
- <vscale x 16 x i32> %0,
- <vscale x 16 x i32> %1,
- i32 9,
- <vscale x 16 x i1> %2,
- i64 %3, i64 1)
-
- ret <vscale x 16 x i32> %a
-}
-
-define <vscale x 1 x i64> @intrinsic_vrsub_vi_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1) nounwind {
-; CHECK-LABEL: intrinsic_vrsub_vi_nxv1i64_nxv1i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
-; CHECK-NEXT: vrsub.vi v8, v8, 9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i64> @llvm.riscv.vrsub.nxv1i64.i64(
- <vscale x 1 x i64> undef,
- <vscale x 1 x i64> %0,
- i64 9,
- i64 %1)
-
- ret <vscale x 1 x i64> %a
-}
-
-define <vscale x 1 x i64> @intrinsic_vrsub_mask_vi_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv1i64_nxv1i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
-; CHECK-NEXT: vrsub.vi v8, v9, 9, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i64> @llvm.riscv.vrsub.mask.nxv1i64.i64(
- <vscale x 1 x i64> %0,
- <vscale x 1 x i64> %1,
- i64 9,
- <vscale x 1 x i1> %2,
- i64 %3, i64 1)
-
- ret <vscale x 1 x i64> %a
-}
-
-define <vscale x 2 x i64> @intrinsic_vrsub_vi_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1) nounwind {
-; CHECK-LABEL: intrinsic_vrsub_vi_nxv2i64_nxv2i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
-; CHECK-NEXT: vrsub.vi v8, v8, 9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i64> @llvm.riscv.vrsub.nxv2i64.i64(
- <vscale x 2 x i64> undef,
- <vscale x 2 x i64> %0,
- i64 9,
- i64 %1)
-
- ret <vscale x 2 x i64> %a
-}
-
-define <vscale x 2 x i64> @intrinsic_vrsub_mask_vi_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv2i64_nxv2i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
-; CHECK-NEXT: vrsub.vi v8, v10, 9, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i64> @llvm.riscv.vrsub.mask.nxv2i64.i64(
- <vscale x 2 x i64> %0,
- <vscale x 2 x i64> %1,
- i64 9,
- <vscale x 2 x i1> %2,
- i64 %3, i64 1)
-
- ret <vscale x 2 x i64> %a
-}
-
-define <vscale x 4 x i64> @intrinsic_vrsub_vi_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1) nounwind {
-; CHECK-LABEL: intrinsic_vrsub_vi_nxv4i64_nxv4i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
-; CHECK-NEXT: vrsub.vi v8, v8, 9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i64> @llvm.riscv.vrsub.nxv4i64.i64(
- <vscale x 4 x i64> undef,
- <vscale x 4 x i64> %0,
- i64 9,
- i64 %1)
-
- ret <vscale x 4 x i64> %a
-}
-
-define <vscale x 4 x i64> @intrinsic_vrsub_mask_vi_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv4i64_nxv4i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
-; CHECK-NEXT: vrsub.vi v8, v12, 9, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i64> @llvm.riscv.vrsub.mask.nxv4i64.i64(
- <vscale x 4 x i64> %0,
- <vscale x 4 x i64> %1,
- i64 9,
- <vscale x 4 x i1> %2,
- i64 %3, i64 1)
-
- ret <vscale x 4 x i64> %a
-}
-
-define <vscale x 8 x i64> @intrinsic_vrsub_vi_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, i64 %1) nounwind {
-; CHECK-LABEL: intrinsic_vrsub_vi_nxv8i64_nxv8i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu
-; CHECK-NEXT: vrsub.vi v8, v8, 9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i64> @llvm.riscv.vrsub.nxv8i64.i64(
- <vscale x 8 x i64> undef,
- <vscale x 8 x i64> %0,
- i64 9,
- i64 %1)
-
- ret <vscale x 8 x i64> %a
-}
-
-define <vscale x 8 x i64> @intrinsic_vrsub_mask_vi_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv8i64_nxv8i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu
-; CHECK-NEXT: vrsub.vi v8, v16, 9, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i64> @llvm.riscv.vrsub.mask.nxv8i64.i64(
- <vscale x 8 x i64> %0,
- <vscale x 8 x i64> %1,
- i64 9,
- <vscale x 8 x i1> %2,
- i64 %3, i64 1)
-
- ret <vscale x 8 x i64> %a
-}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vrsub-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vrsub.ll
similarity index 80%
rename from llvm/test/CodeGen/RISCV/rvv/vrsub-rv32.ll
rename to llvm/test/CodeGen/RISCV/rvv/vrsub.ll
index 422d326e248da..24099fb1b55b2 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vrsub-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vrsub.ll
@@ -1,13 +1,15 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs \
-; RUN: < %s | FileCheck %s
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v \
+; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,RV32
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v \
+; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,RV64
declare <vscale x 1 x i8> @llvm.riscv.vrsub.nxv1i8.i8(
<vscale x 1 x i8>,
<vscale x 1 x i8>,
i8,
- i32);
+ iXLen);
-define <vscale x 1 x i8> @intrinsic_vrsub_vx_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, i8 %1, i32 %2) nounwind {
+define <vscale x 1 x i8> @intrinsic_vrsub_vx_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, i8 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vrsub_vx_nxv1i8_nxv1i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
@@ -18,7 +20,7 @@ entry:
<vscale x 1 x i8> undef,
<vscale x 1 x i8> %0,
i8 %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 1 x i8> %a
}
@@ -28,10 +30,9 @@ declare <vscale x 1 x i8> @llvm.riscv.vrsub.mask.nxv1i8.i8(
<vscale x 1 x i8>,
i8,
<vscale x 1 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 1 x i8> @intrinsic_vrsub_mask_vx_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+define <vscale x 1 x i8> @intrinsic_vrsub_mask_vx_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vrsub_mask_vx_nxv1i8_nxv1i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
@@ -43,7 +44,7 @@ entry:
<vscale x 1 x i8> %1,
i8 %2,
<vscale x 1 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 1 x i8> %a
}
@@ -52,9 +53,9 @@ declare <vscale x 2 x i8> @llvm.riscv.vrsub.nxv2i8.i8(
<vscale x 2 x i8>,
<vscale x 2 x i8>,
i8,
- i32);
+ iXLen);
-define <vscale x 2 x i8> @intrinsic_vrsub_vx_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, i8 %1, i32 %2) nounwind {
+define <vscale x 2 x i8> @intrinsic_vrsub_vx_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, i8 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vrsub_vx_nxv2i8_nxv2i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
@@ -65,7 +66,7 @@ entry:
<vscale x 2 x i8> undef,
<vscale x 2 x i8> %0,
i8 %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 2 x i8> %a
}
@@ -75,10 +76,9 @@ declare <vscale x 2 x i8> @llvm.riscv.vrsub.mask.nxv2i8.i8(
<vscale x 2 x i8>,
i8,
<vscale x 2 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 2 x i8> @intrinsic_vrsub_mask_vx_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+define <vscale x 2 x i8> @intrinsic_vrsub_mask_vx_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vrsub_mask_vx_nxv2i8_nxv2i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
@@ -90,7 +90,7 @@ entry:
<vscale x 2 x i8> %1,
i8 %2,
<vscale x 2 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 2 x i8> %a
}
@@ -99,9 +99,9 @@ declare <vscale x 4 x i8> @llvm.riscv.vrsub.nxv4i8.i8(
<vscale x 4 x i8>,
<vscale x 4 x i8>,
i8,
- i32);
+ iXLen);
-define <vscale x 4 x i8> @intrinsic_vrsub_vx_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, i8 %1, i32 %2) nounwind {
+define <vscale x 4 x i8> @intrinsic_vrsub_vx_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, i8 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vrsub_vx_nxv4i8_nxv4i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
@@ -112,7 +112,7 @@ entry:
<vscale x 4 x i8> undef,
<vscale x 4 x i8> %0,
i8 %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 4 x i8> %a
}
@@ -122,10 +122,9 @@ declare <vscale x 4 x i8> @llvm.riscv.vrsub.mask.nxv4i8.i8(
<vscale x 4 x i8>,
i8,
<vscale x 4 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 4 x i8> @intrinsic_vrsub_mask_vx_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+define <vscale x 4 x i8> @intrinsic_vrsub_mask_vx_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vrsub_mask_vx_nxv4i8_nxv4i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
@@ -137,7 +136,7 @@ entry:
<vscale x 4 x i8> %1,
i8 %2,
<vscale x 4 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 4 x i8> %a
}
@@ -146,9 +145,9 @@ declare <vscale x 8 x i8> @llvm.riscv.vrsub.nxv8i8.i8(
<vscale x 8 x i8>,
<vscale x 8 x i8>,
i8,
- i32);
+ iXLen);
-define <vscale x 8 x i8> @intrinsic_vrsub_vx_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, i8 %1, i32 %2) nounwind {
+define <vscale x 8 x i8> @intrinsic_vrsub_vx_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, i8 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vrsub_vx_nxv8i8_nxv8i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
@@ -159,7 +158,7 @@ entry:
<vscale x 8 x i8> undef,
<vscale x 8 x i8> %0,
i8 %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 8 x i8> %a
}
@@ -169,10 +168,9 @@ declare <vscale x 8 x i8> @llvm.riscv.vrsub.mask.nxv8i8.i8(
<vscale x 8 x i8>,
i8,
<vscale x 8 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 8 x i8> @intrinsic_vrsub_mask_vx_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+define <vscale x 8 x i8> @intrinsic_vrsub_mask_vx_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vrsub_mask_vx_nxv8i8_nxv8i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
@@ -184,7 +182,7 @@ entry:
<vscale x 8 x i8> %1,
i8 %2,
<vscale x 8 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 8 x i8> %a
}
@@ -193,9 +191,9 @@ declare <vscale x 16 x i8> @llvm.riscv.vrsub.nxv16i8.i8(
<vscale x 16 x i8>,
<vscale x 16 x i8>,
i8,
- i32);
+ iXLen);
-define <vscale x 16 x i8> @intrinsic_vrsub_vx_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, i8 %1, i32 %2) nounwind {
+define <vscale x 16 x i8> @intrinsic_vrsub_vx_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, i8 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vrsub_vx_nxv16i8_nxv16i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
@@ -206,7 +204,7 @@ entry:
<vscale x 16 x i8> undef,
<vscale x 16 x i8> %0,
i8 %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 16 x i8> %a
}
@@ -216,10 +214,9 @@ declare <vscale x 16 x i8> @llvm.riscv.vrsub.mask.nxv16i8.i8(
<vscale x 16 x i8>,
i8,
<vscale x 16 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 16 x i8> @intrinsic_vrsub_mask_vx_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+define <vscale x 16 x i8> @intrinsic_vrsub_mask_vx_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vrsub_mask_vx_nxv16i8_nxv16i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
@@ -231,7 +228,7 @@ entry:
<vscale x 16 x i8> %1,
i8 %2,
<vscale x 16 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 16 x i8> %a
}
@@ -240,9 +237,9 @@ declare <vscale x 32 x i8> @llvm.riscv.vrsub.nxv32i8.i8(
<vscale x 32 x i8>,
<vscale x 32 x i8>,
i8,
- i32);
+ iXLen);
-define <vscale x 32 x i8> @intrinsic_vrsub_vx_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, i8 %1, i32 %2) nounwind {
+define <vscale x 32 x i8> @intrinsic_vrsub_vx_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, i8 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vrsub_vx_nxv32i8_nxv32i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
@@ -253,7 +250,7 @@ entry:
<vscale x 32 x i8> undef,
<vscale x 32 x i8> %0,
i8 %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 32 x i8> %a
}
@@ -263,10 +260,9 @@ declare <vscale x 32 x i8> @llvm.riscv.vrsub.mask.nxv32i8.i8(
<vscale x 32 x i8>,
i8,
<vscale x 32 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 32 x i8> @intrinsic_vrsub_mask_vx_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
+define <vscale x 32 x i8> @intrinsic_vrsub_mask_vx_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vrsub_mask_vx_nxv32i8_nxv32i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
@@ -278,7 +274,7 @@ entry:
<vscale x 32 x i8> %1,
i8 %2,
<vscale x 32 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 32 x i8> %a
}
@@ -287,9 +283,9 @@ declare <vscale x 64 x i8> @llvm.riscv.vrsub.nxv64i8.i8(
<vscale x 64 x i8>,
<vscale x 64 x i8>,
i8,
- i32);
+ iXLen);
-define <vscale x 64 x i8> @intrinsic_vrsub_vx_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, i8 %1, i32 %2) nounwind {
+define <vscale x 64 x i8> @intrinsic_vrsub_vx_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, i8 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vrsub_vx_nxv64i8_nxv64i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu
@@ -300,7 +296,7 @@ entry:
<vscale x 64 x i8> undef,
<vscale x 64 x i8> %0,
i8 %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 64 x i8> %a
}
@@ -310,10 +306,9 @@ declare <vscale x 64 x i8> @llvm.riscv.vrsub.mask.nxv64i8.i8(
<vscale x 64 x i8>,
i8,
<vscale x 64 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 64 x i8> @intrinsic_vrsub_mask_vx_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i8 %2, <vscale x 64 x i1> %3, i32 %4) nounwind {
+define <vscale x 64 x i8> @intrinsic_vrsub_mask_vx_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i8 %2, <vscale x 64 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vrsub_mask_vx_nxv64i8_nxv64i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu
@@ -325,7 +320,7 @@ entry:
<vscale x 64 x i8> %1,
i8 %2,
<vscale x 64 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 64 x i8> %a
}
@@ -334,9 +329,9 @@ declare <vscale x 1 x i16> @llvm.riscv.vrsub.nxv1i16.i16(
<vscale x 1 x i16>,
<vscale x 1 x i16>,
i16,
- i32);
+ iXLen);
-define <vscale x 1 x i16> @intrinsic_vrsub_vx_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, i16 %1, i32 %2) nounwind {
+define <vscale x 1 x i16> @intrinsic_vrsub_vx_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, i16 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vrsub_vx_nxv1i16_nxv1i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
@@ -347,7 +342,7 @@ entry:
<vscale x 1 x i16> undef,
<vscale x 1 x i16> %0,
i16 %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 1 x i16> %a
}
@@ -357,10 +352,9 @@ declare <vscale x 1 x i16> @llvm.riscv.vrsub.mask.nxv1i16.i16(
<vscale x 1 x i16>,
i16,
<vscale x 1 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 1 x i16> @intrinsic_vrsub_mask_vx_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+define <vscale x 1 x i16> @intrinsic_vrsub_mask_vx_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vrsub_mask_vx_nxv1i16_nxv1i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
@@ -372,7 +366,7 @@ entry:
<vscale x 1 x i16> %1,
i16 %2,
<vscale x 1 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 1 x i16> %a
}
@@ -381,9 +375,9 @@ declare <vscale x 2 x i16> @llvm.riscv.vrsub.nxv2i16.i16(
<vscale x 2 x i16>,
<vscale x 2 x i16>,
i16,
- i32);
+ iXLen);
-define <vscale x 2 x i16> @intrinsic_vrsub_vx_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, i16 %1, i32 %2) nounwind {
+define <vscale x 2 x i16> @intrinsic_vrsub_vx_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, i16 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vrsub_vx_nxv2i16_nxv2i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
@@ -394,7 +388,7 @@ entry:
<vscale x 2 x i16> undef,
<vscale x 2 x i16> %0,
i16 %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 2 x i16> %a
}
@@ -404,10 +398,9 @@ declare <vscale x 2 x i16> @llvm.riscv.vrsub.mask.nxv2i16.i16(
<vscale x 2 x i16>,
i16,
<vscale x 2 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 2 x i16> @intrinsic_vrsub_mask_vx_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+define <vscale x 2 x i16> @intrinsic_vrsub_mask_vx_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vrsub_mask_vx_nxv2i16_nxv2i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
@@ -419,7 +412,7 @@ entry:
<vscale x 2 x i16> %1,
i16 %2,
<vscale x 2 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 2 x i16> %a
}
@@ -428,9 +421,9 @@ declare <vscale x 4 x i16> @llvm.riscv.vrsub.nxv4i16.i16(
<vscale x 4 x i16>,
<vscale x 4 x i16>,
i16,
- i32);
+ iXLen);
-define <vscale x 4 x i16> @intrinsic_vrsub_vx_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, i16 %1, i32 %2) nounwind {
+define <vscale x 4 x i16> @intrinsic_vrsub_vx_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, i16 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vrsub_vx_nxv4i16_nxv4i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
@@ -441,7 +434,7 @@ entry:
<vscale x 4 x i16> undef,
<vscale x 4 x i16> %0,
i16 %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 4 x i16> %a
}
@@ -451,10 +444,9 @@ declare <vscale x 4 x i16> @llvm.riscv.vrsub.mask.nxv4i16.i16(
<vscale x 4 x i16>,
i16,
<vscale x 4 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 4 x i16> @intrinsic_vrsub_mask_vx_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+define <vscale x 4 x i16> @intrinsic_vrsub_mask_vx_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vrsub_mask_vx_nxv4i16_nxv4i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
@@ -466,7 +458,7 @@ entry:
<vscale x 4 x i16> %1,
i16 %2,
<vscale x 4 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 4 x i16> %a
}
@@ -475,9 +467,9 @@ declare <vscale x 8 x i16> @llvm.riscv.vrsub.nxv8i16.i16(
<vscale x 8 x i16>,
<vscale x 8 x i16>,
i16,
- i32);
+ iXLen);
-define <vscale x 8 x i16> @intrinsic_vrsub_vx_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, i16 %1, i32 %2) nounwind {
+define <vscale x 8 x i16> @intrinsic_vrsub_vx_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, i16 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vrsub_vx_nxv8i16_nxv8i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
@@ -488,7 +480,7 @@ entry:
<vscale x 8 x i16> undef,
<vscale x 8 x i16> %0,
i16 %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 8 x i16> %a
}
@@ -498,10 +490,9 @@ declare <vscale x 8 x i16> @llvm.riscv.vrsub.mask.nxv8i16.i16(
<vscale x 8 x i16>,
i16,
<vscale x 8 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 8 x i16> @intrinsic_vrsub_mask_vx_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+define <vscale x 8 x i16> @intrinsic_vrsub_mask_vx_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vrsub_mask_vx_nxv8i16_nxv8i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
@@ -513,7 +504,7 @@ entry:
<vscale x 8 x i16> %1,
i16 %2,
<vscale x 8 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 8 x i16> %a
}
@@ -522,9 +513,9 @@ declare <vscale x 16 x i16> @llvm.riscv.vrsub.nxv16i16.i16(
<vscale x 16 x i16>,
<vscale x 16 x i16>,
i16,
- i32);
+ iXLen);
-define <vscale x 16 x i16> @intrinsic_vrsub_vx_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, i16 %1, i32 %2) nounwind {
+define <vscale x 16 x i16> @intrinsic_vrsub_vx_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, i16 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vrsub_vx_nxv16i16_nxv16i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
@@ -535,7 +526,7 @@ entry:
<vscale x 16 x i16> undef,
<vscale x 16 x i16> %0,
i16 %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 16 x i16> %a
}
@@ -545,10 +536,9 @@ declare <vscale x 16 x i16> @llvm.riscv.vrsub.mask.nxv16i16.i16(
<vscale x 16 x i16>,
i16,
<vscale x 16 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 16 x i16> @intrinsic_vrsub_mask_vx_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+define <vscale x 16 x i16> @intrinsic_vrsub_mask_vx_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vrsub_mask_vx_nxv16i16_nxv16i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
@@ -560,7 +550,7 @@ entry:
<vscale x 16 x i16> %1,
i16 %2,
<vscale x 16 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 16 x i16> %a
}
@@ -569,9 +559,9 @@ declare <vscale x 32 x i16> @llvm.riscv.vrsub.nxv32i16.i16(
<vscale x 32 x i16>,
<vscale x 32 x i16>,
i16,
- i32);
+ iXLen);
-define <vscale x 32 x i16> @intrinsic_vrsub_vx_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, i16 %1, i32 %2) nounwind {
+define <vscale x 32 x i16> @intrinsic_vrsub_vx_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, i16 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vrsub_vx_nxv32i16_nxv32i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu
@@ -582,7 +572,7 @@ entry:
<vscale x 32 x i16> undef,
<vscale x 32 x i16> %0,
i16 %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 32 x i16> %a
}
@@ -592,10 +582,9 @@ declare <vscale x 32 x i16> @llvm.riscv.vrsub.mask.nxv32i16.i16(
<vscale x 32 x i16>,
i16,
<vscale x 32 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 32 x i16> @intrinsic_vrsub_mask_vx_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, i16 %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
+define <vscale x 32 x i16> @intrinsic_vrsub_mask_vx_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, i16 %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vrsub_mask_vx_nxv32i16_nxv32i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu
@@ -607,7 +596,7 @@ entry:
<vscale x 32 x i16> %1,
i16 %2,
<vscale x 32 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 32 x i16> %a
}
@@ -616,9 +605,9 @@ declare <vscale x 1 x i32> @llvm.riscv.vrsub.nxv1i32.i32(
<vscale x 1 x i32>,
<vscale x 1 x i32>,
i32,
- i32);
+ iXLen);
-define <vscale x 1 x i32> @intrinsic_vrsub_vx_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, i32 %1, i32 %2) nounwind {
+define <vscale x 1 x i32> @intrinsic_vrsub_vx_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, i32 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vrsub_vx_nxv1i32_nxv1i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
@@ -629,7 +618,7 @@ entry:
<vscale x 1 x i32> undef,
<vscale x 1 x i32> %0,
i32 %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 1 x i32> %a
}
@@ -639,10 +628,9 @@ declare <vscale x 1 x i32> @llvm.riscv.vrsub.mask.nxv1i32.i32(
<vscale x 1 x i32>,
i32,
<vscale x 1 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 1 x i32> @intrinsic_vrsub_mask_vx_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+define <vscale x 1 x i32> @intrinsic_vrsub_mask_vx_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vrsub_mask_vx_nxv1i32_nxv1i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
@@ -654,7 +642,7 @@ entry:
<vscale x 1 x i32> %1,
i32 %2,
<vscale x 1 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 1 x i32> %a
}
@@ -663,9 +651,9 @@ declare <vscale x 2 x i32> @llvm.riscv.vrsub.nxv2i32.i32(
<vscale x 2 x i32>,
<vscale x 2 x i32>,
i32,
- i32);
+ iXLen);
-define <vscale x 2 x i32> @intrinsic_vrsub_vx_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, i32 %1, i32 %2) nounwind {
+define <vscale x 2 x i32> @intrinsic_vrsub_vx_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, i32 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vrsub_vx_nxv2i32_nxv2i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
@@ -676,7 +664,7 @@ entry:
<vscale x 2 x i32> undef,
<vscale x 2 x i32> %0,
i32 %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 2 x i32> %a
}
@@ -686,10 +674,9 @@ declare <vscale x 2 x i32> @llvm.riscv.vrsub.mask.nxv2i32.i32(
<vscale x 2 x i32>,
i32,
<vscale x 2 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 2 x i32> @intrinsic_vrsub_mask_vx_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+define <vscale x 2 x i32> @intrinsic_vrsub_mask_vx_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vrsub_mask_vx_nxv2i32_nxv2i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
@@ -701,7 +688,7 @@ entry:
<vscale x 2 x i32> %1,
i32 %2,
<vscale x 2 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 2 x i32> %a
}
@@ -710,9 +697,9 @@ declare <vscale x 4 x i32> @llvm.riscv.vrsub.nxv4i32.i32(
<vscale x 4 x i32>,
<vscale x 4 x i32>,
i32,
- i32);
+ iXLen);
-define <vscale x 4 x i32> @intrinsic_vrsub_vx_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, i32 %1, i32 %2) nounwind {
+define <vscale x 4 x i32> @intrinsic_vrsub_vx_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, i32 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vrsub_vx_nxv4i32_nxv4i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
@@ -723,7 +710,7 @@ entry:
<vscale x 4 x i32> undef,
<vscale x 4 x i32> %0,
i32 %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 4 x i32> %a
}
@@ -733,10 +720,9 @@ declare <vscale x 4 x i32> @llvm.riscv.vrsub.mask.nxv4i32.i32(
<vscale x 4 x i32>,
i32,
<vscale x 4 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 4 x i32> @intrinsic_vrsub_mask_vx_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+define <vscale x 4 x i32> @intrinsic_vrsub_mask_vx_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vrsub_mask_vx_nxv4i32_nxv4i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
@@ -748,7 +734,7 @@ entry:
<vscale x 4 x i32> %1,
i32 %2,
<vscale x 4 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 4 x i32> %a
}
@@ -757,9 +743,9 @@ declare <vscale x 8 x i32> @llvm.riscv.vrsub.nxv8i32.i32(
<vscale x 8 x i32>,
<vscale x 8 x i32>,
i32,
- i32);
+ iXLen);
-define <vscale x 8 x i32> @intrinsic_vrsub_vx_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, i32 %1, i32 %2) nounwind {
+define <vscale x 8 x i32> @intrinsic_vrsub_vx_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, i32 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vrsub_vx_nxv8i32_nxv8i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
@@ -770,7 +756,7 @@ entry:
<vscale x 8 x i32> undef,
<vscale x 8 x i32> %0,
i32 %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 8 x i32> %a
}
@@ -780,10 +766,9 @@ declare <vscale x 8 x i32> @llvm.riscv.vrsub.mask.nxv8i32.i32(
<vscale x 8 x i32>,
i32,
<vscale x 8 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 8 x i32> @intrinsic_vrsub_mask_vx_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+define <vscale x 8 x i32> @intrinsic_vrsub_mask_vx_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vrsub_mask_vx_nxv8i32_nxv8i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
@@ -795,7 +780,7 @@ entry:
<vscale x 8 x i32> %1,
i32 %2,
<vscale x 8 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 8 x i32> %a
}
@@ -804,9 +789,9 @@ declare <vscale x 16 x i32> @llvm.riscv.vrsub.nxv16i32.i32(
<vscale x 16 x i32>,
<vscale x 16 x i32>,
i32,
- i32);
+ iXLen);
-define <vscale x 16 x i32> @intrinsic_vrsub_vx_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, i32 %1, i32 %2) nounwind {
+define <vscale x 16 x i32> @intrinsic_vrsub_vx_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, i32 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vrsub_vx_nxv16i32_nxv16i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu
@@ -817,7 +802,7 @@ entry:
<vscale x 16 x i32> undef,
<vscale x 16 x i32> %0,
i32 %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 16 x i32> %a
}
@@ -827,10 +812,9 @@ declare <vscale x 16 x i32> @llvm.riscv.vrsub.mask.nxv16i32.i32(
<vscale x 16 x i32>,
i32,
<vscale x 16 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 16 x i32> @intrinsic_vrsub_mask_vx_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+define <vscale x 16 x i32> @intrinsic_vrsub_mask_vx_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vrsub_mask_vx_nxv16i32_nxv16i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu
@@ -842,7 +826,7 @@ entry:
<vscale x 16 x i32> %1,
i32 %2,
<vscale x 16 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 16 x i32> %a
}
@@ -851,26 +835,32 @@ declare <vscale x 1 x i64> @llvm.riscv.vrsub.nxv1i64.i64(
<vscale x 1 x i64>,
<vscale x 1 x i64>,
i64,
- i32);
-
-define <vscale x 1 x i64> @intrinsic_vrsub_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vrsub_vx_nxv1i64_nxv1i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addi sp, sp, -16
-; CHECK-NEXT: sw a1, 12(sp)
-; CHECK-NEXT: sw a0, 8(sp)
-; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
-; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v9, (a0), zero
-; CHECK-NEXT: vsub.vv v8, v9, v8
-; CHECK-NEXT: addi sp, sp, 16
-; CHECK-NEXT: ret
+ iXLen);
+
+define <vscale x 1 x i64> @intrinsic_vrsub_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, iXLen %2) nounwind {
+; RV32-LABEL: intrinsic_vrsub_vx_nxv1i64_nxv1i64_i64:
+; RV32: # %bb.0: # %entry
+; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: sw a1, 12(sp)
+; RV32-NEXT: sw a0, 8(sp)
+; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
+; RV32-NEXT: addi a0, sp, 8
+; RV32-NEXT: vlse64.v v9, (a0), zero
+; RV32-NEXT: vsub.vv v8, v9, v8
+; RV32-NEXT: addi sp, sp, 16
+; RV32-NEXT: ret
+;
+; RV64-LABEL: intrinsic_vrsub_vx_nxv1i64_nxv1i64_i64:
+; RV64: # %bb.0: # %entry
+; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, mu
+; RV64-NEXT: vrsub.vx v8, v8, a0
+; RV64-NEXT: ret
entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vrsub.nxv1i64.i64(
<vscale x 1 x i64> undef,
<vscale x 1 x i64> %0,
i64 %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 1 x i64> %a
}
@@ -880,28 +870,33 @@ declare <vscale x 1 x i64> @llvm.riscv.vrsub.mask.nxv1i64.i64(
<vscale x 1 x i64>,
i64,
<vscale x 1 x i1>,
- i32,
- i32);
-
-define <vscale x 1 x i64> @intrinsic_vrsub_mask_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vrsub_mask_vx_nxv1i64_nxv1i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addi sp, sp, -16
-; CHECK-NEXT: sw a1, 12(sp)
-; CHECK-NEXT: sw a0, 8(sp)
-; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
-; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v10, (a0), zero
-; CHECK-NEXT: vsub.vv v8, v10, v9, v0.t
-; CHECK-NEXT: addi sp, sp, 16
-; CHECK-NEXT: ret
+ iXLen, iXLen);
+
+define <vscale x 1 x i64> @intrinsic_vrsub_mask_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
+; RV32-LABEL: intrinsic_vrsub_mask_vx_nxv1i64_nxv1i64_i64:
+; RV32: # %bb.0: # %entry
+; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: sw a1, 12(sp)
+; RV32-NEXT: sw a0, 8(sp)
+; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
+; RV32-NEXT: addi a0, sp, 8
+; RV32-NEXT: vlse64.v v10, (a0), zero
+; RV32-NEXT: vsub.vv v8, v10, v9, v0.t
+; RV32-NEXT: addi sp, sp, 16
+; RV32-NEXT: ret
+;
+; RV64-LABEL: intrinsic_vrsub_mask_vx_nxv1i64_nxv1i64_i64:
+; RV64: # %bb.0: # %entry
+; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, mu
+; RV64-NEXT: vrsub.vx v8, v9, a0, v0.t
+; RV64-NEXT: ret
entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vrsub.mask.nxv1i64.i64(
<vscale x 1 x i64> %0,
<vscale x 1 x i64> %1,
i64 %2,
<vscale x 1 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 1 x i64> %a
}
@@ -910,26 +905,32 @@ declare <vscale x 2 x i64> @llvm.riscv.vrsub.nxv2i64.i64(
<vscale x 2 x i64>,
<vscale x 2 x i64>,
i64,
- i32);
-
-define <vscale x 2 x i64> @intrinsic_vrsub_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vrsub_vx_nxv2i64_nxv2i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addi sp, sp, -16
-; CHECK-NEXT: sw a1, 12(sp)
-; CHECK-NEXT: sw a0, 8(sp)
-; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
-; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v10, (a0), zero
-; CHECK-NEXT: vsub.vv v8, v10, v8
-; CHECK-NEXT: addi sp, sp, 16
-; CHECK-NEXT: ret
+ iXLen);
+
+define <vscale x 2 x i64> @intrinsic_vrsub_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, iXLen %2) nounwind {
+; RV32-LABEL: intrinsic_vrsub_vx_nxv2i64_nxv2i64_i64:
+; RV32: # %bb.0: # %entry
+; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: sw a1, 12(sp)
+; RV32-NEXT: sw a0, 8(sp)
+; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
+; RV32-NEXT: addi a0, sp, 8
+; RV32-NEXT: vlse64.v v10, (a0), zero
+; RV32-NEXT: vsub.vv v8, v10, v8
+; RV32-NEXT: addi sp, sp, 16
+; RV32-NEXT: ret
+;
+; RV64-LABEL: intrinsic_vrsub_vx_nxv2i64_nxv2i64_i64:
+; RV64: # %bb.0: # %entry
+; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, mu
+; RV64-NEXT: vrsub.vx v8, v8, a0
+; RV64-NEXT: ret
entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vrsub.nxv2i64.i64(
<vscale x 2 x i64> undef,
<vscale x 2 x i64> %0,
i64 %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 2 x i64> %a
}
@@ -939,28 +940,33 @@ declare <vscale x 2 x i64> @llvm.riscv.vrsub.mask.nxv2i64.i64(
<vscale x 2 x i64>,
i64,
<vscale x 2 x i1>,
- i32,
- i32);
-
-define <vscale x 2 x i64> @intrinsic_vrsub_mask_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vrsub_mask_vx_nxv2i64_nxv2i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addi sp, sp, -16
-; CHECK-NEXT: sw a1, 12(sp)
-; CHECK-NEXT: sw a0, 8(sp)
-; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
-; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v12, (a0), zero
-; CHECK-NEXT: vsub.vv v8, v12, v10, v0.t
-; CHECK-NEXT: addi sp, sp, 16
-; CHECK-NEXT: ret
+ iXLen, iXLen);
+
+define <vscale x 2 x i64> @intrinsic_vrsub_mask_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
+; RV32-LABEL: intrinsic_vrsub_mask_vx_nxv2i64_nxv2i64_i64:
+; RV32: # %bb.0: # %entry
+; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: sw a1, 12(sp)
+; RV32-NEXT: sw a0, 8(sp)
+; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
+; RV32-NEXT: addi a0, sp, 8
+; RV32-NEXT: vlse64.v v12, (a0), zero
+; RV32-NEXT: vsub.vv v8, v12, v10, v0.t
+; RV32-NEXT: addi sp, sp, 16
+; RV32-NEXT: ret
+;
+; RV64-LABEL: intrinsic_vrsub_mask_vx_nxv2i64_nxv2i64_i64:
+; RV64: # %bb.0: # %entry
+; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, mu
+; RV64-NEXT: vrsub.vx v8, v10, a0, v0.t
+; RV64-NEXT: ret
entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vrsub.mask.nxv2i64.i64(
<vscale x 2 x i64> %0,
<vscale x 2 x i64> %1,
i64 %2,
<vscale x 2 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 2 x i64> %a
}
@@ -969,26 +975,32 @@ declare <vscale x 4 x i64> @llvm.riscv.vrsub.nxv4i64.i64(
<vscale x 4 x i64>,
<vscale x 4 x i64>,
i64,
- i32);
-
-define <vscale x 4 x i64> @intrinsic_vrsub_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vrsub_vx_nxv4i64_nxv4i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addi sp, sp, -16
-; CHECK-NEXT: sw a1, 12(sp)
-; CHECK-NEXT: sw a0, 8(sp)
-; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
-; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v12, (a0), zero
-; CHECK-NEXT: vsub.vv v8, v12, v8
-; CHECK-NEXT: addi sp, sp, 16
-; CHECK-NEXT: ret
+ iXLen);
+
+define <vscale x 4 x i64> @intrinsic_vrsub_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, iXLen %2) nounwind {
+; RV32-LABEL: intrinsic_vrsub_vx_nxv4i64_nxv4i64_i64:
+; RV32: # %bb.0: # %entry
+; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: sw a1, 12(sp)
+; RV32-NEXT: sw a0, 8(sp)
+; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
+; RV32-NEXT: addi a0, sp, 8
+; RV32-NEXT: vlse64.v v12, (a0), zero
+; RV32-NEXT: vsub.vv v8, v12, v8
+; RV32-NEXT: addi sp, sp, 16
+; RV32-NEXT: ret
+;
+; RV64-LABEL: intrinsic_vrsub_vx_nxv4i64_nxv4i64_i64:
+; RV64: # %bb.0: # %entry
+; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu
+; RV64-NEXT: vrsub.vx v8, v8, a0
+; RV64-NEXT: ret
entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vrsub.nxv4i64.i64(
<vscale x 4 x i64> undef,
<vscale x 4 x i64> %0,
i64 %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 4 x i64> %a
}
@@ -998,28 +1010,33 @@ declare <vscale x 4 x i64> @llvm.riscv.vrsub.mask.nxv4i64.i64(
<vscale x 4 x i64>,
i64,
<vscale x 4 x i1>,
- i32,
- i32);
-
-define <vscale x 4 x i64> @intrinsic_vrsub_mask_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vrsub_mask_vx_nxv4i64_nxv4i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addi sp, sp, -16
-; CHECK-NEXT: sw a1, 12(sp)
-; CHECK-NEXT: sw a0, 8(sp)
-; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
-; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v16, (a0), zero
-; CHECK-NEXT: vsub.vv v8, v16, v12, v0.t
-; CHECK-NEXT: addi sp, sp, 16
-; CHECK-NEXT: ret
+ iXLen, iXLen);
+
+define <vscale x 4 x i64> @intrinsic_vrsub_mask_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
+; RV32-LABEL: intrinsic_vrsub_mask_vx_nxv4i64_nxv4i64_i64:
+; RV32: # %bb.0: # %entry
+; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: sw a1, 12(sp)
+; RV32-NEXT: sw a0, 8(sp)
+; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
+; RV32-NEXT: addi a0, sp, 8
+; RV32-NEXT: vlse64.v v16, (a0), zero
+; RV32-NEXT: vsub.vv v8, v16, v12, v0.t
+; RV32-NEXT: addi sp, sp, 16
+; RV32-NEXT: ret
+;
+; RV64-LABEL: intrinsic_vrsub_mask_vx_nxv4i64_nxv4i64_i64:
+; RV64: # %bb.0: # %entry
+; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu
+; RV64-NEXT: vrsub.vx v8, v12, a0, v0.t
+; RV64-NEXT: ret
entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vrsub.mask.nxv4i64.i64(
<vscale x 4 x i64> %0,
<vscale x 4 x i64> %1,
i64 %2,
<vscale x 4 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 4 x i64> %a
}
@@ -1028,26 +1045,32 @@ declare <vscale x 8 x i64> @llvm.riscv.vrsub.nxv8i64.i64(
<vscale x 8 x i64>,
<vscale x 8 x i64>,
i64,
- i32);
-
-define <vscale x 8 x i64> @intrinsic_vrsub_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, i64 %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vrsub_vx_nxv8i64_nxv8i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addi sp, sp, -16
-; CHECK-NEXT: sw a1, 12(sp)
-; CHECK-NEXT: sw a0, 8(sp)
-; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, mu
-; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v16, (a0), zero
-; CHECK-NEXT: vsub.vv v8, v16, v8
-; CHECK-NEXT: addi sp, sp, 16
-; CHECK-NEXT: ret
+ iXLen);
+
+define <vscale x 8 x i64> @intrinsic_vrsub_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, i64 %1, iXLen %2) nounwind {
+; RV32-LABEL: intrinsic_vrsub_vx_nxv8i64_nxv8i64_i64:
+; RV32: # %bb.0: # %entry
+; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: sw a1, 12(sp)
+; RV32-NEXT: sw a0, 8(sp)
+; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu
+; RV32-NEXT: addi a0, sp, 8
+; RV32-NEXT: vlse64.v v16, (a0), zero
+; RV32-NEXT: vsub.vv v8, v16, v8
+; RV32-NEXT: addi sp, sp, 16
+; RV32-NEXT: ret
+;
+; RV64-LABEL: intrinsic_vrsub_vx_nxv8i64_nxv8i64_i64:
+; RV64: # %bb.0: # %entry
+; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, mu
+; RV64-NEXT: vrsub.vx v8, v8, a0
+; RV64-NEXT: ret
entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vrsub.nxv8i64.i64(
<vscale x 8 x i64> undef,
<vscale x 8 x i64> %0,
i64 %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 8 x i64> %a
}
@@ -1057,33 +1080,38 @@ declare <vscale x 8 x i64> @llvm.riscv.vrsub.mask.nxv8i64.i64(
<vscale x 8 x i64>,
i64,
<vscale x 8 x i1>,
- i32,
- i32);
-
-define <vscale x 8 x i64> @intrinsic_vrsub_mask_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vrsub_mask_vx_nxv8i64_nxv8i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addi sp, sp, -16
-; CHECK-NEXT: sw a1, 12(sp)
-; CHECK-NEXT: sw a0, 8(sp)
-; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, mu
-; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v24, (a0), zero
-; CHECK-NEXT: vsub.vv v8, v24, v16, v0.t
-; CHECK-NEXT: addi sp, sp, 16
-; CHECK-NEXT: ret
+ iXLen, iXLen);
+
+define <vscale x 8 x i64> @intrinsic_vrsub_mask_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
+; RV32-LABEL: intrinsic_vrsub_mask_vx_nxv8i64_nxv8i64_i64:
+; RV32: # %bb.0: # %entry
+; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: sw a1, 12(sp)
+; RV32-NEXT: sw a0, 8(sp)
+; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu
+; RV32-NEXT: addi a0, sp, 8
+; RV32-NEXT: vlse64.v v24, (a0), zero
+; RV32-NEXT: vsub.vv v8, v24, v16, v0.t
+; RV32-NEXT: addi sp, sp, 16
+; RV32-NEXT: ret
+;
+; RV64-LABEL: intrinsic_vrsub_mask_vx_nxv8i64_nxv8i64_i64:
+; RV64: # %bb.0: # %entry
+; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, mu
+; RV64-NEXT: vrsub.vx v8, v16, a0, v0.t
+; RV64-NEXT: ret
entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vrsub.mask.nxv8i64.i64(
<vscale x 8 x i64> %0,
<vscale x 8 x i64> %1,
i64 %2,
<vscale x 8 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 8 x i64> %a
}
-define <vscale x 1 x i8> @intrinsic_vrsub_vi_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, i32 %1) nounwind {
+define <vscale x 1 x i8> @intrinsic_vrsub_vi_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vrsub_vi_nxv1i8_nxv1i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
@@ -1094,12 +1122,12 @@ entry:
<vscale x 1 x i8> undef,
<vscale x 1 x i8> %0,
i8 9,
- i32 %1)
+ iXLen %1)
ret <vscale x 1 x i8> %a
}
-define <vscale x 1 x i8> @intrinsic_vrsub_mask_vi_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
+define <vscale x 1 x i8> @intrinsic_vrsub_mask_vi_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv1i8_nxv1i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
@@ -1111,12 +1139,12 @@ entry:
<vscale x 1 x i8> %1,
i8 -9,
<vscale x 1 x i1> %2,
- i32 %3, i32 1)
+ iXLen %3, iXLen 1)
ret <vscale x 1 x i8> %a
}
-define <vscale x 2 x i8> @intrinsic_vrsub_vi_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, i32 %1) nounwind {
+define <vscale x 2 x i8> @intrinsic_vrsub_vi_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vrsub_vi_nxv2i8_nxv2i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
@@ -1127,12 +1155,12 @@ entry:
<vscale x 2 x i8> undef,
<vscale x 2 x i8> %0,
i8 9,
- i32 %1)
+ iXLen %1)
ret <vscale x 2 x i8> %a
}
-define <vscale x 2 x i8> @intrinsic_vrsub_mask_vi_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
+define <vscale x 2 x i8> @intrinsic_vrsub_mask_vi_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv2i8_nxv2i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
@@ -1144,12 +1172,12 @@ entry:
<vscale x 2 x i8> %1,
i8 -9,
<vscale x 2 x i1> %2,
- i32 %3, i32 1)
+ iXLen %3, iXLen 1)
ret <vscale x 2 x i8> %a
}
-define <vscale x 4 x i8> @intrinsic_vrsub_vi_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, i32 %1) nounwind {
+define <vscale x 4 x i8> @intrinsic_vrsub_vi_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vrsub_vi_nxv4i8_nxv4i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
@@ -1160,12 +1188,12 @@ entry:
<vscale x 4 x i8> undef,
<vscale x 4 x i8> %0,
i8 9,
- i32 %1)
+ iXLen %1)
ret <vscale x 4 x i8> %a
}
-define <vscale x 4 x i8> @intrinsic_vrsub_mask_vi_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
+define <vscale x 4 x i8> @intrinsic_vrsub_mask_vi_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv4i8_nxv4i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
@@ -1177,12 +1205,12 @@ entry:
<vscale x 4 x i8> %1,
i8 -9,
<vscale x 4 x i1> %2,
- i32 %3, i32 1)
+ iXLen %3, iXLen 1)
ret <vscale x 4 x i8> %a
}
-define <vscale x 8 x i8> @intrinsic_vrsub_vi_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, i32 %1) nounwind {
+define <vscale x 8 x i8> @intrinsic_vrsub_vi_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vrsub_vi_nxv8i8_nxv8i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
@@ -1193,12 +1221,12 @@ entry:
<vscale x 8 x i8> undef,
<vscale x 8 x i8> %0,
i8 9,
- i32 %1)
+ iXLen %1)
ret <vscale x 8 x i8> %a
}
-define <vscale x 8 x i8> @intrinsic_vrsub_mask_vi_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
+define <vscale x 8 x i8> @intrinsic_vrsub_mask_vi_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv8i8_nxv8i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
@@ -1210,12 +1238,12 @@ entry:
<vscale x 8 x i8> %1,
i8 -9,
<vscale x 8 x i1> %2,
- i32 %3, i32 1)
+ iXLen %3, iXLen 1)
ret <vscale x 8 x i8> %a
}
-define <vscale x 16 x i8> @intrinsic_vrsub_vi_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, i32 %1) nounwind {
+define <vscale x 16 x i8> @intrinsic_vrsub_vi_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vrsub_vi_nxv16i8_nxv16i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
@@ -1226,12 +1254,12 @@ entry:
<vscale x 16 x i8> undef,
<vscale x 16 x i8> %0,
i8 9,
- i32 %1)
+ iXLen %1)
ret <vscale x 16 x i8> %a
}
-define <vscale x 16 x i8> @intrinsic_vrsub_mask_vi_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i1> %2, i32 %3) nounwind {
+define <vscale x 16 x i8> @intrinsic_vrsub_mask_vi_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv16i8_nxv16i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
@@ -1243,12 +1271,12 @@ entry:
<vscale x 16 x i8> %1,
i8 -9,
<vscale x 16 x i1> %2,
- i32 %3, i32 1)
+ iXLen %3, iXLen 1)
ret <vscale x 16 x i8> %a
}
-define <vscale x 32 x i8> @intrinsic_vrsub_vi_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, i32 %1) nounwind {
+define <vscale x 32 x i8> @intrinsic_vrsub_vi_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vrsub_vi_nxv32i8_nxv32i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
@@ -1259,12 +1287,12 @@ entry:
<vscale x 32 x i8> undef,
<vscale x 32 x i8> %0,
i8 9,
- i32 %1)
+ iXLen %1)
ret <vscale x 32 x i8> %a
}
-define <vscale x 32 x i8> @intrinsic_vrsub_mask_vi_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i1> %2, i32 %3) nounwind {
+define <vscale x 32 x i8> @intrinsic_vrsub_mask_vi_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv32i8_nxv32i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
@@ -1276,12 +1304,12 @@ entry:
<vscale x 32 x i8> %1,
i8 -9,
<vscale x 32 x i1> %2,
- i32 %3, i32 1)
+ iXLen %3, iXLen 1)
ret <vscale x 32 x i8> %a
}
-define <vscale x 64 x i8> @intrinsic_vrsub_vi_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, i32 %1) nounwind {
+define <vscale x 64 x i8> @intrinsic_vrsub_vi_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vrsub_vi_nxv64i8_nxv64i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, mu
@@ -1292,12 +1320,12 @@ entry:
<vscale x 64 x i8> undef,
<vscale x 64 x i8> %0,
i8 9,
- i32 %1)
+ iXLen %1)
ret <vscale x 64 x i8> %a
}
-define <vscale x 64 x i8> @intrinsic_vrsub_mask_vi_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i1> %2, i32 %3) nounwind {
+define <vscale x 64 x i8> @intrinsic_vrsub_mask_vi_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv64i8_nxv64i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, mu
@@ -1309,12 +1337,12 @@ entry:
<vscale x 64 x i8> %1,
i8 -9,
<vscale x 64 x i1> %2,
- i32 %3, i32 1)
+ iXLen %3, iXLen 1)
ret <vscale x 64 x i8> %a
}
-define <vscale x 1 x i16> @intrinsic_vrsub_vi_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, i32 %1) nounwind {
+define <vscale x 1 x i16> @intrinsic_vrsub_vi_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vrsub_vi_nxv1i16_nxv1i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
@@ -1325,12 +1353,12 @@ entry:
<vscale x 1 x i16> undef,
<vscale x 1 x i16> %0,
i16 9,
- i32 %1)
+ iXLen %1)
ret <vscale x 1 x i16> %a
}
-define <vscale x 1 x i16> @intrinsic_vrsub_mask_vi_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
+define <vscale x 1 x i16> @intrinsic_vrsub_mask_vi_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv1i16_nxv1i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
@@ -1342,12 +1370,12 @@ entry:
<vscale x 1 x i16> %1,
i16 -9,
<vscale x 1 x i1> %2,
- i32 %3, i32 1)
+ iXLen %3, iXLen 1)
ret <vscale x 1 x i16> %a
}
-define <vscale x 2 x i16> @intrinsic_vrsub_vi_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, i32 %1) nounwind {
+define <vscale x 2 x i16> @intrinsic_vrsub_vi_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vrsub_vi_nxv2i16_nxv2i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
@@ -1358,12 +1386,12 @@ entry:
<vscale x 2 x i16> undef,
<vscale x 2 x i16> %0,
i16 9,
- i32 %1)
+ iXLen %1)
ret <vscale x 2 x i16> %a
}
-define <vscale x 2 x i16> @intrinsic_vrsub_mask_vi_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
+define <vscale x 2 x i16> @intrinsic_vrsub_mask_vi_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv2i16_nxv2i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
@@ -1375,12 +1403,12 @@ entry:
<vscale x 2 x i16> %1,
i16 -9,
<vscale x 2 x i1> %2,
- i32 %3, i32 1)
+ iXLen %3, iXLen 1)
ret <vscale x 2 x i16> %a
}
-define <vscale x 4 x i16> @intrinsic_vrsub_vi_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, i32 %1) nounwind {
+define <vscale x 4 x i16> @intrinsic_vrsub_vi_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vrsub_vi_nxv4i16_nxv4i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
@@ -1391,12 +1419,12 @@ entry:
<vscale x 4 x i16> undef,
<vscale x 4 x i16> %0,
i16 9,
- i32 %1)
+ iXLen %1)
ret <vscale x 4 x i16> %a
}
-define <vscale x 4 x i16> @intrinsic_vrsub_mask_vi_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
+define <vscale x 4 x i16> @intrinsic_vrsub_mask_vi_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv4i16_nxv4i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
@@ -1408,12 +1436,12 @@ entry:
<vscale x 4 x i16> %1,
i16 -9,
<vscale x 4 x i1> %2,
- i32 %3, i32 1)
+ iXLen %3, iXLen 1)
ret <vscale x 4 x i16> %a
}
-define <vscale x 8 x i16> @intrinsic_vrsub_vi_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, i32 %1) nounwind {
+define <vscale x 8 x i16> @intrinsic_vrsub_vi_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vrsub_vi_nxv8i16_nxv8i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
@@ -1424,12 +1452,12 @@ entry:
<vscale x 8 x i16> undef,
<vscale x 8 x i16> %0,
i16 9,
- i32 %1)
+ iXLen %1)
ret <vscale x 8 x i16> %a
}
-define <vscale x 8 x i16> @intrinsic_vrsub_mask_vi_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
+define <vscale x 8 x i16> @intrinsic_vrsub_mask_vi_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv8i16_nxv8i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
@@ -1441,12 +1469,12 @@ entry:
<vscale x 8 x i16> %1,
i16 -9,
<vscale x 8 x i1> %2,
- i32 %3, i32 1)
+ iXLen %3, iXLen 1)
ret <vscale x 8 x i16> %a
}
-define <vscale x 16 x i16> @intrinsic_vrsub_vi_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, i32 %1) nounwind {
+define <vscale x 16 x i16> @intrinsic_vrsub_vi_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vrsub_vi_nxv16i16_nxv16i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
@@ -1457,12 +1485,12 @@ entry:
<vscale x 16 x i16> undef,
<vscale x 16 x i16> %0,
i16 9,
- i32 %1)
+ iXLen %1)
ret <vscale x 16 x i16> %a
}
-define <vscale x 16 x i16> @intrinsic_vrsub_mask_vi_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i1> %2, i32 %3) nounwind {
+define <vscale x 16 x i16> @intrinsic_vrsub_mask_vi_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv16i16_nxv16i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
@@ -1474,12 +1502,12 @@ entry:
<vscale x 16 x i16> %1,
i16 -9,
<vscale x 16 x i1> %2,
- i32 %3, i32 1)
+ iXLen %3, iXLen 1)
ret <vscale x 16 x i16> %a
}
-define <vscale x 32 x i16> @intrinsic_vrsub_vi_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, i32 %1) nounwind {
+define <vscale x 32 x i16> @intrinsic_vrsub_vi_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vrsub_vi_nxv32i16_nxv32i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, mu
@@ -1490,12 +1518,12 @@ entry:
<vscale x 32 x i16> undef,
<vscale x 32 x i16> %0,
i16 9,
- i32 %1)
+ iXLen %1)
ret <vscale x 32 x i16> %a
}
-define <vscale x 32 x i16> @intrinsic_vrsub_mask_vi_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i1> %2, i32 %3) nounwind {
+define <vscale x 32 x i16> @intrinsic_vrsub_mask_vi_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv32i16_nxv32i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, mu
@@ -1507,12 +1535,12 @@ entry:
<vscale x 32 x i16> %1,
i16 -9,
<vscale x 32 x i1> %2,
- i32 %3, i32 1)
+ iXLen %3, iXLen 1)
ret <vscale x 32 x i16> %a
}
-define <vscale x 1 x i32> @intrinsic_vrsub_vi_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, i32 %1) nounwind {
+define <vscale x 1 x i32> @intrinsic_vrsub_vi_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vrsub_vi_nxv1i32_nxv1i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
@@ -1523,12 +1551,12 @@ entry:
<vscale x 1 x i32> undef,
<vscale x 1 x i32> %0,
i32 9,
- i32 %1)
+ iXLen %1)
ret <vscale x 1 x i32> %a
}
-define <vscale x 1 x i32> @intrinsic_vrsub_mask_vi_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
+define <vscale x 1 x i32> @intrinsic_vrsub_mask_vi_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv1i32_nxv1i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
@@ -1540,12 +1568,12 @@ entry:
<vscale x 1 x i32> %1,
i32 -9,
<vscale x 1 x i1> %2,
- i32 %3, i32 1)
+ iXLen %3, iXLen 1)
ret <vscale x 1 x i32> %a
}
-define <vscale x 2 x i32> @intrinsic_vrsub_vi_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, i32 %1) nounwind {
+define <vscale x 2 x i32> @intrinsic_vrsub_vi_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vrsub_vi_nxv2i32_nxv2i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
@@ -1556,12 +1584,12 @@ entry:
<vscale x 2 x i32> undef,
<vscale x 2 x i32> %0,
i32 9,
- i32 %1)
+ iXLen %1)
ret <vscale x 2 x i32> %a
}
-define <vscale x 2 x i32> @intrinsic_vrsub_mask_vi_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
+define <vscale x 2 x i32> @intrinsic_vrsub_mask_vi_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv2i32_nxv2i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
@@ -1573,12 +1601,12 @@ entry:
<vscale x 2 x i32> %1,
i32 -9,
<vscale x 2 x i1> %2,
- i32 %3, i32 1)
+ iXLen %3, iXLen 1)
ret <vscale x 2 x i32> %a
}
-define <vscale x 4 x i32> @intrinsic_vrsub_vi_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, i32 %1) nounwind {
+define <vscale x 4 x i32> @intrinsic_vrsub_vi_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vrsub_vi_nxv4i32_nxv4i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
@@ -1589,12 +1617,12 @@ entry:
<vscale x 4 x i32> undef,
<vscale x 4 x i32> %0,
i32 9,
- i32 %1)
+ iXLen %1)
ret <vscale x 4 x i32> %a
}
-define <vscale x 4 x i32> @intrinsic_vrsub_mask_vi_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
+define <vscale x 4 x i32> @intrinsic_vrsub_mask_vi_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv4i32_nxv4i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
@@ -1606,12 +1634,12 @@ entry:
<vscale x 4 x i32> %1,
i32 -9,
<vscale x 4 x i1> %2,
- i32 %3, i32 1)
+ iXLen %3, iXLen 1)
ret <vscale x 4 x i32> %a
}
-define <vscale x 8 x i32> @intrinsic_vrsub_vi_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, i32 %1) nounwind {
+define <vscale x 8 x i32> @intrinsic_vrsub_vi_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vrsub_vi_nxv8i32_nxv8i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
@@ -1622,12 +1650,12 @@ entry:
<vscale x 8 x i32> undef,
<vscale x 8 x i32> %0,
i32 9,
- i32 %1)
+ iXLen %1)
ret <vscale x 8 x i32> %a
}
-define <vscale x 8 x i32> @intrinsic_vrsub_mask_vi_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
+define <vscale x 8 x i32> @intrinsic_vrsub_mask_vi_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv8i32_nxv8i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
@@ -1639,12 +1667,12 @@ entry:
<vscale x 8 x i32> %1,
i32 -9,
<vscale x 8 x i1> %2,
- i32 %3, i32 1)
+ iXLen %3, iXLen 1)
ret <vscale x 8 x i32> %a
}
-define <vscale x 16 x i32> @intrinsic_vrsub_vi_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, i32 %1) nounwind {
+define <vscale x 16 x i32> @intrinsic_vrsub_vi_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vrsub_vi_nxv16i32_nxv16i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu
@@ -1655,12 +1683,12 @@ entry:
<vscale x 16 x i32> undef,
<vscale x 16 x i32> %0,
i32 9,
- i32 %1)
+ iXLen %1)
ret <vscale x 16 x i32> %a
}
-define <vscale x 16 x i32> @intrinsic_vrsub_mask_vi_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i1> %2, i32 %3) nounwind {
+define <vscale x 16 x i32> @intrinsic_vrsub_mask_vi_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv16i32_nxv16i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu
@@ -1672,12 +1700,12 @@ entry:
<vscale x 16 x i32> %1,
i32 -9,
<vscale x 16 x i1> %2,
- i32 %3, i32 1)
+ iXLen %3, iXLen 1)
ret <vscale x 16 x i32> %a
}
-define <vscale x 1 x i64> @intrinsic_vrsub_vi_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, i32 %1) nounwind {
+define <vscale x 1 x i64> @intrinsic_vrsub_vi_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vrsub_vi_nxv1i64_nxv1i64_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
@@ -1688,12 +1716,12 @@ entry:
<vscale x 1 x i64> undef,
<vscale x 1 x i64> %0,
i64 9,
- i32 %1)
+ iXLen %1)
ret <vscale x 1 x i64> %a
}
-define <vscale x 1 x i64> @intrinsic_vrsub_mask_vi_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
+define <vscale x 1 x i64> @intrinsic_vrsub_mask_vi_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv1i64_nxv1i64_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
@@ -1705,12 +1733,12 @@ entry:
<vscale x 1 x i64> %1,
i64 9,
<vscale x 1 x i1> %2,
- i32 %3, i32 1)
+ iXLen %3, iXLen 1)
ret <vscale x 1 x i64> %a
}
-define <vscale x 2 x i64> @intrinsic_vrsub_vi_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, i32 %1) nounwind {
+define <vscale x 2 x i64> @intrinsic_vrsub_vi_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vrsub_vi_nxv2i64_nxv2i64_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
@@ -1721,12 +1749,12 @@ entry:
<vscale x 2 x i64> undef,
<vscale x 2 x i64> %0,
i64 9,
- i32 %1)
+ iXLen %1)
ret <vscale x 2 x i64> %a
}
-define <vscale x 2 x i64> @intrinsic_vrsub_mask_vi_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
+define <vscale x 2 x i64> @intrinsic_vrsub_mask_vi_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv2i64_nxv2i64_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
@@ -1738,12 +1766,12 @@ entry:
<vscale x 2 x i64> %1,
i64 9,
<vscale x 2 x i1> %2,
- i32 %3, i32 1)
+ iXLen %3, iXLen 1)
ret <vscale x 2 x i64> %a
}
-define <vscale x 4 x i64> @intrinsic_vrsub_vi_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, i32 %1) nounwind {
+define <vscale x 4 x i64> @intrinsic_vrsub_vi_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vrsub_vi_nxv4i64_nxv4i64_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
@@ -1754,12 +1782,12 @@ entry:
<vscale x 4 x i64> undef,
<vscale x 4 x i64> %0,
i64 9,
- i32 %1)
+ iXLen %1)
ret <vscale x 4 x i64> %a
}
-define <vscale x 4 x i64> @intrinsic_vrsub_mask_vi_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
+define <vscale x 4 x i64> @intrinsic_vrsub_mask_vi_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv4i64_nxv4i64_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
@@ -1771,12 +1799,12 @@ entry:
<vscale x 4 x i64> %1,
i64 9,
<vscale x 4 x i1> %2,
- i32 %3, i32 1)
+ iXLen %3, iXLen 1)
ret <vscale x 4 x i64> %a
}
-define <vscale x 8 x i64> @intrinsic_vrsub_vi_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, i32 %1) nounwind {
+define <vscale x 8 x i64> @intrinsic_vrsub_vi_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vrsub_vi_nxv8i64_nxv8i64_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu
@@ -1787,12 +1815,12 @@ entry:
<vscale x 8 x i64> undef,
<vscale x 8 x i64> %0,
i64 9,
- i32 %1)
+ iXLen %1)
ret <vscale x 8 x i64> %a
}
-define <vscale x 8 x i64> @intrinsic_vrsub_mask_vi_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
+define <vscale x 8 x i64> @intrinsic_vrsub_mask_vi_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv8i64_nxv8i64_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu
@@ -1804,7 +1832,7 @@ entry:
<vscale x 8 x i64> %1,
i64 9,
<vscale x 8 x i1> %2,
- i32 %3, i32 1)
+ iXLen %3, iXLen 1)
ret <vscale x 8 x i64> %a
}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vsub-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vsub-rv64.ll
deleted file mode 100644
index 2cb7f359dcf0d..0000000000000
--- a/llvm/test/CodeGen/RISCV/rvv/vsub-rv64.ll
+++ /dev/null
@@ -1,2800 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs \
-; RUN: < %s | FileCheck %s
-declare <vscale x 1 x i8> @llvm.riscv.vsub.nxv1i8.nxv1i8(
- <vscale x 1 x i8>,
- <vscale x 1 x i8>,
- <vscale x 1 x i8>,
- i64);
-
-define <vscale x 1 x i8> @intrinsic_vsub_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vsub_vv_nxv1i8_nxv1i8_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
-; CHECK-NEXT: vsub.vv v8, v8, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i8> @llvm.riscv.vsub.nxv1i8.nxv1i8(
- <vscale x 1 x i8> undef,
- <vscale x 1 x i8> %0,
- <vscale x 1 x i8> %1,
- i64 %2)
-
- ret <vscale x 1 x i8> %a
-}
-
-declare <vscale x 1 x i8> @llvm.riscv.vsub.mask.nxv1i8.nxv1i8(
- <vscale x 1 x i8>,
- <vscale x 1 x i8>,
- <vscale x 1 x i8>,
- <vscale x 1 x i1>,
- i64,
- i64);
-
-define <vscale x 1 x i8> @intrinsic_vsub_mask_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv1i8_nxv1i8_nxv1i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
-; CHECK-NEXT: vsub.vv v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i8> @llvm.riscv.vsub.mask.nxv1i8.nxv1i8(
- <vscale x 1 x i8> %0,
- <vscale x 1 x i8> %1,
- <vscale x 1 x i8> %2,
- <vscale x 1 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 1 x i8> %a
-}
-
-declare <vscale x 2 x i8> @llvm.riscv.vsub.nxv2i8.nxv2i8(
- <vscale x 2 x i8>,
- <vscale x 2 x i8>,
- <vscale x 2 x i8>,
- i64);
-
-define <vscale x 2 x i8> @intrinsic_vsub_vv_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vsub_vv_nxv2i8_nxv2i8_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
-; CHECK-NEXT: vsub.vv v8, v8, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i8> @llvm.riscv.vsub.nxv2i8.nxv2i8(
- <vscale x 2 x i8> undef,
- <vscale x 2 x i8> %0,
- <vscale x 2 x i8> %1,
- i64 %2)
-
- ret <vscale x 2 x i8> %a
-}
-
-declare <vscale x 2 x i8> @llvm.riscv.vsub.mask.nxv2i8.nxv2i8(
- <vscale x 2 x i8>,
- <vscale x 2 x i8>,
- <vscale x 2 x i8>,
- <vscale x 2 x i1>,
- i64,
- i64);
-
-define <vscale x 2 x i8> @intrinsic_vsub_mask_vv_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv2i8_nxv2i8_nxv2i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
-; CHECK-NEXT: vsub.vv v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i8> @llvm.riscv.vsub.mask.nxv2i8.nxv2i8(
- <vscale x 2 x i8> %0,
- <vscale x 2 x i8> %1,
- <vscale x 2 x i8> %2,
- <vscale x 2 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 2 x i8> %a
-}
-
-declare <vscale x 4 x i8> @llvm.riscv.vsub.nxv4i8.nxv4i8(
- <vscale x 4 x i8>,
- <vscale x 4 x i8>,
- <vscale x 4 x i8>,
- i64);
-
-define <vscale x 4 x i8> @intrinsic_vsub_vv_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vsub_vv_nxv4i8_nxv4i8_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
-; CHECK-NEXT: vsub.vv v8, v8, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i8> @llvm.riscv.vsub.nxv4i8.nxv4i8(
- <vscale x 4 x i8> undef,
- <vscale x 4 x i8> %0,
- <vscale x 4 x i8> %1,
- i64 %2)
-
- ret <vscale x 4 x i8> %a
-}
-
-declare <vscale x 4 x i8> @llvm.riscv.vsub.mask.nxv4i8.nxv4i8(
- <vscale x 4 x i8>,
- <vscale x 4 x i8>,
- <vscale x 4 x i8>,
- <vscale x 4 x i1>,
- i64,
- i64);
-
-define <vscale x 4 x i8> @intrinsic_vsub_mask_vv_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv4i8_nxv4i8_nxv4i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
-; CHECK-NEXT: vsub.vv v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i8> @llvm.riscv.vsub.mask.nxv4i8.nxv4i8(
- <vscale x 4 x i8> %0,
- <vscale x 4 x i8> %1,
- <vscale x 4 x i8> %2,
- <vscale x 4 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 4 x i8> %a
-}
-
-declare <vscale x 8 x i8> @llvm.riscv.vsub.nxv8i8.nxv8i8(
- <vscale x 8 x i8>,
- <vscale x 8 x i8>,
- <vscale x 8 x i8>,
- i64);
-
-define <vscale x 8 x i8> @intrinsic_vsub_vv_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vsub_vv_nxv8i8_nxv8i8_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
-; CHECK-NEXT: vsub.vv v8, v8, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i8> @llvm.riscv.vsub.nxv8i8.nxv8i8(
- <vscale x 8 x i8> undef,
- <vscale x 8 x i8> %0,
- <vscale x 8 x i8> %1,
- i64 %2)
-
- ret <vscale x 8 x i8> %a
-}
-
-declare <vscale x 8 x i8> @llvm.riscv.vsub.mask.nxv8i8.nxv8i8(
- <vscale x 8 x i8>,
- <vscale x 8 x i8>,
- <vscale x 8 x i8>,
- <vscale x 8 x i1>,
- i64,
- i64);
-
-define <vscale x 8 x i8> @intrinsic_vsub_mask_vv_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv8i8_nxv8i8_nxv8i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
-; CHECK-NEXT: vsub.vv v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i8> @llvm.riscv.vsub.mask.nxv8i8.nxv8i8(
- <vscale x 8 x i8> %0,
- <vscale x 8 x i8> %1,
- <vscale x 8 x i8> %2,
- <vscale x 8 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 8 x i8> %a
-}
-
-declare <vscale x 16 x i8> @llvm.riscv.vsub.nxv16i8.nxv16i8(
- <vscale x 16 x i8>,
- <vscale x 16 x i8>,
- <vscale x 16 x i8>,
- i64);
-
-define <vscale x 16 x i8> @intrinsic_vsub_vv_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vsub_vv_nxv16i8_nxv16i8_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
-; CHECK-NEXT: vsub.vv v8, v8, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i8> @llvm.riscv.vsub.nxv16i8.nxv16i8(
- <vscale x 16 x i8> undef,
- <vscale x 16 x i8> %0,
- <vscale x 16 x i8> %1,
- i64 %2)
-
- ret <vscale x 16 x i8> %a
-}
-
-declare <vscale x 16 x i8> @llvm.riscv.vsub.mask.nxv16i8.nxv16i8(
- <vscale x 16 x i8>,
- <vscale x 16 x i8>,
- <vscale x 16 x i8>,
- <vscale x 16 x i1>,
- i64,
- i64);
-
-define <vscale x 16 x i8> @intrinsic_vsub_mask_vv_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv16i8_nxv16i8_nxv16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
-; CHECK-NEXT: vsub.vv v8, v10, v12, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i8> @llvm.riscv.vsub.mask.nxv16i8.nxv16i8(
- <vscale x 16 x i8> %0,
- <vscale x 16 x i8> %1,
- <vscale x 16 x i8> %2,
- <vscale x 16 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 16 x i8> %a
-}
-
-declare <vscale x 32 x i8> @llvm.riscv.vsub.nxv32i8.nxv32i8(
- <vscale x 32 x i8>,
- <vscale x 32 x i8>,
- <vscale x 32 x i8>,
- i64);
-
-define <vscale x 32 x i8> @intrinsic_vsub_vv_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vsub_vv_nxv32i8_nxv32i8_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
-; CHECK-NEXT: vsub.vv v8, v8, v12
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 32 x i8> @llvm.riscv.vsub.nxv32i8.nxv32i8(
- <vscale x 32 x i8> undef,
- <vscale x 32 x i8> %0,
- <vscale x 32 x i8> %1,
- i64 %2)
-
- ret <vscale x 32 x i8> %a
-}
-
-declare <vscale x 32 x i8> @llvm.riscv.vsub.mask.nxv32i8.nxv32i8(
- <vscale x 32 x i8>,
- <vscale x 32 x i8>,
- <vscale x 32 x i8>,
- <vscale x 32 x i1>,
- i64,
- i64);
-
-define <vscale x 32 x i8> @intrinsic_vsub_mask_vv_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv32i8_nxv32i8_nxv32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
-; CHECK-NEXT: vsub.vv v8, v12, v16, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 32 x i8> @llvm.riscv.vsub.mask.nxv32i8.nxv32i8(
- <vscale x 32 x i8> %0,
- <vscale x 32 x i8> %1,
- <vscale x 32 x i8> %2,
- <vscale x 32 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 32 x i8> %a
-}
-
-declare <vscale x 64 x i8> @llvm.riscv.vsub.nxv64i8.nxv64i8(
- <vscale x 64 x i8>,
- <vscale x 64 x i8>,
- <vscale x 64 x i8>,
- i64);
-
-define <vscale x 64 x i8> @intrinsic_vsub_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vsub_vv_nxv64i8_nxv64i8_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, mu
-; CHECK-NEXT: vsub.vv v8, v8, v16
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 64 x i8> @llvm.riscv.vsub.nxv64i8.nxv64i8(
- <vscale x 64 x i8> undef,
- <vscale x 64 x i8> %0,
- <vscale x 64 x i8> %1,
- i64 %2)
-
- ret <vscale x 64 x i8> %a
-}
-
-declare <vscale x 64 x i8> @llvm.riscv.vsub.mask.nxv64i8.nxv64i8(
- <vscale x 64 x i8>,
- <vscale x 64 x i8>,
- <vscale x 64 x i8>,
- <vscale x 64 x i1>,
- i64,
- i64);
-
-define <vscale x 64 x i8> @intrinsic_vsub_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv64i8_nxv64i8_nxv64i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vl8r.v v24, (a0)
-; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu
-; CHECK-NEXT: vsub.vv v8, v16, v24, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 64 x i8> @llvm.riscv.vsub.mask.nxv64i8.nxv64i8(
- <vscale x 64 x i8> %0,
- <vscale x 64 x i8> %1,
- <vscale x 64 x i8> %2,
- <vscale x 64 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 64 x i8> %a
-}
-
-declare <vscale x 1 x i16> @llvm.riscv.vsub.nxv1i16.nxv1i16(
- <vscale x 1 x i16>,
- <vscale x 1 x i16>,
- <vscale x 1 x i16>,
- i64);
-
-define <vscale x 1 x i16> @intrinsic_vsub_vv_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vsub_vv_nxv1i16_nxv1i16_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vsub.vv v8, v8, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i16> @llvm.riscv.vsub.nxv1i16.nxv1i16(
- <vscale x 1 x i16> undef,
- <vscale x 1 x i16> %0,
- <vscale x 1 x i16> %1,
- i64 %2)
-
- ret <vscale x 1 x i16> %a
-}
-
-declare <vscale x 1 x i16> @llvm.riscv.vsub.mask.nxv1i16.nxv1i16(
- <vscale x 1 x i16>,
- <vscale x 1 x i16>,
- <vscale x 1 x i16>,
- <vscale x 1 x i1>,
- i64,
- i64);
-
-define <vscale x 1 x i16> @intrinsic_vsub_mask_vv_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv1i16_nxv1i16_nxv1i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vsub.vv v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i16> @llvm.riscv.vsub.mask.nxv1i16.nxv1i16(
- <vscale x 1 x i16> %0,
- <vscale x 1 x i16> %1,
- <vscale x 1 x i16> %2,
- <vscale x 1 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 1 x i16> %a
-}
-
-declare <vscale x 2 x i16> @llvm.riscv.vsub.nxv2i16.nxv2i16(
- <vscale x 2 x i16>,
- <vscale x 2 x i16>,
- <vscale x 2 x i16>,
- i64);
-
-define <vscale x 2 x i16> @intrinsic_vsub_vv_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vsub_vv_nxv2i16_nxv2i16_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vsub.vv v8, v8, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i16> @llvm.riscv.vsub.nxv2i16.nxv2i16(
- <vscale x 2 x i16> undef,
- <vscale x 2 x i16> %0,
- <vscale x 2 x i16> %1,
- i64 %2)
-
- ret <vscale x 2 x i16> %a
-}
-
-declare <vscale x 2 x i16> @llvm.riscv.vsub.mask.nxv2i16.nxv2i16(
- <vscale x 2 x i16>,
- <vscale x 2 x i16>,
- <vscale x 2 x i16>,
- <vscale x 2 x i1>,
- i64,
- i64);
-
-define <vscale x 2 x i16> @intrinsic_vsub_mask_vv_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv2i16_nxv2i16_nxv2i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vsub.vv v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i16> @llvm.riscv.vsub.mask.nxv2i16.nxv2i16(
- <vscale x 2 x i16> %0,
- <vscale x 2 x i16> %1,
- <vscale x 2 x i16> %2,
- <vscale x 2 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 2 x i16> %a
-}
-
-declare <vscale x 4 x i16> @llvm.riscv.vsub.nxv4i16.nxv4i16(
- <vscale x 4 x i16>,
- <vscale x 4 x i16>,
- <vscale x 4 x i16>,
- i64);
-
-define <vscale x 4 x i16> @intrinsic_vsub_vv_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vsub_vv_nxv4i16_nxv4i16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vsub.vv v8, v8, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i16> @llvm.riscv.vsub.nxv4i16.nxv4i16(
- <vscale x 4 x i16> undef,
- <vscale x 4 x i16> %0,
- <vscale x 4 x i16> %1,
- i64 %2)
-
- ret <vscale x 4 x i16> %a
-}
-
-declare <vscale x 4 x i16> @llvm.riscv.vsub.mask.nxv4i16.nxv4i16(
- <vscale x 4 x i16>,
- <vscale x 4 x i16>,
- <vscale x 4 x i16>,
- <vscale x 4 x i1>,
- i64,
- i64);
-
-define <vscale x 4 x i16> @intrinsic_vsub_mask_vv_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv4i16_nxv4i16_nxv4i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vsub.vv v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i16> @llvm.riscv.vsub.mask.nxv4i16.nxv4i16(
- <vscale x 4 x i16> %0,
- <vscale x 4 x i16> %1,
- <vscale x 4 x i16> %2,
- <vscale x 4 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 4 x i16> %a
-}
-
-declare <vscale x 8 x i16> @llvm.riscv.vsub.nxv8i16.nxv8i16(
- <vscale x 8 x i16>,
- <vscale x 8 x i16>,
- <vscale x 8 x i16>,
- i64);
-
-define <vscale x 8 x i16> @intrinsic_vsub_vv_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vsub_vv_nxv8i16_nxv8i16_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vsub.vv v8, v8, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i16> @llvm.riscv.vsub.nxv8i16.nxv8i16(
- <vscale x 8 x i16> undef,
- <vscale x 8 x i16> %0,
- <vscale x 8 x i16> %1,
- i64 %2)
-
- ret <vscale x 8 x i16> %a
-}
-
-declare <vscale x 8 x i16> @llvm.riscv.vsub.mask.nxv8i16.nxv8i16(
- <vscale x 8 x i16>,
- <vscale x 8 x i16>,
- <vscale x 8 x i16>,
- <vscale x 8 x i1>,
- i64,
- i64);
-
-define <vscale x 8 x i16> @intrinsic_vsub_mask_vv_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv8i16_nxv8i16_nxv8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vsub.vv v8, v10, v12, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i16> @llvm.riscv.vsub.mask.nxv8i16.nxv8i16(
- <vscale x 8 x i16> %0,
- <vscale x 8 x i16> %1,
- <vscale x 8 x i16> %2,
- <vscale x 8 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 8 x i16> %a
-}
-
-declare <vscale x 16 x i16> @llvm.riscv.vsub.nxv16i16.nxv16i16(
- <vscale x 16 x i16>,
- <vscale x 16 x i16>,
- <vscale x 16 x i16>,
- i64);
-
-define <vscale x 16 x i16> @intrinsic_vsub_vv_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vsub_vv_nxv16i16_nxv16i16_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
-; CHECK-NEXT: vsub.vv v8, v8, v12
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i16> @llvm.riscv.vsub.nxv16i16.nxv16i16(
- <vscale x 16 x i16> undef,
- <vscale x 16 x i16> %0,
- <vscale x 16 x i16> %1,
- i64 %2)
-
- ret <vscale x 16 x i16> %a
-}
-
-declare <vscale x 16 x i16> @llvm.riscv.vsub.mask.nxv16i16.nxv16i16(
- <vscale x 16 x i16>,
- <vscale x 16 x i16>,
- <vscale x 16 x i16>,
- <vscale x 16 x i1>,
- i64,
- i64);
-
-define <vscale x 16 x i16> @intrinsic_vsub_mask_vv_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv16i16_nxv16i16_nxv16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
-; CHECK-NEXT: vsub.vv v8, v12, v16, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i16> @llvm.riscv.vsub.mask.nxv16i16.nxv16i16(
- <vscale x 16 x i16> %0,
- <vscale x 16 x i16> %1,
- <vscale x 16 x i16> %2,
- <vscale x 16 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 16 x i16> %a
-}
-
-declare <vscale x 32 x i16> @llvm.riscv.vsub.nxv32i16.nxv32i16(
- <vscale x 32 x i16>,
- <vscale x 32 x i16>,
- <vscale x 32 x i16>,
- i64);
-
-define <vscale x 32 x i16> @intrinsic_vsub_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vsub_vv_nxv32i16_nxv32i16_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, mu
-; CHECK-NEXT: vsub.vv v8, v8, v16
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 32 x i16> @llvm.riscv.vsub.nxv32i16.nxv32i16(
- <vscale x 32 x i16> undef,
- <vscale x 32 x i16> %0,
- <vscale x 32 x i16> %1,
- i64 %2)
-
- ret <vscale x 32 x i16> %a
-}
-
-declare <vscale x 32 x i16> @llvm.riscv.vsub.mask.nxv32i16.nxv32i16(
- <vscale x 32 x i16>,
- <vscale x 32 x i16>,
- <vscale x 32 x i16>,
- <vscale x 32 x i1>,
- i64,
- i64);
-
-define <vscale x 32 x i16> @intrinsic_vsub_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv32i16_nxv32i16_nxv32i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vl8re16.v v24, (a0)
-; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu
-; CHECK-NEXT: vsub.vv v8, v16, v24, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 32 x i16> @llvm.riscv.vsub.mask.nxv32i16.nxv32i16(
- <vscale x 32 x i16> %0,
- <vscale x 32 x i16> %1,
- <vscale x 32 x i16> %2,
- <vscale x 32 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 32 x i16> %a
-}
-
-declare <vscale x 1 x i32> @llvm.riscv.vsub.nxv1i32.nxv1i32(
- <vscale x 1 x i32>,
- <vscale x 1 x i32>,
- <vscale x 1 x i32>,
- i64);
-
-define <vscale x 1 x i32> @intrinsic_vsub_vv_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vsub_vv_nxv1i32_nxv1i32_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vsub.vv v8, v8, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i32> @llvm.riscv.vsub.nxv1i32.nxv1i32(
- <vscale x 1 x i32> undef,
- <vscale x 1 x i32> %0,
- <vscale x 1 x i32> %1,
- i64 %2)
-
- ret <vscale x 1 x i32> %a
-}
-
-declare <vscale x 1 x i32> @llvm.riscv.vsub.mask.nxv1i32.nxv1i32(
- <vscale x 1 x i32>,
- <vscale x 1 x i32>,
- <vscale x 1 x i32>,
- <vscale x 1 x i1>,
- i64,
- i64);
-
-define <vscale x 1 x i32> @intrinsic_vsub_mask_vv_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv1i32_nxv1i32_nxv1i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vsub.vv v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i32> @llvm.riscv.vsub.mask.nxv1i32.nxv1i32(
- <vscale x 1 x i32> %0,
- <vscale x 1 x i32> %1,
- <vscale x 1 x i32> %2,
- <vscale x 1 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 1 x i32> %a
-}
-
-declare <vscale x 2 x i32> @llvm.riscv.vsub.nxv2i32.nxv2i32(
- <vscale x 2 x i32>,
- <vscale x 2 x i32>,
- <vscale x 2 x i32>,
- i64);
-
-define <vscale x 2 x i32> @intrinsic_vsub_vv_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vsub_vv_nxv2i32_nxv2i32_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vsub.vv v8, v8, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i32> @llvm.riscv.vsub.nxv2i32.nxv2i32(
- <vscale x 2 x i32> undef,
- <vscale x 2 x i32> %0,
- <vscale x 2 x i32> %1,
- i64 %2)
-
- ret <vscale x 2 x i32> %a
-}
-
-declare <vscale x 2 x i32> @llvm.riscv.vsub.mask.nxv2i32.nxv2i32(
- <vscale x 2 x i32>,
- <vscale x 2 x i32>,
- <vscale x 2 x i32>,
- <vscale x 2 x i1>,
- i64,
- i64);
-
-define <vscale x 2 x i32> @intrinsic_vsub_mask_vv_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv2i32_nxv2i32_nxv2i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vsub.vv v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i32> @llvm.riscv.vsub.mask.nxv2i32.nxv2i32(
- <vscale x 2 x i32> %0,
- <vscale x 2 x i32> %1,
- <vscale x 2 x i32> %2,
- <vscale x 2 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 2 x i32> %a
-}
-
-declare <vscale x 4 x i32> @llvm.riscv.vsub.nxv4i32.nxv4i32(
- <vscale x 4 x i32>,
- <vscale x 4 x i32>,
- <vscale x 4 x i32>,
- i64);
-
-define <vscale x 4 x i32> @intrinsic_vsub_vv_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vsub_vv_nxv4i32_nxv4i32_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vsub.vv v8, v8, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i32> @llvm.riscv.vsub.nxv4i32.nxv4i32(
- <vscale x 4 x i32> undef,
- <vscale x 4 x i32> %0,
- <vscale x 4 x i32> %1,
- i64 %2)
-
- ret <vscale x 4 x i32> %a
-}
-
-declare <vscale x 4 x i32> @llvm.riscv.vsub.mask.nxv4i32.nxv4i32(
- <vscale x 4 x i32>,
- <vscale x 4 x i32>,
- <vscale x 4 x i32>,
- <vscale x 4 x i1>,
- i64,
- i64);
-
-define <vscale x 4 x i32> @intrinsic_vsub_mask_vv_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv4i32_nxv4i32_nxv4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vsub.vv v8, v10, v12, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i32> @llvm.riscv.vsub.mask.nxv4i32.nxv4i32(
- <vscale x 4 x i32> %0,
- <vscale x 4 x i32> %1,
- <vscale x 4 x i32> %2,
- <vscale x 4 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 4 x i32> %a
-}
-
-declare <vscale x 8 x i32> @llvm.riscv.vsub.nxv8i32.nxv8i32(
- <vscale x 8 x i32>,
- <vscale x 8 x i32>,
- <vscale x 8 x i32>,
- i64);
-
-define <vscale x 8 x i32> @intrinsic_vsub_vv_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vsub_vv_nxv8i32_nxv8i32_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
-; CHECK-NEXT: vsub.vv v8, v8, v12
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i32> @llvm.riscv.vsub.nxv8i32.nxv8i32(
- <vscale x 8 x i32> undef,
- <vscale x 8 x i32> %0,
- <vscale x 8 x i32> %1,
- i64 %2)
-
- ret <vscale x 8 x i32> %a
-}
-
-declare <vscale x 8 x i32> @llvm.riscv.vsub.mask.nxv8i32.nxv8i32(
- <vscale x 8 x i32>,
- <vscale x 8 x i32>,
- <vscale x 8 x i32>,
- <vscale x 8 x i1>,
- i64,
- i64);
-
-define <vscale x 8 x i32> @intrinsic_vsub_mask_vv_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv8i32_nxv8i32_nxv8i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
-; CHECK-NEXT: vsub.vv v8, v12, v16, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i32> @llvm.riscv.vsub.mask.nxv8i32.nxv8i32(
- <vscale x 8 x i32> %0,
- <vscale x 8 x i32> %1,
- <vscale x 8 x i32> %2,
- <vscale x 8 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 8 x i32> %a
-}
-
-declare <vscale x 16 x i32> @llvm.riscv.vsub.nxv16i32.nxv16i32(
- <vscale x 16 x i32>,
- <vscale x 16 x i32>,
- <vscale x 16 x i32>,
- i64);
-
-define <vscale x 16 x i32> @intrinsic_vsub_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vsub_vv_nxv16i32_nxv16i32_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu
-; CHECK-NEXT: vsub.vv v8, v8, v16
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i32> @llvm.riscv.vsub.nxv16i32.nxv16i32(
- <vscale x 16 x i32> undef,
- <vscale x 16 x i32> %0,
- <vscale x 16 x i32> %1,
- i64 %2)
-
- ret <vscale x 16 x i32> %a
-}
-
-declare <vscale x 16 x i32> @llvm.riscv.vsub.mask.nxv16i32.nxv16i32(
- <vscale x 16 x i32>,
- <vscale x 16 x i32>,
- <vscale x 16 x i32>,
- <vscale x 16 x i1>,
- i64,
- i64);
-
-define <vscale x 16 x i32> @intrinsic_vsub_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv16i32_nxv16i32_nxv16i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vl8re32.v v24, (a0)
-; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu
-; CHECK-NEXT: vsub.vv v8, v16, v24, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i32> @llvm.riscv.vsub.mask.nxv16i32.nxv16i32(
- <vscale x 16 x i32> %0,
- <vscale x 16 x i32> %1,
- <vscale x 16 x i32> %2,
- <vscale x 16 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 16 x i32> %a
-}
-
-declare <vscale x 1 x i64> @llvm.riscv.vsub.nxv1i64.nxv1i64(
- <vscale x 1 x i64>,
- <vscale x 1 x i64>,
- <vscale x 1 x i64>,
- i64);
-
-define <vscale x 1 x i64> @intrinsic_vsub_vv_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vsub_vv_nxv1i64_nxv1i64_nxv1i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
-; CHECK-NEXT: vsub.vv v8, v8, v9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i64> @llvm.riscv.vsub.nxv1i64.nxv1i64(
- <vscale x 1 x i64> undef,
- <vscale x 1 x i64> %0,
- <vscale x 1 x i64> %1,
- i64 %2)
-
- ret <vscale x 1 x i64> %a
-}
-
-declare <vscale x 1 x i64> @llvm.riscv.vsub.mask.nxv1i64.nxv1i64(
- <vscale x 1 x i64>,
- <vscale x 1 x i64>,
- <vscale x 1 x i64>,
- <vscale x 1 x i1>,
- i64,
- i64);
-
-define <vscale x 1 x i64> @intrinsic_vsub_mask_vv_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv1i64_nxv1i64_nxv1i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
-; CHECK-NEXT: vsub.vv v8, v9, v10, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i64> @llvm.riscv.vsub.mask.nxv1i64.nxv1i64(
- <vscale x 1 x i64> %0,
- <vscale x 1 x i64> %1,
- <vscale x 1 x i64> %2,
- <vscale x 1 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 1 x i64> %a
-}
-
-declare <vscale x 2 x i64> @llvm.riscv.vsub.nxv2i64.nxv2i64(
- <vscale x 2 x i64>,
- <vscale x 2 x i64>,
- <vscale x 2 x i64>,
- i64);
-
-define <vscale x 2 x i64> @intrinsic_vsub_vv_nxv2i64_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vsub_vv_nxv2i64_nxv2i64_nxv2i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
-; CHECK-NEXT: vsub.vv v8, v8, v10
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i64> @llvm.riscv.vsub.nxv2i64.nxv2i64(
- <vscale x 2 x i64> undef,
- <vscale x 2 x i64> %0,
- <vscale x 2 x i64> %1,
- i64 %2)
-
- ret <vscale x 2 x i64> %a
-}
-
-declare <vscale x 2 x i64> @llvm.riscv.vsub.mask.nxv2i64.nxv2i64(
- <vscale x 2 x i64>,
- <vscale x 2 x i64>,
- <vscale x 2 x i64>,
- <vscale x 2 x i1>,
- i64,
- i64);
-
-define <vscale x 2 x i64> @intrinsic_vsub_mask_vv_nxv2i64_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv2i64_nxv2i64_nxv2i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
-; CHECK-NEXT: vsub.vv v8, v10, v12, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i64> @llvm.riscv.vsub.mask.nxv2i64.nxv2i64(
- <vscale x 2 x i64> %0,
- <vscale x 2 x i64> %1,
- <vscale x 2 x i64> %2,
- <vscale x 2 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 2 x i64> %a
-}
-
-declare <vscale x 4 x i64> @llvm.riscv.vsub.nxv4i64.nxv4i64(
- <vscale x 4 x i64>,
- <vscale x 4 x i64>,
- <vscale x 4 x i64>,
- i64);
-
-define <vscale x 4 x i64> @intrinsic_vsub_vv_nxv4i64_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vsub_vv_nxv4i64_nxv4i64_nxv4i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
-; CHECK-NEXT: vsub.vv v8, v8, v12
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i64> @llvm.riscv.vsub.nxv4i64.nxv4i64(
- <vscale x 4 x i64> undef,
- <vscale x 4 x i64> %0,
- <vscale x 4 x i64> %1,
- i64 %2)
-
- ret <vscale x 4 x i64> %a
-}
-
-declare <vscale x 4 x i64> @llvm.riscv.vsub.mask.nxv4i64.nxv4i64(
- <vscale x 4 x i64>,
- <vscale x 4 x i64>,
- <vscale x 4 x i64>,
- <vscale x 4 x i1>,
- i64,
- i64);
-
-define <vscale x 4 x i64> @intrinsic_vsub_mask_vv_nxv4i64_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv4i64_nxv4i64_nxv4i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
-; CHECK-NEXT: vsub.vv v8, v12, v16, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i64> @llvm.riscv.vsub.mask.nxv4i64.nxv4i64(
- <vscale x 4 x i64> %0,
- <vscale x 4 x i64> %1,
- <vscale x 4 x i64> %2,
- <vscale x 4 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 4 x i64> %a
-}
-
-declare <vscale x 8 x i64> @llvm.riscv.vsub.nxv8i64.nxv8i64(
- <vscale x 8 x i64>,
- <vscale x 8 x i64>,
- <vscale x 8 x i64>,
- i64);
-
-define <vscale x 8 x i64> @intrinsic_vsub_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vsub_vv_nxv8i64_nxv8i64_nxv8i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu
-; CHECK-NEXT: vsub.vv v8, v8, v16
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i64> @llvm.riscv.vsub.nxv8i64.nxv8i64(
- <vscale x 8 x i64> undef,
- <vscale x 8 x i64> %0,
- <vscale x 8 x i64> %1,
- i64 %2)
-
- ret <vscale x 8 x i64> %a
-}
-
-declare <vscale x 8 x i64> @llvm.riscv.vsub.mask.nxv8i64.nxv8i64(
- <vscale x 8 x i64>,
- <vscale x 8 x i64>,
- <vscale x 8 x i64>,
- <vscale x 8 x i1>,
- i64,
- i64);
-
-define <vscale x 8 x i64> @intrinsic_vsub_mask_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv8i64_nxv8i64_nxv8i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vl8re64.v v24, (a0)
-; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu
-; CHECK-NEXT: vsub.vv v8, v16, v24, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i64> @llvm.riscv.vsub.mask.nxv8i64.nxv8i64(
- <vscale x 8 x i64> %0,
- <vscale x 8 x i64> %1,
- <vscale x 8 x i64> %2,
- <vscale x 8 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 8 x i64> %a
-}
-
-declare <vscale x 1 x i8> @llvm.riscv.vsub.nxv1i8.i8(
- <vscale x 1 x i8>,
- <vscale x 1 x i8>,
- i8,
- i64);
-
-define <vscale x 1 x i8> @intrinsic_vsub_vx_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, i8 %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vsub_vx_nxv1i8_nxv1i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
-; CHECK-NEXT: vsub.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i8> @llvm.riscv.vsub.nxv1i8.i8(
- <vscale x 1 x i8> undef,
- <vscale x 1 x i8> %0,
- i8 %1,
- i64 %2)
-
- ret <vscale x 1 x i8> %a
-}
-
-declare <vscale x 1 x i8> @llvm.riscv.vsub.mask.nxv1i8.i8(
- <vscale x 1 x i8>,
- <vscale x 1 x i8>,
- i8,
- <vscale x 1 x i1>,
- i64,
- i64);
-
-define <vscale x 1 x i8> @intrinsic_vsub_mask_vx_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vsub_mask_vx_nxv1i8_nxv1i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
-; CHECK-NEXT: vsub.vx v8, v9, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i8> @llvm.riscv.vsub.mask.nxv1i8.i8(
- <vscale x 1 x i8> %0,
- <vscale x 1 x i8> %1,
- i8 %2,
- <vscale x 1 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 1 x i8> %a
-}
-
-declare <vscale x 2 x i8> @llvm.riscv.vsub.nxv2i8.i8(
- <vscale x 2 x i8>,
- <vscale x 2 x i8>,
- i8,
- i64);
-
-define <vscale x 2 x i8> @intrinsic_vsub_vx_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, i8 %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vsub_vx_nxv2i8_nxv2i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
-; CHECK-NEXT: vsub.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i8> @llvm.riscv.vsub.nxv2i8.i8(
- <vscale x 2 x i8> undef,
- <vscale x 2 x i8> %0,
- i8 %1,
- i64 %2)
-
- ret <vscale x 2 x i8> %a
-}
-
-declare <vscale x 2 x i8> @llvm.riscv.vsub.mask.nxv2i8.i8(
- <vscale x 2 x i8>,
- <vscale x 2 x i8>,
- i8,
- <vscale x 2 x i1>,
- i64,
- i64);
-
-define <vscale x 2 x i8> @intrinsic_vsub_mask_vx_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vsub_mask_vx_nxv2i8_nxv2i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
-; CHECK-NEXT: vsub.vx v8, v9, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i8> @llvm.riscv.vsub.mask.nxv2i8.i8(
- <vscale x 2 x i8> %0,
- <vscale x 2 x i8> %1,
- i8 %2,
- <vscale x 2 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 2 x i8> %a
-}
-
-declare <vscale x 4 x i8> @llvm.riscv.vsub.nxv4i8.i8(
- <vscale x 4 x i8>,
- <vscale x 4 x i8>,
- i8,
- i64);
-
-define <vscale x 4 x i8> @intrinsic_vsub_vx_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, i8 %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vsub_vx_nxv4i8_nxv4i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
-; CHECK-NEXT: vsub.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i8> @llvm.riscv.vsub.nxv4i8.i8(
- <vscale x 4 x i8> undef,
- <vscale x 4 x i8> %0,
- i8 %1,
- i64 %2)
-
- ret <vscale x 4 x i8> %a
-}
-
-declare <vscale x 4 x i8> @llvm.riscv.vsub.mask.nxv4i8.i8(
- <vscale x 4 x i8>,
- <vscale x 4 x i8>,
- i8,
- <vscale x 4 x i1>,
- i64,
- i64);
-
-define <vscale x 4 x i8> @intrinsic_vsub_mask_vx_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vsub_mask_vx_nxv4i8_nxv4i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
-; CHECK-NEXT: vsub.vx v8, v9, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i8> @llvm.riscv.vsub.mask.nxv4i8.i8(
- <vscale x 4 x i8> %0,
- <vscale x 4 x i8> %1,
- i8 %2,
- <vscale x 4 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 4 x i8> %a
-}
-
-declare <vscale x 8 x i8> @llvm.riscv.vsub.nxv8i8.i8(
- <vscale x 8 x i8>,
- <vscale x 8 x i8>,
- i8,
- i64);
-
-define <vscale x 8 x i8> @intrinsic_vsub_vx_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, i8 %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vsub_vx_nxv8i8_nxv8i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
-; CHECK-NEXT: vsub.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i8> @llvm.riscv.vsub.nxv8i8.i8(
- <vscale x 8 x i8> undef,
- <vscale x 8 x i8> %0,
- i8 %1,
- i64 %2)
-
- ret <vscale x 8 x i8> %a
-}
-
-declare <vscale x 8 x i8> @llvm.riscv.vsub.mask.nxv8i8.i8(
- <vscale x 8 x i8>,
- <vscale x 8 x i8>,
- i8,
- <vscale x 8 x i1>,
- i64,
- i64);
-
-define <vscale x 8 x i8> @intrinsic_vsub_mask_vx_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vsub_mask_vx_nxv8i8_nxv8i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
-; CHECK-NEXT: vsub.vx v8, v9, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i8> @llvm.riscv.vsub.mask.nxv8i8.i8(
- <vscale x 8 x i8> %0,
- <vscale x 8 x i8> %1,
- i8 %2,
- <vscale x 8 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 8 x i8> %a
-}
-
-declare <vscale x 16 x i8> @llvm.riscv.vsub.nxv16i8.i8(
- <vscale x 16 x i8>,
- <vscale x 16 x i8>,
- i8,
- i64);
-
-define <vscale x 16 x i8> @intrinsic_vsub_vx_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, i8 %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vsub_vx_nxv16i8_nxv16i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
-; CHECK-NEXT: vsub.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i8> @llvm.riscv.vsub.nxv16i8.i8(
- <vscale x 16 x i8> undef,
- <vscale x 16 x i8> %0,
- i8 %1,
- i64 %2)
-
- ret <vscale x 16 x i8> %a
-}
-
-declare <vscale x 16 x i8> @llvm.riscv.vsub.mask.nxv16i8.i8(
- <vscale x 16 x i8>,
- <vscale x 16 x i8>,
- i8,
- <vscale x 16 x i1>,
- i64,
- i64);
-
-define <vscale x 16 x i8> @intrinsic_vsub_mask_vx_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vsub_mask_vx_nxv16i8_nxv16i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
-; CHECK-NEXT: vsub.vx v8, v10, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i8> @llvm.riscv.vsub.mask.nxv16i8.i8(
- <vscale x 16 x i8> %0,
- <vscale x 16 x i8> %1,
- i8 %2,
- <vscale x 16 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 16 x i8> %a
-}
-
-declare <vscale x 32 x i8> @llvm.riscv.vsub.nxv32i8.i8(
- <vscale x 32 x i8>,
- <vscale x 32 x i8>,
- i8,
- i64);
-
-define <vscale x 32 x i8> @intrinsic_vsub_vx_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, i8 %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vsub_vx_nxv32i8_nxv32i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
-; CHECK-NEXT: vsub.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 32 x i8> @llvm.riscv.vsub.nxv32i8.i8(
- <vscale x 32 x i8> undef,
- <vscale x 32 x i8> %0,
- i8 %1,
- i64 %2)
-
- ret <vscale x 32 x i8> %a
-}
-
-declare <vscale x 32 x i8> @llvm.riscv.vsub.mask.nxv32i8.i8(
- <vscale x 32 x i8>,
- <vscale x 32 x i8>,
- i8,
- <vscale x 32 x i1>,
- i64,
- i64);
-
-define <vscale x 32 x i8> @intrinsic_vsub_mask_vx_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vsub_mask_vx_nxv32i8_nxv32i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
-; CHECK-NEXT: vsub.vx v8, v12, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 32 x i8> @llvm.riscv.vsub.mask.nxv32i8.i8(
- <vscale x 32 x i8> %0,
- <vscale x 32 x i8> %1,
- i8 %2,
- <vscale x 32 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 32 x i8> %a
-}
-
-declare <vscale x 64 x i8> @llvm.riscv.vsub.nxv64i8.i8(
- <vscale x 64 x i8>,
- <vscale x 64 x i8>,
- i8,
- i64);
-
-define <vscale x 64 x i8> @intrinsic_vsub_vx_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, i8 %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vsub_vx_nxv64i8_nxv64i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu
-; CHECK-NEXT: vsub.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 64 x i8> @llvm.riscv.vsub.nxv64i8.i8(
- <vscale x 64 x i8> undef,
- <vscale x 64 x i8> %0,
- i8 %1,
- i64 %2)
-
- ret <vscale x 64 x i8> %a
-}
-
-declare <vscale x 64 x i8> @llvm.riscv.vsub.mask.nxv64i8.i8(
- <vscale x 64 x i8>,
- <vscale x 64 x i8>,
- i8,
- <vscale x 64 x i1>,
- i64,
- i64);
-
-define <vscale x 64 x i8> @intrinsic_vsub_mask_vx_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i8 %2, <vscale x 64 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vsub_mask_vx_nxv64i8_nxv64i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu
-; CHECK-NEXT: vsub.vx v8, v16, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 64 x i8> @llvm.riscv.vsub.mask.nxv64i8.i8(
- <vscale x 64 x i8> %0,
- <vscale x 64 x i8> %1,
- i8 %2,
- <vscale x 64 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 64 x i8> %a
-}
-
-declare <vscale x 1 x i16> @llvm.riscv.vsub.nxv1i16.i16(
- <vscale x 1 x i16>,
- <vscale x 1 x i16>,
- i16,
- i64);
-
-define <vscale x 1 x i16> @intrinsic_vsub_vx_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, i16 %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vsub_vx_nxv1i16_nxv1i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
-; CHECK-NEXT: vsub.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i16> @llvm.riscv.vsub.nxv1i16.i16(
- <vscale x 1 x i16> undef,
- <vscale x 1 x i16> %0,
- i16 %1,
- i64 %2)
-
- ret <vscale x 1 x i16> %a
-}
-
-declare <vscale x 1 x i16> @llvm.riscv.vsub.mask.nxv1i16.i16(
- <vscale x 1 x i16>,
- <vscale x 1 x i16>,
- i16,
- <vscale x 1 x i1>,
- i64,
- i64);
-
-define <vscale x 1 x i16> @intrinsic_vsub_mask_vx_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vsub_mask_vx_nxv1i16_nxv1i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
-; CHECK-NEXT: vsub.vx v8, v9, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i16> @llvm.riscv.vsub.mask.nxv1i16.i16(
- <vscale x 1 x i16> %0,
- <vscale x 1 x i16> %1,
- i16 %2,
- <vscale x 1 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 1 x i16> %a
-}
-
-declare <vscale x 2 x i16> @llvm.riscv.vsub.nxv2i16.i16(
- <vscale x 2 x i16>,
- <vscale x 2 x i16>,
- i16,
- i64);
-
-define <vscale x 2 x i16> @intrinsic_vsub_vx_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, i16 %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vsub_vx_nxv2i16_nxv2i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
-; CHECK-NEXT: vsub.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i16> @llvm.riscv.vsub.nxv2i16.i16(
- <vscale x 2 x i16> undef,
- <vscale x 2 x i16> %0,
- i16 %1,
- i64 %2)
-
- ret <vscale x 2 x i16> %a
-}
-
-declare <vscale x 2 x i16> @llvm.riscv.vsub.mask.nxv2i16.i16(
- <vscale x 2 x i16>,
- <vscale x 2 x i16>,
- i16,
- <vscale x 2 x i1>,
- i64,
- i64);
-
-define <vscale x 2 x i16> @intrinsic_vsub_mask_vx_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vsub_mask_vx_nxv2i16_nxv2i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
-; CHECK-NEXT: vsub.vx v8, v9, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i16> @llvm.riscv.vsub.mask.nxv2i16.i16(
- <vscale x 2 x i16> %0,
- <vscale x 2 x i16> %1,
- i16 %2,
- <vscale x 2 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 2 x i16> %a
-}
-
-declare <vscale x 4 x i16> @llvm.riscv.vsub.nxv4i16.i16(
- <vscale x 4 x i16>,
- <vscale x 4 x i16>,
- i16,
- i64);
-
-define <vscale x 4 x i16> @intrinsic_vsub_vx_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, i16 %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vsub_vx_nxv4i16_nxv4i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
-; CHECK-NEXT: vsub.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i16> @llvm.riscv.vsub.nxv4i16.i16(
- <vscale x 4 x i16> undef,
- <vscale x 4 x i16> %0,
- i16 %1,
- i64 %2)
-
- ret <vscale x 4 x i16> %a
-}
-
-declare <vscale x 4 x i16> @llvm.riscv.vsub.mask.nxv4i16.i16(
- <vscale x 4 x i16>,
- <vscale x 4 x i16>,
- i16,
- <vscale x 4 x i1>,
- i64,
- i64);
-
-define <vscale x 4 x i16> @intrinsic_vsub_mask_vx_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vsub_mask_vx_nxv4i16_nxv4i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
-; CHECK-NEXT: vsub.vx v8, v9, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i16> @llvm.riscv.vsub.mask.nxv4i16.i16(
- <vscale x 4 x i16> %0,
- <vscale x 4 x i16> %1,
- i16 %2,
- <vscale x 4 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 4 x i16> %a
-}
-
-declare <vscale x 8 x i16> @llvm.riscv.vsub.nxv8i16.i16(
- <vscale x 8 x i16>,
- <vscale x 8 x i16>,
- i16,
- i64);
-
-define <vscale x 8 x i16> @intrinsic_vsub_vx_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, i16 %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vsub_vx_nxv8i16_nxv8i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
-; CHECK-NEXT: vsub.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i16> @llvm.riscv.vsub.nxv8i16.i16(
- <vscale x 8 x i16> undef,
- <vscale x 8 x i16> %0,
- i16 %1,
- i64 %2)
-
- ret <vscale x 8 x i16> %a
-}
-
-declare <vscale x 8 x i16> @llvm.riscv.vsub.mask.nxv8i16.i16(
- <vscale x 8 x i16>,
- <vscale x 8 x i16>,
- i16,
- <vscale x 8 x i1>,
- i64,
- i64);
-
-define <vscale x 8 x i16> @intrinsic_vsub_mask_vx_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vsub_mask_vx_nxv8i16_nxv8i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
-; CHECK-NEXT: vsub.vx v8, v10, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i16> @llvm.riscv.vsub.mask.nxv8i16.i16(
- <vscale x 8 x i16> %0,
- <vscale x 8 x i16> %1,
- i16 %2,
- <vscale x 8 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 8 x i16> %a
-}
-
-declare <vscale x 16 x i16> @llvm.riscv.vsub.nxv16i16.i16(
- <vscale x 16 x i16>,
- <vscale x 16 x i16>,
- i16,
- i64);
-
-define <vscale x 16 x i16> @intrinsic_vsub_vx_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, i16 %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vsub_vx_nxv16i16_nxv16i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
-; CHECK-NEXT: vsub.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i16> @llvm.riscv.vsub.nxv16i16.i16(
- <vscale x 16 x i16> undef,
- <vscale x 16 x i16> %0,
- i16 %1,
- i64 %2)
-
- ret <vscale x 16 x i16> %a
-}
-
-declare <vscale x 16 x i16> @llvm.riscv.vsub.mask.nxv16i16.i16(
- <vscale x 16 x i16>,
- <vscale x 16 x i16>,
- i16,
- <vscale x 16 x i1>,
- i64,
- i64);
-
-define <vscale x 16 x i16> @intrinsic_vsub_mask_vx_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vsub_mask_vx_nxv16i16_nxv16i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
-; CHECK-NEXT: vsub.vx v8, v12, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i16> @llvm.riscv.vsub.mask.nxv16i16.i16(
- <vscale x 16 x i16> %0,
- <vscale x 16 x i16> %1,
- i16 %2,
- <vscale x 16 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 16 x i16> %a
-}
-
-declare <vscale x 32 x i16> @llvm.riscv.vsub.nxv32i16.i16(
- <vscale x 32 x i16>,
- <vscale x 32 x i16>,
- i16,
- i64);
-
-define <vscale x 32 x i16> @intrinsic_vsub_vx_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, i16 %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vsub_vx_nxv32i16_nxv32i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu
-; CHECK-NEXT: vsub.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 32 x i16> @llvm.riscv.vsub.nxv32i16.i16(
- <vscale x 32 x i16> undef,
- <vscale x 32 x i16> %0,
- i16 %1,
- i64 %2)
-
- ret <vscale x 32 x i16> %a
-}
-
-declare <vscale x 32 x i16> @llvm.riscv.vsub.mask.nxv32i16.i16(
- <vscale x 32 x i16>,
- <vscale x 32 x i16>,
- i16,
- <vscale x 32 x i1>,
- i64,
- i64);
-
-define <vscale x 32 x i16> @intrinsic_vsub_mask_vx_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, i16 %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vsub_mask_vx_nxv32i16_nxv32i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu
-; CHECK-NEXT: vsub.vx v8, v16, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 32 x i16> @llvm.riscv.vsub.mask.nxv32i16.i16(
- <vscale x 32 x i16> %0,
- <vscale x 32 x i16> %1,
- i16 %2,
- <vscale x 32 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 32 x i16> %a
-}
-
-declare <vscale x 1 x i32> @llvm.riscv.vsub.nxv1i32.i32(
- <vscale x 1 x i32>,
- <vscale x 1 x i32>,
- i32,
- i64);
-
-define <vscale x 1 x i32> @intrinsic_vsub_vx_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, i32 %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vsub_vx_nxv1i32_nxv1i32_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
-; CHECK-NEXT: vsub.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i32> @llvm.riscv.vsub.nxv1i32.i32(
- <vscale x 1 x i32> undef,
- <vscale x 1 x i32> %0,
- i32 %1,
- i64 %2)
-
- ret <vscale x 1 x i32> %a
-}
-
-declare <vscale x 1 x i32> @llvm.riscv.vsub.mask.nxv1i32.i32(
- <vscale x 1 x i32>,
- <vscale x 1 x i32>,
- i32,
- <vscale x 1 x i1>,
- i64,
- i64);
-
-define <vscale x 1 x i32> @intrinsic_vsub_mask_vx_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vsub_mask_vx_nxv1i32_nxv1i32_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
-; CHECK-NEXT: vsub.vx v8, v9, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i32> @llvm.riscv.vsub.mask.nxv1i32.i32(
- <vscale x 1 x i32> %0,
- <vscale x 1 x i32> %1,
- i32 %2,
- <vscale x 1 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 1 x i32> %a
-}
-
-declare <vscale x 2 x i32> @llvm.riscv.vsub.nxv2i32.i32(
- <vscale x 2 x i32>,
- <vscale x 2 x i32>,
- i32,
- i64);
-
-define <vscale x 2 x i32> @intrinsic_vsub_vx_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, i32 %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vsub_vx_nxv2i32_nxv2i32_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
-; CHECK-NEXT: vsub.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i32> @llvm.riscv.vsub.nxv2i32.i32(
- <vscale x 2 x i32> undef,
- <vscale x 2 x i32> %0,
- i32 %1,
- i64 %2)
-
- ret <vscale x 2 x i32> %a
-}
-
-declare <vscale x 2 x i32> @llvm.riscv.vsub.mask.nxv2i32.i32(
- <vscale x 2 x i32>,
- <vscale x 2 x i32>,
- i32,
- <vscale x 2 x i1>,
- i64,
- i64);
-
-define <vscale x 2 x i32> @intrinsic_vsub_mask_vx_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vsub_mask_vx_nxv2i32_nxv2i32_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
-; CHECK-NEXT: vsub.vx v8, v9, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i32> @llvm.riscv.vsub.mask.nxv2i32.i32(
- <vscale x 2 x i32> %0,
- <vscale x 2 x i32> %1,
- i32 %2,
- <vscale x 2 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 2 x i32> %a
-}
-
-declare <vscale x 4 x i32> @llvm.riscv.vsub.nxv4i32.i32(
- <vscale x 4 x i32>,
- <vscale x 4 x i32>,
- i32,
- i64);
-
-define <vscale x 4 x i32> @intrinsic_vsub_vx_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, i32 %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vsub_vx_nxv4i32_nxv4i32_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; CHECK-NEXT: vsub.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i32> @llvm.riscv.vsub.nxv4i32.i32(
- <vscale x 4 x i32> undef,
- <vscale x 4 x i32> %0,
- i32 %1,
- i64 %2)
-
- ret <vscale x 4 x i32> %a
-}
-
-declare <vscale x 4 x i32> @llvm.riscv.vsub.mask.nxv4i32.i32(
- <vscale x 4 x i32>,
- <vscale x 4 x i32>,
- i32,
- <vscale x 4 x i1>,
- i64,
- i64);
-
-define <vscale x 4 x i32> @intrinsic_vsub_mask_vx_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vsub_mask_vx_nxv4i32_nxv4i32_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
-; CHECK-NEXT: vsub.vx v8, v10, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i32> @llvm.riscv.vsub.mask.nxv4i32.i32(
- <vscale x 4 x i32> %0,
- <vscale x 4 x i32> %1,
- i32 %2,
- <vscale x 4 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 4 x i32> %a
-}
-
-declare <vscale x 8 x i32> @llvm.riscv.vsub.nxv8i32.i32(
- <vscale x 8 x i32>,
- <vscale x 8 x i32>,
- i32,
- i64);
-
-define <vscale x 8 x i32> @intrinsic_vsub_vx_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, i32 %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vsub_vx_nxv8i32_nxv8i32_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
-; CHECK-NEXT: vsub.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i32> @llvm.riscv.vsub.nxv8i32.i32(
- <vscale x 8 x i32> undef,
- <vscale x 8 x i32> %0,
- i32 %1,
- i64 %2)
-
- ret <vscale x 8 x i32> %a
-}
-
-declare <vscale x 8 x i32> @llvm.riscv.vsub.mask.nxv8i32.i32(
- <vscale x 8 x i32>,
- <vscale x 8 x i32>,
- i32,
- <vscale x 8 x i1>,
- i64,
- i64);
-
-define <vscale x 8 x i32> @intrinsic_vsub_mask_vx_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vsub_mask_vx_nxv8i32_nxv8i32_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
-; CHECK-NEXT: vsub.vx v8, v12, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i32> @llvm.riscv.vsub.mask.nxv8i32.i32(
- <vscale x 8 x i32> %0,
- <vscale x 8 x i32> %1,
- i32 %2,
- <vscale x 8 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 8 x i32> %a
-}
-
-declare <vscale x 16 x i32> @llvm.riscv.vsub.nxv16i32.i32(
- <vscale x 16 x i32>,
- <vscale x 16 x i32>,
- i32,
- i64);
-
-define <vscale x 16 x i32> @intrinsic_vsub_vx_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, i32 %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vsub_vx_nxv16i32_nxv16i32_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu
-; CHECK-NEXT: vsub.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i32> @llvm.riscv.vsub.nxv16i32.i32(
- <vscale x 16 x i32> undef,
- <vscale x 16 x i32> %0,
- i32 %1,
- i64 %2)
-
- ret <vscale x 16 x i32> %a
-}
-
-declare <vscale x 16 x i32> @llvm.riscv.vsub.mask.nxv16i32.i32(
- <vscale x 16 x i32>,
- <vscale x 16 x i32>,
- i32,
- <vscale x 16 x i1>,
- i64,
- i64);
-
-define <vscale x 16 x i32> @intrinsic_vsub_mask_vx_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vsub_mask_vx_nxv16i32_nxv16i32_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu
-; CHECK-NEXT: vsub.vx v8, v16, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i32> @llvm.riscv.vsub.mask.nxv16i32.i32(
- <vscale x 16 x i32> %0,
- <vscale x 16 x i32> %1,
- i32 %2,
- <vscale x 16 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 16 x i32> %a
-}
-
-declare <vscale x 1 x i64> @llvm.riscv.vsub.nxv1i64.i64(
- <vscale x 1 x i64>,
- <vscale x 1 x i64>,
- i64,
- i64);
-
-define <vscale x 1 x i64> @intrinsic_vsub_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vsub_vx_nxv1i64_nxv1i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
-; CHECK-NEXT: vsub.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i64> @llvm.riscv.vsub.nxv1i64.i64(
- <vscale x 1 x i64> undef,
- <vscale x 1 x i64> %0,
- i64 %1,
- i64 %2)
-
- ret <vscale x 1 x i64> %a
-}
-
-declare <vscale x 1 x i64> @llvm.riscv.vsub.mask.nxv1i64.i64(
- <vscale x 1 x i64>,
- <vscale x 1 x i64>,
- i64,
- <vscale x 1 x i1>,
- i64,
- i64);
-
-define <vscale x 1 x i64> @intrinsic_vsub_mask_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vsub_mask_vx_nxv1i64_nxv1i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
-; CHECK-NEXT: vsub.vx v8, v9, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i64> @llvm.riscv.vsub.mask.nxv1i64.i64(
- <vscale x 1 x i64> %0,
- <vscale x 1 x i64> %1,
- i64 %2,
- <vscale x 1 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 1 x i64> %a
-}
-
-declare <vscale x 2 x i64> @llvm.riscv.vsub.nxv2i64.i64(
- <vscale x 2 x i64>,
- <vscale x 2 x i64>,
- i64,
- i64);
-
-define <vscale x 2 x i64> @intrinsic_vsub_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vsub_vx_nxv2i64_nxv2i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
-; CHECK-NEXT: vsub.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i64> @llvm.riscv.vsub.nxv2i64.i64(
- <vscale x 2 x i64> undef,
- <vscale x 2 x i64> %0,
- i64 %1,
- i64 %2)
-
- ret <vscale x 2 x i64> %a
-}
-
-declare <vscale x 2 x i64> @llvm.riscv.vsub.mask.nxv2i64.i64(
- <vscale x 2 x i64>,
- <vscale x 2 x i64>,
- i64,
- <vscale x 2 x i1>,
- i64,
- i64);
-
-define <vscale x 2 x i64> @intrinsic_vsub_mask_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vsub_mask_vx_nxv2i64_nxv2i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
-; CHECK-NEXT: vsub.vx v8, v10, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i64> @llvm.riscv.vsub.mask.nxv2i64.i64(
- <vscale x 2 x i64> %0,
- <vscale x 2 x i64> %1,
- i64 %2,
- <vscale x 2 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 2 x i64> %a
-}
-
-declare <vscale x 4 x i64> @llvm.riscv.vsub.nxv4i64.i64(
- <vscale x 4 x i64>,
- <vscale x 4 x i64>,
- i64,
- i64);
-
-define <vscale x 4 x i64> @intrinsic_vsub_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vsub_vx_nxv4i64_nxv4i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
-; CHECK-NEXT: vsub.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i64> @llvm.riscv.vsub.nxv4i64.i64(
- <vscale x 4 x i64> undef,
- <vscale x 4 x i64> %0,
- i64 %1,
- i64 %2)
-
- ret <vscale x 4 x i64> %a
-}
-
-declare <vscale x 4 x i64> @llvm.riscv.vsub.mask.nxv4i64.i64(
- <vscale x 4 x i64>,
- <vscale x 4 x i64>,
- i64,
- <vscale x 4 x i1>,
- i64,
- i64);
-
-define <vscale x 4 x i64> @intrinsic_vsub_mask_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vsub_mask_vx_nxv4i64_nxv4i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
-; CHECK-NEXT: vsub.vx v8, v12, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i64> @llvm.riscv.vsub.mask.nxv4i64.i64(
- <vscale x 4 x i64> %0,
- <vscale x 4 x i64> %1,
- i64 %2,
- <vscale x 4 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 4 x i64> %a
-}
-
-declare <vscale x 8 x i64> @llvm.riscv.vsub.nxv8i64.i64(
- <vscale x 8 x i64>,
- <vscale x 8 x i64>,
- i64,
- i64);
-
-define <vscale x 8 x i64> @intrinsic_vsub_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, i64 %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vsub_vx_nxv8i64_nxv8i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu
-; CHECK-NEXT: vsub.vx v8, v8, a0
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i64> @llvm.riscv.vsub.nxv8i64.i64(
- <vscale x 8 x i64> undef,
- <vscale x 8 x i64> %0,
- i64 %1,
- i64 %2)
-
- ret <vscale x 8 x i64> %a
-}
-
-declare <vscale x 8 x i64> @llvm.riscv.vsub.mask.nxv8i64.i64(
- <vscale x 8 x i64>,
- <vscale x 8 x i64>,
- i64,
- <vscale x 8 x i1>,
- i64,
- i64);
-
-define <vscale x 8 x i64> @intrinsic_vsub_mask_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
-; CHECK-LABEL: intrinsic_vsub_mask_vx_nxv8i64_nxv8i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu
-; CHECK-NEXT: vsub.vx v8, v16, a0, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i64> @llvm.riscv.vsub.mask.nxv8i64.i64(
- <vscale x 8 x i64> %0,
- <vscale x 8 x i64> %1,
- i64 %2,
- <vscale x 8 x i1> %3,
- i64 %4, i64 1)
-
- ret <vscale x 8 x i64> %a
-}
-
-define <vscale x 1 x i8> @intrinsic_vsub_vi_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, i64 %1) nounwind {
-; CHECK-LABEL: intrinsic_vsub_vi_nxv1i8_nxv1i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
-; CHECK-NEXT: vadd.vi v8, v8, -9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i8> @llvm.riscv.vsub.nxv1i8.i8(
- <vscale x 1 x i8> undef,
- <vscale x 1 x i8> %0,
- i8 9,
- i64 %1)
-
- ret <vscale x 1 x i8> %a
-}
-
-define <vscale x 1 x i8> @intrinsic_vsub_mask_vi_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vsub_mask_vi_nxv1i8_nxv1i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
-; CHECK-NEXT: vadd.vi v8, v9, -9, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i8> @llvm.riscv.vsub.mask.nxv1i8.i8(
- <vscale x 1 x i8> %0,
- <vscale x 1 x i8> %1,
- i8 9,
- <vscale x 1 x i1> %2,
- i64 %3, i64 1)
-
- ret <vscale x 1 x i8> %a
-}
-
-define <vscale x 2 x i8> @intrinsic_vsub_vi_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, i64 %1) nounwind {
-; CHECK-LABEL: intrinsic_vsub_vi_nxv2i8_nxv2i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
-; CHECK-NEXT: vadd.vi v8, v8, -9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i8> @llvm.riscv.vsub.nxv2i8.i8(
- <vscale x 2 x i8> undef,
- <vscale x 2 x i8> %0,
- i8 9,
- i64 %1)
-
- ret <vscale x 2 x i8> %a
-}
-
-define <vscale x 2 x i8> @intrinsic_vsub_mask_vi_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vsub_mask_vi_nxv2i8_nxv2i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
-; CHECK-NEXT: vadd.vi v8, v9, -9, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i8> @llvm.riscv.vsub.mask.nxv2i8.i8(
- <vscale x 2 x i8> %0,
- <vscale x 2 x i8> %1,
- i8 9,
- <vscale x 2 x i1> %2,
- i64 %3, i64 1)
-
- ret <vscale x 2 x i8> %a
-}
-
-define <vscale x 4 x i8> @intrinsic_vsub_vi_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, i64 %1) nounwind {
-; CHECK-LABEL: intrinsic_vsub_vi_nxv4i8_nxv4i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
-; CHECK-NEXT: vadd.vi v8, v8, -9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i8> @llvm.riscv.vsub.nxv4i8.i8(
- <vscale x 4 x i8> undef,
- <vscale x 4 x i8> %0,
- i8 9,
- i64 %1)
-
- ret <vscale x 4 x i8> %a
-}
-
-define <vscale x 4 x i8> @intrinsic_vsub_mask_vi_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vsub_mask_vi_nxv4i8_nxv4i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
-; CHECK-NEXT: vadd.vi v8, v9, -9, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i8> @llvm.riscv.vsub.mask.nxv4i8.i8(
- <vscale x 4 x i8> %0,
- <vscale x 4 x i8> %1,
- i8 9,
- <vscale x 4 x i1> %2,
- i64 %3, i64 1)
-
- ret <vscale x 4 x i8> %a
-}
-
-define <vscale x 8 x i8> @intrinsic_vsub_vi_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, i64 %1) nounwind {
-; CHECK-LABEL: intrinsic_vsub_vi_nxv8i8_nxv8i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
-; CHECK-NEXT: vadd.vi v8, v8, -9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i8> @llvm.riscv.vsub.nxv8i8.i8(
- <vscale x 8 x i8> undef,
- <vscale x 8 x i8> %0,
- i8 9,
- i64 %1)
-
- ret <vscale x 8 x i8> %a
-}
-
-define <vscale x 8 x i8> @intrinsic_vsub_mask_vi_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vsub_mask_vi_nxv8i8_nxv8i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
-; CHECK-NEXT: vadd.vi v8, v9, -9, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i8> @llvm.riscv.vsub.mask.nxv8i8.i8(
- <vscale x 8 x i8> %0,
- <vscale x 8 x i8> %1,
- i8 9,
- <vscale x 8 x i1> %2,
- i64 %3, i64 1)
-
- ret <vscale x 8 x i8> %a
-}
-
-define <vscale x 16 x i8> @intrinsic_vsub_vi_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, i64 %1) nounwind {
-; CHECK-LABEL: intrinsic_vsub_vi_nxv16i8_nxv16i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
-; CHECK-NEXT: vadd.vi v8, v8, -9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i8> @llvm.riscv.vsub.nxv16i8.i8(
- <vscale x 16 x i8> undef,
- <vscale x 16 x i8> %0,
- i8 9,
- i64 %1)
-
- ret <vscale x 16 x i8> %a
-}
-
-define <vscale x 16 x i8> @intrinsic_vsub_mask_vi_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i1> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vsub_mask_vi_nxv16i8_nxv16i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
-; CHECK-NEXT: vadd.vi v8, v10, -9, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i8> @llvm.riscv.vsub.mask.nxv16i8.i8(
- <vscale x 16 x i8> %0,
- <vscale x 16 x i8> %1,
- i8 9,
- <vscale x 16 x i1> %2,
- i64 %3, i64 1)
-
- ret <vscale x 16 x i8> %a
-}
-
-define <vscale x 32 x i8> @intrinsic_vsub_vi_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, i64 %1) nounwind {
-; CHECK-LABEL: intrinsic_vsub_vi_nxv32i8_nxv32i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
-; CHECK-NEXT: vadd.vi v8, v8, -9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 32 x i8> @llvm.riscv.vsub.nxv32i8.i8(
- <vscale x 32 x i8> undef,
- <vscale x 32 x i8> %0,
- i8 9,
- i64 %1)
-
- ret <vscale x 32 x i8> %a
-}
-
-define <vscale x 32 x i8> @intrinsic_vsub_mask_vi_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i1> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vsub_mask_vi_nxv32i8_nxv32i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
-; CHECK-NEXT: vadd.vi v8, v12, -9, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 32 x i8> @llvm.riscv.vsub.mask.nxv32i8.i8(
- <vscale x 32 x i8> %0,
- <vscale x 32 x i8> %1,
- i8 9,
- <vscale x 32 x i1> %2,
- i64 %3, i64 1)
-
- ret <vscale x 32 x i8> %a
-}
-
-define <vscale x 64 x i8> @intrinsic_vsub_vi_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, i64 %1) nounwind {
-; CHECK-LABEL: intrinsic_vsub_vi_nxv64i8_nxv64i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, mu
-; CHECK-NEXT: vadd.vi v8, v8, -9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 64 x i8> @llvm.riscv.vsub.nxv64i8.i8(
- <vscale x 64 x i8> undef,
- <vscale x 64 x i8> %0,
- i8 9,
- i64 %1)
-
- ret <vscale x 64 x i8> %a
-}
-
-define <vscale x 64 x i8> @intrinsic_vsub_mask_vi_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i1> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vsub_mask_vi_nxv64i8_nxv64i8_i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, mu
-; CHECK-NEXT: vadd.vi v8, v16, -9, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 64 x i8> @llvm.riscv.vsub.mask.nxv64i8.i8(
- <vscale x 64 x i8> %0,
- <vscale x 64 x i8> %1,
- i8 9,
- <vscale x 64 x i1> %2,
- i64 %3, i64 1)
-
- ret <vscale x 64 x i8> %a
-}
-
-define <vscale x 1 x i16> @intrinsic_vsub_vi_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, i64 %1) nounwind {
-; CHECK-LABEL: intrinsic_vsub_vi_nxv1i16_nxv1i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vadd.vi v8, v8, -9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i16> @llvm.riscv.vsub.nxv1i16.i16(
- <vscale x 1 x i16> undef,
- <vscale x 1 x i16> %0,
- i16 9,
- i64 %1)
-
- ret <vscale x 1 x i16> %a
-}
-
-define <vscale x 1 x i16> @intrinsic_vsub_mask_vi_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vsub_mask_vi_nxv1i16_nxv1i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
-; CHECK-NEXT: vadd.vi v8, v9, -9, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i16> @llvm.riscv.vsub.mask.nxv1i16.i16(
- <vscale x 1 x i16> %0,
- <vscale x 1 x i16> %1,
- i16 9,
- <vscale x 1 x i1> %2,
- i64 %3, i64 1)
-
- ret <vscale x 1 x i16> %a
-}
-
-define <vscale x 2 x i16> @intrinsic_vsub_vi_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, i64 %1) nounwind {
-; CHECK-LABEL: intrinsic_vsub_vi_nxv2i16_nxv2i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vadd.vi v8, v8, -9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i16> @llvm.riscv.vsub.nxv2i16.i16(
- <vscale x 2 x i16> undef,
- <vscale x 2 x i16> %0,
- i16 9,
- i64 %1)
-
- ret <vscale x 2 x i16> %a
-}
-
-define <vscale x 2 x i16> @intrinsic_vsub_mask_vi_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vsub_mask_vi_nxv2i16_nxv2i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vadd.vi v8, v9, -9, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i16> @llvm.riscv.vsub.mask.nxv2i16.i16(
- <vscale x 2 x i16> %0,
- <vscale x 2 x i16> %1,
- i16 9,
- <vscale x 2 x i1> %2,
- i64 %3, i64 1)
-
- ret <vscale x 2 x i16> %a
-}
-
-define <vscale x 4 x i16> @intrinsic_vsub_vi_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, i64 %1) nounwind {
-; CHECK-LABEL: intrinsic_vsub_vi_nxv4i16_nxv4i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vadd.vi v8, v8, -9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i16> @llvm.riscv.vsub.nxv4i16.i16(
- <vscale x 4 x i16> undef,
- <vscale x 4 x i16> %0,
- i16 9,
- i64 %1)
-
- ret <vscale x 4 x i16> %a
-}
-
-define <vscale x 4 x i16> @intrinsic_vsub_mask_vi_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vsub_mask_vi_nxv4i16_nxv4i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
-; CHECK-NEXT: vadd.vi v8, v9, -9, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i16> @llvm.riscv.vsub.mask.nxv4i16.i16(
- <vscale x 4 x i16> %0,
- <vscale x 4 x i16> %1,
- i16 9,
- <vscale x 4 x i1> %2,
- i64 %3, i64 1)
-
- ret <vscale x 4 x i16> %a
-}
-
-define <vscale x 8 x i16> @intrinsic_vsub_vi_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, i64 %1) nounwind {
-; CHECK-LABEL: intrinsic_vsub_vi_nxv8i16_nxv8i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vadd.vi v8, v8, -9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i16> @llvm.riscv.vsub.nxv8i16.i16(
- <vscale x 8 x i16> undef,
- <vscale x 8 x i16> %0,
- i16 9,
- i64 %1)
-
- ret <vscale x 8 x i16> %a
-}
-
-define <vscale x 8 x i16> @intrinsic_vsub_mask_vi_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vsub_mask_vi_nxv8i16_nxv8i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
-; CHECK-NEXT: vadd.vi v8, v10, -9, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i16> @llvm.riscv.vsub.mask.nxv8i16.i16(
- <vscale x 8 x i16> %0,
- <vscale x 8 x i16> %1,
- i16 9,
- <vscale x 8 x i1> %2,
- i64 %3, i64 1)
-
- ret <vscale x 8 x i16> %a
-}
-
-define <vscale x 16 x i16> @intrinsic_vsub_vi_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, i64 %1) nounwind {
-; CHECK-LABEL: intrinsic_vsub_vi_nxv16i16_nxv16i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
-; CHECK-NEXT: vadd.vi v8, v8, -9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i16> @llvm.riscv.vsub.nxv16i16.i16(
- <vscale x 16 x i16> undef,
- <vscale x 16 x i16> %0,
- i16 9,
- i64 %1)
-
- ret <vscale x 16 x i16> %a
-}
-
-define <vscale x 16 x i16> @intrinsic_vsub_mask_vi_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i1> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vsub_mask_vi_nxv16i16_nxv16i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
-; CHECK-NEXT: vadd.vi v8, v12, -9, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i16> @llvm.riscv.vsub.mask.nxv16i16.i16(
- <vscale x 16 x i16> %0,
- <vscale x 16 x i16> %1,
- i16 9,
- <vscale x 16 x i1> %2,
- i64 %3, i64 1)
-
- ret <vscale x 16 x i16> %a
-}
-
-define <vscale x 32 x i16> @intrinsic_vsub_vi_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, i64 %1) nounwind {
-; CHECK-LABEL: intrinsic_vsub_vi_nxv32i16_nxv32i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, mu
-; CHECK-NEXT: vadd.vi v8, v8, -9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 32 x i16> @llvm.riscv.vsub.nxv32i16.i16(
- <vscale x 32 x i16> undef,
- <vscale x 32 x i16> %0,
- i16 9,
- i64 %1)
-
- ret <vscale x 32 x i16> %a
-}
-
-define <vscale x 32 x i16> @intrinsic_vsub_mask_vi_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i1> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vsub_mask_vi_nxv32i16_nxv32i16_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, mu
-; CHECK-NEXT: vadd.vi v8, v16, -9, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 32 x i16> @llvm.riscv.vsub.mask.nxv32i16.i16(
- <vscale x 32 x i16> %0,
- <vscale x 32 x i16> %1,
- i16 9,
- <vscale x 32 x i1> %2,
- i64 %3, i64 1)
-
- ret <vscale x 32 x i16> %a
-}
-
-define <vscale x 1 x i32> @intrinsic_vsub_vi_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, i64 %1) nounwind {
-; CHECK-LABEL: intrinsic_vsub_vi_nxv1i32_nxv1i32_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vadd.vi v8, v8, -9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i32> @llvm.riscv.vsub.nxv1i32.i32(
- <vscale x 1 x i32> undef,
- <vscale x 1 x i32> %0,
- i32 9,
- i64 %1)
-
- ret <vscale x 1 x i32> %a
-}
-
-define <vscale x 1 x i32> @intrinsic_vsub_mask_vi_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vsub_mask_vi_nxv1i32_nxv1i32_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vadd.vi v8, v9, -9, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i32> @llvm.riscv.vsub.mask.nxv1i32.i32(
- <vscale x 1 x i32> %0,
- <vscale x 1 x i32> %1,
- i32 9,
- <vscale x 1 x i1> %2,
- i64 %3, i64 1)
-
- ret <vscale x 1 x i32> %a
-}
-
-define <vscale x 2 x i32> @intrinsic_vsub_vi_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, i64 %1) nounwind {
-; CHECK-LABEL: intrinsic_vsub_vi_nxv2i32_nxv2i32_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vadd.vi v8, v8, -9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i32> @llvm.riscv.vsub.nxv2i32.i32(
- <vscale x 2 x i32> undef,
- <vscale x 2 x i32> %0,
- i32 9,
- i64 %1)
-
- ret <vscale x 2 x i32> %a
-}
-
-define <vscale x 2 x i32> @intrinsic_vsub_mask_vi_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vsub_mask_vi_nxv2i32_nxv2i32_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT: vadd.vi v8, v9, -9, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i32> @llvm.riscv.vsub.mask.nxv2i32.i32(
- <vscale x 2 x i32> %0,
- <vscale x 2 x i32> %1,
- i32 9,
- <vscale x 2 x i1> %2,
- i64 %3, i64 1)
-
- ret <vscale x 2 x i32> %a
-}
-
-define <vscale x 4 x i32> @intrinsic_vsub_vi_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, i64 %1) nounwind {
-; CHECK-LABEL: intrinsic_vsub_vi_nxv4i32_nxv4i32_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vadd.vi v8, v8, -9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i32> @llvm.riscv.vsub.nxv4i32.i32(
- <vscale x 4 x i32> undef,
- <vscale x 4 x i32> %0,
- i32 9,
- i64 %1)
-
- ret <vscale x 4 x i32> %a
-}
-
-define <vscale x 4 x i32> @intrinsic_vsub_mask_vi_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vsub_mask_vi_nxv4i32_nxv4i32_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
-; CHECK-NEXT: vadd.vi v8, v10, -9, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i32> @llvm.riscv.vsub.mask.nxv4i32.i32(
- <vscale x 4 x i32> %0,
- <vscale x 4 x i32> %1,
- i32 9,
- <vscale x 4 x i1> %2,
- i64 %3, i64 1)
-
- ret <vscale x 4 x i32> %a
-}
-
-define <vscale x 8 x i32> @intrinsic_vsub_vi_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, i64 %1) nounwind {
-; CHECK-LABEL: intrinsic_vsub_vi_nxv8i32_nxv8i32_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
-; CHECK-NEXT: vadd.vi v8, v8, -9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i32> @llvm.riscv.vsub.nxv8i32.i32(
- <vscale x 8 x i32> undef,
- <vscale x 8 x i32> %0,
- i32 9,
- i64 %1)
-
- ret <vscale x 8 x i32> %a
-}
-
-define <vscale x 8 x i32> @intrinsic_vsub_mask_vi_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vsub_mask_vi_nxv8i32_nxv8i32_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
-; CHECK-NEXT: vadd.vi v8, v12, -9, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i32> @llvm.riscv.vsub.mask.nxv8i32.i32(
- <vscale x 8 x i32> %0,
- <vscale x 8 x i32> %1,
- i32 9,
- <vscale x 8 x i1> %2,
- i64 %3, i64 1)
-
- ret <vscale x 8 x i32> %a
-}
-
-define <vscale x 16 x i32> @intrinsic_vsub_vi_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, i64 %1) nounwind {
-; CHECK-LABEL: intrinsic_vsub_vi_nxv16i32_nxv16i32_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu
-; CHECK-NEXT: vadd.vi v8, v8, -9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i32> @llvm.riscv.vsub.nxv16i32.i32(
- <vscale x 16 x i32> undef,
- <vscale x 16 x i32> %0,
- i32 9,
- i64 %1)
-
- ret <vscale x 16 x i32> %a
-}
-
-define <vscale x 16 x i32> @intrinsic_vsub_mask_vi_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i1> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vsub_mask_vi_nxv16i32_nxv16i32_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu
-; CHECK-NEXT: vadd.vi v8, v16, -9, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i32> @llvm.riscv.vsub.mask.nxv16i32.i32(
- <vscale x 16 x i32> %0,
- <vscale x 16 x i32> %1,
- i32 9,
- <vscale x 16 x i1> %2,
- i64 %3, i64 1)
-
- ret <vscale x 16 x i32> %a
-}
-
-define <vscale x 1 x i64> @intrinsic_vsub_vi_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1) nounwind {
-; CHECK-LABEL: intrinsic_vsub_vi_nxv1i64_nxv1i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
-; CHECK-NEXT: vadd.vi v8, v8, -9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i64> @llvm.riscv.vsub.nxv1i64.i64(
- <vscale x 1 x i64> undef,
- <vscale x 1 x i64> %0,
- i64 9,
- i64 %1)
-
- ret <vscale x 1 x i64> %a
-}
-
-define <vscale x 1 x i64> @intrinsic_vsub_mask_vi_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vsub_mask_vi_nxv1i64_nxv1i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
-; CHECK-NEXT: vadd.vi v8, v9, -9, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i64> @llvm.riscv.vsub.mask.nxv1i64.i64(
- <vscale x 1 x i64> %0,
- <vscale x 1 x i64> %1,
- i64 9,
- <vscale x 1 x i1> %2,
- i64 %3, i64 1)
-
- ret <vscale x 1 x i64> %a
-}
-
-define <vscale x 2 x i64> @intrinsic_vsub_vi_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1) nounwind {
-; CHECK-LABEL: intrinsic_vsub_vi_nxv2i64_nxv2i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
-; CHECK-NEXT: vadd.vi v8, v8, -9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i64> @llvm.riscv.vsub.nxv2i64.i64(
- <vscale x 2 x i64> undef,
- <vscale x 2 x i64> %0,
- i64 9,
- i64 %1)
-
- ret <vscale x 2 x i64> %a
-}
-
-define <vscale x 2 x i64> @intrinsic_vsub_mask_vi_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vsub_mask_vi_nxv2i64_nxv2i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
-; CHECK-NEXT: vadd.vi v8, v10, -9, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i64> @llvm.riscv.vsub.mask.nxv2i64.i64(
- <vscale x 2 x i64> %0,
- <vscale x 2 x i64> %1,
- i64 9,
- <vscale x 2 x i1> %2,
- i64 %3, i64 1)
-
- ret <vscale x 2 x i64> %a
-}
-
-define <vscale x 4 x i64> @intrinsic_vsub_vi_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1) nounwind {
-; CHECK-LABEL: intrinsic_vsub_vi_nxv4i64_nxv4i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
-; CHECK-NEXT: vadd.vi v8, v8, -9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i64> @llvm.riscv.vsub.nxv4i64.i64(
- <vscale x 4 x i64> undef,
- <vscale x 4 x i64> %0,
- i64 9,
- i64 %1)
-
- ret <vscale x 4 x i64> %a
-}
-
-define <vscale x 4 x i64> @intrinsic_vsub_mask_vi_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vsub_mask_vi_nxv4i64_nxv4i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
-; CHECK-NEXT: vadd.vi v8, v12, -9, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i64> @llvm.riscv.vsub.mask.nxv4i64.i64(
- <vscale x 4 x i64> %0,
- <vscale x 4 x i64> %1,
- i64 9,
- <vscale x 4 x i1> %2,
- i64 %3, i64 1)
-
- ret <vscale x 4 x i64> %a
-}
-
-define <vscale x 8 x i64> @intrinsic_vsub_vi_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, i64 %1) nounwind {
-; CHECK-LABEL: intrinsic_vsub_vi_nxv8i64_nxv8i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu
-; CHECK-NEXT: vadd.vi v8, v8, -9
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i64> @llvm.riscv.vsub.nxv8i64.i64(
- <vscale x 8 x i64> undef,
- <vscale x 8 x i64> %0,
- i64 9,
- i64 %1)
-
- ret <vscale x 8 x i64> %a
-}
-
-define <vscale x 8 x i64> @intrinsic_vsub_mask_vi_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
-; CHECK-LABEL: intrinsic_vsub_mask_vi_nxv8i64_nxv8i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu
-; CHECK-NEXT: vadd.vi v8, v16, -9, v0.t
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i64> @llvm.riscv.vsub.mask.nxv8i64.i64(
- <vscale x 8 x i64> %0,
- <vscale x 8 x i64> %1,
- i64 9,
- <vscale x 8 x i1> %2,
- i64 %3, i64 1)
-
- ret <vscale x 8 x i64> %a
-}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vsub-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vsub.ll
similarity index 83%
rename from llvm/test/CodeGen/RISCV/rvv/vsub-rv32.ll
rename to llvm/test/CodeGen/RISCV/rvv/vsub.ll
index 4f0bff3562ace..6b9c5419e7f7d 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vsub-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vsub.ll
@@ -1,13 +1,15 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs \
-; RUN: < %s | FileCheck %s
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v \
+; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,RV32
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v \
+; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,RV64
declare <vscale x 1 x i8> @llvm.riscv.vsub.nxv1i8.nxv1i8(
<vscale x 1 x i8>,
<vscale x 1 x i8>,
<vscale x 1 x i8>,
- i32);
+ iXLen);
-define <vscale x 1 x i8> @intrinsic_vsub_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i32 %2) nounwind {
+define <vscale x 1 x i8> @intrinsic_vsub_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vsub_vv_nxv1i8_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
@@ -18,7 +20,7 @@ entry:
<vscale x 1 x i8> undef,
<vscale x 1 x i8> %0,
<vscale x 1 x i8> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 1 x i8> %a
}
@@ -28,10 +30,9 @@ declare <vscale x 1 x i8> @llvm.riscv.vsub.mask.nxv1i8.nxv1i8(
<vscale x 1 x i8>,
<vscale x 1 x i8>,
<vscale x 1 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 1 x i8> @intrinsic_vsub_mask_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+define <vscale x 1 x i8> @intrinsic_vsub_mask_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv1i8_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
@@ -43,7 +44,7 @@ entry:
<vscale x 1 x i8> %1,
<vscale x 1 x i8> %2,
<vscale x 1 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 1 x i8> %a
}
@@ -52,9 +53,9 @@ declare <vscale x 2 x i8> @llvm.riscv.vsub.nxv2i8.nxv2i8(
<vscale x 2 x i8>,
<vscale x 2 x i8>,
<vscale x 2 x i8>,
- i32);
+ iXLen);
-define <vscale x 2 x i8> @intrinsic_vsub_vv_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i32 %2) nounwind {
+define <vscale x 2 x i8> @intrinsic_vsub_vv_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vsub_vv_nxv2i8_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
@@ -65,7 +66,7 @@ entry:
<vscale x 2 x i8> undef,
<vscale x 2 x i8> %0,
<vscale x 2 x i8> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 2 x i8> %a
}
@@ -75,10 +76,9 @@ declare <vscale x 2 x i8> @llvm.riscv.vsub.mask.nxv2i8.nxv2i8(
<vscale x 2 x i8>,
<vscale x 2 x i8>,
<vscale x 2 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 2 x i8> @intrinsic_vsub_mask_vv_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+define <vscale x 2 x i8> @intrinsic_vsub_mask_vv_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv2i8_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
@@ -90,7 +90,7 @@ entry:
<vscale x 2 x i8> %1,
<vscale x 2 x i8> %2,
<vscale x 2 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 2 x i8> %a
}
@@ -99,9 +99,9 @@ declare <vscale x 4 x i8> @llvm.riscv.vsub.nxv4i8.nxv4i8(
<vscale x 4 x i8>,
<vscale x 4 x i8>,
<vscale x 4 x i8>,
- i32);
+ iXLen);
-define <vscale x 4 x i8> @intrinsic_vsub_vv_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i32 %2) nounwind {
+define <vscale x 4 x i8> @intrinsic_vsub_vv_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vsub_vv_nxv4i8_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
@@ -112,7 +112,7 @@ entry:
<vscale x 4 x i8> undef,
<vscale x 4 x i8> %0,
<vscale x 4 x i8> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 4 x i8> %a
}
@@ -122,10 +122,9 @@ declare <vscale x 4 x i8> @llvm.riscv.vsub.mask.nxv4i8.nxv4i8(
<vscale x 4 x i8>,
<vscale x 4 x i8>,
<vscale x 4 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 4 x i8> @intrinsic_vsub_mask_vv_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+define <vscale x 4 x i8> @intrinsic_vsub_mask_vv_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv4i8_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
@@ -137,7 +136,7 @@ entry:
<vscale x 4 x i8> %1,
<vscale x 4 x i8> %2,
<vscale x 4 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 4 x i8> %a
}
@@ -146,9 +145,9 @@ declare <vscale x 8 x i8> @llvm.riscv.vsub.nxv8i8.nxv8i8(
<vscale x 8 x i8>,
<vscale x 8 x i8>,
<vscale x 8 x i8>,
- i32);
+ iXLen);
-define <vscale x 8 x i8> @intrinsic_vsub_vv_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i32 %2) nounwind {
+define <vscale x 8 x i8> @intrinsic_vsub_vv_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vsub_vv_nxv8i8_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
@@ -159,7 +158,7 @@ entry:
<vscale x 8 x i8> undef,
<vscale x 8 x i8> %0,
<vscale x 8 x i8> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 8 x i8> %a
}
@@ -169,10 +168,9 @@ declare <vscale x 8 x i8> @llvm.riscv.vsub.mask.nxv8i8.nxv8i8(
<vscale x 8 x i8>,
<vscale x 8 x i8>,
<vscale x 8 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 8 x i8> @intrinsic_vsub_mask_vv_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+define <vscale x 8 x i8> @intrinsic_vsub_mask_vv_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv8i8_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
@@ -184,7 +182,7 @@ entry:
<vscale x 8 x i8> %1,
<vscale x 8 x i8> %2,
<vscale x 8 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 8 x i8> %a
}
@@ -193,9 +191,9 @@ declare <vscale x 16 x i8> @llvm.riscv.vsub.nxv16i8.nxv16i8(
<vscale x 16 x i8>,
<vscale x 16 x i8>,
<vscale x 16 x i8>,
- i32);
+ iXLen);
-define <vscale x 16 x i8> @intrinsic_vsub_vv_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i32 %2) nounwind {
+define <vscale x 16 x i8> @intrinsic_vsub_vv_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vsub_vv_nxv16i8_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
@@ -206,7 +204,7 @@ entry:
<vscale x 16 x i8> undef,
<vscale x 16 x i8> %0,
<vscale x 16 x i8> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 16 x i8> %a
}
@@ -216,10 +214,9 @@ declare <vscale x 16 x i8> @llvm.riscv.vsub.mask.nxv16i8.nxv16i8(
<vscale x 16 x i8>,
<vscale x 16 x i8>,
<vscale x 16 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 16 x i8> @intrinsic_vsub_mask_vv_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+define <vscale x 16 x i8> @intrinsic_vsub_mask_vv_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv16i8_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
@@ -231,7 +228,7 @@ entry:
<vscale x 16 x i8> %1,
<vscale x 16 x i8> %2,
<vscale x 16 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 16 x i8> %a
}
@@ -240,9 +237,9 @@ declare <vscale x 32 x i8> @llvm.riscv.vsub.nxv32i8.nxv32i8(
<vscale x 32 x i8>,
<vscale x 32 x i8>,
<vscale x 32 x i8>,
- i32);
+ iXLen);
-define <vscale x 32 x i8> @intrinsic_vsub_vv_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i32 %2) nounwind {
+define <vscale x 32 x i8> @intrinsic_vsub_vv_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vsub_vv_nxv32i8_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
@@ -253,7 +250,7 @@ entry:
<vscale x 32 x i8> undef,
<vscale x 32 x i8> %0,
<vscale x 32 x i8> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 32 x i8> %a
}
@@ -263,10 +260,9 @@ declare <vscale x 32 x i8> @llvm.riscv.vsub.mask.nxv32i8.nxv32i8(
<vscale x 32 x i8>,
<vscale x 32 x i8>,
<vscale x 32 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 32 x i8> @intrinsic_vsub_mask_vv_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
+define <vscale x 32 x i8> @intrinsic_vsub_mask_vv_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv32i8_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
@@ -278,7 +274,7 @@ entry:
<vscale x 32 x i8> %1,
<vscale x 32 x i8> %2,
<vscale x 32 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 32 x i8> %a
}
@@ -287,9 +283,9 @@ declare <vscale x 64 x i8> @llvm.riscv.vsub.nxv64i8.nxv64i8(
<vscale x 64 x i8>,
<vscale x 64 x i8>,
<vscale x 64 x i8>,
- i32);
+ iXLen);
-define <vscale x 64 x i8> @intrinsic_vsub_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i32 %2) nounwind {
+define <vscale x 64 x i8> @intrinsic_vsub_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vsub_vv_nxv64i8_nxv64i8_nxv64i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, mu
@@ -300,7 +296,7 @@ entry:
<vscale x 64 x i8> undef,
<vscale x 64 x i8> %0,
<vscale x 64 x i8> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 64 x i8> %a
}
@@ -310,10 +306,9 @@ declare <vscale x 64 x i8> @llvm.riscv.vsub.mask.nxv64i8.nxv64i8(
<vscale x 64 x i8>,
<vscale x 64 x i8>,
<vscale x 64 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 64 x i8> @intrinsic_vsub_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, i32 %4) nounwind {
+define <vscale x 64 x i8> @intrinsic_vsub_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv64i8_nxv64i8_nxv64i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vl8r.v v24, (a0)
@@ -326,7 +321,7 @@ entry:
<vscale x 64 x i8> %1,
<vscale x 64 x i8> %2,
<vscale x 64 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 64 x i8> %a
}
@@ -335,9 +330,9 @@ declare <vscale x 1 x i16> @llvm.riscv.vsub.nxv1i16.nxv1i16(
<vscale x 1 x i16>,
<vscale x 1 x i16>,
<vscale x 1 x i16>,
- i32);
+ iXLen);
-define <vscale x 1 x i16> @intrinsic_vsub_vv_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i32 %2) nounwind {
+define <vscale x 1 x i16> @intrinsic_vsub_vv_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vsub_vv_nxv1i16_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
@@ -348,7 +343,7 @@ entry:
<vscale x 1 x i16> undef,
<vscale x 1 x i16> %0,
<vscale x 1 x i16> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 1 x i16> %a
}
@@ -358,10 +353,9 @@ declare <vscale x 1 x i16> @llvm.riscv.vsub.mask.nxv1i16.nxv1i16(
<vscale x 1 x i16>,
<vscale x 1 x i16>,
<vscale x 1 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 1 x i16> @intrinsic_vsub_mask_vv_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+define <vscale x 1 x i16> @intrinsic_vsub_mask_vv_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv1i16_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
@@ -373,7 +367,7 @@ entry:
<vscale x 1 x i16> %1,
<vscale x 1 x i16> %2,
<vscale x 1 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 1 x i16> %a
}
@@ -382,9 +376,9 @@ declare <vscale x 2 x i16> @llvm.riscv.vsub.nxv2i16.nxv2i16(
<vscale x 2 x i16>,
<vscale x 2 x i16>,
<vscale x 2 x i16>,
- i32);
+ iXLen);
-define <vscale x 2 x i16> @intrinsic_vsub_vv_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i32 %2) nounwind {
+define <vscale x 2 x i16> @intrinsic_vsub_vv_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vsub_vv_nxv2i16_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
@@ -395,7 +389,7 @@ entry:
<vscale x 2 x i16> undef,
<vscale x 2 x i16> %0,
<vscale x 2 x i16> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 2 x i16> %a
}
@@ -405,10 +399,9 @@ declare <vscale x 2 x i16> @llvm.riscv.vsub.mask.nxv2i16.nxv2i16(
<vscale x 2 x i16>,
<vscale x 2 x i16>,
<vscale x 2 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 2 x i16> @intrinsic_vsub_mask_vv_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+define <vscale x 2 x i16> @intrinsic_vsub_mask_vv_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv2i16_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
@@ -420,7 +413,7 @@ entry:
<vscale x 2 x i16> %1,
<vscale x 2 x i16> %2,
<vscale x 2 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 2 x i16> %a
}
@@ -429,9 +422,9 @@ declare <vscale x 4 x i16> @llvm.riscv.vsub.nxv4i16.nxv4i16(
<vscale x 4 x i16>,
<vscale x 4 x i16>,
<vscale x 4 x i16>,
- i32);
+ iXLen);
-define <vscale x 4 x i16> @intrinsic_vsub_vv_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i32 %2) nounwind {
+define <vscale x 4 x i16> @intrinsic_vsub_vv_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vsub_vv_nxv4i16_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
@@ -442,7 +435,7 @@ entry:
<vscale x 4 x i16> undef,
<vscale x 4 x i16> %0,
<vscale x 4 x i16> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 4 x i16> %a
}
@@ -452,10 +445,9 @@ declare <vscale x 4 x i16> @llvm.riscv.vsub.mask.nxv4i16.nxv4i16(
<vscale x 4 x i16>,
<vscale x 4 x i16>,
<vscale x 4 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 4 x i16> @intrinsic_vsub_mask_vv_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+define <vscale x 4 x i16> @intrinsic_vsub_mask_vv_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv4i16_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
@@ -467,7 +459,7 @@ entry:
<vscale x 4 x i16> %1,
<vscale x 4 x i16> %2,
<vscale x 4 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 4 x i16> %a
}
@@ -476,9 +468,9 @@ declare <vscale x 8 x i16> @llvm.riscv.vsub.nxv8i16.nxv8i16(
<vscale x 8 x i16>,
<vscale x 8 x i16>,
<vscale x 8 x i16>,
- i32);
+ iXLen);
-define <vscale x 8 x i16> @intrinsic_vsub_vv_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i32 %2) nounwind {
+define <vscale x 8 x i16> @intrinsic_vsub_vv_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vsub_vv_nxv8i16_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
@@ -489,7 +481,7 @@ entry:
<vscale x 8 x i16> undef,
<vscale x 8 x i16> %0,
<vscale x 8 x i16> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 8 x i16> %a
}
@@ -499,10 +491,9 @@ declare <vscale x 8 x i16> @llvm.riscv.vsub.mask.nxv8i16.nxv8i16(
<vscale x 8 x i16>,
<vscale x 8 x i16>,
<vscale x 8 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 8 x i16> @intrinsic_vsub_mask_vv_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+define <vscale x 8 x i16> @intrinsic_vsub_mask_vv_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv8i16_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
@@ -514,7 +505,7 @@ entry:
<vscale x 8 x i16> %1,
<vscale x 8 x i16> %2,
<vscale x 8 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 8 x i16> %a
}
@@ -523,9 +514,9 @@ declare <vscale x 16 x i16> @llvm.riscv.vsub.nxv16i16.nxv16i16(
<vscale x 16 x i16>,
<vscale x 16 x i16>,
<vscale x 16 x i16>,
- i32);
+ iXLen);
-define <vscale x 16 x i16> @intrinsic_vsub_vv_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i32 %2) nounwind {
+define <vscale x 16 x i16> @intrinsic_vsub_vv_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vsub_vv_nxv16i16_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
@@ -536,7 +527,7 @@ entry:
<vscale x 16 x i16> undef,
<vscale x 16 x i16> %0,
<vscale x 16 x i16> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 16 x i16> %a
}
@@ -546,10 +537,9 @@ declare <vscale x 16 x i16> @llvm.riscv.vsub.mask.nxv16i16.nxv16i16(
<vscale x 16 x i16>,
<vscale x 16 x i16>,
<vscale x 16 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 16 x i16> @intrinsic_vsub_mask_vv_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+define <vscale x 16 x i16> @intrinsic_vsub_mask_vv_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv16i16_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
@@ -561,7 +551,7 @@ entry:
<vscale x 16 x i16> %1,
<vscale x 16 x i16> %2,
<vscale x 16 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 16 x i16> %a
}
@@ -570,9 +560,9 @@ declare <vscale x 32 x i16> @llvm.riscv.vsub.nxv32i16.nxv32i16(
<vscale x 32 x i16>,
<vscale x 32 x i16>,
<vscale x 32 x i16>,
- i32);
+ iXLen);
-define <vscale x 32 x i16> @intrinsic_vsub_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, i32 %2) nounwind {
+define <vscale x 32 x i16> @intrinsic_vsub_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vsub_vv_nxv32i16_nxv32i16_nxv32i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, mu
@@ -583,7 +573,7 @@ entry:
<vscale x 32 x i16> undef,
<vscale x 32 x i16> %0,
<vscale x 32 x i16> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 32 x i16> %a
}
@@ -593,10 +583,9 @@ declare <vscale x 32 x i16> @llvm.riscv.vsub.mask.nxv32i16.nxv32i16(
<vscale x 32 x i16>,
<vscale x 32 x i16>,
<vscale x 32 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 32 x i16> @intrinsic_vsub_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
+define <vscale x 32 x i16> @intrinsic_vsub_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv32i16_nxv32i16_nxv32i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vl8re16.v v24, (a0)
@@ -609,7 +598,7 @@ entry:
<vscale x 32 x i16> %1,
<vscale x 32 x i16> %2,
<vscale x 32 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 32 x i16> %a
}
@@ -618,9 +607,9 @@ declare <vscale x 1 x i32> @llvm.riscv.vsub.nxv1i32.nxv1i32(
<vscale x 1 x i32>,
<vscale x 1 x i32>,
<vscale x 1 x i32>,
- i32);
+ iXLen);
-define <vscale x 1 x i32> @intrinsic_vsub_vv_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2) nounwind {
+define <vscale x 1 x i32> @intrinsic_vsub_vv_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vsub_vv_nxv1i32_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
@@ -631,7 +620,7 @@ entry:
<vscale x 1 x i32> undef,
<vscale x 1 x i32> %0,
<vscale x 1 x i32> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 1 x i32> %a
}
@@ -641,10 +630,9 @@ declare <vscale x 1 x i32> @llvm.riscv.vsub.mask.nxv1i32.nxv1i32(
<vscale x 1 x i32>,
<vscale x 1 x i32>,
<vscale x 1 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 1 x i32> @intrinsic_vsub_mask_vv_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+define <vscale x 1 x i32> @intrinsic_vsub_mask_vv_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv1i32_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
@@ -656,7 +644,7 @@ entry:
<vscale x 1 x i32> %1,
<vscale x 1 x i32> %2,
<vscale x 1 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 1 x i32> %a
}
@@ -665,9 +653,9 @@ declare <vscale x 2 x i32> @llvm.riscv.vsub.nxv2i32.nxv2i32(
<vscale x 2 x i32>,
<vscale x 2 x i32>,
<vscale x 2 x i32>,
- i32);
+ iXLen);
-define <vscale x 2 x i32> @intrinsic_vsub_vv_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2) nounwind {
+define <vscale x 2 x i32> @intrinsic_vsub_vv_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vsub_vv_nxv2i32_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
@@ -678,7 +666,7 @@ entry:
<vscale x 2 x i32> undef,
<vscale x 2 x i32> %0,
<vscale x 2 x i32> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 2 x i32> %a
}
@@ -688,10 +676,9 @@ declare <vscale x 2 x i32> @llvm.riscv.vsub.mask.nxv2i32.nxv2i32(
<vscale x 2 x i32>,
<vscale x 2 x i32>,
<vscale x 2 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 2 x i32> @intrinsic_vsub_mask_vv_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+define <vscale x 2 x i32> @intrinsic_vsub_mask_vv_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv2i32_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
@@ -703,7 +690,7 @@ entry:
<vscale x 2 x i32> %1,
<vscale x 2 x i32> %2,
<vscale x 2 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 2 x i32> %a
}
@@ -712,9 +699,9 @@ declare <vscale x 4 x i32> @llvm.riscv.vsub.nxv4i32.nxv4i32(
<vscale x 4 x i32>,
<vscale x 4 x i32>,
<vscale x 4 x i32>,
- i32);
+ iXLen);
-define <vscale x 4 x i32> @intrinsic_vsub_vv_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2) nounwind {
+define <vscale x 4 x i32> @intrinsic_vsub_vv_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vsub_vv_nxv4i32_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
@@ -725,7 +712,7 @@ entry:
<vscale x 4 x i32> undef,
<vscale x 4 x i32> %0,
<vscale x 4 x i32> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 4 x i32> %a
}
@@ -735,10 +722,9 @@ declare <vscale x 4 x i32> @llvm.riscv.vsub.mask.nxv4i32.nxv4i32(
<vscale x 4 x i32>,
<vscale x 4 x i32>,
<vscale x 4 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 4 x i32> @intrinsic_vsub_mask_vv_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+define <vscale x 4 x i32> @intrinsic_vsub_mask_vv_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv4i32_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
@@ -750,7 +736,7 @@ entry:
<vscale x 4 x i32> %1,
<vscale x 4 x i32> %2,
<vscale x 4 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 4 x i32> %a
}
@@ -759,9 +745,9 @@ declare <vscale x 8 x i32> @llvm.riscv.vsub.nxv8i32.nxv8i32(
<vscale x 8 x i32>,
<vscale x 8 x i32>,
<vscale x 8 x i32>,
- i32);
+ iXLen);
-define <vscale x 8 x i32> @intrinsic_vsub_vv_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2) nounwind {
+define <vscale x 8 x i32> @intrinsic_vsub_vv_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vsub_vv_nxv8i32_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
@@ -772,7 +758,7 @@ entry:
<vscale x 8 x i32> undef,
<vscale x 8 x i32> %0,
<vscale x 8 x i32> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 8 x i32> %a
}
@@ -782,10 +768,9 @@ declare <vscale x 8 x i32> @llvm.riscv.vsub.mask.nxv8i32.nxv8i32(
<vscale x 8 x i32>,
<vscale x 8 x i32>,
<vscale x 8 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 8 x i32> @intrinsic_vsub_mask_vv_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+define <vscale x 8 x i32> @intrinsic_vsub_mask_vv_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv8i32_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
@@ -797,7 +782,7 @@ entry:
<vscale x 8 x i32> %1,
<vscale x 8 x i32> %2,
<vscale x 8 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 8 x i32> %a
}
@@ -806,9 +791,9 @@ declare <vscale x 16 x i32> @llvm.riscv.vsub.nxv16i32.nxv16i32(
<vscale x 16 x i32>,
<vscale x 16 x i32>,
<vscale x 16 x i32>,
- i32);
+ iXLen);
-define <vscale x 16 x i32> @intrinsic_vsub_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2) nounwind {
+define <vscale x 16 x i32> @intrinsic_vsub_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vsub_vv_nxv16i32_nxv16i32_nxv16i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu
@@ -819,7 +804,7 @@ entry:
<vscale x 16 x i32> undef,
<vscale x 16 x i32> %0,
<vscale x 16 x i32> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 16 x i32> %a
}
@@ -829,10 +814,9 @@ declare <vscale x 16 x i32> @llvm.riscv.vsub.mask.nxv16i32.nxv16i32(
<vscale x 16 x i32>,
<vscale x 16 x i32>,
<vscale x 16 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 16 x i32> @intrinsic_vsub_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+define <vscale x 16 x i32> @intrinsic_vsub_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv16i32_nxv16i32_nxv16i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vl8re32.v v24, (a0)
@@ -845,7 +829,7 @@ entry:
<vscale x 16 x i32> %1,
<vscale x 16 x i32> %2,
<vscale x 16 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 16 x i32> %a
}
@@ -854,9 +838,9 @@ declare <vscale x 1 x i64> @llvm.riscv.vsub.nxv1i64.nxv1i64(
<vscale x 1 x i64>,
<vscale x 1 x i64>,
<vscale x 1 x i64>,
- i32);
+ iXLen);
-define <vscale x 1 x i64> @intrinsic_vsub_vv_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i32 %2) nounwind {
+define <vscale x 1 x i64> @intrinsic_vsub_vv_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vsub_vv_nxv1i64_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
@@ -867,7 +851,7 @@ entry:
<vscale x 1 x i64> undef,
<vscale x 1 x i64> %0,
<vscale x 1 x i64> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 1 x i64> %a
}
@@ -877,10 +861,9 @@ declare <vscale x 1 x i64> @llvm.riscv.vsub.mask.nxv1i64.nxv1i64(
<vscale x 1 x i64>,
<vscale x 1 x i64>,
<vscale x 1 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 1 x i64> @intrinsic_vsub_mask_vv_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+define <vscale x 1 x i64> @intrinsic_vsub_mask_vv_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv1i64_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
@@ -892,7 +875,7 @@ entry:
<vscale x 1 x i64> %1,
<vscale x 1 x i64> %2,
<vscale x 1 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 1 x i64> %a
}
@@ -901,9 +884,9 @@ declare <vscale x 2 x i64> @llvm.riscv.vsub.nxv2i64.nxv2i64(
<vscale x 2 x i64>,
<vscale x 2 x i64>,
<vscale x 2 x i64>,
- i32);
+ iXLen);
-define <vscale x 2 x i64> @intrinsic_vsub_vv_nxv2i64_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i32 %2) nounwind {
+define <vscale x 2 x i64> @intrinsic_vsub_vv_nxv2i64_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vsub_vv_nxv2i64_nxv2i64_nxv2i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
@@ -914,7 +897,7 @@ entry:
<vscale x 2 x i64> undef,
<vscale x 2 x i64> %0,
<vscale x 2 x i64> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 2 x i64> %a
}
@@ -924,10 +907,9 @@ declare <vscale x 2 x i64> @llvm.riscv.vsub.mask.nxv2i64.nxv2i64(
<vscale x 2 x i64>,
<vscale x 2 x i64>,
<vscale x 2 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 2 x i64> @intrinsic_vsub_mask_vv_nxv2i64_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+define <vscale x 2 x i64> @intrinsic_vsub_mask_vv_nxv2i64_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv2i64_nxv2i64_nxv2i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
@@ -939,7 +921,7 @@ entry:
<vscale x 2 x i64> %1,
<vscale x 2 x i64> %2,
<vscale x 2 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 2 x i64> %a
}
@@ -948,9 +930,9 @@ declare <vscale x 4 x i64> @llvm.riscv.vsub.nxv4i64.nxv4i64(
<vscale x 4 x i64>,
<vscale x 4 x i64>,
<vscale x 4 x i64>,
- i32);
+ iXLen);
-define <vscale x 4 x i64> @intrinsic_vsub_vv_nxv4i64_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i32 %2) nounwind {
+define <vscale x 4 x i64> @intrinsic_vsub_vv_nxv4i64_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vsub_vv_nxv4i64_nxv4i64_nxv4i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
@@ -961,7 +943,7 @@ entry:
<vscale x 4 x i64> undef,
<vscale x 4 x i64> %0,
<vscale x 4 x i64> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 4 x i64> %a
}
@@ -971,10 +953,9 @@ declare <vscale x 4 x i64> @llvm.riscv.vsub.mask.nxv4i64.nxv4i64(
<vscale x 4 x i64>,
<vscale x 4 x i64>,
<vscale x 4 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 4 x i64> @intrinsic_vsub_mask_vv_nxv4i64_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+define <vscale x 4 x i64> @intrinsic_vsub_mask_vv_nxv4i64_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv4i64_nxv4i64_nxv4i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
@@ -986,7 +967,7 @@ entry:
<vscale x 4 x i64> %1,
<vscale x 4 x i64> %2,
<vscale x 4 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 4 x i64> %a
}
@@ -995,9 +976,9 @@ declare <vscale x 8 x i64> @llvm.riscv.vsub.nxv8i64.nxv8i64(
<vscale x 8 x i64>,
<vscale x 8 x i64>,
<vscale x 8 x i64>,
- i32);
+ iXLen);
-define <vscale x 8 x i64> @intrinsic_vsub_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i32 %2) nounwind {
+define <vscale x 8 x i64> @intrinsic_vsub_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vsub_vv_nxv8i64_nxv8i64_nxv8i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu
@@ -1008,7 +989,7 @@ entry:
<vscale x 8 x i64> undef,
<vscale x 8 x i64> %0,
<vscale x 8 x i64> %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 8 x i64> %a
}
@@ -1018,10 +999,9 @@ declare <vscale x 8 x i64> @llvm.riscv.vsub.mask.nxv8i64.nxv8i64(
<vscale x 8 x i64>,
<vscale x 8 x i64>,
<vscale x 8 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 8 x i64> @intrinsic_vsub_mask_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+define <vscale x 8 x i64> @intrinsic_vsub_mask_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv8i64_nxv8i64_nxv8i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vl8re64.v v24, (a0)
@@ -1034,7 +1014,7 @@ entry:
<vscale x 8 x i64> %1,
<vscale x 8 x i64> %2,
<vscale x 8 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 8 x i64> %a
}
@@ -1043,9 +1023,9 @@ declare <vscale x 1 x i8> @llvm.riscv.vsub.nxv1i8.i8(
<vscale x 1 x i8>,
<vscale x 1 x i8>,
i8,
- i32);
+ iXLen);
-define <vscale x 1 x i8> @intrinsic_vsub_vx_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, i8 %1, i32 %2) nounwind {
+define <vscale x 1 x i8> @intrinsic_vsub_vx_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, i8 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vsub_vx_nxv1i8_nxv1i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
@@ -1056,7 +1036,7 @@ entry:
<vscale x 1 x i8> undef,
<vscale x 1 x i8> %0,
i8 %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 1 x i8> %a
}
@@ -1066,10 +1046,9 @@ declare <vscale x 1 x i8> @llvm.riscv.vsub.mask.nxv1i8.i8(
<vscale x 1 x i8>,
i8,
<vscale x 1 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 1 x i8> @intrinsic_vsub_mask_vx_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+define <vscale x 1 x i8> @intrinsic_vsub_mask_vx_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vsub_mask_vx_nxv1i8_nxv1i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
@@ -1081,7 +1060,7 @@ entry:
<vscale x 1 x i8> %1,
i8 %2,
<vscale x 1 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 1 x i8> %a
}
@@ -1090,9 +1069,9 @@ declare <vscale x 2 x i8> @llvm.riscv.vsub.nxv2i8.i8(
<vscale x 2 x i8>,
<vscale x 2 x i8>,
i8,
- i32);
+ iXLen);
-define <vscale x 2 x i8> @intrinsic_vsub_vx_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, i8 %1, i32 %2) nounwind {
+define <vscale x 2 x i8> @intrinsic_vsub_vx_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, i8 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vsub_vx_nxv2i8_nxv2i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
@@ -1103,7 +1082,7 @@ entry:
<vscale x 2 x i8> undef,
<vscale x 2 x i8> %0,
i8 %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 2 x i8> %a
}
@@ -1113,10 +1092,9 @@ declare <vscale x 2 x i8> @llvm.riscv.vsub.mask.nxv2i8.i8(
<vscale x 2 x i8>,
i8,
<vscale x 2 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 2 x i8> @intrinsic_vsub_mask_vx_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+define <vscale x 2 x i8> @intrinsic_vsub_mask_vx_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vsub_mask_vx_nxv2i8_nxv2i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
@@ -1128,7 +1106,7 @@ entry:
<vscale x 2 x i8> %1,
i8 %2,
<vscale x 2 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 2 x i8> %a
}
@@ -1137,9 +1115,9 @@ declare <vscale x 4 x i8> @llvm.riscv.vsub.nxv4i8.i8(
<vscale x 4 x i8>,
<vscale x 4 x i8>,
i8,
- i32);
+ iXLen);
-define <vscale x 4 x i8> @intrinsic_vsub_vx_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, i8 %1, i32 %2) nounwind {
+define <vscale x 4 x i8> @intrinsic_vsub_vx_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, i8 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vsub_vx_nxv4i8_nxv4i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
@@ -1150,7 +1128,7 @@ entry:
<vscale x 4 x i8> undef,
<vscale x 4 x i8> %0,
i8 %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 4 x i8> %a
}
@@ -1160,10 +1138,9 @@ declare <vscale x 4 x i8> @llvm.riscv.vsub.mask.nxv4i8.i8(
<vscale x 4 x i8>,
i8,
<vscale x 4 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 4 x i8> @intrinsic_vsub_mask_vx_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+define <vscale x 4 x i8> @intrinsic_vsub_mask_vx_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vsub_mask_vx_nxv4i8_nxv4i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
@@ -1175,7 +1152,7 @@ entry:
<vscale x 4 x i8> %1,
i8 %2,
<vscale x 4 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 4 x i8> %a
}
@@ -1184,9 +1161,9 @@ declare <vscale x 8 x i8> @llvm.riscv.vsub.nxv8i8.i8(
<vscale x 8 x i8>,
<vscale x 8 x i8>,
i8,
- i32);
+ iXLen);
-define <vscale x 8 x i8> @intrinsic_vsub_vx_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, i8 %1, i32 %2) nounwind {
+define <vscale x 8 x i8> @intrinsic_vsub_vx_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, i8 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vsub_vx_nxv8i8_nxv8i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
@@ -1197,7 +1174,7 @@ entry:
<vscale x 8 x i8> undef,
<vscale x 8 x i8> %0,
i8 %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 8 x i8> %a
}
@@ -1207,10 +1184,9 @@ declare <vscale x 8 x i8> @llvm.riscv.vsub.mask.nxv8i8.i8(
<vscale x 8 x i8>,
i8,
<vscale x 8 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 8 x i8> @intrinsic_vsub_mask_vx_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+define <vscale x 8 x i8> @intrinsic_vsub_mask_vx_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vsub_mask_vx_nxv8i8_nxv8i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
@@ -1222,7 +1198,7 @@ entry:
<vscale x 8 x i8> %1,
i8 %2,
<vscale x 8 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 8 x i8> %a
}
@@ -1231,9 +1207,9 @@ declare <vscale x 16 x i8> @llvm.riscv.vsub.nxv16i8.i8(
<vscale x 16 x i8>,
<vscale x 16 x i8>,
i8,
- i32);
+ iXLen);
-define <vscale x 16 x i8> @intrinsic_vsub_vx_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, i8 %1, i32 %2) nounwind {
+define <vscale x 16 x i8> @intrinsic_vsub_vx_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, i8 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vsub_vx_nxv16i8_nxv16i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
@@ -1244,7 +1220,7 @@ entry:
<vscale x 16 x i8> undef,
<vscale x 16 x i8> %0,
i8 %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 16 x i8> %a
}
@@ -1254,10 +1230,9 @@ declare <vscale x 16 x i8> @llvm.riscv.vsub.mask.nxv16i8.i8(
<vscale x 16 x i8>,
i8,
<vscale x 16 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 16 x i8> @intrinsic_vsub_mask_vx_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+define <vscale x 16 x i8> @intrinsic_vsub_mask_vx_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vsub_mask_vx_nxv16i8_nxv16i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
@@ -1269,7 +1244,7 @@ entry:
<vscale x 16 x i8> %1,
i8 %2,
<vscale x 16 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 16 x i8> %a
}
@@ -1278,9 +1253,9 @@ declare <vscale x 32 x i8> @llvm.riscv.vsub.nxv32i8.i8(
<vscale x 32 x i8>,
<vscale x 32 x i8>,
i8,
- i32);
+ iXLen);
-define <vscale x 32 x i8> @intrinsic_vsub_vx_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, i8 %1, i32 %2) nounwind {
+define <vscale x 32 x i8> @intrinsic_vsub_vx_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, i8 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vsub_vx_nxv32i8_nxv32i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
@@ -1291,7 +1266,7 @@ entry:
<vscale x 32 x i8> undef,
<vscale x 32 x i8> %0,
i8 %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 32 x i8> %a
}
@@ -1301,10 +1276,9 @@ declare <vscale x 32 x i8> @llvm.riscv.vsub.mask.nxv32i8.i8(
<vscale x 32 x i8>,
i8,
<vscale x 32 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 32 x i8> @intrinsic_vsub_mask_vx_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
+define <vscale x 32 x i8> @intrinsic_vsub_mask_vx_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vsub_mask_vx_nxv32i8_nxv32i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
@@ -1316,7 +1290,7 @@ entry:
<vscale x 32 x i8> %1,
i8 %2,
<vscale x 32 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 32 x i8> %a
}
@@ -1325,9 +1299,9 @@ declare <vscale x 64 x i8> @llvm.riscv.vsub.nxv64i8.i8(
<vscale x 64 x i8>,
<vscale x 64 x i8>,
i8,
- i32);
+ iXLen);
-define <vscale x 64 x i8> @intrinsic_vsub_vx_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, i8 %1, i32 %2) nounwind {
+define <vscale x 64 x i8> @intrinsic_vsub_vx_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, i8 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vsub_vx_nxv64i8_nxv64i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu
@@ -1338,7 +1312,7 @@ entry:
<vscale x 64 x i8> undef,
<vscale x 64 x i8> %0,
i8 %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 64 x i8> %a
}
@@ -1348,10 +1322,9 @@ declare <vscale x 64 x i8> @llvm.riscv.vsub.mask.nxv64i8.i8(
<vscale x 64 x i8>,
i8,
<vscale x 64 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 64 x i8> @intrinsic_vsub_mask_vx_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i8 %2, <vscale x 64 x i1> %3, i32 %4) nounwind {
+define <vscale x 64 x i8> @intrinsic_vsub_mask_vx_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i8 %2, <vscale x 64 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vsub_mask_vx_nxv64i8_nxv64i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu
@@ -1363,7 +1336,7 @@ entry:
<vscale x 64 x i8> %1,
i8 %2,
<vscale x 64 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 64 x i8> %a
}
@@ -1372,9 +1345,9 @@ declare <vscale x 1 x i16> @llvm.riscv.vsub.nxv1i16.i16(
<vscale x 1 x i16>,
<vscale x 1 x i16>,
i16,
- i32);
+ iXLen);
-define <vscale x 1 x i16> @intrinsic_vsub_vx_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, i16 %1, i32 %2) nounwind {
+define <vscale x 1 x i16> @intrinsic_vsub_vx_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, i16 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vsub_vx_nxv1i16_nxv1i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
@@ -1385,7 +1358,7 @@ entry:
<vscale x 1 x i16> undef,
<vscale x 1 x i16> %0,
i16 %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 1 x i16> %a
}
@@ -1395,10 +1368,9 @@ declare <vscale x 1 x i16> @llvm.riscv.vsub.mask.nxv1i16.i16(
<vscale x 1 x i16>,
i16,
<vscale x 1 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 1 x i16> @intrinsic_vsub_mask_vx_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+define <vscale x 1 x i16> @intrinsic_vsub_mask_vx_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vsub_mask_vx_nxv1i16_nxv1i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
@@ -1410,7 +1382,7 @@ entry:
<vscale x 1 x i16> %1,
i16 %2,
<vscale x 1 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 1 x i16> %a
}
@@ -1419,9 +1391,9 @@ declare <vscale x 2 x i16> @llvm.riscv.vsub.nxv2i16.i16(
<vscale x 2 x i16>,
<vscale x 2 x i16>,
i16,
- i32);
+ iXLen);
-define <vscale x 2 x i16> @intrinsic_vsub_vx_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, i16 %1, i32 %2) nounwind {
+define <vscale x 2 x i16> @intrinsic_vsub_vx_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, i16 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vsub_vx_nxv2i16_nxv2i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
@@ -1432,7 +1404,7 @@ entry:
<vscale x 2 x i16> undef,
<vscale x 2 x i16> %0,
i16 %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 2 x i16> %a
}
@@ -1442,10 +1414,9 @@ declare <vscale x 2 x i16> @llvm.riscv.vsub.mask.nxv2i16.i16(
<vscale x 2 x i16>,
i16,
<vscale x 2 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 2 x i16> @intrinsic_vsub_mask_vx_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+define <vscale x 2 x i16> @intrinsic_vsub_mask_vx_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vsub_mask_vx_nxv2i16_nxv2i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
@@ -1457,7 +1428,7 @@ entry:
<vscale x 2 x i16> %1,
i16 %2,
<vscale x 2 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 2 x i16> %a
}
@@ -1466,9 +1437,9 @@ declare <vscale x 4 x i16> @llvm.riscv.vsub.nxv4i16.i16(
<vscale x 4 x i16>,
<vscale x 4 x i16>,
i16,
- i32);
+ iXLen);
-define <vscale x 4 x i16> @intrinsic_vsub_vx_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, i16 %1, i32 %2) nounwind {
+define <vscale x 4 x i16> @intrinsic_vsub_vx_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, i16 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vsub_vx_nxv4i16_nxv4i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
@@ -1479,7 +1450,7 @@ entry:
<vscale x 4 x i16> undef,
<vscale x 4 x i16> %0,
i16 %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 4 x i16> %a
}
@@ -1489,10 +1460,9 @@ declare <vscale x 4 x i16> @llvm.riscv.vsub.mask.nxv4i16.i16(
<vscale x 4 x i16>,
i16,
<vscale x 4 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 4 x i16> @intrinsic_vsub_mask_vx_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+define <vscale x 4 x i16> @intrinsic_vsub_mask_vx_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vsub_mask_vx_nxv4i16_nxv4i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
@@ -1504,7 +1474,7 @@ entry:
<vscale x 4 x i16> %1,
i16 %2,
<vscale x 4 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 4 x i16> %a
}
@@ -1513,9 +1483,9 @@ declare <vscale x 8 x i16> @llvm.riscv.vsub.nxv8i16.i16(
<vscale x 8 x i16>,
<vscale x 8 x i16>,
i16,
- i32);
+ iXLen);
-define <vscale x 8 x i16> @intrinsic_vsub_vx_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, i16 %1, i32 %2) nounwind {
+define <vscale x 8 x i16> @intrinsic_vsub_vx_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, i16 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vsub_vx_nxv8i16_nxv8i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
@@ -1526,7 +1496,7 @@ entry:
<vscale x 8 x i16> undef,
<vscale x 8 x i16> %0,
i16 %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 8 x i16> %a
}
@@ -1536,10 +1506,9 @@ declare <vscale x 8 x i16> @llvm.riscv.vsub.mask.nxv8i16.i16(
<vscale x 8 x i16>,
i16,
<vscale x 8 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 8 x i16> @intrinsic_vsub_mask_vx_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+define <vscale x 8 x i16> @intrinsic_vsub_mask_vx_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vsub_mask_vx_nxv8i16_nxv8i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
@@ -1551,7 +1520,7 @@ entry:
<vscale x 8 x i16> %1,
i16 %2,
<vscale x 8 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 8 x i16> %a
}
@@ -1560,9 +1529,9 @@ declare <vscale x 16 x i16> @llvm.riscv.vsub.nxv16i16.i16(
<vscale x 16 x i16>,
<vscale x 16 x i16>,
i16,
- i32);
+ iXLen);
-define <vscale x 16 x i16> @intrinsic_vsub_vx_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, i16 %1, i32 %2) nounwind {
+define <vscale x 16 x i16> @intrinsic_vsub_vx_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, i16 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vsub_vx_nxv16i16_nxv16i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
@@ -1573,7 +1542,7 @@ entry:
<vscale x 16 x i16> undef,
<vscale x 16 x i16> %0,
i16 %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 16 x i16> %a
}
@@ -1583,10 +1552,9 @@ declare <vscale x 16 x i16> @llvm.riscv.vsub.mask.nxv16i16.i16(
<vscale x 16 x i16>,
i16,
<vscale x 16 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 16 x i16> @intrinsic_vsub_mask_vx_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+define <vscale x 16 x i16> @intrinsic_vsub_mask_vx_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vsub_mask_vx_nxv16i16_nxv16i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
@@ -1598,7 +1566,7 @@ entry:
<vscale x 16 x i16> %1,
i16 %2,
<vscale x 16 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 16 x i16> %a
}
@@ -1607,9 +1575,9 @@ declare <vscale x 32 x i16> @llvm.riscv.vsub.nxv32i16.i16(
<vscale x 32 x i16>,
<vscale x 32 x i16>,
i16,
- i32);
+ iXLen);
-define <vscale x 32 x i16> @intrinsic_vsub_vx_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, i16 %1, i32 %2) nounwind {
+define <vscale x 32 x i16> @intrinsic_vsub_vx_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, i16 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vsub_vx_nxv32i16_nxv32i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu
@@ -1620,7 +1588,7 @@ entry:
<vscale x 32 x i16> undef,
<vscale x 32 x i16> %0,
i16 %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 32 x i16> %a
}
@@ -1630,10 +1598,9 @@ declare <vscale x 32 x i16> @llvm.riscv.vsub.mask.nxv32i16.i16(
<vscale x 32 x i16>,
i16,
<vscale x 32 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 32 x i16> @intrinsic_vsub_mask_vx_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, i16 %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
+define <vscale x 32 x i16> @intrinsic_vsub_mask_vx_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, i16 %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vsub_mask_vx_nxv32i16_nxv32i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu
@@ -1645,7 +1612,7 @@ entry:
<vscale x 32 x i16> %1,
i16 %2,
<vscale x 32 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 32 x i16> %a
}
@@ -1654,9 +1621,9 @@ declare <vscale x 1 x i32> @llvm.riscv.vsub.nxv1i32.i32(
<vscale x 1 x i32>,
<vscale x 1 x i32>,
i32,
- i32);
+ iXLen);
-define <vscale x 1 x i32> @intrinsic_vsub_vx_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, i32 %1, i32 %2) nounwind {
+define <vscale x 1 x i32> @intrinsic_vsub_vx_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, i32 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vsub_vx_nxv1i32_nxv1i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
@@ -1667,7 +1634,7 @@ entry:
<vscale x 1 x i32> undef,
<vscale x 1 x i32> %0,
i32 %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 1 x i32> %a
}
@@ -1677,10 +1644,9 @@ declare <vscale x 1 x i32> @llvm.riscv.vsub.mask.nxv1i32.i32(
<vscale x 1 x i32>,
i32,
<vscale x 1 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 1 x i32> @intrinsic_vsub_mask_vx_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+define <vscale x 1 x i32> @intrinsic_vsub_mask_vx_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vsub_mask_vx_nxv1i32_nxv1i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
@@ -1692,7 +1658,7 @@ entry:
<vscale x 1 x i32> %1,
i32 %2,
<vscale x 1 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 1 x i32> %a
}
@@ -1701,9 +1667,9 @@ declare <vscale x 2 x i32> @llvm.riscv.vsub.nxv2i32.i32(
<vscale x 2 x i32>,
<vscale x 2 x i32>,
i32,
- i32);
+ iXLen);
-define <vscale x 2 x i32> @intrinsic_vsub_vx_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, i32 %1, i32 %2) nounwind {
+define <vscale x 2 x i32> @intrinsic_vsub_vx_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, i32 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vsub_vx_nxv2i32_nxv2i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
@@ -1714,7 +1680,7 @@ entry:
<vscale x 2 x i32> undef,
<vscale x 2 x i32> %0,
i32 %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 2 x i32> %a
}
@@ -1724,10 +1690,9 @@ declare <vscale x 2 x i32> @llvm.riscv.vsub.mask.nxv2i32.i32(
<vscale x 2 x i32>,
i32,
<vscale x 2 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 2 x i32> @intrinsic_vsub_mask_vx_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+define <vscale x 2 x i32> @intrinsic_vsub_mask_vx_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vsub_mask_vx_nxv2i32_nxv2i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
@@ -1739,7 +1704,7 @@ entry:
<vscale x 2 x i32> %1,
i32 %2,
<vscale x 2 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 2 x i32> %a
}
@@ -1748,9 +1713,9 @@ declare <vscale x 4 x i32> @llvm.riscv.vsub.nxv4i32.i32(
<vscale x 4 x i32>,
<vscale x 4 x i32>,
i32,
- i32);
+ iXLen);
-define <vscale x 4 x i32> @intrinsic_vsub_vx_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, i32 %1, i32 %2) nounwind {
+define <vscale x 4 x i32> @intrinsic_vsub_vx_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, i32 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vsub_vx_nxv4i32_nxv4i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
@@ -1761,7 +1726,7 @@ entry:
<vscale x 4 x i32> undef,
<vscale x 4 x i32> %0,
i32 %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 4 x i32> %a
}
@@ -1771,10 +1736,9 @@ declare <vscale x 4 x i32> @llvm.riscv.vsub.mask.nxv4i32.i32(
<vscale x 4 x i32>,
i32,
<vscale x 4 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 4 x i32> @intrinsic_vsub_mask_vx_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+define <vscale x 4 x i32> @intrinsic_vsub_mask_vx_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vsub_mask_vx_nxv4i32_nxv4i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
@@ -1786,7 +1750,7 @@ entry:
<vscale x 4 x i32> %1,
i32 %2,
<vscale x 4 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 4 x i32> %a
}
@@ -1795,9 +1759,9 @@ declare <vscale x 8 x i32> @llvm.riscv.vsub.nxv8i32.i32(
<vscale x 8 x i32>,
<vscale x 8 x i32>,
i32,
- i32);
+ iXLen);
-define <vscale x 8 x i32> @intrinsic_vsub_vx_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, i32 %1, i32 %2) nounwind {
+define <vscale x 8 x i32> @intrinsic_vsub_vx_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, i32 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vsub_vx_nxv8i32_nxv8i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
@@ -1808,7 +1772,7 @@ entry:
<vscale x 8 x i32> undef,
<vscale x 8 x i32> %0,
i32 %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 8 x i32> %a
}
@@ -1818,10 +1782,9 @@ declare <vscale x 8 x i32> @llvm.riscv.vsub.mask.nxv8i32.i32(
<vscale x 8 x i32>,
i32,
<vscale x 8 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 8 x i32> @intrinsic_vsub_mask_vx_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+define <vscale x 8 x i32> @intrinsic_vsub_mask_vx_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vsub_mask_vx_nxv8i32_nxv8i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
@@ -1833,7 +1796,7 @@ entry:
<vscale x 8 x i32> %1,
i32 %2,
<vscale x 8 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 8 x i32> %a
}
@@ -1842,9 +1805,9 @@ declare <vscale x 16 x i32> @llvm.riscv.vsub.nxv16i32.i32(
<vscale x 16 x i32>,
<vscale x 16 x i32>,
i32,
- i32);
+ iXLen);
-define <vscale x 16 x i32> @intrinsic_vsub_vx_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, i32 %1, i32 %2) nounwind {
+define <vscale x 16 x i32> @intrinsic_vsub_vx_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, i32 %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vsub_vx_nxv16i32_nxv16i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu
@@ -1855,7 +1818,7 @@ entry:
<vscale x 16 x i32> undef,
<vscale x 16 x i32> %0,
i32 %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 16 x i32> %a
}
@@ -1865,10 +1828,9 @@ declare <vscale x 16 x i32> @llvm.riscv.vsub.mask.nxv16i32.i32(
<vscale x 16 x i32>,
i32,
<vscale x 16 x i1>,
- i32,
- i32);
+ iXLen, iXLen);
-define <vscale x 16 x i32> @intrinsic_vsub_mask_vx_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+define <vscale x 16 x i32> @intrinsic_vsub_mask_vx_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vsub_mask_vx_nxv16i32_nxv16i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu
@@ -1880,7 +1842,7 @@ entry:
<vscale x 16 x i32> %1,
i32 %2,
<vscale x 16 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 16 x i32> %a
}
@@ -1889,26 +1851,32 @@ declare <vscale x 1 x i64> @llvm.riscv.vsub.nxv1i64.i64(
<vscale x 1 x i64>,
<vscale x 1 x i64>,
i64,
- i32);
-
-define <vscale x 1 x i64> @intrinsic_vsub_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vsub_vx_nxv1i64_nxv1i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addi sp, sp, -16
-; CHECK-NEXT: sw a1, 12(sp)
-; CHECK-NEXT: sw a0, 8(sp)
-; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
-; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v9, (a0), zero
-; CHECK-NEXT: vsub.vv v8, v8, v9
-; CHECK-NEXT: addi sp, sp, 16
-; CHECK-NEXT: ret
+ iXLen);
+
+define <vscale x 1 x i64> @intrinsic_vsub_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, iXLen %2) nounwind {
+; RV32-LABEL: intrinsic_vsub_vx_nxv1i64_nxv1i64_i64:
+; RV32: # %bb.0: # %entry
+; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: sw a1, 12(sp)
+; RV32-NEXT: sw a0, 8(sp)
+; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
+; RV32-NEXT: addi a0, sp, 8
+; RV32-NEXT: vlse64.v v9, (a0), zero
+; RV32-NEXT: vsub.vv v8, v8, v9
+; RV32-NEXT: addi sp, sp, 16
+; RV32-NEXT: ret
+;
+; RV64-LABEL: intrinsic_vsub_vx_nxv1i64_nxv1i64_i64:
+; RV64: # %bb.0: # %entry
+; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, mu
+; RV64-NEXT: vsub.vx v8, v8, a0
+; RV64-NEXT: ret
entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vsub.nxv1i64.i64(
<vscale x 1 x i64> undef,
<vscale x 1 x i64> %0,
i64 %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 1 x i64> %a
}
@@ -1918,28 +1886,33 @@ declare <vscale x 1 x i64> @llvm.riscv.vsub.mask.nxv1i64.i64(
<vscale x 1 x i64>,
i64,
<vscale x 1 x i1>,
- i32,
- i32);
-
-define <vscale x 1 x i64> @intrinsic_vsub_mask_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vsub_mask_vx_nxv1i64_nxv1i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addi sp, sp, -16
-; CHECK-NEXT: sw a1, 12(sp)
-; CHECK-NEXT: sw a0, 8(sp)
-; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
-; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v10, (a0), zero
-; CHECK-NEXT: vsub.vv v8, v9, v10, v0.t
-; CHECK-NEXT: addi sp, sp, 16
-; CHECK-NEXT: ret
+ iXLen, iXLen);
+
+define <vscale x 1 x i64> @intrinsic_vsub_mask_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
+; RV32-LABEL: intrinsic_vsub_mask_vx_nxv1i64_nxv1i64_i64:
+; RV32: # %bb.0: # %entry
+; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: sw a1, 12(sp)
+; RV32-NEXT: sw a0, 8(sp)
+; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
+; RV32-NEXT: addi a0, sp, 8
+; RV32-NEXT: vlse64.v v10, (a0), zero
+; RV32-NEXT: vsub.vv v8, v9, v10, v0.t
+; RV32-NEXT: addi sp, sp, 16
+; RV32-NEXT: ret
+;
+; RV64-LABEL: intrinsic_vsub_mask_vx_nxv1i64_nxv1i64_i64:
+; RV64: # %bb.0: # %entry
+; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, mu
+; RV64-NEXT: vsub.vx v8, v9, a0, v0.t
+; RV64-NEXT: ret
entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vsub.mask.nxv1i64.i64(
<vscale x 1 x i64> %0,
<vscale x 1 x i64> %1,
i64 %2,
<vscale x 1 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 1 x i64> %a
}
@@ -1948,26 +1921,32 @@ declare <vscale x 2 x i64> @llvm.riscv.vsub.nxv2i64.i64(
<vscale x 2 x i64>,
<vscale x 2 x i64>,
i64,
- i32);
-
-define <vscale x 2 x i64> @intrinsic_vsub_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vsub_vx_nxv2i64_nxv2i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addi sp, sp, -16
-; CHECK-NEXT: sw a1, 12(sp)
-; CHECK-NEXT: sw a0, 8(sp)
-; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
-; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v10, (a0), zero
-; CHECK-NEXT: vsub.vv v8, v8, v10
-; CHECK-NEXT: addi sp, sp, 16
-; CHECK-NEXT: ret
+ iXLen);
+
+define <vscale x 2 x i64> @intrinsic_vsub_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, iXLen %2) nounwind {
+; RV32-LABEL: intrinsic_vsub_vx_nxv2i64_nxv2i64_i64:
+; RV32: # %bb.0: # %entry
+; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: sw a1, 12(sp)
+; RV32-NEXT: sw a0, 8(sp)
+; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
+; RV32-NEXT: addi a0, sp, 8
+; RV32-NEXT: vlse64.v v10, (a0), zero
+; RV32-NEXT: vsub.vv v8, v8, v10
+; RV32-NEXT: addi sp, sp, 16
+; RV32-NEXT: ret
+;
+; RV64-LABEL: intrinsic_vsub_vx_nxv2i64_nxv2i64_i64:
+; RV64: # %bb.0: # %entry
+; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, mu
+; RV64-NEXT: vsub.vx v8, v8, a0
+; RV64-NEXT: ret
entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vsub.nxv2i64.i64(
<vscale x 2 x i64> undef,
<vscale x 2 x i64> %0,
i64 %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 2 x i64> %a
}
@@ -1977,28 +1956,33 @@ declare <vscale x 2 x i64> @llvm.riscv.vsub.mask.nxv2i64.i64(
<vscale x 2 x i64>,
i64,
<vscale x 2 x i1>,
- i32,
- i32);
-
-define <vscale x 2 x i64> @intrinsic_vsub_mask_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vsub_mask_vx_nxv2i64_nxv2i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addi sp, sp, -16
-; CHECK-NEXT: sw a1, 12(sp)
-; CHECK-NEXT: sw a0, 8(sp)
-; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
-; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v12, (a0), zero
-; CHECK-NEXT: vsub.vv v8, v10, v12, v0.t
-; CHECK-NEXT: addi sp, sp, 16
-; CHECK-NEXT: ret
+ iXLen, iXLen);
+
+define <vscale x 2 x i64> @intrinsic_vsub_mask_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
+; RV32-LABEL: intrinsic_vsub_mask_vx_nxv2i64_nxv2i64_i64:
+; RV32: # %bb.0: # %entry
+; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: sw a1, 12(sp)
+; RV32-NEXT: sw a0, 8(sp)
+; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
+; RV32-NEXT: addi a0, sp, 8
+; RV32-NEXT: vlse64.v v12, (a0), zero
+; RV32-NEXT: vsub.vv v8, v10, v12, v0.t
+; RV32-NEXT: addi sp, sp, 16
+; RV32-NEXT: ret
+;
+; RV64-LABEL: intrinsic_vsub_mask_vx_nxv2i64_nxv2i64_i64:
+; RV64: # %bb.0: # %entry
+; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, mu
+; RV64-NEXT: vsub.vx v8, v10, a0, v0.t
+; RV64-NEXT: ret
entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vsub.mask.nxv2i64.i64(
<vscale x 2 x i64> %0,
<vscale x 2 x i64> %1,
i64 %2,
<vscale x 2 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 2 x i64> %a
}
@@ -2007,26 +1991,32 @@ declare <vscale x 4 x i64> @llvm.riscv.vsub.nxv4i64.i64(
<vscale x 4 x i64>,
<vscale x 4 x i64>,
i64,
- i32);
-
-define <vscale x 4 x i64> @intrinsic_vsub_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vsub_vx_nxv4i64_nxv4i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addi sp, sp, -16
-; CHECK-NEXT: sw a1, 12(sp)
-; CHECK-NEXT: sw a0, 8(sp)
-; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
-; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v12, (a0), zero
-; CHECK-NEXT: vsub.vv v8, v8, v12
-; CHECK-NEXT: addi sp, sp, 16
-; CHECK-NEXT: ret
+ iXLen);
+
+define <vscale x 4 x i64> @intrinsic_vsub_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, iXLen %2) nounwind {
+; RV32-LABEL: intrinsic_vsub_vx_nxv4i64_nxv4i64_i64:
+; RV32: # %bb.0: # %entry
+; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: sw a1, 12(sp)
+; RV32-NEXT: sw a0, 8(sp)
+; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
+; RV32-NEXT: addi a0, sp, 8
+; RV32-NEXT: vlse64.v v12, (a0), zero
+; RV32-NEXT: vsub.vv v8, v8, v12
+; RV32-NEXT: addi sp, sp, 16
+; RV32-NEXT: ret
+;
+; RV64-LABEL: intrinsic_vsub_vx_nxv4i64_nxv4i64_i64:
+; RV64: # %bb.0: # %entry
+; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu
+; RV64-NEXT: vsub.vx v8, v8, a0
+; RV64-NEXT: ret
entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vsub.nxv4i64.i64(
<vscale x 4 x i64> undef,
<vscale x 4 x i64> %0,
i64 %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 4 x i64> %a
}
@@ -2036,28 +2026,33 @@ declare <vscale x 4 x i64> @llvm.riscv.vsub.mask.nxv4i64.i64(
<vscale x 4 x i64>,
i64,
<vscale x 4 x i1>,
- i32,
- i32);
-
-define <vscale x 4 x i64> @intrinsic_vsub_mask_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vsub_mask_vx_nxv4i64_nxv4i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addi sp, sp, -16
-; CHECK-NEXT: sw a1, 12(sp)
-; CHECK-NEXT: sw a0, 8(sp)
-; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
-; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v16, (a0), zero
-; CHECK-NEXT: vsub.vv v8, v12, v16, v0.t
-; CHECK-NEXT: addi sp, sp, 16
-; CHECK-NEXT: ret
+ iXLen, iXLen);
+
+define <vscale x 4 x i64> @intrinsic_vsub_mask_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
+; RV32-LABEL: intrinsic_vsub_mask_vx_nxv4i64_nxv4i64_i64:
+; RV32: # %bb.0: # %entry
+; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: sw a1, 12(sp)
+; RV32-NEXT: sw a0, 8(sp)
+; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
+; RV32-NEXT: addi a0, sp, 8
+; RV32-NEXT: vlse64.v v16, (a0), zero
+; RV32-NEXT: vsub.vv v8, v12, v16, v0.t
+; RV32-NEXT: addi sp, sp, 16
+; RV32-NEXT: ret
+;
+; RV64-LABEL: intrinsic_vsub_mask_vx_nxv4i64_nxv4i64_i64:
+; RV64: # %bb.0: # %entry
+; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu
+; RV64-NEXT: vsub.vx v8, v12, a0, v0.t
+; RV64-NEXT: ret
entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vsub.mask.nxv4i64.i64(
<vscale x 4 x i64> %0,
<vscale x 4 x i64> %1,
i64 %2,
<vscale x 4 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 4 x i64> %a
}
@@ -2066,26 +2061,32 @@ declare <vscale x 8 x i64> @llvm.riscv.vsub.nxv8i64.i64(
<vscale x 8 x i64>,
<vscale x 8 x i64>,
i64,
- i32);
-
-define <vscale x 8 x i64> @intrinsic_vsub_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, i64 %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vsub_vx_nxv8i64_nxv8i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addi sp, sp, -16
-; CHECK-NEXT: sw a1, 12(sp)
-; CHECK-NEXT: sw a0, 8(sp)
-; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, mu
-; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v16, (a0), zero
-; CHECK-NEXT: vsub.vv v8, v8, v16
-; CHECK-NEXT: addi sp, sp, 16
-; CHECK-NEXT: ret
+ iXLen);
+
+define <vscale x 8 x i64> @intrinsic_vsub_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, i64 %1, iXLen %2) nounwind {
+; RV32-LABEL: intrinsic_vsub_vx_nxv8i64_nxv8i64_i64:
+; RV32: # %bb.0: # %entry
+; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: sw a1, 12(sp)
+; RV32-NEXT: sw a0, 8(sp)
+; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu
+; RV32-NEXT: addi a0, sp, 8
+; RV32-NEXT: vlse64.v v16, (a0), zero
+; RV32-NEXT: vsub.vv v8, v8, v16
+; RV32-NEXT: addi sp, sp, 16
+; RV32-NEXT: ret
+;
+; RV64-LABEL: intrinsic_vsub_vx_nxv8i64_nxv8i64_i64:
+; RV64: # %bb.0: # %entry
+; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, mu
+; RV64-NEXT: vsub.vx v8, v8, a0
+; RV64-NEXT: ret
entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vsub.nxv8i64.i64(
<vscale x 8 x i64> undef,
<vscale x 8 x i64> %0,
i64 %1,
- i32 %2)
+ iXLen %2)
ret <vscale x 8 x i64> %a
}
@@ -2095,33 +2096,38 @@ declare <vscale x 8 x i64> @llvm.riscv.vsub.mask.nxv8i64.i64(
<vscale x 8 x i64>,
i64,
<vscale x 8 x i1>,
- i32,
- i32);
-
-define <vscale x 8 x i64> @intrinsic_vsub_mask_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
-; CHECK-LABEL: intrinsic_vsub_mask_vx_nxv8i64_nxv8i64_i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addi sp, sp, -16
-; CHECK-NEXT: sw a1, 12(sp)
-; CHECK-NEXT: sw a0, 8(sp)
-; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, mu
-; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v24, (a0), zero
-; CHECK-NEXT: vsub.vv v8, v16, v24, v0.t
-; CHECK-NEXT: addi sp, sp, 16
-; CHECK-NEXT: ret
+ iXLen, iXLen);
+
+define <vscale x 8 x i64> @intrinsic_vsub_mask_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
+; RV32-LABEL: intrinsic_vsub_mask_vx_nxv8i64_nxv8i64_i64:
+; RV32: # %bb.0: # %entry
+; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: sw a1, 12(sp)
+; RV32-NEXT: sw a0, 8(sp)
+; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu
+; RV32-NEXT: addi a0, sp, 8
+; RV32-NEXT: vlse64.v v24, (a0), zero
+; RV32-NEXT: vsub.vv v8, v16, v24, v0.t
+; RV32-NEXT: addi sp, sp, 16
+; RV32-NEXT: ret
+;
+; RV64-LABEL: intrinsic_vsub_mask_vx_nxv8i64_nxv8i64_i64:
+; RV64: # %bb.0: # %entry
+; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, mu
+; RV64-NEXT: vsub.vx v8, v16, a0, v0.t
+; RV64-NEXT: ret
entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vsub.mask.nxv8i64.i64(
<vscale x 8 x i64> %0,
<vscale x 8 x i64> %1,
i64 %2,
<vscale x 8 x i1> %3,
- i32 %4, i32 1)
+ iXLen %4, iXLen 1)
ret <vscale x 8 x i64> %a
}
-define <vscale x 1 x i8> @intrinsic_vsub_vi_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, i32 %1) nounwind {
+define <vscale x 1 x i8> @intrinsic_vsub_vi_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vsub_vi_nxv1i8_nxv1i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
@@ -2132,12 +2138,12 @@ entry:
<vscale x 1 x i8> undef,
<vscale x 1 x i8> %0,
i8 9,
- i32 %1)
+ iXLen %1)
ret <vscale x 1 x i8> %a
}
-define <vscale x 1 x i8> @intrinsic_vsub_mask_vi_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
+define <vscale x 1 x i8> @intrinsic_vsub_mask_vi_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vsub_mask_vi_nxv1i8_nxv1i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
@@ -2149,12 +2155,12 @@ entry:
<vscale x 1 x i8> %1,
i8 -9,
<vscale x 1 x i1> %2,
- i32 %3, i32 1)
+ iXLen %3, iXLen 1)
ret <vscale x 1 x i8> %a
}
-define <vscale x 2 x i8> @intrinsic_vsub_vi_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, i32 %1) nounwind {
+define <vscale x 2 x i8> @intrinsic_vsub_vi_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vsub_vi_nxv2i8_nxv2i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
@@ -2165,12 +2171,12 @@ entry:
<vscale x 2 x i8> undef,
<vscale x 2 x i8> %0,
i8 9,
- i32 %1)
+ iXLen %1)
ret <vscale x 2 x i8> %a
}
-define <vscale x 2 x i8> @intrinsic_vsub_mask_vi_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
+define <vscale x 2 x i8> @intrinsic_vsub_mask_vi_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vsub_mask_vi_nxv2i8_nxv2i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
@@ -2182,12 +2188,12 @@ entry:
<vscale x 2 x i8> %1,
i8 -9,
<vscale x 2 x i1> %2,
- i32 %3, i32 1)
+ iXLen %3, iXLen 1)
ret <vscale x 2 x i8> %a
}
-define <vscale x 4 x i8> @intrinsic_vsub_vi_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, i32 %1) nounwind {
+define <vscale x 4 x i8> @intrinsic_vsub_vi_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vsub_vi_nxv4i8_nxv4i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
@@ -2198,12 +2204,12 @@ entry:
<vscale x 4 x i8> undef,
<vscale x 4 x i8> %0,
i8 9,
- i32 %1)
+ iXLen %1)
ret <vscale x 4 x i8> %a
}
-define <vscale x 4 x i8> @intrinsic_vsub_mask_vi_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
+define <vscale x 4 x i8> @intrinsic_vsub_mask_vi_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vsub_mask_vi_nxv4i8_nxv4i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
@@ -2215,12 +2221,12 @@ entry:
<vscale x 4 x i8> %1,
i8 -9,
<vscale x 4 x i1> %2,
- i32 %3, i32 1)
+ iXLen %3, iXLen 1)
ret <vscale x 4 x i8> %a
}
-define <vscale x 8 x i8> @intrinsic_vsub_vi_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, i32 %1) nounwind {
+define <vscale x 8 x i8> @intrinsic_vsub_vi_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vsub_vi_nxv8i8_nxv8i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
@@ -2231,12 +2237,12 @@ entry:
<vscale x 8 x i8> undef,
<vscale x 8 x i8> %0,
i8 9,
- i32 %1)
+ iXLen %1)
ret <vscale x 8 x i8> %a
}
-define <vscale x 8 x i8> @intrinsic_vsub_mask_vi_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
+define <vscale x 8 x i8> @intrinsic_vsub_mask_vi_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vsub_mask_vi_nxv8i8_nxv8i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
@@ -2248,12 +2254,12 @@ entry:
<vscale x 8 x i8> %1,
i8 -9,
<vscale x 8 x i1> %2,
- i32 %3, i32 1)
+ iXLen %3, iXLen 1)
ret <vscale x 8 x i8> %a
}
-define <vscale x 16 x i8> @intrinsic_vsub_vi_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, i32 %1) nounwind {
+define <vscale x 16 x i8> @intrinsic_vsub_vi_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vsub_vi_nxv16i8_nxv16i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
@@ -2264,12 +2270,12 @@ entry:
<vscale x 16 x i8> undef,
<vscale x 16 x i8> %0,
i8 9,
- i32 %1)
+ iXLen %1)
ret <vscale x 16 x i8> %a
}
-define <vscale x 16 x i8> @intrinsic_vsub_mask_vi_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i1> %2, i32 %3) nounwind {
+define <vscale x 16 x i8> @intrinsic_vsub_mask_vi_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vsub_mask_vi_nxv16i8_nxv16i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
@@ -2281,12 +2287,12 @@ entry:
<vscale x 16 x i8> %1,
i8 -9,
<vscale x 16 x i1> %2,
- i32 %3, i32 1)
+ iXLen %3, iXLen 1)
ret <vscale x 16 x i8> %a
}
-define <vscale x 32 x i8> @intrinsic_vsub_vi_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, i32 %1) nounwind {
+define <vscale x 32 x i8> @intrinsic_vsub_vi_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vsub_vi_nxv32i8_nxv32i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
@@ -2297,12 +2303,12 @@ entry:
<vscale x 32 x i8> undef,
<vscale x 32 x i8> %0,
i8 9,
- i32 %1)
+ iXLen %1)
ret <vscale x 32 x i8> %a
}
-define <vscale x 32 x i8> @intrinsic_vsub_mask_vi_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i1> %2, i32 %3) nounwind {
+define <vscale x 32 x i8> @intrinsic_vsub_mask_vi_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vsub_mask_vi_nxv32i8_nxv32i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
@@ -2314,12 +2320,12 @@ entry:
<vscale x 32 x i8> %1,
i8 -9,
<vscale x 32 x i1> %2,
- i32 %3, i32 1)
+ iXLen %3, iXLen 1)
ret <vscale x 32 x i8> %a
}
-define <vscale x 64 x i8> @intrinsic_vsub_vi_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, i32 %1) nounwind {
+define <vscale x 64 x i8> @intrinsic_vsub_vi_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vsub_vi_nxv64i8_nxv64i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, mu
@@ -2330,12 +2336,12 @@ entry:
<vscale x 64 x i8> undef,
<vscale x 64 x i8> %0,
i8 -9,
- i32 %1)
+ iXLen %1)
ret <vscale x 64 x i8> %a
}
-define <vscale x 64 x i8> @intrinsic_vsub_mask_vi_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i1> %2, i32 %3) nounwind {
+define <vscale x 64 x i8> @intrinsic_vsub_mask_vi_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vsub_mask_vi_nxv64i8_nxv64i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, mu
@@ -2347,12 +2353,12 @@ entry:
<vscale x 64 x i8> %1,
i8 -9,
<vscale x 64 x i1> %2,
- i32 %3, i32 1)
+ iXLen %3, iXLen 1)
ret <vscale x 64 x i8> %a
}
-define <vscale x 1 x i16> @intrinsic_vsub_vi_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, i32 %1) nounwind {
+define <vscale x 1 x i16> @intrinsic_vsub_vi_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vsub_vi_nxv1i16_nxv1i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
@@ -2363,12 +2369,12 @@ entry:
<vscale x 1 x i16> undef,
<vscale x 1 x i16> %0,
i16 9,
- i32 %1)
+ iXLen %1)
ret <vscale x 1 x i16> %a
}
-define <vscale x 1 x i16> @intrinsic_vsub_mask_vi_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
+define <vscale x 1 x i16> @intrinsic_vsub_mask_vi_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vsub_mask_vi_nxv1i16_nxv1i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
@@ -2380,12 +2386,12 @@ entry:
<vscale x 1 x i16> %1,
i16 -9,
<vscale x 1 x i1> %2,
- i32 %3, i32 1)
+ iXLen %3, iXLen 1)
ret <vscale x 1 x i16> %a
}
-define <vscale x 2 x i16> @intrinsic_vsub_vi_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, i32 %1) nounwind {
+define <vscale x 2 x i16> @intrinsic_vsub_vi_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vsub_vi_nxv2i16_nxv2i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
@@ -2396,12 +2402,12 @@ entry:
<vscale x 2 x i16> undef,
<vscale x 2 x i16> %0,
i16 9,
- i32 %1)
+ iXLen %1)
ret <vscale x 2 x i16> %a
}
-define <vscale x 2 x i16> @intrinsic_vsub_mask_vi_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
+define <vscale x 2 x i16> @intrinsic_vsub_mask_vi_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vsub_mask_vi_nxv2i16_nxv2i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
@@ -2413,12 +2419,12 @@ entry:
<vscale x 2 x i16> %1,
i16 -9,
<vscale x 2 x i1> %2,
- i32 %3, i32 1)
+ iXLen %3, iXLen 1)
ret <vscale x 2 x i16> %a
}
-define <vscale x 4 x i16> @intrinsic_vsub_vi_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, i32 %1) nounwind {
+define <vscale x 4 x i16> @intrinsic_vsub_vi_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vsub_vi_nxv4i16_nxv4i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
@@ -2429,12 +2435,12 @@ entry:
<vscale x 4 x i16> undef,
<vscale x 4 x i16> %0,
i16 9,
- i32 %1)
+ iXLen %1)
ret <vscale x 4 x i16> %a
}
-define <vscale x 4 x i16> @intrinsic_vsub_mask_vi_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
+define <vscale x 4 x i16> @intrinsic_vsub_mask_vi_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vsub_mask_vi_nxv4i16_nxv4i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
@@ -2446,12 +2452,12 @@ entry:
<vscale x 4 x i16> %1,
i16 -9,
<vscale x 4 x i1> %2,
- i32 %3, i32 1)
+ iXLen %3, iXLen 1)
ret <vscale x 4 x i16> %a
}
-define <vscale x 8 x i16> @intrinsic_vsub_vi_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, i32 %1) nounwind {
+define <vscale x 8 x i16> @intrinsic_vsub_vi_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vsub_vi_nxv8i16_nxv8i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
@@ -2462,12 +2468,12 @@ entry:
<vscale x 8 x i16> undef,
<vscale x 8 x i16> %0,
i16 9,
- i32 %1)
+ iXLen %1)
ret <vscale x 8 x i16> %a
}
-define <vscale x 8 x i16> @intrinsic_vsub_mask_vi_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
+define <vscale x 8 x i16> @intrinsic_vsub_mask_vi_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vsub_mask_vi_nxv8i16_nxv8i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
@@ -2479,12 +2485,12 @@ entry:
<vscale x 8 x i16> %1,
i16 -9,
<vscale x 8 x i1> %2,
- i32 %3, i32 1)
+ iXLen %3, iXLen 1)
ret <vscale x 8 x i16> %a
}
-define <vscale x 16 x i16> @intrinsic_vsub_vi_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, i32 %1) nounwind {
+define <vscale x 16 x i16> @intrinsic_vsub_vi_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vsub_vi_nxv16i16_nxv16i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
@@ -2495,12 +2501,12 @@ entry:
<vscale x 16 x i16> undef,
<vscale x 16 x i16> %0,
i16 9,
- i32 %1)
+ iXLen %1)
ret <vscale x 16 x i16> %a
}
-define <vscale x 16 x i16> @intrinsic_vsub_mask_vi_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i1> %2, i32 %3) nounwind {
+define <vscale x 16 x i16> @intrinsic_vsub_mask_vi_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vsub_mask_vi_nxv16i16_nxv16i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
@@ -2512,12 +2518,12 @@ entry:
<vscale x 16 x i16> %1,
i16 -9,
<vscale x 16 x i1> %2,
- i32 %3, i32 1)
+ iXLen %3, iXLen 1)
ret <vscale x 16 x i16> %a
}
-define <vscale x 32 x i16> @intrinsic_vsub_vi_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, i32 %1) nounwind {
+define <vscale x 32 x i16> @intrinsic_vsub_vi_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vsub_vi_nxv32i16_nxv32i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, mu
@@ -2528,12 +2534,12 @@ entry:
<vscale x 32 x i16> undef,
<vscale x 32 x i16> %0,
i16 9,
- i32 %1)
+ iXLen %1)
ret <vscale x 32 x i16> %a
}
-define <vscale x 32 x i16> @intrinsic_vsub_mask_vi_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i1> %2, i32 %3) nounwind {
+define <vscale x 32 x i16> @intrinsic_vsub_mask_vi_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vsub_mask_vi_nxv32i16_nxv32i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, mu
@@ -2545,12 +2551,12 @@ entry:
<vscale x 32 x i16> %1,
i16 -9,
<vscale x 32 x i1> %2,
- i32 %3, i32 1)
+ iXLen %3, iXLen 1)
ret <vscale x 32 x i16> %a
}
-define <vscale x 1 x i32> @intrinsic_vsub_vi_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, i32 %1) nounwind {
+define <vscale x 1 x i32> @intrinsic_vsub_vi_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vsub_vi_nxv1i32_nxv1i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
@@ -2561,12 +2567,12 @@ entry:
<vscale x 1 x i32> undef,
<vscale x 1 x i32> %0,
i32 9,
- i32 %1)
+ iXLen %1)
ret <vscale x 1 x i32> %a
}
-define <vscale x 1 x i32> @intrinsic_vsub_mask_vi_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
+define <vscale x 1 x i32> @intrinsic_vsub_mask_vi_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vsub_mask_vi_nxv1i32_nxv1i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
@@ -2578,12 +2584,12 @@ entry:
<vscale x 1 x i32> %1,
i32 -9,
<vscale x 1 x i1> %2,
- i32 %3, i32 1)
+ iXLen %3, iXLen 1)
ret <vscale x 1 x i32> %a
}
-define <vscale x 2 x i32> @intrinsic_vsub_vi_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, i32 %1) nounwind {
+define <vscale x 2 x i32> @intrinsic_vsub_vi_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vsub_vi_nxv2i32_nxv2i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
@@ -2594,12 +2600,12 @@ entry:
<vscale x 2 x i32> undef,
<vscale x 2 x i32> %0,
i32 9,
- i32 %1)
+ iXLen %1)
ret <vscale x 2 x i32> %a
}
-define <vscale x 2 x i32> @intrinsic_vsub_mask_vi_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
+define <vscale x 2 x i32> @intrinsic_vsub_mask_vi_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vsub_mask_vi_nxv2i32_nxv2i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
@@ -2611,12 +2617,12 @@ entry:
<vscale x 2 x i32> %1,
i32 -9,
<vscale x 2 x i1> %2,
- i32 %3, i32 1)
+ iXLen %3, iXLen 1)
ret <vscale x 2 x i32> %a
}
-define <vscale x 4 x i32> @intrinsic_vsub_vi_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, i32 %1) nounwind {
+define <vscale x 4 x i32> @intrinsic_vsub_vi_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vsub_vi_nxv4i32_nxv4i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
@@ -2627,12 +2633,12 @@ entry:
<vscale x 4 x i32> undef,
<vscale x 4 x i32> %0,
i32 9,
- i32 %1)
+ iXLen %1)
ret <vscale x 4 x i32> %a
}
-define <vscale x 4 x i32> @intrinsic_vsub_mask_vi_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
+define <vscale x 4 x i32> @intrinsic_vsub_mask_vi_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vsub_mask_vi_nxv4i32_nxv4i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
@@ -2644,12 +2650,12 @@ entry:
<vscale x 4 x i32> %1,
i32 -9,
<vscale x 4 x i1> %2,
- i32 %3, i32 1)
+ iXLen %3, iXLen 1)
ret <vscale x 4 x i32> %a
}
-define <vscale x 8 x i32> @intrinsic_vsub_vi_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, i32 %1) nounwind {
+define <vscale x 8 x i32> @intrinsic_vsub_vi_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vsub_vi_nxv8i32_nxv8i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
@@ -2660,12 +2666,12 @@ entry:
<vscale x 8 x i32> undef,
<vscale x 8 x i32> %0,
i32 9,
- i32 %1)
+ iXLen %1)
ret <vscale x 8 x i32> %a
}
-define <vscale x 8 x i32> @intrinsic_vsub_mask_vi_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
+define <vscale x 8 x i32> @intrinsic_vsub_mask_vi_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vsub_mask_vi_nxv8i32_nxv8i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
@@ -2677,12 +2683,12 @@ entry:
<vscale x 8 x i32> %1,
i32 -9,
<vscale x 8 x i1> %2,
- i32 %3, i32 1)
+ iXLen %3, iXLen 1)
ret <vscale x 8 x i32> %a
}
-define <vscale x 16 x i32> @intrinsic_vsub_vi_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, i32 %1) nounwind {
+define <vscale x 16 x i32> @intrinsic_vsub_vi_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vsub_vi_nxv16i32_nxv16i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu
@@ -2693,12 +2699,12 @@ entry:
<vscale x 16 x i32> undef,
<vscale x 16 x i32> %0,
i32 9,
- i32 %1)
+ iXLen %1)
ret <vscale x 16 x i32> %a
}
-define <vscale x 16 x i32> @intrinsic_vsub_mask_vi_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i1> %2, i32 %3) nounwind {
+define <vscale x 16 x i32> @intrinsic_vsub_mask_vi_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vsub_mask_vi_nxv16i32_nxv16i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu
@@ -2710,12 +2716,12 @@ entry:
<vscale x 16 x i32> %1,
i32 -9,
<vscale x 16 x i1> %2,
- i32 %3, i32 1)
+ iXLen %3, iXLen 1)
ret <vscale x 16 x i32> %a
}
-define <vscale x 1 x i64> @intrinsic_vsub_vi_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, i32 %1) nounwind {
+define <vscale x 1 x i64> @intrinsic_vsub_vi_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vsub_vi_nxv1i64_nxv1i64_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
@@ -2726,12 +2732,12 @@ entry:
<vscale x 1 x i64> undef,
<vscale x 1 x i64> %0,
i64 9,
- i32 %1)
+ iXLen %1)
ret <vscale x 1 x i64> %a
}
-define <vscale x 1 x i64> @intrinsic_vsub_mask_vi_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
+define <vscale x 1 x i64> @intrinsic_vsub_mask_vi_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vsub_mask_vi_nxv1i64_nxv1i64_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
@@ -2743,12 +2749,12 @@ entry:
<vscale x 1 x i64> %1,
i64 9,
<vscale x 1 x i1> %2,
- i32 %3, i32 1)
+ iXLen %3, iXLen 1)
ret <vscale x 1 x i64> %a
}
-define <vscale x 2 x i64> @intrinsic_vsub_vi_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, i32 %1) nounwind {
+define <vscale x 2 x i64> @intrinsic_vsub_vi_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vsub_vi_nxv2i64_nxv2i64_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
@@ -2759,12 +2765,12 @@ entry:
<vscale x 2 x i64> undef,
<vscale x 2 x i64> %0,
i64 9,
- i32 %1)
+ iXLen %1)
ret <vscale x 2 x i64> %a
}
-define <vscale x 2 x i64> @intrinsic_vsub_mask_vi_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
+define <vscale x 2 x i64> @intrinsic_vsub_mask_vi_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vsub_mask_vi_nxv2i64_nxv2i64_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
@@ -2776,12 +2782,12 @@ entry:
<vscale x 2 x i64> %1,
i64 9,
<vscale x 2 x i1> %2,
- i32 %3, i32 1)
+ iXLen %3, iXLen 1)
ret <vscale x 2 x i64> %a
}
-define <vscale x 4 x i64> @intrinsic_vsub_vi_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, i32 %1) nounwind {
+define <vscale x 4 x i64> @intrinsic_vsub_vi_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vsub_vi_nxv4i64_nxv4i64_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
@@ -2792,12 +2798,12 @@ entry:
<vscale x 4 x i64> undef,
<vscale x 4 x i64> %0,
i64 9,
- i32 %1)
+ iXLen %1)
ret <vscale x 4 x i64> %a
}
-define <vscale x 4 x i64> @intrinsic_vsub_mask_vi_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
+define <vscale x 4 x i64> @intrinsic_vsub_mask_vi_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vsub_mask_vi_nxv4i64_nxv4i64_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
@@ -2809,12 +2815,12 @@ entry:
<vscale x 4 x i64> %1,
i64 9,
<vscale x 4 x i1> %2,
- i32 %3, i32 1)
+ iXLen %3, iXLen 1)
ret <vscale x 4 x i64> %a
}
-define <vscale x 8 x i64> @intrinsic_vsub_vi_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, i32 %1) nounwind {
+define <vscale x 8 x i64> @intrinsic_vsub_vi_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vsub_vi_nxv8i64_nxv8i64_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu
@@ -2825,12 +2831,12 @@ entry:
<vscale x 8 x i64> undef,
<vscale x 8 x i64> %0,
i64 9,
- i32 %1)
+ iXLen %1)
ret <vscale x 8 x i64> %a
}
-define <vscale x 8 x i64> @intrinsic_vsub_mask_vi_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
+define <vscale x 8 x i64> @intrinsic_vsub_mask_vi_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vsub_mask_vi_nxv8i64_nxv8i64_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu
@@ -2842,7 +2848,7 @@ entry:
<vscale x 8 x i64> %1,
i64 9,
<vscale x 8 x i1> %2,
- i32 %3, i32 1)
+ iXLen %3, iXLen 1)
ret <vscale x 8 x i64> %a
}
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