[PATCH] D120548: [AArch64] Try to convert signed to unsigned pred to re-use zext.

[Dave Green via Phabricator via llvm-commits]

dmgreen added inline comments.
Herald added a project: All.


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:17096-17097
+    if (isUnsignedIntSetCC(CC))
+      Op1ExtV =
+          DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::v16i32, Op->getOperand(1));
+  }
----------------
Should this be overriding Op1ExtV?


================
Comment at: llvm/test/CodeGen/AArch64/vselect-ext.ll:169
 ; CHECK:       ; %bb.0: ; %entry
-; CHECK-NEXT:    movi.2d v1, #0xffffffffffffffff
-; CHECK-NEXT:    ushll.8h v2, v0, #0
-; CHECK-NEXT:    ushll2.8h v3, v0, #0
-; CHECK-NEXT:    ushll.4s v4, v2, #0
-; CHECK-NEXT:    cmgt.16b v0, v0, v1
-; CHECK-NEXT:    ushll.4s v5, v3, #0
-; CHECK-NEXT:    ushll2.4s v1, v3, #0
-; CHECK-NEXT:    sshll.8h v3, v0, #0
-; CHECK-NEXT:    sshll2.8h v0, v0, #0
-; CHECK-NEXT:    ushll2.4s v2, v2, #0
-; CHECK-NEXT:    sshll.4s v6, v3, #0
-; CHECK-NEXT:    sshll.4s v7, v0, #0
-; CHECK-NEXT:    sshll2.4s v0, v0, #0
-; CHECK-NEXT:    sshll2.4s v16, v3, #0
-; CHECK-NEXT:    and.16b v3, v1, v0
-; CHECK-NEXT:    and.16b v1, v2, v16
-; CHECK-NEXT:    and.16b v2, v5, v7
-; CHECK-NEXT:    and.16b v0, v4, v6
+; CHECK-NEXT:    movi.2d v1, #0x0000ff000000ff
+; CHECK-NEXT:    ushll2.8h v2, v0, #0
----------------
This doesn't seem to be correct.


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https://reviews.llvm.org/D120548