[llvm] d05ddb8 - [VP] vp.sitofp cast intrinsic and docs
Simon Moll via llvm-commits
llvm-commits at lists.llvm.org
Wed Mar 2 01:17:32 PST 2022
Author: Simon Moll
Date: 2022-03-02T10:16:19+01:00
New Revision: d05ddb86f6cb24d0d152db65f419006929a42f61
URL: https://github.com/llvm/llvm-project/commit/d05ddb86f6cb24d0d152db65f419006929a42f61
DIFF: https://github.com/llvm/llvm-project/commit/d05ddb86f6cb24d0d152db65f419006929a42f61.diff
LOG: [VP] vp.sitofp cast intrinsic and docs
Reviewed By: frasercrmck
Differential Revision: https://reviews.llvm.org/D119922
Added:
Modified:
llvm/docs/LangRef.rst
llvm/include/llvm/IR/Intrinsics.td
llvm/include/llvm/IR/VPIntrinsics.def
llvm/lib/IR/IntrinsicInst.cpp
llvm/test/Verifier/vp-intrinsics.ll
llvm/unittests/IR/VPIntrinsicTest.cpp
Removed:
################################################################################
diff --git a/llvm/docs/LangRef.rst b/llvm/docs/LangRef.rst
index e8edf893de2f6..495d5a3cfd327 100644
--- a/llvm/docs/LangRef.rst
+++ b/llvm/docs/LangRef.rst
@@ -20073,6 +20073,61 @@ Examples:
%t = fptosi <4 x float> %a to <4 x i32>
%also.r = select <4 x i1> %mask, <4 x float> %t, <4 x float> undef
+.. _int_vp_sitofp:
+
+'``llvm.vp.sitofp.*``' Intrinsics
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+Syntax:
+"""""""
+This is an overloaded intrinsic.
+
+::
+
+ declare <16 x float> @llvm.vp.sitofp.v16f32.v16i32 (<16 x i32> <op>, <16 x i1> <mask>, i32 <vector_length>)
+ declare <vscale x 4 x float> @llvm.vp.sitofp.nxv4f32.nxv4i32 (<vscale x 4 x i32> <op>, <vscale x 4 x i1> <mask>, i32 <vector_length>)
+ declare <256 x double> @llvm.vp.sitofp.v256f64.v256i64 (<256 x i64> <op>, <256 x i1> <mask>, i32 <vector_length>)
+
+Overview:
+"""""""""
+
+The '``llvm.vp.sitofp``' intrinsic converts its signed integer operand to the
+:ref:`floating-point <t_floating>` return type. The operation has a mask and
+an explicit vector length parameter.
+
+
+Arguments:
+""""""""""
+
+The '``llvm.vp.sitofp``' intrinsic takes a value to cast as its first operand.
+The value to cast must be vector of :ref:`integer <t_integer>` type. The
+return type is the type to cast the value to. The return type must be a vector
+of :ref:`floating-point <t_floating>` type. The second operand is the vector
+mask. The return type, the value to cast, and the vector mask have the same
+number of elements. The third operand is the explicit vector length of the
+operation.
+
+Semantics:
+""""""""""
+
+The '``llvm.vp.sitofp``' intrinsic interprets its first operand as a signed
+integer quantity and converts it to the corresponding floating-point value. If
+the value cannot be exactly represented, it is rounded using the default
+rounding mode. The conversion is performed on lane positions below the
+explicit vector length and where the vector mask is true. Masked-off lanes are
+undefined.
+
+Examples:
+"""""""""
+
+.. code-block:: llvm
+
+ %r = call <4 x float> @llvm.vp.sitofp.v4f32.v4i32(<4 x i32> %a, <4 x i1> %mask, i32 %evl)
+ ;; For all lanes below %evl, %r is lane-wise equivalent to %also.r
+
+ %t = sitofp <4 x i32> %a to <4 x float>
+ %also.r = select <4 x i1> %mask, <4 x float> %t, <4 x float> undef
+
.. _int_mload_mstore:
diff --git a/llvm/include/llvm/IR/Intrinsics.td b/llvm/include/llvm/IR/Intrinsics.td
index 30333ca47db0b..9456e10bb44e3 100644
--- a/llvm/include/llvm/IR/Intrinsics.td
+++ b/llvm/include/llvm/IR/Intrinsics.td
@@ -1529,6 +1529,10 @@ def int_vp_fptosi : DefaultAttrsIntrinsic<[ llvm_anyvector_ty ],
[ llvm_anyvector_ty,
LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
llvm_i32_ty]>;
+def int_vp_sitofp : DefaultAttrsIntrinsic<[ llvm_anyvector_ty ],
+ [ llvm_anyvector_ty,
+ LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
+ llvm_i32_ty]>;
// Shuffles.
def int_vp_select : DefaultAttrsIntrinsic<[ llvm_anyvector_ty ],
diff --git a/llvm/include/llvm/IR/VPIntrinsics.def b/llvm/include/llvm/IR/VPIntrinsics.def
index 004bd8abcdb7a..f80b3bd399572 100644
--- a/llvm/include/llvm/IR/VPIntrinsics.def
+++ b/llvm/include/llvm/IR/VPIntrinsics.def
@@ -245,6 +245,9 @@ END_REGISTER_VP(vp_fma, VP_FMA)
// llvm.vp.fptosi(x,mask,vlen)
HELPER_REGISTER_CAST_VP(fptosi, VP_FPTOSI, FPToSI, 0)
+// llvm.vp.sitofp(x,mask,vlen)
+HELPER_REGISTER_CAST_VP(sitofp, VP_SITOFP, SIToFP, 1)
+
#undef HELPER_REGISTER_CAST_VP
///// } Type Casts
diff --git a/llvm/lib/IR/IntrinsicInst.cpp b/llvm/lib/IR/IntrinsicInst.cpp
index f217ccf34099b..bfcc732628686 100644
--- a/llvm/lib/IR/IntrinsicInst.cpp
+++ b/llvm/lib/IR/IntrinsicInst.cpp
@@ -493,6 +493,7 @@ Function *VPIntrinsic::getDeclarationForParams(Module *M, Intrinsic::ID VPID,
break;
}
case Intrinsic::vp_fptosi:
+ case Intrinsic::vp_sitofp:
VPFunc =
Intrinsic::getDeclaration(M, VPID, {ReturnType, Params[0]->getType()});
break;
diff --git a/llvm/test/Verifier/vp-intrinsics.ll b/llvm/test/Verifier/vp-intrinsics.ll
index cd43da0d182bf..ed55b6b880dd5 100644
--- a/llvm/test/Verifier/vp-intrinsics.ll
+++ b/llvm/test/Verifier/vp-intrinsics.ll
@@ -1,4 +1,4 @@
-; RUN: opt --verify %s
+; RUN: opt --verify --disable-output %s
define void @test_vp_int(<8 x i32> %i0, <8 x i32> %i1, <8 x i1> %m, i32 %n) {
%r0 = call <8 x i32> @llvm.vp.add.v8i32(<8 x i32> %i0, <8 x i32> %i1, <8 x i1> %m, i32 %n)
@@ -57,6 +57,12 @@ define void @test_vp_splice1(<vscale x 8 x i32> %i0, <vscale x 8 x i32> %i1, <vs
ret void
}
+define void @test_vp_int_fp_conversions(<8 x i32> %i0, <8 x float> %f0, <8 x i1> %mask, i32 %evl) {
+ %r0 = call <8 x float> @llvm.vp.sitofp.v8f32.v8i32(<8 x i32> %i0, <8 x i1> %mask, i32 %evl)
+ %r1 = call <8 x i32> @llvm.vp.fptosi.v8i32.v8f32(<8 x float> %f0, <8 x i1> %mask, i32 %evl)
+ ret void
+}
+
; integer arith
declare <8 x i32> @llvm.vp.add.v8i32(<8 x i32>, <8 x i32>, <8 x i1>, i32)
declare <8 x i32> @llvm.vp.sub.v8i32(<8 x i32>, <8 x i32>, <8 x i1>, i32)
@@ -92,6 +98,9 @@ declare float @llvm.vp.reduce.fmin.v8f32(float, <8 x float>, <8 x i1>, i32)
declare float @llvm.vp.reduce.fmax.v8f32(float, <8 x float>, <8 x i1>, i32)
declare float @llvm.vp.reduce.fadd.v8f32(float, <8 x float>, <8 x i1>, i32)
declare float @llvm.vp.reduce.fmul.v8f32(float, <8 x float>, <8 x i1>, i32)
+; casts
+declare <8 x float> @llvm.vp.sitofp.v8f32.v8i32(<8 x i32>, <8 x i1>, i32)
+declare <8 x i32> @llvm.vp.fptosi.v8i32.v8f32(<8 x float>, <8 x i1>, i32)
; shuffles
declare <8 x i32> @llvm.experimental.vp.splice.v8i32(<8 x i32>, <8 x i32>, i32, <8 x i1>, i32, i32)
declare <vscale x 8 x i32> @llvm.experimental.vp.splice.nxv8i32(<vscale x 8 x i32>, <vscale x 8 x i32>, i32, <vscale x 8 x i1>, i32, i32)
diff --git a/llvm/unittests/IR/VPIntrinsicTest.cpp b/llvm/unittests/IR/VPIntrinsicTest.cpp
index d00a293445cf0..6ebbf4430ae00 100644
--- a/llvm/unittests/IR/VPIntrinsicTest.cpp
+++ b/llvm/unittests/IR/VPIntrinsicTest.cpp
@@ -82,6 +82,8 @@ class VPIntrinsicTest : public testing::Test {
Str << " declare <8 x i32> @llvm.vp.fptosi.v8i32"
<< ".v8f32(<8 x float>, <8 x i1>, i32) ";
+ Str << " declare <8 x float> @llvm.vp.sitofp.v8f32"
+ << ".v8i32(<8 x i32>, <8 x i1>, i32) ";
return parseAssemblyString(Str.str(), Err, C);
}
More information about the llvm-commits
mailing list