[llvm] db85cd7 - [RISCV] Add FMV_W_X and FMV_H_X instrutions to hasAllNBitUsers

[Lian Wang via llvm-commits]

Author: Lian Wang
Date: 2022-03-01T08:13:59Z
New Revision: db85cd729a0e3bd26e1ff27a510ab04272ba0a27

URL: https://github.com/llvm/llvm-project/commit/db85cd729a0e3bd26e1ff27a510ab04272ba0a27
DIFF: https://github.com/llvm/llvm-project/commit/db85cd729a0e3bd26e1ff27a510ab04272ba0a27.diff

LOG: [RISCV] Add FMV_W_X and FMV_H_X instrutions to hasAllNBitUsers

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D120699

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
index 06e32eb2827aa..0bb6ac8b7b011 100644
--- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -1850,6 +1850,7 @@ bool RISCVDAGToDAGISel::hasAllNBitUsers(SDNode *Node, unsigned Bits) const {
     case RISCV::CTZW:
     case RISCV::CPOPW:
     case RISCV::SLLI_UW:
+    case RISCV::FMV_W_X:
     case RISCV::FCVT_H_W:
     case RISCV::FCVT_H_WU:
     case RISCV::FCVT_S_W:
@@ -1873,6 +1874,7 @@ bool RISCVDAGToDAGISel::hasAllNBitUsers(SDNode *Node, unsigned Bits) const {
         return false;
       break;
     case RISCV::SEXT_H:
+    case RISCV::FMV_H_X:
     case RISCV::ZEXT_H_RV32:
     case RISCV::ZEXT_H_RV64:
       if (Bits < 16)