[llvm] 5d91a8a - [RISCV] Add schedule class for Zbp extension and Zbr extension
Lian Wang via llvm-commits
llvm-commits at lists.llvm.org
Mon Feb 28 23:45:46 PST 2022
Author: lian wang
Date: 2022-03-01T07:35:59Z
New Revision: 5d91a8a707dbc55aaaedad70c76fd24931498367
URL: https://github.com/llvm/llvm-project/commit/5d91a8a707dbc55aaaedad70c76fd24931498367
DIFF: https://github.com/llvm/llvm-project/commit/5d91a8a707dbc55aaaedad70c76fd24931498367.diff
LOG: [RISCV] Add schedule class for Zbp extension and Zbr extension
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D120012
Added:
Modified:
llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
llvm/lib/Target/RISCV/RISCVSchedRocket.td
llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
llvm/lib/Target/RISCV/RISCVScheduleB.td
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
index c588dafcdb7d0..c6c564175cd2b 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
@@ -397,32 +397,48 @@ def BEXTI : RVBShift_ri<0b01001, 0b101, OPC_OP_IMM, "bexti">,
} // Predicates = [HasStdExtZbs]
let Predicates = [HasStdExtZbp] in {
-def GORC : ALU_rr<0b0010100, 0b101, "gorc">, Sched<[]>;
-def GREV : ALU_rr<0b0110100, 0b101, "grev">, Sched<[]>;
-
-def GREVI : RVBShift_ri<0b01101, 0b101, OPC_OP_IMM, "grevi">, Sched<[]>;
-def GORCI : RVBShift_ri<0b00101, 0b101, OPC_OP_IMM, "gorci">, Sched<[]>;
-
-def SHFL : ALU_rr<0b0000100, 0b001, "shfl">, Sched<[]>;
-def UNSHFL : ALU_rr<0b0000100, 0b101, "unshfl">, Sched<[]>;
-
-def SHFLI : RVBShfl_ri<0b0000100, 0b001, OPC_OP_IMM, "shfli">, Sched<[]>;
-def UNSHFLI : RVBShfl_ri<0b0000100, 0b101, OPC_OP_IMM, "unshfli">, Sched<[]>;
-
-def XPERM_H : ALU_rr<0b0010100, 0b110, "xperm.h">, Sched<[]>;
+def GORC : ALU_rr<0b0010100, 0b101, "gorc">,
+ Sched<[WriteORC, ReadORC, ReadORC]>;
+def GREV : ALU_rr<0b0110100, 0b101, "grev">,
+ Sched<[WriteREV, ReadREV, ReadREV]>;
+
+def GREVI : RVBShift_ri<0b01101, 0b101, OPC_OP_IMM, "grevi">,
+ Sched<[WriteREVImm, ReadREVImm]>;
+def GORCI : RVBShift_ri<0b00101, 0b101, OPC_OP_IMM, "gorci">,
+ Sched<[WriteORCImm, ReadORCImm]>;
+
+def SHFL : ALU_rr<0b0000100, 0b001, "shfl">,
+ Sched<[WriteSHFL, ReadSHFL, ReadSHFL]>;
+def UNSHFL : ALU_rr<0b0000100, 0b101, "unshfl">,
+ Sched<[WriteUNSHFL, ReadUNSHFL, ReadUNSHFL]>;
+
+def SHFLI : RVBShfl_ri<0b0000100, 0b001, OPC_OP_IMM, "shfli">,
+ Sched<[WriteSHFLImm, ReadSHFLImm]>;
+def UNSHFLI : RVBShfl_ri<0b0000100, 0b101, OPC_OP_IMM, "unshfli">,
+ Sched<[WriteUNSHFLImm, ReadUNSHFLImm]>;
+
+def XPERM_H : ALU_rr<0b0010100, 0b110, "xperm.h">,
+ Sched<[WriteXPERMH, ReadXPERMH, ReadXPERMH]>;
} // Predicates = [HasStdExtZbp]
let Predicates = [HasStdExtZbp, IsRV64] in {
-def GORCW : ALUW_rr<0b0010100, 0b101, "gorcw">, Sched<[]>;
-def GREVW : ALUW_rr<0b0110100, 0b101, "grevw">, Sched<[]>;
-
-def GORCIW : RVBShiftW_ri<0b0010100, 0b101, OPC_OP_IMM_32, "gorciw">, Sched<[]>;
-def GREVIW : RVBShiftW_ri<0b0110100, 0b101, OPC_OP_IMM_32, "greviw">, Sched<[]>;
-
-def SHFLW : ALUW_rr<0b0000100, 0b001, "shflw">, Sched<[]>;
-def UNSHFLW : ALUW_rr<0b0000100, 0b101, "unshflw">, Sched<[]>;
-
-def XPERM_W : ALU_rr<0b0010100, 0b000, "xperm.w">, Sched<[]>;
+def GORCW : ALUW_rr<0b0010100, 0b101, "gorcw">,
+ Sched<[WriteORC32, ReadORC32, ReadORC32]>;
+def GREVW : ALUW_rr<0b0110100, 0b101, "grevw">,
+ Sched<[WriteREV32, ReadREV32, ReadREV32]>;
+
+def GORCIW : RVBShiftW_ri<0b0010100, 0b101, OPC_OP_IMM_32, "gorciw">,
+ Sched<[WriteREVImm32, ReadREVImm32]>;
+def GREVIW : RVBShiftW_ri<0b0110100, 0b101, OPC_OP_IMM_32, "greviw">,
+ Sched<[WriteORCImm32, ReadORCImm32]>;
+
+def SHFLW : ALUW_rr<0b0000100, 0b001, "shflw">,
+ Sched<[WriteSHFL32, ReadSHFL32, ReadSHFL32]>;
+def UNSHFLW : ALUW_rr<0b0000100, 0b101, "unshflw">,
+ Sched<[WriteUNSHFL32, ReadUNSHFL32, ReadUNSHFL32]>;
+
+def XPERM_W : ALU_rr<0b0010100, 0b000, "xperm.w">,
+ Sched<[WriteXPERMW, ReadXPERMW, ReadXPERMW]>;
} // Predicates = [HasStdExtZbp, IsRV64]
// These instructions were named xperm.n and xperm.b in the last version of
@@ -486,26 +502,26 @@ def SEXT_H : RVBUnary<0b0110000, 0b00101, 0b001, OPC_OP_IMM, "sext.h">,
let Predicates = [HasStdExtZbr] in {
def CRC32_B : RVBUnary<0b0110000, 0b10000, 0b001, OPC_OP_IMM, "crc32.b">,
- Sched<[]>;
+ Sched<[WriteCRCB, ReadCRCB]>;
def CRC32_H : RVBUnary<0b0110000, 0b10001, 0b001, OPC_OP_IMM, "crc32.h">,
- Sched<[]>;
+ Sched<[WriteCRCH, ReadCRCH]>;
def CRC32_W : RVBUnary<0b0110000, 0b10010, 0b001, OPC_OP_IMM, "crc32.w">,
- Sched<[]>;
+ Sched<[WriteCRCW, ReadCRCW]>;
def CRC32C_B : RVBUnary<0b0110000, 0b11000, 0b001, OPC_OP_IMM, "crc32c.b">,
- Sched<[]>;
+ Sched<[WriteCRCCB, ReadCRCCB]>;
def CRC32C_H : RVBUnary<0b0110000, 0b11001, 0b001, OPC_OP_IMM, "crc32c.h">,
- Sched<[]>;
+ Sched<[WriteCRCCH, ReadCRCCH]>;
def CRC32C_W : RVBUnary<0b0110000, 0b11010, 0b001, OPC_OP_IMM, "crc32c.w">,
- Sched<[]>;
+ Sched<[WriteCRCCW, ReadCRCCW]>;
} // Predicates = [HasStdExtZbr]
let Predicates = [HasStdExtZbr, IsRV64] in {
def CRC32_D : RVBUnary<0b0110000, 0b10011, 0b001, OPC_OP_IMM, "crc32.d">,
- Sched<[]>;
+ Sched<[WriteCRCD, ReadCRCD]>;
def CRC32C_D : RVBUnary<0b0110000, 0b11011, 0b001, OPC_OP_IMM, "crc32c.d">,
- Sched<[]>;
+ Sched<[WriteCRCCD, ReadCRCCD]>;
} // Predicates = [HasStdExtZbr, IsRV64]
let Predicates = [HasStdExtZbc] in {
@@ -550,18 +566,23 @@ def BCOMPRESSW : ALUW_rr<0b0000100, 0b110, "bcompressw">,
} // Predicates = [HasStdExtZbe, IsRV64]
let Predicates = [HasStdExtZbpOrZbkb] in {
-def PACK : ALU_rr<0b0000100, 0b100, "pack">, Sched<[]>;
-def PACKH : ALU_rr<0b0000100, 0b111, "packh">, Sched<[]>;
+def PACK : ALU_rr<0b0000100, 0b100, "pack">,
+ Sched<[WritePACK, ReadPACK, ReadPACK]>;
+def PACKH : ALU_rr<0b0000100, 0b111, "packh">,
+ Sched<[WritePACK, ReadPACK, ReadPACK]>;
} // Predicates = [HasStdExtZbpOrZbkb]
let Predicates = [HasStdExtZbpOrZbkb, IsRV64] in
-def PACKW : ALUW_rr<0b0000100, 0b100, "packw">, Sched<[]>;
+def PACKW : ALUW_rr<0b0000100, 0b100, "packw">,
+ Sched<[WritePACK32, ReadPACK32, ReadPACK32]>;
let Predicates = [HasStdExtZbp] in
-def PACKU : ALU_rr<0b0100100, 0b100, "packu">, Sched<[]>;
+def PACKU : ALU_rr<0b0100100, 0b100, "packu">,
+ Sched<[WritePACKU, ReadPACKU, ReadPACKU]>;
let Predicates = [HasStdExtZbp, IsRV64] in
-def PACKUW : ALUW_rr<0b0100100, 0b100, "packuw">, Sched<[]>;
+def PACKUW : ALUW_rr<0b0100100, 0b100, "packuw">,
+ Sched<[WritePACKU32, ReadPACKU32, ReadPACKU32]>;
let Predicates = [HasStdExtZbm, IsRV64] in {
def BMATFLIP : RVBUnary<0b0110000, 0b00011, 0b001, OPC_OP_IMM, "bmatflip">,
diff --git a/llvm/lib/Target/RISCV/RISCVSchedRocket.td b/llvm/lib/Target/RISCV/RISCVSchedRocket.td
index ae36c40bc7ac2..5a3c8deb7943b 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedRocket.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedRocket.td
@@ -245,6 +245,8 @@ defm : UnsupportedSchedZbs;
defm : UnsupportedSchedZbe;
defm : UnsupportedSchedZbf;
defm : UnsupportedSchedZbm;
+defm : UnsupportedSchedZbp;
+defm : UnsupportedSchedZbr;
defm : UnsupportedSchedZbt;
defm : UnsupportedSchedZfh;
}
diff --git a/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td b/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
index ccb62091443bc..cfbd9722d7bc6 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
@@ -232,6 +232,8 @@ defm : UnsupportedSchedZbs;
defm : UnsupportedSchedZbe;
defm : UnsupportedSchedZbf;
defm : UnsupportedSchedZbm;
+defm : UnsupportedSchedZbp;
+defm : UnsupportedSchedZbr;
defm : UnsupportedSchedZbt;
defm : UnsupportedSchedZfh;
}
diff --git a/llvm/lib/Target/RISCV/RISCVScheduleB.td b/llvm/lib/Target/RISCV/RISCVScheduleB.td
index 097dce5e4f47a..4bfe7b316eeb1 100644
--- a/llvm/lib/Target/RISCV/RISCVScheduleB.td
+++ b/llvm/lib/Target/RISCV/RISCVScheduleB.td
@@ -46,6 +46,38 @@ def WriteBFP32 : SchedWrite; // BFPW
// Zbm extension
def WriteBMatrix : SchedWrite; // bmator/bmatxor/bmatflip
+// Zbp extension
+def WriteORC : SchedWrite; // gorc
+def WriteREV : SchedWrite; // grev
+def WriteORC32 : SchedWrite; // gorcw
+def WriteREV32 : SchedWrite; // grevw
+def WriteREVImm : SchedWrite; // grevi
+def WriteORCImm : SchedWrite; // gorci
+def WriteREVImm32 : SchedWrite; // greviw
+def WriteORCImm32 : SchedWrite; // gorciw
+def WriteSHFL : SchedWrite; // shfl
+def WriteUNSHFL : SchedWrite; // unshfl
+def WriteSHFL32 : SchedWrite; // shflw
+def WriteUNSHFL32 : SchedWrite; // unshflw
+def WriteSHFLImm : SchedWrite; // shfli
+def WriteUNSHFLImm : SchedWrite; // unshfli
+def WriteXPERMH : SchedWrite; // xperm.h
+def WriteXPERMW : SchedWrite; // xperm.w
+def WritePACK : SchedWrite; // pack/packh
+def WritePACK32 : SchedWrite; // packw
+def WritePACKU : SchedWrite; // packu
+def WritePACKU32 : SchedWrite; // packuw
+
+// Zbr extension
+def WriteCRCB : SchedWrite; // crc32.b
+def WriteCRCH : SchedWrite; // crc32.h
+def WriteCRCW : SchedWrite; // crc32.w
+def WriteCRCD : SchedWrite; // crc32.d
+def WriteCRCCB : SchedWrite; // crc32c.b
+def WriteCRCCH : SchedWrite; // crc32c.h
+def WriteCRCCW : SchedWrite; // crc32c.w
+def WriteCRCCD : SchedWrite; // crc32c.d
+
// Zbt extension
def WriteCMix : SchedWrite; // cmix
def WriteCMov : SchedWrite; // cmov
@@ -94,6 +126,38 @@ def ReadBFP32 : SchedRead; // BFPW
// Zbm extension
def ReadBMatrix : SchedRead; // bmator/bmatxor/bmatflip
+// Zbp extension
+def ReadORC : SchedRead; // gorc
+def ReadREV : SchedRead; // grev
+def ReadORC32 : SchedRead; // gorcw
+def ReadREV32 : SchedRead; // grevw
+def ReadREVImm : SchedRead; // grevi
+def ReadORCImm : SchedRead; // groci
+def ReadREVImm32 : SchedRead; // greviw
+def ReadORCImm32 : SchedRead; // gorciw
+def ReadSHFL : SchedRead; // shfl
+def ReadUNSHFL : SchedRead; // unshfl
+def ReadSHFL32 : SchedRead; // shflw
+def ReadUNSHFL32 : SchedRead; // unshflw
+def ReadSHFLImm : SchedRead; // shfli
+def ReadUNSHFLImm : SchedRead; // unshfli
+def ReadXPERMH : SchedRead; // xperm.h
+def ReadXPERMW : SchedRead; // xperm.w
+def ReadPACK : SchedRead; // pack/packh
+def ReadPACK32 : SchedRead; // packw
+def ReadPACKU : SchedRead; // packu
+def ReadPACKU32 : SchedRead; // packuw
+
+// Zbr extension
+def ReadCRCB : SchedRead; // crc32.b
+def ReadCRCH : SchedRead; // crc32.h
+def ReadCRCW : SchedRead; // crc32.w
+def ReadCRCD : SchedRead; // crc32.d
+def ReadCRCCB : SchedRead; // crc32c.b
+def ReadCRCCH : SchedRead; // crc32c.h
+def ReadCRCCW : SchedRead; // crc32c.w
+def ReadCRCCD : SchedRead; // crc32c.d
+
// Zbt extension
def ReadCMix : SchedRead; // cmix
def ReadCMov : SchedRead; // cmov
@@ -194,6 +258,74 @@ def : ReadAdvance<ReadBMatrix, 0>;
}
}
+multiclass UnsupportedSchedZbp {
+let Unsupported = true in {
+def : WriteRes<WriteORC, []>;
+def : WriteRes<WriteREV, []>;
+def : WriteRes<WriteORC32, []>;
+def : WriteRes<WriteREV32, []>;
+def : WriteRes<WriteREVImm, []>;
+def : WriteRes<WriteORCImm, []>;
+def : WriteRes<WriteREVImm32, []>;
+def : WriteRes<WriteORCImm32, []>;
+def : WriteRes<WriteSHFL, []>;
+def : WriteRes<WriteUNSHFL, []>;
+def : WriteRes<WriteSHFL32, []>;
+def : WriteRes<WriteUNSHFL32, []>;
+def : WriteRes<WriteSHFLImm, []>;
+def : WriteRes<WriteUNSHFLImm, []>;
+def : WriteRes<WriteXPERMH, []>;
+def : WriteRes<WriteXPERMW, []>;
+def : WriteRes<WritePACK, []>;
+def : WriteRes<WritePACK32, []>;
+def : WriteRes<WritePACKU, []>;
+def : WriteRes<WritePACKU32, []>;
+
+def : ReadAdvance<ReadORC, 0>;
+def : ReadAdvance<ReadREV, 0>;
+def : ReadAdvance<ReadORC32, 0>;
+def : ReadAdvance<ReadREV32, 0>;
+def : ReadAdvance<ReadREVImm, 0>;
+def : ReadAdvance<ReadORCImm, 0>;
+def : ReadAdvance<ReadREVImm32, 0>;
+def : ReadAdvance<ReadORCImm32, 0>;
+def : ReadAdvance<ReadSHFL, 0>;
+def : ReadAdvance<ReadUNSHFL, 0>;
+def : ReadAdvance<ReadSHFL32, 0>;
+def : ReadAdvance<ReadUNSHFL32, 0>;
+def : ReadAdvance<ReadSHFLImm, 0>;
+def : ReadAdvance<ReadUNSHFLImm, 0>;
+def : ReadAdvance<ReadXPERMH, 0>;
+def : ReadAdvance<ReadXPERMW, 0>;
+def : ReadAdvance<ReadPACK, 0>;
+def : ReadAdvance<ReadPACK32, 0>;
+def : ReadAdvance<ReadPACKU, 0>;
+def : ReadAdvance<ReadPACKU32, 0>;
+}
+}
+
+multiclass UnsupportedSchedZbr {
+let Unsupported = true in {
+def : WriteRes<WriteCRCB, []>;
+def : WriteRes<WriteCRCH, []>;
+def : WriteRes<WriteCRCW, []>;
+def : WriteRes<WriteCRCD, []>;
+def : WriteRes<WriteCRCCB, []>;
+def : WriteRes<WriteCRCCH, []>;
+def : WriteRes<WriteCRCCW, []>;
+def : WriteRes<WriteCRCCD, []>;
+
+def : ReadAdvance<ReadCRCB, 0>;
+def : ReadAdvance<ReadCRCH, 0>;
+def : ReadAdvance<ReadCRCW, 0>;
+def : ReadAdvance<ReadCRCD, 0>;
+def : ReadAdvance<ReadCRCCB, 0>;
+def : ReadAdvance<ReadCRCCH, 0>;
+def : ReadAdvance<ReadCRCCW, 0>;
+def : ReadAdvance<ReadCRCCD, 0>;
+}
+}
+
multiclass UnsupportedSchedZbt {
let Unsupported = true in {
def : WriteRes<WriteCMix, []>;
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