[PATCH] D120462: [AArch64InstrInfo.td] - Lowering fix for cttz intrinsic

[Craig Topper via Phabricator via llvm-commits]

craig.topper added a comment.

The correct fix is to generate (select (icmp eq X, 0), 0, cttz X) from AgressiveInstCombine. Then, in performSelectCombine in AArch64ISeLowring.cpp, detect the select pattern and place it with an ISD::AND.

The cttz intrinsic by itself must be able to return 32. You can't put an AND after any cttz. You have to look for a select that uses 0 when cttz returns 32.


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  https://reviews.llvm.org/D120462/new/

https://reviews.llvm.org/D120462