[llvm] 35de512 - [x86] add tests for setcc eq/ne 0/-1 of rotate; NFC
Sanjay Patel via llvm-commits
llvm-commits at lists.llvm.org
Sun Feb 27 08:35:59 PST 2022
Author: Sanjay Patel
Date: 2022-02-27T11:29:26-05:00
New Revision: 35de5125cc2b61088efa7d3358255955a29beb73
URL: https://github.com/llvm/llvm-project/commit/35de5125cc2b61088efa7d3358255955a29beb73
DIFF: https://github.com/llvm/llvm-project/commit/35de5125cc2b61088efa7d3358255955a29beb73.diff
LOG: [x86] add tests for setcc eq/ne 0/-1 of rotate; NFC
The tests are adapted from a similar file for instcombine:
fd807601a78
Added:
llvm/test/CodeGen/X86/setcc-fsh.ll
Modified:
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/X86/setcc-fsh.ll b/llvm/test/CodeGen/X86/setcc-fsh.ll
new file mode 100644
index 0000000000000..90ce627295d40
--- /dev/null
+++ b/llvm/test/CodeGen/X86/setcc-fsh.ll
@@ -0,0 +1,231 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=x86_64-- < %s | FileCheck %s
+
+declare i8 @llvm.fshl.i8(i8, i8, i8)
+declare i32 @llvm.fshl.i32(i32, i32, i32)
+declare i16 @llvm.fshr.i16(i16, i16, i16)
+declare i64 @llvm.fshr.i64(i64, i64, i64)
+declare <4 x i32> @llvm.fshl.v4i32(<4 x i32>, <4 x i32>, <4 x i32>)
+declare void @use16(i16)
+declare void @use32(i32)
+
+define i1 @rotl_eq_0(i8 %x, i8 %y) nounwind {
+; CHECK-LABEL: rotl_eq_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: movl %esi, %ecx
+; CHECK-NEXT: # kill: def $cl killed $cl killed $ecx
+; CHECK-NEXT: rolb %cl, %dil
+; CHECK-NEXT: testb %dil, %dil
+; CHECK-NEXT: sete %al
+; CHECK-NEXT: retq
+ %rot = tail call i8 @llvm.fshl.i8(i8 %x, i8 %x, i8 %y)
+ %r = icmp eq i8 %rot, 0
+ ret i1 %r
+}
+
+; Extra use is ok.
+
+define i1 @rotl_ne_0(i32 %x, i32 %y) nounwind {
+; CHECK-LABEL: rotl_ne_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pushq %rbx
+; CHECK-NEXT: movl %esi, %ecx
+; CHECK-NEXT: movl %edi, %ebx
+; CHECK-NEXT: # kill: def $cl killed $cl killed $ecx
+; CHECK-NEXT: roll %cl, %ebx
+; CHECK-NEXT: movl %ebx, %edi
+; CHECK-NEXT: callq use32 at PLT
+; CHECK-NEXT: testl %ebx, %ebx
+; CHECK-NEXT: setne %al
+; CHECK-NEXT: popq %rbx
+; CHECK-NEXT: retq
+ %rot = tail call i32 @llvm.fshl.i32(i32 %x, i32 %x, i32 %y)
+ call void @use32(i32 %rot)
+ %r = icmp ne i32 %rot, 0
+ ret i1 %r
+}
+
+define i1 @rotl_eq_n1(i8 %x, i8 %y) nounwind {
+; CHECK-LABEL: rotl_eq_n1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: movl %esi, %ecx
+; CHECK-NEXT: # kill: def $cl killed $cl killed $ecx
+; CHECK-NEXT: rolb %cl, %dil
+; CHECK-NEXT: cmpb $-1, %dil
+; CHECK-NEXT: sete %al
+; CHECK-NEXT: retq
+ %rot = tail call i8 @llvm.fshl.i8(i8 %x, i8 %x, i8 %y)
+ %r = icmp eq i8 %rot, -1
+ ret i1 %r
+}
+
+; Vectors work too.
+
+define <4 x i1> @rotl_ne_n1(<4 x i32> %x, <4 x i32> %y) nounwind {
+; CHECK-LABEL: rotl_ne_n1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; CHECK-NEXT: pslld $23, %xmm1
+; CHECK-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; CHECK-NEXT: cvttps2dq %xmm1, %xmm1
+; CHECK-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
+; CHECK-NEXT: pmuludq %xmm1, %xmm0
+; CHECK-NEXT: pshufd {{.*#+}} xmm3 = xmm0[1,3,2,3]
+; CHECK-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
+; CHECK-NEXT: pmuludq %xmm2, %xmm1
+; CHECK-NEXT: pshufd {{.*#+}} xmm2 = xmm1[1,3,2,3]
+; CHECK-NEXT: punpckldq {{.*#+}} xmm3 = xmm3[0],xmm2[0],xmm3[1],xmm2[1]
+; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
+; CHECK-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
+; CHECK-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
+; CHECK-NEXT: por %xmm3, %xmm0
+; CHECK-NEXT: pcmpeqd %xmm1, %xmm1
+; CHECK-NEXT: pcmpeqd %xmm1, %xmm0
+; CHECK-NEXT: pxor %xmm1, %xmm0
+; CHECK-NEXT: retq
+ %rot = tail call <4 x i32> @llvm.fshl.v4i32(<4 x i32>%x, <4 x i32> %x, <4 x i32> %y)
+ %r = icmp ne <4 x i32> %rot, <i32 -1, i32 -1, i32 -1, i32 -1>
+ ret <4 x i1> %r
+}
+
+define <4 x i1> @rotl_ne_n1_undef(<4 x i32> %x, <4 x i32> %y) nounwind {
+; CHECK-LABEL: rotl_ne_n1_undef:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; CHECK-NEXT: pslld $23, %xmm1
+; CHECK-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; CHECK-NEXT: cvttps2dq %xmm1, %xmm1
+; CHECK-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
+; CHECK-NEXT: pmuludq %xmm1, %xmm0
+; CHECK-NEXT: pshufd {{.*#+}} xmm3 = xmm0[1,3,2,3]
+; CHECK-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
+; CHECK-NEXT: pmuludq %xmm2, %xmm1
+; CHECK-NEXT: pshufd {{.*#+}} xmm2 = xmm1[1,3,2,3]
+; CHECK-NEXT: punpckldq {{.*#+}} xmm3 = xmm3[0],xmm2[0],xmm3[1],xmm2[1]
+; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
+; CHECK-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
+; CHECK-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
+; CHECK-NEXT: por %xmm3, %xmm0
+; CHECK-NEXT: pcmpeqd %xmm1, %xmm1
+; CHECK-NEXT: pcmpeqd %xmm1, %xmm0
+; CHECK-NEXT: pxor %xmm1, %xmm0
+; CHECK-NEXT: retq
+ %rot = tail call <4 x i32> @llvm.fshl.v4i32(<4 x i32>%x, <4 x i32> %x, <4 x i32> %y)
+ %r = icmp ne <4 x i32> %rot, <i32 -1, i32 undef, i32 -1, i32 -1>
+ ret <4 x i1> %r
+}
+
+define i1 @rotr_eq_0(i16 %x, i16 %y) nounwind {
+; CHECK-LABEL: rotr_eq_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pushq %rbx
+; CHECK-NEXT: movl %esi, %ecx
+; CHECK-NEXT: movl %edi, %ebx
+; CHECK-NEXT: # kill: def $cl killed $cl killed $ecx
+; CHECK-NEXT: rorw %cl, %bx
+; CHECK-NEXT: movl %ebx, %edi
+; CHECK-NEXT: callq use16 at PLT
+; CHECK-NEXT: testw %bx, %bx
+; CHECK-NEXT: sete %al
+; CHECK-NEXT: popq %rbx
+; CHECK-NEXT: retq
+ %rot = tail call i16 @llvm.fshr.i16(i16 %x, i16 %x, i16 %y)
+ call void @use16(i16 %rot)
+ %r = icmp eq i16 %rot, 0
+ ret i1 %r
+}
+
+define i1 @rotr_ne_0(i64 %x, i64 %y) nounwind {
+; CHECK-LABEL: rotr_ne_0:
+; CHECK: # %bb.0:
+; CHECK-NEXT: movq %rsi, %rcx
+; CHECK-NEXT: # kill: def $cl killed $cl killed $rcx
+; CHECK-NEXT: rorq %cl, %rdi
+; CHECK-NEXT: testq %rdi, %rdi
+; CHECK-NEXT: setne %al
+; CHECK-NEXT: retq
+ %rot = tail call i64 @llvm.fshr.i64(i64 %x, i64 %x, i64 %y)
+ %r = icmp ne i64 %rot, 0
+ ret i1 %r
+}
+
+define i1 @rotr_eq_n1(i64 %x, i64 %y) nounwind {
+; CHECK-LABEL: rotr_eq_n1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: movq %rsi, %rcx
+; CHECK-NEXT: # kill: def $cl killed $cl killed $rcx
+; CHECK-NEXT: rorq %cl, %rdi
+; CHECK-NEXT: cmpq $-1, %rdi
+; CHECK-NEXT: sete %al
+; CHECK-NEXT: retq
+ %rot = tail call i64 @llvm.fshr.i64(i64 %x, i64 %x, i64 %y)
+ %r = icmp eq i64 %rot, -1
+ ret i1 %r
+}
+
+define i1 @rotr_ne_n1(i16 %x, i16 %y) nounwind {
+; CHECK-LABEL: rotr_ne_n1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: movl %esi, %ecx
+; CHECK-NEXT: # kill: def $cl killed $cl killed $ecx
+; CHECK-NEXT: rorw %cl, %di
+; CHECK-NEXT: cmpw $-1, %di
+; CHECK-NEXT: setne %al
+; CHECK-NEXT: retq
+ %rot = tail call i16 @llvm.fshr.i16(i16 %x, i16 %x, i16 %y)
+ %r = icmp ne i16 %rot, -1
+ ret i1 %r
+}
+
+; negative test - wrong constant value
+
+define i1 @rotr_ne_1(i64 %x, i64 %y) nounwind {
+; CHECK-LABEL: rotr_ne_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: movq %rsi, %rcx
+; CHECK-NEXT: # kill: def $cl killed $cl killed $rcx
+; CHECK-NEXT: rorq %cl, %rdi
+; CHECK-NEXT: cmpq $1, %rdi
+; CHECK-NEXT: setne %al
+; CHECK-NEXT: retq
+ %rot = tail call i64 @llvm.fshr.i64(i64 %x, i64 %x, i64 %y)
+ %r = icmp ne i64 %rot, 1
+ ret i1 %r
+}
+
+; negative test - wrong predicate
+
+define i1 @rotr_sgt_n1(i16 %x, i16 %y) nounwind {
+; CHECK-LABEL: rotr_sgt_n1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: movl %esi, %ecx
+; CHECK-NEXT: # kill: def $cl killed $cl killed $ecx
+; CHECK-NEXT: rorw %cl, %di
+; CHECK-NEXT: testw %di, %di
+; CHECK-NEXT: setns %al
+; CHECK-NEXT: retq
+ %rot = tail call i16 @llvm.fshr.i16(i16 %x, i16 %x, i16 %y)
+ %r = icmp sgt i16 %rot, -1
+ ret i1 %r
+}
+
+; negative test - must be a rotate, not general funnel shift
+
+define i1 @fshl_sgt_n1(i8 %x, i8 %y, i8 %z) nounwind {
+; CHECK-LABEL: fshl_sgt_n1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: movl %edx, %ecx
+; CHECK-NEXT: shll $8, %edi
+; CHECK-NEXT: movzbl %sil, %eax
+; CHECK-NEXT: orl %edi, %eax
+; CHECK-NEXT: andb $7, %cl
+; CHECK-NEXT: # kill: def $cl killed $cl killed $ecx
+; CHECK-NEXT: shll %cl, %eax
+; CHECK-NEXT: shrl $8, %eax
+; CHECK-NEXT: cmpb $-1, %al
+; CHECK-NEXT: sete %al
+; CHECK-NEXT: retq
+ %fsh = tail call i8 @llvm.fshl.i8(i8 %x, i8 %y, i8 %z)
+ %r = icmp eq i8 %fsh, -1
+ ret i1 %r
+}
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