[PATCH] D120603: [AArch64][SME] Add rdsvl instruction

[Hsiangkai Wang via Phabricator via llvm-commits]

HsiangKai created this revision.
HsiangKai added reviewers: c-rhodes, rsandifo-arm, paulwalker-arm, david-arm.
Herald added subscribers: hiraditya, kristof.beyls.
HsiangKai requested review of this revision.
Herald added a project: LLVM.
Herald added a subscriber: llvm-commits.

This patch adds support for the following SME instruction:

- RDSVL

The reference can be found here:
https://developer.arm.com/documentation/ddi0602/2021-12


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D120603

Files:
  llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td
  llvm/lib/Target/AArch64/SVEInstrFormats.td
  llvm/test/MC/AArch64/SME/rdsvl-diagnostics.s
  llvm/test/MC/AArch64/SME/rdsvl.s


Index: llvm/test/MC/AArch64/SME/rdsvl.s
===================================================================
--- /dev/null
+++ llvm/test/MC/AArch64/SME/rdsvl.s
@@ -0,0 +1,32 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme < %s \
+// RUN:        | llvm-objdump -d --mattr=+sme - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+rdsvl    x0, #0
+// CHECK-INST: rdsvl    x0, #0
+// CHECK-ENCODING: [0x00,0x58,0xbf,0x04]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 00 58 bf 04 <unknown>
+
+rdsvl    xzr, #-1
+// CHECK-INST: rdsvl    xzr, #-1
+// CHECK-ENCODING: [0xff,0x5f,0xbf,0x04]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: ff 5f bf 04 <unknown>
+
+rdsvl    x23, #31
+// CHECK-INST: rdsvl    x23, #31
+// CHECK-ENCODING: [0xf7,0x5b,0xbf,0x04]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: f7 5b bf 04 <unknown>
+
+rdsvl    x21, #-32
+// CHECK-INST: rdsvl    x21, #-32
+// CHECK-ENCODING: [0x15,0x5c,0xbf,0x04]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 15 5c bf 04 <unknown>
Index: llvm/test/MC/AArch64/SME/rdsvl-diagnostics.s
===================================================================
--- /dev/null
+++ llvm/test/MC/AArch64/SME/rdsvl-diagnostics.s
@@ -0,0 +1,13 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme  2>&1 < %s| FileCheck %s
+
+// Immediate out of upper bound [-32, 31].
+rdsvl x9, #32
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-32, 31].
+// CHECK-NEXT: rdsvl x9, #32
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// rdsvl requires an immediate, not a register.
+rdsvl x9, x10
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-32, 31].
+// CHECK-NEXT: rdsvl x9, x10
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
Index: llvm/lib/Target/AArch64/SVEInstrFormats.td
===================================================================
--- llvm/lib/Target/AArch64/SVEInstrFormats.td
+++ llvm/lib/Target/AArch64/SVEInstrFormats.td
@@ -2522,7 +2522,7 @@
   let Inst{4-0}   = Rd;
 }
 
-class sve_int_read_vl_a<bit op, bits<5> opc2, string asm>
+class sve_int_read_vl_a<bit op, bits<5> opc2, string asm, bit streaming_sve = 0b0>
 : I<(outs GPR64:$Rd), (ins simm6_32b:$imm6),
   asm, "\t$Rd, $imm6",
   "",
@@ -2533,7 +2533,8 @@
   let Inst{22}    = op;
   let Inst{21}    = 0b1;
   let Inst{20-16} = opc2{4-0};
-  let Inst{15-11} = 0b01010;
+  let Inst{15-12} = 0b0101;
+  let Inst{11}    = streaming_sve;
   let Inst{10-5}  = imm6;
   let Inst{4-0}   = Rd;
 }
Index: llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td
===================================================================
--- llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td
+++ llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td
@@ -15,6 +15,7 @@
 //===----------------------------------------------------------------------===//
 
 let Predicates = [HasSME] in {
+def RDSVLI_XI  : sve_int_read_vl_a<0b0, 0b11111, "rdsvl", /*streaming_sve=*/0b1>;
 def ADDSPL_XXI : sve_int_arith_vl<0b1, "addspl", /*streaming_sve=*/0b1>;
 def ADDSVL_XXI : sve_int_arith_vl<0b0, "addsvl", /*streaming_sve=*/0b1>;
 


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