[PATCH] D120516: [SDAG] fold bitwise logic with shifted operands

[Sanjay Patel via Phabricator via llvm-commits]

spatel marked an inline comment as done.
spatel added inline comments.


================
Comment at: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:6705
+                                 SelectionDAG &DAG) {
+  if (!LogicOp.hasOneUse() || !ShiftOp.hasOneUse())
+    return SDValue();
----------------
RKSimon wrote:
> Maybe add an assert that the logic opcode is ISD::OR until we have actual uses for AND/XOR?
Sure - an assert will be good even after the planned follow-ups for the other bitwise logic. I'll put a TODO comment on top of that.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D120516/new/

https://reviews.llvm.org/D120516