[PATCH] D120516: [SDAG] fold bitwise logic with shifted operands

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added a comment.

In D120516#3345807 <https://reviews.llvm.org/D120516#3345807>, @craig.topper wrote:

> In D120516#3345709 <https://reviews.llvm.org/D120516#3345709>, @RKSimon wrote:
>
>> LGTM with one (optional) minor
>
> Am I missing it or did the optional minor not make it to phabricator?

It didn't make it - if you create/delete/undo comments phab sometimes swallows them :-(



================
Comment at: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:6705
+                                 SelectionDAG &DAG) {
+  if (!LogicOp.hasOneUse() || !ShiftOp.hasOneUse())
+    return SDValue();
----------------
Maybe add an assert that the logic opcode is ISD::OR until we have actual uses for AND/XOR?


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