[PATCH] D120428: [AArch64] Optimize safe integer division

Thu Feb 24 09:55:43 PST 2022

dmgreen added inline comments.

================
Comment at: llvm/lib/Target/AArch64/AArch64MIPeepholeOpt.cpp:325
+  auto *RhsDef = MRI->getUniqueVRegDef(RhsReg);
+  auto *FlagsDef = MRI->getUniqueVRegDef(FlagsReg);
+
----------------
Kmeakin wrote:
> dmgreen wrote:
> > Isn't FlagsReg AArch64::NZCV? How does that work with getUniqueVRegDef?
> `FlagsReg` is indeed `NZCV`, but it is updated by flag-setting instructions (eg `SUBS`), so `getUniqueVRegDef` will return the instruction that sets the flags. 
Sure, but it's a physical register, not a vreg. Which was why I was surprised it worked. I was surprised it didn't assert that the register was virtual.

Does it work if there are multiple instructions defining nzcv in the function?

================
Comment at: llvm/test/CodeGen/AArch64/checked-int-div.ll:2
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=aarch64-gnu-linux -mcpu=neoversen1 -o - | FileCheck %s
+
----------------
Kmeakin wrote:
> dmgreen wrote:
> > neoversen1 isn't a valid cpu. Does this not work in other cases due to the costs of div being too high to ifcvt?
> `llc -mcpu=help --mtriple=aarch64--` lists `neoversen1` as an option. Any out of order CPU should do (the cost model defaults to in order, which results in div not being ifcvted)
I think it would be "neoverse-n1", https://godbolt.org/z/5KEGbcfdo.

Repository:
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CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D120428/new/

https://reviews.llvm.org/D120428