[PATCH] D120302: [RISCV] DAG Combine vcpop and vfirst with VL=0 to li imm

[Chenbing.Zheng via Phabricator via llvm-commits]

Chenbing.Zheng updated this revision to Diff 410508.
Chenbing.Zheng retitled this revision from "[RISCV] Expend vcpop and vfirst with VL=0 to li imm" to "[RISCV] DAG Combine vcpop and vfirst with VL=0 to li imm".
Chenbing.Zheng added a comment.

move to DAGCombine


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D120302/new/

https://reviews.llvm.org/D120302

Files:
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/test/CodeGen/RISCV/rvv/vcpop.ll
  llvm/test/CodeGen/RISCV/rvv/vfirst.ll


Index: llvm/test/CodeGen/RISCV/rvv/vfirst.ll
===================================================================
--- llvm/test/CodeGen/RISCV/rvv/vfirst.ll
+++ llvm/test/CodeGen/RISCV/rvv/vfirst.ll
@@ -24,8 +24,7 @@
 define iXLen @intrinsic_vfirst_m_nxv1i1_zero(<vscale x 1 x i1> %0) nounwind {
 ; CHECK-LABEL: intrinsic_vfirst_m_nxv1i1_zero:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetivli zero, 0, e8, mf8, ta, mu
-; CHECK-NEXT:    vfirst.m a0, v0
+; CHECK-NEXT:    li a0, -1
 ; CHECK-NEXT:    ret
 entry:
   %a = call iXLen @llvm.riscv.vfirst.iXLen.nxv1i1(
@@ -60,10 +59,7 @@
 define iXLen @intrinsic_vfirst_mask_m_nxv1i1_zero(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1) nounwind {
 ; CHECK-LABEL: intrinsic_vfirst_mask_m_nxv1i1_zero:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v9, v0
-; CHECK-NEXT:    vsetivli zero, 0, e8, mf8, ta, mu
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vfirst.m a0, v9, v0.t
+; CHECK-NEXT:    li a0, -1
 ; CHECK-NEXT:    ret
 entry:
   %a = call iXLen @llvm.riscv.vfirst.mask.iXLen.nxv1i1(
Index: llvm/test/CodeGen/RISCV/rvv/vcpop.ll
===================================================================
--- llvm/test/CodeGen/RISCV/rvv/vcpop.ll
+++ llvm/test/CodeGen/RISCV/rvv/vcpop.ll
@@ -24,8 +24,7 @@
 define iXLen @intrinsic_vcpop_m_nxv1i1_zero(<vscale x 1 x i1> %0) nounwind {
 ; CHECK-LABEL: intrinsic_vcpop_m_nxv1i1_zero:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetivli zero, 0, e8, mf8, ta, mu
-; CHECK-NEXT:    vcpop.m a0, v0
+; CHECK-NEXT:    li a0, 0
 ; CHECK-NEXT:    ret
 entry:
   %a = call iXLen @llvm.riscv.vcpop.iXLen.nxv1i1(
@@ -60,10 +59,7 @@
 define iXLen @intrinsic_vcpop_mask_m_nxv1i1_zero(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1) nounwind {
 ; CHECK-LABEL: intrinsic_vcpop_mask_m_nxv1i1_zero:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmv1r.v v9, v0
-; CHECK-NEXT:    vsetivli zero, 0, e8, mf8, ta, mu
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vcpop.m a0, v9, v0.t
+; CHECK-NEXT:    li a0, 0
 ; CHECK-NEXT:    ret
 entry:
   %a = call iXLen @llvm.riscv.vcpop.mask.iXLen.nxv1i1(
Index: llvm/lib/Target/RISCV/RISCVISelLowering.cpp
===================================================================
--- llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -1071,6 +1071,7 @@
   setTargetDAGCombine(ISD::ROTL);
   setTargetDAGCombine(ISD::ROTR);
   setTargetDAGCombine(ISD::ANY_EXTEND);
+  setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
   if (Subtarget.hasStdExtF()) {
     setTargetDAGCombine(ISD::ZERO_EXTEND);
     setTargetDAGCombine(ISD::FP_TO_SINT);
@@ -8490,6 +8491,35 @@
 
     break;
   }
+  case ISD::INTRINSIC_WO_CHAIN: {
+    unsigned IntNo = N->getConstantOperandVal(0);
+    switch (IntNo) {
+      // By default we do not combine any intrinsic.
+    default:
+      return SDValue();
+    case Intrinsic::riscv_vcpop:
+    case Intrinsic::riscv_vcpop_mask:
+    case Intrinsic::riscv_vfirst:
+    case Intrinsic::riscv_vfirst_mask: {
+      SDValue VL = N->getOperand(2);
+      if (IntNo == Intrinsic::riscv_vcpop_mask ||
+          IntNo == Intrinsic::riscv_vfirst_mask)
+        VL = N->getOperand(3);
+      auto *C = dyn_cast<ConstantSDNode>(VL);
+      if (!C || !C->isZero())
+        return SDValue();
+      // If VL is 0, vcpop -> li 0, vfirst -> li -1.
+      SDLoc DL(N);
+      EVT VT = VL.getValueType();
+      SDValue Zero = DAG.getConstant(0, DL, VT);
+      SDValue Imm = Zero;
+      if (IntNo == Intrinsic::riscv_vfirst ||
+          IntNo == Intrinsic::riscv_vfirst_mask)
+        Imm = DAG.getConstant(-1, DL, VT);
+      return DAG.getNode(ISD::ADD, DL, VT, Zero, Imm);
+    }
+    }
+  }
   }
 
   return SDValue();


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