[PATCH] D119973: RegAllocGreedy: Fix last chance recolor assert in impossible case
Mikael Holmén via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Tue Feb 22 00:52:01 PST 2022
uabelho added a comment.
In D119973#3335940 <https://reviews.llvm.org/D119973#3335940>, @arsenm wrote:
> In D119973#3335832 <https://reviews.llvm.org/D119973#3335832>, @arsenm wrote:
>
>> In D119973#3335710 <https://reviews.llvm.org/D119973#3335710>, @arsenm wrote:
>>
>>> In D119973#3335190 <https://reviews.llvm.org/D119973#3335190>, @uabelho wrote:
>>>
>>>> In a failing example we have a bundle like this with heavy register use:
>>>>
>>>> BUNDLE [...] {
>>>> inst1 %234:Aquad
>>>> inst1 %235:Aquad
>>>> undef %235.sub0:Aquad = inst2 %211:A, %237.sub0:Aquad
>>>> undef %235.sub1:Aquad = inst2 %226:A, %237.sub1:Aquad
>>>> undef %235.sub2:Aquad = inst2 %229:A, %237.sub0:Aquad
>>>> undef %235.sub3:Aquad = inst2 %232:A, %237.sub1:Aquad
>>>> }
>>>
>>> Can you fill out more context with the surrounding instructions + ranges? Theoretically I can reconstruct the same scenario using -stress-regalloc
>>
>> So far by guessing I've only seen cases that fail to compile either way. However I'm guessing what we need is the assigned register is a strict superset of the interfering register
>
> Does it work if you change regsOverlap to isSuperRegisterEq?
Changing
TRI->regsOverlap(VRM->getPhys(Intf->reg()), PhysReg)))) &&
into
TRI->isSuperRegisterEq(VRM->getPhys(Intf->reg()), PhysReg)))) &&
does not help since Intf is
%211 [912r,960r:0) 0 at 912r weight:INF
and we have this allocation
[%211 -> $b0] A
And we're examining if using b3210 for %237:Aquad would work.
b0 overlaps with b3210 so the test with regsOverlap makes mayRecolorAllInterferences bail out.
And b3210 is a super reg of b0, so using isSuperRegisterEq also makes mayRecolorAllInterferences bail out.
If you meant to try out
TRI->isSuperRegisterEq(PhysReg, VRM->getPhys(Intf->reg()))))) &&
then yes, that helps since b0 is not a super register of b3210.
I dumped LIS and VRM when entering tryLastChanceRecoloring and cut out and simplified what I think are the important parts:
%211 [912r,960r:0) 0 at 912r weight:INF
%226 [920r,960r:0) 0 at 920r weight:INF
%229 [928r,960r:0) 0 at 928r weight:INF
%232 [932r,960r:0) 0 at 932r weight:INF
%234 [940r,960r:0) 0 at 940r weight:INF
%235 [944r,960r:1)[960r,968r:0) 0 at 960r 1 at 944r weight:INF
%237 [952r,960r:0) 0 at 952r weight:INF
[...]
912B %211:A = loadA %stack.4
920B %226:A = loadA %stack.6
928B %229:A = loadA %stack.8
932B %232:A = loadA %stack.10
940B %234:Aquad = loadAquad %stack.11
944B %235:Aquad = loadAquad %stack.12
952B %237:Aquad = loadAquad %stack.0
960B BUNDLE [...] {
inst1 %234:Aquad
inst1 %235:Aquad
undef %235.sub0:Aquad = inst2 %211:A, %237.sub0:Aquad
undef %235.sub1:Aquad = inst2 %226:A, %237.sub1:Aquad
undef %235.sub2:Aquad = inst2 %229:A, %237.sub0:Aquad
undef %235.sub3:Aquad = inst2 %232:A, %237.sub1:Aquad
}
968B storeAquad %235:Aquad, %stack.12
[...]
[%234 -> $a3210] Aquad
[%235 -> $b7654] Aquad
[%211 -> $b0_32] A
[%226 -> $b3_32] A
[%229 -> $b2_32] A
[%232 -> $a4_32] A
And to repeat: with the new regsOverlap check we get:
Try to assign: %237 [952r,960r:0) 0 at 952r weight:INF to $a3210
Early abort: the interference is not recolorable.
Some interferences cannot be recolored.
Try to assign: %237 [952r,960r:0) 0 at 952r weight:INF to $b3210
Early abort: the interference is not recolorable.
Some interferences cannot be recolored.
Try to assign: %237 [952r,960r:0) 0 at 952r weight:INF to $b7654
Early abort: the interference is not recolorable.
Some interferences cannot be recolored.
Try to assign: %237 [952r,960r:0) 0 at 952r weight:INF to $a7654
Early abort: the interference is not recolorable.
Some interferences cannot be recolored.
LLVM ERROR: ran out of registers during register allocation
but before, without it, it also really explored the
Try to assign: %237 [952r,960r:0) 0 at 952r weight:INF to $b3210
path, and finally succeeded since that way it could shuffle the fragmented free A registers around to form a free Aquad.
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https://reviews.llvm.org/D119973/new/
https://reviews.llvm.org/D119973
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