[PATCH] D119973: RegAllocGreedy: Fix last chance recolor assert in impossible case

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added a comment.

In D119973#3335832 <https://reviews.llvm.org/D119973#3335832>, @arsenm wrote:

> In D119973#3335710 <https://reviews.llvm.org/D119973#3335710>, @arsenm wrote:
>
>> In D119973#3335190 <https://reviews.llvm.org/D119973#3335190>, @uabelho wrote:
>>
>>> In a failing example we have a bundle like this with heavy register use:
>>>
>>>   BUNDLE [...] {
>>>     inst1 %234:Aquad
>>>     inst1 %235:Aquad
>>>     undef %235.sub0:Aquad = inst2 %211:A, %237.sub0:Aquad
>>>     undef %235.sub1:Aquad = inst2 %226:A, %237.sub1:Aquad
>>>     undef %235.sub2:Aquad = inst2 %229:A, %237.sub0:Aquad
>>>     undef %235.sub3:Aquad = inst2 %232:A, %237.sub1:Aquad
>>>   }
>>
>> Can you fill out more context with the surrounding instructions + ranges? Theoretically I can reconstruct the same scenario using -stress-regalloc
>
> So far by guessing I've only seen cases that fail to compile either way. However I'm guessing what we need is the assigned register is a strict superset of the interfering register

Does it work if you change regsOverlap to isSuperRegisterEq?


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