[PATCH] D120094: [CallingConv] Generate isArgumentRegister() predicate via tablegen

[Bill Wendling via Phabricator via llvm-commits]

void updated this revision to Diff 410396.
void marked an inline comment as done.
void added a comment.

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Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D120094/new/

https://reviews.llvm.org/D120094

Files:
  llvm/lib/Target/RISCV/RISCVRegisterInfo.h


Index: llvm/lib/Target/RISCV/RISCVRegisterInfo.h
===================================================================
--- llvm/lib/Target/RISCV/RISCVRegisterInfo.h
+++ llvm/lib/Target/RISCV/RISCVRegisterInfo.h
@@ -70,7 +70,7 @@
   unsigned getRegisterCostTableIndex(const MachineFunction &MF) const override;
 
   bool isCCArgumentReg(MachineFunction &, MCRegister) const override {
-    llvm_unreachable("isCCArgumentReg not implmented for RISCV");
+    llvm_unreachable("isCCArgumentReg not implemented for RISCV");
     return false;
   }
 };


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