[PATCH] D120226: [RISCV] Support mask policy for RVV IR intrinsics.

[Zakk Chen via Phabricator via llvm-commits]

khchen added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td:1155
   let HasMergeOp = 1;
+  let IsValidMaskPolicy = 1;
   let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
----------------
craig.topper wrote:
> VPseudoBinaryMask appears to only be used by VPseudoTernary which is used by reductions. But reduction shouldn't have IsValidMaskPolicy?
Yes, I missed it again, thanks!


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D120226/new/

https://reviews.llvm.org/D120226