[PATCH] D120226: [RISCV] Support mask policy for RVV IR intrinsics.
Zakk Chen via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Mon Feb 21 00:42:16 PST 2022
khchen updated this revision to Diff 410239.
khchen added a comment.
Address Craig's comments, thanks!
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D120226/new/
https://reviews.llvm.org/D120226
Files:
llvm/include/llvm/IR/IntrinsicsRISCV.td
llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
llvm/lib/Target/RISCV/RISCVInstrFormats.td
llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
llvm/test/CodeGen/RISCV/rvv/masked-tama.ll
llvm/test/CodeGen/RISCV/rvv/masked-tamu.ll
llvm/test/CodeGen/RISCV/rvv/masked-tuma.ll
llvm/test/CodeGen/RISCV/rvv/masked-tumu.ll
llvm/test/CodeGen/RISCV/rvv/vadd-policy.ll
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