[PATCH] D119171: [SelectionDAG][RISCV][ARM][PowerPC][X86][WebAssembly] Change default abs expansion to use sra (X, size(X)-1); sub (xor (X, Y), Y).

[Craig Topper via Phabricator via llvm-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG440c4b705ad1: [SelectionDAG][RISCV][ARM][PowerPC][X86][WebAssembly] Change default abs… (authored by craig.topper).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D119171/new/

https://reviews.llvm.org/D119171

Files:
  llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
  llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
  llvm/test/CodeGen/PowerPC/ppc64-P9-vabsd.ll
  llvm/test/CodeGen/RISCV/rv32zbb.ll
  llvm/test/CodeGen/RISCV/rv64zbb.ll
  llvm/test/CodeGen/Thumb/iabs.ll
  llvm/test/CodeGen/Thumb/optionaldef-scheduling.ll
  llvm/test/CodeGen/Thumb2/abs.ll
  llvm/test/CodeGen/WebAssembly/PR41149.ll
  llvm/test/CodeGen/X86/abs.ll
  llvm/test/CodeGen/X86/combine-abs.ll
  llvm/test/CodeGen/X86/iabs.ll
  llvm/test/CodeGen/X86/neg-abs.ll
  llvm/test/CodeGen/X86/viabs.ll
  llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/basic.ll.expected

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